Solid-state imaging device, package, and imaging system

Abstract

The present disclosure pertains to a solid-state imaging device, a package, and an imaging system which enable suppression of reduction in image quality. A solid-state imaging device according to an aspect of the present technology comprises: a photoelectric conversion unit configured by using a material having a smaller band gap energy than silicon; and a circuit board joined to the photoelectric conversion unit. The circuit board has a pixel signal generation circuit that generates a pixel signal having a voltage value corresponding to charges generated at the photoelectric conversion unit, a thermometer circuit that detects the temperature of the circuit board, and a temperature control signal generation circuit that acquires temperature information indicating the temperature detected by the thermometer circuit, and generates a temperature control signal on the basis of the acquired temperature information.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device, a package, and an imaging system.

Background Art

[0002] In recent years, solid-state imaging devices such as CMOS (Complementary Metal Oxide Semiconductor) image sensors (CIS: CMOS Image Sensor) have become extremely popular and are being used to replace film-based imaging devices in various fields. Solid-state imaging devices are not only used in place of film-based imaging devices in normal visible light photography, but are also remarkable in the use of non-visible light photography such as ultraviolet rays, infrared rays, X-rays, and gamma rays.

[0003] Furthermore, among imaging devices having a photoelectric conversion film in solid-state imaging devices, there are imaging devices that handle holes as carriers for photoelectric conversion. For example, photoelectric conversion films that use holes as carriers for photoelectric conversion include quantum (Q: Quantum) dots, InGaAs (indium gallium arsenide) sensors, and organic compounds. In particular, solid-state imaging devices using InGaAs as a photoelectric conversion film have low dark current and a bandgap energy narrower than that of silicon, and can capture long-wavelength light such as infrared light, so they are expected to be applied to high-sensitivity infrared cameras and the like.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, image sensors that use materials with a smaller bandgap energy than silicon, such as InGaAs, as the photoelectric conversion film are more sensitive to temperature fluctuations than image sensors that use silicon as the photoelectric conversion film. As a result, a large amount of dark current is generated as the temperature rises, which leads to a problem of degraded image quality.

[0006] Therefore, this disclosure proposes a solid-state imaging device, package, and imaging system capable of suppressing the degradation of image quality. [Means for solving the problem]

[0007] To solve the above problems, one embodiment of a solid-state imaging device according to the present disclosure comprises a photoelectric conversion unit made of a material having a smaller bandgap energy than silicon, and a circuit board bonded to the photoelectric conversion unit, wherein the circuit board includes a pixel signal generation circuit that generates a pixel signal with a voltage value corresponding to the charge generated in the photoelectric conversion unit, a thermometer circuit that detects the temperature of the circuit board, and a temperature control signal generation circuit that acquires temperature information indicating the temperature detected by the thermometer circuit and generates a temperature control signal based on the acquired temperature information. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram showing a schematic configuration example of a solid-state imaging device according to the first embodiment. [Figure 2] This is a circuit diagram showing a schematic configuration example of a sensor pixel according to the first embodiment. [Figure 3] This is a perspective view showing a schematic configuration example of a solid-state imaging device according to the first embodiment. [Figure 4] This is a cross-sectional view showing an example of the cross-sectional configuration of a solid-state imaging device according to the first embodiment. [Figure 5] This is a schematic plan view showing the general configuration of the light-receiving element according to the first embodiment. [Figure 6] This is a schematic diagram showing the cross-sectional configuration along line AA in Figure 5. [Figure 7]This is a cross-sectional view showing the pixel structure of the first embodiment. [Figure 8] This is a plan view showing an example configuration of a sensor package according to the first embodiment. [Figure 9] This is a cross-sectional view showing an example of the configuration of a sensor package according to the first embodiment. [Figure 10] This is an exploded cross-sectional view showing an example of the configuration of a sensor package according to the first embodiment. [Figure 11] This is a plan view showing an example of the configuration of the upper surface of a package substrate according to the first embodiment. [Figure 12] This is a plan view illustrating the positional relationship between the package substrate and the ceramic interposer substrate according to the first embodiment. [Figure 13] This is a cross-sectional view showing an example of the configuration of a Peltier element according to the first embodiment. [Figure 14] This figure illustrates a schematic configuration example and circuit layout of an imaging system according to a first system configuration example of the first embodiment. [Figure 15] This is a diagram illustrating the temperature control signal. [Figure 16] This is a block diagram showing an example of a system control circuit related to the first system configuration example of the first embodiment. [Figure 17] This diagram illustrates the first example of the timing for acquiring temperature information. [Figure 18] This diagram illustrates a second example of the timing for acquiring temperature information. [Figure 19] This diagram illustrates the temperature control signal output from the duty cycle adjustment circuit. [Figure 20] This is a diagram illustrating the driver circuit. [Figure 21] This is a flowchart showing the temperature control process 1. [Figure 22] This is a flowchart showing the continuous temperature control process. [Figure 23] This diagram illustrates a third example of the timing for acquiring temperature information. [Figure 24]It is a flowchart showing temperature control process 2. [Figure 25] It is a diagram for explaining a fourth example of the timing for acquiring temperature information. [Figure 26] It is a flowchart showing temperature control process 3. [Figure 27] It is a diagram for explaining test external terminals. [Figure 28] It is a diagram for explaining a schematic configuration example of an imaging system and a circuit layout according to a first system configuration example of the second embodiment. [Figure 29] It is a block diagram showing an example of a system control circuit according to a first system configuration example of the second embodiment. [Figure 30] It is a diagram for explaining external terminals according to a first system configuration example of the second embodiment. [Figure 31] It is a circuit diagram showing an example of a thermometer circuit. [Figure 32] It is a block diagram showing a schematic configuration example of an imaging system according to a first system configuration example of the third embodiment. [Figure 33] It is a layout diagram for explaining the arrangement of a thermometer circuit according to a first example of the third embodiment. [Figure 34] It is a diagram showing an example of the input / output of a solid-state imaging device. [Figure 35] It is a block diagram showing an example of a schematic configuration of a vehicle control system. [Figure 36] It is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit.

MODE FOR CARRYING OUT THE INVENTION

[0009] Hereinafter, an embodiment of the present disclosure will be described in detail based on the drawings. In the following embodiments, the same parts are denoted by the same reference numerals, and redundant descriptions are omitted.

[0010] Also, the present disclosure will be described in accordance with the following item order. 1. First 2. First Embodiment 2.1 Example Configuration 2.2 Example of cross-sectional structure around the photoelectric conversion unit 2.3 Example Configuration of a Solid-State Imaging Device 2.4 Joint structure example 2.5 Packaging of Solid State Imaging Devices 2.6 Temperature Control Mechanism 2.7 Location of the temperature sensor (thermometer circuit) 2.8 Example of a schematic configuration of an imaging system 2.8.1 Example of System Configuration 1 2.8.1.1 Temperature control signal 2.8.1.2 System Control Circuit 2.8.1.3 First example of timing for acquiring temperature information 2.8.1.4 Second example of the timing for acquiring temperature information 2.8.1.5 Temperature control signal output from the duty cycle adjustment circuit 2.8.1.6 Example of a driver circuit 2.8.1.7 Flow of Temperature Control Process 1 2.8.1.8 Flowchart of Continuous Temperature Control Process 2.8.1.9 Third example of the timing for acquiring temperature information 2.8.1.10 Flow of Temperature Control Process 2 2.8.1.11 Fourth example of the timing for acquiring temperature information 2.8.1.12 Flow of Temperature Control Process 3 2.8.1.13 Test External Terminals 2.8.2 Example of a second system configuration (multiple temperature control elements) 2.8.2.1 System Control Circuit 2.8.2.2 External terminals 2.8.2.3 Thermometer circuit 2.8.3 Example of System Configuration 3 (with Multiple Temperature Value Averaging Function) 2.8.3.1 Example Configuration of a Solid State Imaging Device 3. Examples of applications to mobile devices

[0011] 1. Introduction A typical solid-state imaging device (hereinafter also called an image sensor) converts incident light into electricity using a photoelectric conversion unit such as a photodiode formed in a silicon substrate, and generates an image based on the resulting charge.

[0012] Furthermore, in recent years, image sensors using compound semiconductors and other materials in the photoelectric conversion film have also emerged. An example of this is a short-wave infrared (SWIR) sensor with stacked InGaAs layers.

[0013] CMOS image sensors (CIS) use a photoelectric conversion section on a silicon substrate as a light-receiving element, and their sensitivity wavelength is physically limited to about 1100 nm (nanometers). However, by using compounds such as InGaAs in the photoelectric conversion film, it is possible to create image sensors that are sensitive to infrared light with wavelengths of 1200 nm or higher.

[0014] This is because InGaAs has a smaller bandgap energy than silicon, allowing for photoelectric conversion even with long wavelengths of light above 1200 nm.

[0015] However, photoelectric conversion materials with a smaller bandgap energy than silicon are more sensitive to temperature fluctuations than silicon. Therefore, they generate more noise, known as dark current, as the temperature increases.

[0016] To suppress the generation of dark current, which is a type of noise, it is conceivable to provide a mechanism (hereinafter also called a temperature control mechanism) within the package housing the image sensor that cools or maintains the chip containing the photoelectric conversion film (hereinafter also called the sensor chip) at a constant temperature.

[0017] For the temperature control mechanism, for example, a Peltier element can be used. In that case, a discrete thermistor element for measuring the chip temperature is attached to the sensor chip, and a temperature control signal generation circuit and a driver circuit located outside the sensor chip control the Peltier element based on the current or voltage output from the thermistor element.

[0018] For example, the Peltier element inside the package is controlled by applying current or voltage from a driver circuit outside the package through an external terminal provided on the package.

[0019] Furthermore, the voltage or current correlated with the temperature detected by the thermistor element within the package is input to the temperature control signal generation circuit through the package's external terminals.

[0020] However, the above configuration presents the following challenges.

[0021] First, the purpose of temperature control is to eliminate temperature-induced noise generated in the sensor chip. However, in configurations where discrete thermistor elements are physically mounted within the package, the temperature of the sensor chip is not always accurately monitored. Because the thermal resistance from the sensor chip to the thermistor element varies depending on the mounting conditions, the error in the signal output from the thermistor element is also large.

[0022] Furthermore, since thermistor elements generally have an analog output, they have low robustness against external noise. Wiring is required to input the output of the thermistor element to an external temperature control signal generation circuit, but since control signal lines and power supply lines are routed in parallel with this wiring, capacitance is likely to occur.

[0023] Furthermore, if a Peltier element is used as a temperature control mechanism, the heat generated by this Peltier element needs to be dissipated to the outside of the package. Therefore, a large area without terminals is required on the back of the package, which limits the number of terminals that can be provided on the package. In addition, in addition to the control terminals for the image sensor and the power terminals, terminals are needed to output the thermistor element's output to the outside of the package and to input the control signal for the Peltier element into the package, which further reduces the number of terminals on the package.

[0024] Furthermore, adding a thermistor element to the package can lead to a decrease in the yield of the image sensor product due to defects in the thermistor element itself or improper mounting.

[0025] Therefore, in the following embodiment, we propose a solid-state imaging device and imaging system that can suppress the deterioration of image quality by solving at least one of the above problems.

[0026] 2. First Embodiment First, a solid-state imaging apparatus and imaging system according to the first embodiment of this disclosure will be described in detail with reference to the drawings.

[0027] 2.1 Example Configuration Figure 1 is a block diagram showing a schematic configuration example of a solid-state imaging device according to the first embodiment. Figure 2 is a circuit diagram showing a schematic configuration example of a sensor pixel according to the first embodiment. Figure 3 is a perspective view showing a schematic configuration example of a solid-state imaging device according to the first embodiment.

[0028] As shown in Figure 1, the solid-state imaging device 1 is, for example, an infrared image sensor and is sensitive to light with a wavelength of 1200 nm or more. The solid-state imaging device 1 includes a pixel array section 10 in which a plurality of sensor pixels 11, each containing a photoelectric conversion element, are arranged in a matrix in two dimensions. The sensor pixels 11 are composed of, for example, a pixel circuit 14 that performs photoelectric conversion and a readout circuit 15 that outputs a pixel signal based on the charge output from the pixel circuit 14, as shown in Figure 2.

[0029] The pixel circuit 14 includes, for example, a photodiode PD, a transfer transistor TRG, a floating diffusion FD, and an emission transistor OFG. The transfer transistor TRG and the emission transistor OFG are, for example, NMOS (Metal Oxide Semiconductor) transistors. The photodiode PD corresponds to one specific example of the "photoelectric conversion unit" of this disclosure.

[0030] A photodiode PD is a photoelectric conversion unit that absorbs light of a predetermined wavelength (for example, light in the infrared region with wavelengths of 1200 nm or more) to generate a signal charge. The photoelectric conversion material that constitutes the photodiode PD may include, for example, compound semiconductors such as III-V semiconductors.

[0031] Examples of III-V semiconductors used in photodiodes (PDs) include InGaP, InAlP, InGaAs, InAlAs, and compound semiconductors with a chalcopyrite structure. Compound semiconductors with a chalcopyrite structure are materials that provide a high light absorption coefficient and high sensitivity over a wide wavelength range, and are preferably used as n-type semiconductor materials for photoelectric conversion. In addition to the compound semiconductors mentioned above, photodiodes (PDs) may also be composed of amorphous silicon (Si), germanium (Ge), quantum dot photoelectric conversion films, organic photoelectric conversion films, etc. The following description will illustrate the case in which InGaAs is used in a photodiode (PD).

[0032] The cathode of the photodiode PD is connected to the source of the transfer transistor TRG, and the anode of the photodiode PD is connected to a power line to which voltage Vtop is applied. The drain of the transfer transistor TRG is connected to a floating diffusion FD, and the gate of the transfer transistor TRG is connected to the pixel drive line 12.

[0033] The transfer transistor TRG is connected between the cathode of the photodiode PD and the floating diffusion FD, and transfers the charge held in the photodiode PD to the floating diffusion FD in response to a control signal applied to the gate electrode. The drain of the transfer transistor TRG is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TRG is connected to the pixel drive line 12.

[0034] The floating diffusion region (FD) is a floating diffusion region that temporarily holds the charge transferred from the photodiode PD via the transfer transistor TRG. A readout circuit 15 is connected to the floating diffusion region (FD), and a vertical signal line 13 is connected via the readout circuit 15. The floating diffusion region (FD) is connected to the input terminal of the readout circuit 15.

[0035] In the emission transistor (OFG), the drain is connected to the power line to which the voltage Vdr is applied, and the source is connected to the cathode of the photodiode PD. The emission transistor (OFG) initializes (resets) the charge of the photodiode PD in response to the control signal applied to the gate electrode.

[0036] The readout circuit 15 includes, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. The source of the reset transistor RST (the input terminal of the readout circuit 15) is connected to a floating diffusion FD, and the drain of the reset transistor RST is connected to the power line VDD and the drain of the amplification transistor AMP. The gate of the reset transistor RST is connected to the pixel drive line 12. The source of the amplification transistor AMP is connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is connected to the source of the reset transistor RST. The source of the selection transistor SEL (the output terminal of the readout circuit 15) is connected to the vertical signal line 13, and the gate of the selection transistor SEL is connected to the pixel drive line 12.

[0037] The reset transistor RST initializes (resets) the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned ON, it resets the potential of the floating diffusion FD to the potential of the power line VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 15. The amplification transistor AMP generates a signal with a voltage corresponding to the level of charge held in the floating diffusion FD as the pixel signal. In other words, the amplification transistor AMP generates a signal with a voltage corresponding to the amount of light received at the sensor pixel 11 as the pixel signal. The amplification transistor AMP constitutes a source follower type amplifier and outputs a pixel signal with a voltage corresponding to the level of charge generated by the photodiode PD. When the selection transistor SEL is turned ON, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to that potential to the horizontal selection circuit 40, described later, via the vertical signal line 13.

[0038] The selection transistor SEL may be provided between the power line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is connected to the power line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is connected to the pixel drive line 12. The source of the amplification transistor AMP (the output terminal of the readout circuit 15) is connected to the vertical signal line 13, and the gate of the amplification transistor AMP is connected to the source of the reset transistor RST.

[0039] The solid-state imaging device 1 comprises two substrates (a light-receiving substrate 100 and a circuit board 200), as shown in Figure 3, for example. The solid-state imaging device 1 has a three-dimensional structure (also called a laminated structure) formed by bonding the two substrates (the light-receiving substrate 100 and the circuit board 200) together.

[0040] The light-receiving substrate 100 has a structure in which multiple photodiodes PD are formed in a matrix on an InGaAs substrate. The upper surface of the light-receiving substrate 100 (the surface opposite to the circuit board 200) is the light-receiving surface 100A.

[0041] The circuit board 200 has a structure in which, for example, a pixel signal generation circuit region 200A and a peripheral circuit region 200B are provided on one side of a silicon (Si) substrate.

[0042] In the pixel signal generation circuit region 200A, multiple pixel signal generation circuits 45 are formed in a matrix. Each pixel signal generation circuit 45 is a circuit of the sensor pixel 11 excluding the photodiode PD.

[0043] The light-receiving substrate 100 is bonded to the pixel signal generation circuit region 200A of the circuit board 200. This is because the light-receiving substrate 100 does not fundamentally have circuit elements such as transistors built into it, and mainly functions as a photoelectric conversion film. Furthermore, if a compound semiconductor that is sensitive to light with wavelengths longer than 1200 nm is used for the light-receiving substrate 100, it will also photoelectrically convert light emitted from circuit elements. Therefore, if circuit elements other than the pixel circuit 14 (excluding the photodiode PD) exist below the light-receiving substrate 100, the uniformity of the sensitivity of the pixel array may be impaired by the light emitted from these circuit elements.

[0044] The peripheral circuit region 200B contains logic circuits for processing pixel signals, including, for example, a vertical drive circuit 20, a horizontal drive circuit 30, a horizontal selection circuit 40, a system control circuit 16, a film voltage control unit 17, and a voltage generation circuit 18. These logic circuits output a pixel signal (digital value) for each sensor pixel 11 to the outside.

[0045] Furthermore, the peripheral circuit region 200B that is not covered by the light-receiving substrate 100 may be covered with an insulating film such as passivation.

[0046] Thus, the solid-state imaging device 1 comprises a pixel array unit 10, a vertical drive circuit 20, a horizontal drive circuit 30, a horizontal selection circuit 40, a system control circuit 16, a film voltage control unit 17, and a voltage generation circuit 18.

[0047] The system control circuit 16 generates clock signals and control signals that serve as a reference for the operation of the vertical drive circuit 20, horizontal drive circuit 30, horizontal selection circuit 40, and film voltage control unit 17, etc., based on the master clock, and provides them to the vertical drive circuit 20, horizontal selection circuit 40, and film voltage control unit 17, etc.

[0048] The vertical drive circuit 20 includes, for example, a shift register, and controls the row scanning of multiple sensor pixels 11 via multiple pixel drive lines 12.

[0049] The horizontal selection circuit 40 is a circuit in which, for example, an ADC (Analog-to-Digital Converter) 40a and a switching element 40b are provided for each pixel row (or vertical signal line 13) of the pixel array section 10. The ADC 40a performs A / D conversion of the pixel signal. The ADC 40a is capable of varying the analog range R and is set to the analog range R based on a range setting value input from an external source. In this embodiment, the analog range R is assumed to be set to Ra.

[0050] A vertical signal line 13 is connected to the input terminal of the ADC 40a, and a switch element 40b is connected to the output terminal of the ADC 40a. The horizontal drive circuit 30 is composed of, for example, a shift register, and drives each switch element 40b of the horizontal selection circuit 40 in sequence. By sequentially driving each switch element 40b with the horizontal drive circuit 30, each pixel signal transmitted through each of the vertical signal lines 13 is sequentially output to the horizontal signal line 40c and input to a DSP circuit or the like.

[0051] The film voltage control unit 17 controls the film voltage Vf applied to each photodiode PD based on the pixel signal obtained from the sensor pixel 11. The film voltage control unit 17 outputs a control signal for controlling the film voltage Vf to the voltage generation circuit 18. The voltage generation circuit 18 generates analog voltages (voltages Vtop and Vdr) based on the control signal input from the film voltage control unit 17 and applies them to each photodiode PD via the power line. In other words, the film voltage control unit 17 and the voltage generation circuit 18 control the image quality of the image data obtained from the pixel signal by applying a film voltage Vf based on the pixel signal obtained from the sensor pixel 11 to each photodiode PD.

[0052] 2.2 Example of cross-sectional structure around the photoelectric conversion unit Figure 4 is a cross-sectional view showing an example of the cross-sectional configuration around the photoelectric conversion unit (photodiode PD) in a solid-state imaging device according to the first embodiment. As shown in Figure 4, in the solid-state imaging device 1, the light-receiving substrate 100 has an n-type semiconductor film 21 which is a photoelectric conversion unit (photodiode PD). The n-type semiconductor film 21 is formed over the entire surface of the pixel array 10 and is composed of, for example, the material described above as the material used for the photodiode PD. In the following description, other configurations will be explained assuming that the n-type semiconductor film 21 is composed of InGaAs.

[0053] The light-receiving substrate 100 further has a p-type semiconductor layer 22 for each sensor pixel 11, which is in contact with the circuit board 200 side of the n-type semiconductor film 21. Each p-type semiconductor layer 22 is formed of a high-density p-type semiconductor, for example, p-type InGaAs. The p-type semiconductor layer 22 functions as an electrode (second electrode) of the photodiode PD. A predetermined voltage Vdr is applied to the p-type semiconductor layer 22 via an ON-state emission transistor OFG, or the voltage Vdd of the power line VDD is applied via an ON-state transfer transistor TRG and a reset transistor RST. The light-receiving substrate 100 further has an n-type semiconductor layer 23 that separates each p-type semiconductor layer 22 from each other. The n-type semiconductor layer 23 is formed in the same layer as each p-type semiconductor layer 22, and is for example, n-type InP.

[0054] The light-receiving substrate 100 further has an n-type semiconductor layer 24 in contact with the light-receiving surface 100A side of the n-type semiconductor film 21. The n-type semiconductor layer 24 is formed of an n-type semiconductor with a higher concentration than the n-type semiconductor film 21, and is formed of, for example, n-type InGaAs, n-type InP, or n-type InAlAs. The n-type semiconductor layer 24 functions as a barrier layer to prevent the backflow of charge generated in the n-type semiconductor film 21. The light-receiving substrate 100 further has an anti-reflective film 25 in contact with the light-receiving surface 100A side of the n-type semiconductor layer 24. The anti-reflective film 25 is formed of, for example, silicon nitride (SiN), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), tantalum oxide (Ta2Ta5), titanium oxide (TiO2), etc. The n-type semiconductor layer 24 also functions as the upper electrode (first electrode) of the electrodes that sandwich the n-type semiconductor film 21 from above and below. A predetermined voltage Vtop is applied to the upper electrode.

[0055] The light-receiving substrate 100 further includes a color filter 26 and an on-chip lens 27 on the anti-reflective coating 25. The color filter 26 is composed of multiple filters 26R that selectively transmit red light, multiple filters 26G that selectively transmit green light, and multiple filters 26G that selectively transmit blue light. One of the filters 26R, 26G, and 26B is provided for each sensor pixel 11, and is arranged, for example, in a Bayer array in a plane parallel to the light-receiving surface 100A. In Figure 4, a sensor pixel 11 provided with filter 26R is denoted as 11R, a sensor pixel 11 provided with filter 26G is denoted as 11G, and a sensor pixel 11 provided with filter 26B is denoted as 11B. The color filter 26 may be omitted if necessary.

[0056] The light-receiving substrate 100 further has a passivation layer 28 and an insulating layer 29 below the p-type semiconductor layer 22 and the n-type semiconductor layer 23. The light-receiving substrate 100 further has a connecting electrode 31 that penetrates the passivation layer 28 and is in contact with the p-type semiconductor layer 22, and a bump electrode 32 that penetrates the insulating layer 29 and is in contact with the connecting electrode 31. One pair of connecting electrodes 31 and bump electrodes 32 is provided for each sensor pixel 11. The bump electrode 32 is bonded to the connecting layer 43 (described later) of the circuit board 200 and is electrically connected to the connecting layer 43. The bump electrode 32 is bonded to the connecting layer 43 of the circuit board 200, for example, when the light-receiving substrate 100 and the circuit board 200 are bonded to each other.

[0057] The passivation layer 28 and the insulating layer 29 may be configured as interlayer insulating layers. In this case, at least one of the passivation layer 28 and the insulating layer 29 may have a multilayer structure. When the passivation layer 28 and the insulating layer 29 are interlayer insulating layers, the connecting electrode 31 and the bump electrode 32 may be part of the wiring provided in the interlayer insulating layer. In this case, the wiring of this interlayer insulating layer (bump electrode 32) and the wiring of the interlayer insulating layer 42 in the circuit board 200 (connecting layer 43) are directly joined, thereby electrically connecting the light receiving substrate 100 (e.g., photodiode PD) and the circuit board 200 (e.g., pixel circuits 14 other than the photodiode PD and readout circuits 15).

[0058] The circuit board 200 includes a support substrate 41 and an interlayer insulating layer 42. The support substrate 41 is made of, for example, a silicon (Si) substrate. The interlayer insulating layer 42 is provided between the support substrate 41 and the insulating layer 291 (light-receiving substrate 100). The interlayer insulating layer 42 is provided with, for example, multiple connection layers 43, multiple read electrodes 44, multiple pixel signal generation circuits 45, and multiple wirings 46 in order from the position closest to the light-receiving substrate 100. Multiple sets of connection layers 43, read electrodes 44, pixel signal generation circuits 45, and wirings 46 are provided one set for each sensor pixel 11. Multiple interlayer insulating layers 42 within the interlayer insulating layer 42 are provided, for example, within a ROIC (Read Out IC) for reading charge from each photodiode PD. The above-mentioned logic circuits are provided in the part of the interlayer insulating layer 42 of the circuit board 200 that corresponds to the peripheral circuit region 200B.

[0059] 2.3 Example Configuration of a Solid-State Imaging Device Figures 5 and 6 show examples of the configuration of a solid-state imaging device according to the first embodiment. Figure 5 shows the planar configuration of the solid-state imaging device 1, and Figure 6 shows the cross-sectional configuration along line AA in Figure 5. This solid-state imaging device 1 is provided with, for example, a plurality of light-receiving unit regions P (sensor pixels 11) arranged in two dimensions (Figure 6).

[0060] The solid-state imaging device 1 has a central element region R1 and a peripheral region R2 located outside the element region R1 and surrounding it (Figure 5). The solid-state imaging device 1 has a conductive film 33 that extends from the element region R1 to the peripheral region R2. This conductive film 33 has an opening in the region facing the central part of the element region R1.

[0061] The solid-state imaging device 1 has a laminated structure of a light-receiving substrate 100 and a circuit board 200 (Figure 6). One side of the light-receiving substrate 100 is the light incident surface (light incident surface S1), and the side opposite to the light incident surface S1 (the other side) is the bonding surface with the circuit board 200 (bonding surface S2).

[0062] The light-receiving substrate 100 has, in order from the position closest to the circuit board 200, an insulating layer 29, a connecting electrode 31, a semiconductor layer 21A, an n-type semiconductor layer 24, and an anti-reflective film 25. The surface of the semiconductor layer 21A facing the insulating layer 29 and the end surface (side surface) are covered with a passivation layer 28. The circuit board 200 is a so-called ROIC (Readout Integrated Circuit) and has a wiring layer 35 and an interlayer insulating layer 42 in contact with the bonding surface S2 of the light-receiving substrate 100, and a support substrate 41 facing the light-receiving substrate 100 with the wiring layer 35 and interlayer insulating layer 42 in between.

[0063] The light-receiving substrate 100 has a semiconductor layer 21A in the element region R1. In other words, the region where the semiconductor layer 21A is provided is the element region R1 of the solid-state imaging device 1. Of the element region R1, the region exposed from the conductive film 33 (the region facing the opening of the conductive film 33) is the light-receiving region. Of the element region R1, the region covered by the conductive film 33 is the OPB (Optical Black) region R1B. The OPB region R1B is provided so as to surround the light-receiving region. The OPB region R1B is used to obtain a black level pixel signal. The light-receiving substrate 100 has an embedded layer 36 together with a passivation layer 28 in the peripheral region R2. Holes H1 and H2 are provided in the peripheral region R2 that penetrate the light-receiving substrate 100 and reach the circuit board 200. In the solid-state imaging device 1, light is incident from the light incident surface S1 of the light-receiving substrate 100, passing through the anti-reflective film 25, the n-type semiconductor layer 24, and the n-type semiconductor layer 24 to the semiconductor layer 21A. The signal charge converted photoelectrically in the semiconductor layer 21A moves through the connecting electrode 31 and the insulating layer 29 and is read out by the circuit board 200. The configuration of each part will be described below.

[0064] The insulating layer 29 is provided across the element region R1 and the peripheral region R2, and has a bonding surface S2 with the circuit board 200. In the solid-state imaging device 1, this bonding surface S2 of the light-receiving substrate 100 is provided in the element region R1 and the peripheral region R2, and for example, the bonding surface S2 of the element region R1 and the bonding surface S2 of the peripheral region R2 form the same plane. As will be described later, in the solid-state imaging device 1, the bonding surface S2 of the peripheral region R2 is formed by providing an embedded layer 36.

[0065] The insulating layer 29 has, for example, bump electrodes 32 and dummy electrodes 32D in the interlayer insulating films 29A and 29B that constitute the insulating layer 29. For example, the interlayer insulating film 29B is placed on the circuit board 200 side and the interlayer insulating film 29A is placed on the p-type semiconductor layer 22 side, and these interlayer insulating films 29A and 29B are stacked together. The interlayer insulating films 29A and 29B are made of, for example, an inorganic insulating material. Examples of this inorganic insulating material include silicon nitride (SiN), aluminum oxide (Al2O3), silicon dioxide (SiO2), and hafnium oxide (HfO2). The interlayer insulating films 29A and 29B may be made of the same inorganic insulating material.

[0066] The bump electrodes 32 are provided, for example, in the element region R1. These bump electrodes 32 are for electrically connecting the connecting electrode 31 and the circuit board 200, and are provided for each pixel P in the element region R1. Adjacent bump electrodes 32 are electrically isolated by the embedding layer 36 and the interlayer insulating films 29A and 29B. The bump electrodes 32 are made of, for example, copper (Cu) pads and are exposed to the bonding surface S2. The dummy electrode 32D is provided, for example, in the peripheral region R2. This dummy electrode 32D is connected to the dummy connecting layer 43D of the wiring layer 35, which will be described later. By providing this dummy electrode 32D and dummy connecting layer 43D, it is possible to improve the strength of the peripheral region R2. The dummy electrode 32D is formed, for example, in the same process as the bump electrode 32. The dummy electrode 32D is made of, for example, copper (Cu) pads and is exposed to the bonding surface S2.

[0067] The connecting electrode 31, provided between the bump electrode 32 and the semiconductor layer 21A, is an electrode (anode) to which a voltage is supplied for reading out the signal charge (hole or electron; for convenience, the signal charge will be described as a hole) generated in the n-type semiconductor film 21. A connecting electrode 31 is provided for each pixel P in the element region R1. The connecting electrode 31 is provided so as to fill the opening of the passivation layer 28 and is in contact with the semiconductor layer 21A (more specifically, the diffusion region 22A). The connecting electrode 31 is, for example, larger than the opening of the passivation layer 28, and a part of the connecting electrode 31 is provided in the embedding layer 36. That is, the upper surface of the connecting electrode 31 (the surface on the semiconductor layer 21A side) is in contact with the diffusion region 22A, and the lower surface and part of the side of the connecting electrode 31 are in contact with the embedding layer 36. Adjacent connecting electrodes 31 are electrically isolated by the passivation layer 28 and the embedding layer 36.

[0068] The connecting electrode 31 is composed of, for example, one of the following elements: titanium (Ti), tungsten (W), titanium nitride (TiN), platinum (Pt), gold (Au), germanium (Ge), palladium (Pd), zinc (Zn), nickel (Ni), and aluminum (Al), or an alloy containing at least one of these elements. The connecting electrode 31 may be a single film of such constituent material, or it may be a multilayer film combining two or more of these elements. For example, the connecting electrode 31 is composed of a multilayer film of titanium and tungsten. The thickness of the connecting electrode 31 is, for example, several tens of nanometers to several hundred nanometers.

[0069] The semiconductor layer 21A includes, for example, a p-type semiconductor layer 22, an n-type semiconductor film 21, and an n-type semiconductor layer 24, starting from a position close to the insulating layer 29. The p-type semiconductor layer 22, the n-type semiconductor film 21, and the n-type semiconductor layer 24 have the same planar shape, and their respective end faces are located at the same position in a plan view.

[0070] The p-type semiconductor layer 22 is provided in common to all pixels P, for example, and is located between the passivation layer 28 and the n-type semiconductor film 21. The p-type semiconductor layer 22 is for electrically isolating adjacent pixels P, and the p-type semiconductor layer 22 is provided with, for example, multiple diffusion regions 22A. By using a compound semiconductor material with a band gap larger than that of the compound semiconductor material constituting the n-type semiconductor film 21 for the p-type semiconductor layer 22, it is possible to suppress dark current. For example, n-type InP (indium phosphide) can be used for the p-type semiconductor layer 22.

[0071] The diffusion regions 22A provided in the p-type semiconductor layer 22 are spaced apart from each other. A diffusion region 22A is provided for each pixel P, and a connecting electrode 31 is connected to each diffusion region 22A. A diffusion region 22A is also provided in the OPB region R1B. The diffusion region 22A is for reading out the signal charge generated in the n-type semiconductor film 21 for each pixel P, and contains, for example, p-type impurities. Examples of p-type impurities include Zn (zinc). In this way, a pn junction interface is formed between the diffusion region 22A and the p-type semiconductor layer 22 other than the diffusion region 22A, so that adjacent pixels P are electrically isolated. The diffusion region 22A is provided, for example, in the thickness direction of the p-type semiconductor layer 22, and also in a part of the thickness direction of the n-type semiconductor film 21.

[0072] The n-type semiconductor film 21 between the connecting electrode 31 and the n-type semiconductor layer 24, more specifically between the p-type semiconductor layer 22 and the n-type semiconductor layer 24, is provided in common to all pixels P, for example. This n-type semiconductor film 21 absorbs light of a predetermined wavelength to generate a signal charge, and is composed of a compound semiconductor material such as an i-type III-V semiconductor. Examples of compound semiconductor materials that constitute the n-type semiconductor film 21 include InGaAs (indium gallium arsenide), InAsSb (indium arsenide antimony), InAs (indium arsenide), InSb (indium antimony), and HgCdTe (mercury cadmium telluride). The n-type semiconductor film 21 may also be composed of Ge (germanium). In the n-type semiconductor film 21, for example, photoelectric conversion of light with wavelengths from the visible region to the short-infrared region occurs.

[0073] The n-type semiconductor layer 24 is provided in common to all pixels P, for example. This n-type semiconductor layer 24 is provided between the n-type semiconductor film 21 and the n-type semiconductor layer 24, and is in contact with them. The n-type semiconductor layer 24 is a region where charge discharged from the n-type semiconductor layer 24 moves, and is composed of a compound semiconductor containing n-type impurities, for example. For the n-type semiconductor layer 24, n-type InP (indium phosphide) can be used, for example.

[0074] The n-type semiconductor layer 24 is provided, for example, as a common electrode for each pixel P, on the n-type semiconductor layer 24 (on the light incident side) and in contact with the n-type semiconductor layer 24. The n-type semiconductor layer 24 is for discharging charges that are not used as signal charges from the charges generated in the n-type semiconductor film 21 (cathode). For example, when a hole is read out as a signal charge from the connecting electrode 31, electrons can be discharged through this n-type semiconductor layer 24. The n-type semiconductor layer 24 is made of a conductive film that can transmit incident light such as infrared light. For example, ITO (Indium Tin Oxide) or ITiO (In2O3-TiO2) can be used for the n-type semiconductor layer 24. The n-type semiconductor layer 24 may be provided in a grid pattern, for example, to separate adjacent pixels P. It is possible to use a conductive material with low light transmittance for this n-type semiconductor layer 24.

[0075] The anti-reflective film 25 covers the n-type semiconductor layer 24 from the light incident surface S1 side. The anti-reflective film 25 may have an anti-reflective function. For example, silicon nitride (SiN), aluminum oxide (Al2O3), silicon dioxide (SiO2), and tantalum oxide (Ta2O3) can be used for the anti-reflective film 25. The anti-reflective film 25 has an opening 37H in the OPB region R1B. The opening 37H is provided, for example, in a frame-like shape surrounding the light-receiving region (Figure 5). The opening 37H may be, for example, a square or circular hole in a plan view. The conductive film 33 is electrically connected to the n-type semiconductor layer 24 through the opening 37H of the anti-reflective film 25.

[0076] The passivation layer 28 is provided between the p-type semiconductor layer 22 and the embedding layer 36, and covers the end faces of the p-type semiconductor layer 22, the n-type semiconductor film 21, the n-type semiconductor layer 24, and the n-type semiconductor layer 24, and is in contact with the anti-reflective film 25 in the peripheral region R2. This passivation layer 28 is composed of an oxide such as silicon oxide (SiOX) or aluminum oxide (Al2O3). The passivation layer 28 may also be composed of a laminated structure consisting of multiple films. The passivation layer 28 may also be composed of a silicon (Si)-based insulating material such as silicon oxynitride (SiON), carbon-containing silicon oxide (SiOC), silicon nitride (SiN), and silicon carbide (SiC). The thickness of the passivation layer 28 is, for example, several tens of nanometers to several hundred nanometers.

[0077] The conductive film 33 is provided extending from the OPB region R1B to the hole H1 in the peripheral region R2. This conductive film 33 is in contact with the n-type semiconductor layer 24 at the opening 37H of the anti-reflective film 25 provided in the OPB region R1B, and is also in contact with the wiring 46 of the circuit board 200 through the hole H1. As a result, voltage is supplied from the circuit board 200 to the n-type semiconductor layer 24 via the conductive film 33. The conductive film 33 functions as a voltage supply path to the n-type semiconductor layer 24 and also functions as a light-shielding film, forming the OPB region R1B. The conductive film 33 is composed of a metallic material including, for example, tungsten (W), aluminum (Al), titanium (Ti), molybdenum (Mo), tantalum (Ta), or copper (Cu). A passivation film may be provided on the conductive film 33.

[0078] An adhesive layer B may be provided between the edge of the n-type semiconductor layer 24 and the n-type semiconductor layer 24. This adhesive layer B is used when forming the solid-state imaging device 1, as will be described later, and plays the role of bonding the semiconductor layer 21A to a temporary substrate (not shown). The adhesive layer B is made of, for example, tetraethoxysilane (TEOS) or silicon oxide (SiO2). The adhesive layer B is provided, for example, wider than the end face of the p-type semiconductor layer 22, and together with the semiconductor layer 21A, is covered by the embedding layer 36. A passivation layer 28 is provided between the adhesive layer B and the embedding layer 36.

[0079] The adhesive layer B may extend over a wide area of ​​the peripheral region R2. For example, it may extend from near the edge of the semiconductor layer 21A (device region R1) to the space between holes H1 and H2. Alternatively, the adhesive layer B may extend from near the edge of the semiconductor layer 21A (device region R1) to the chip edge (chip edge E).

[0080] The embedded layer 36 is used in the manufacturing process of the solid-state imaging device 1 to fill the step difference between the temporary substrate and the semiconductor layer 21A. As will be described in detail later, in this embodiment, since this embedded layer 36 is formed, the occurrence of manufacturing process defects caused by the step difference between the semiconductor layer 21A and the temporary substrate is suppressed.

[0081] The embedded layer 36 in the peripheral region R2 is provided between the insulating layer 29 and the passivation layer 28, and between the insulating layer 29 and the anti-reflective film 25, and has a thickness greater than or equal to the thickness of the semiconductor layer 21A. Here, since the embedded layer 36 is provided surrounding the semiconductor layer 21A, a region around the semiconductor layer 21A (peripheral region R2) is formed. This makes it possible to provide a bonding surface S2 with the circuit board 200 in this peripheral region R2. If a bonding surface S2 is formed in the peripheral region R2, the thickness of the embedded layer 36 may be reduced, but it is preferable that the embedded layer 36 covers the semiconductor layer 21A in the thickness direction, and that the entire end face of the semiconductor layer 21A is covered by the embedded layer 36. By the embedded layer 36 covering the entire end face of the semiconductor layer 21A via the passivation layer 28, the intrusion of moisture into the semiconductor layer 21A can be effectively suppressed. The embedded layer 36 of the element region R1 is provided between the semiconductor layer 21A and the insulating layer 29 so as to cover the connecting electrode 31.

[0082] The surface of the embedded layer 36 on the joint surface S2 is flattened, and in the peripheral region R2, an insulating layer 29 is provided on this flattened surface of the embedded layer 36. For the embedded layer 36, inorganic insulating materials such as silicon oxide (SiO₂X), silicon nitride (SiN), silicon oxynitride (SiON), carbon-containing silicon oxide (SiOC), and silicon carbide (SiC) can be used.

[0083] As described later, in the process of manufacturing the solid-state imaging device 1, after forming the embedded layer 36, an insulating layer 29 including interlayer insulating films 29A and 29B and bump electrodes 32 is formed above the embedded layer 36. A circuit board 200 including a wiring layer 35 is bonded to a light-receiving substrate 100 including this insulating layer 29 to form the solid-state imaging device 1. At this time, the bump electrodes 32 of the insulating layer 29 and the connecting layer 43 of the wiring layer 35 are connected. The bump electrodes 32 and the connecting layer 43 have, for example, Cu pads, and the bump electrodes 32 and the connecting layer 43 are connected by direct bonding of these Cu pads. When the bump electrodes 32 are formed using the CMP (Chemical Mechanical Polishing) method, the embedded layer 36, which is positioned below the copper film to be polished, is required to have a hardness that can withstand the stress during polishing. Furthermore, in order to directly bond the Cu pads of the bump electrodes 32 and the connecting layer 43, it is necessary to form the light-receiving substrate 100 and the circuit board 200 to be extremely flat. Therefore, it is preferable that the embedded layer 36, which is positioned beneath the copper film, has hardness sufficient to withstand the stress during polishing. Specifically, it is preferable that the constituent material of the embedded layer 36 is a material with higher hardness than the encapsulant or organic material that is positioned around the die in a typical semiconductor package. Examples of materials with such high hardness include inorganic insulating materials. The embedded layer 36 can be formed by depositing this inorganic insulating material using, for example, CVD (Chemical Vapor Deposition), sputtering, or coating methods.

[0084] The embedded layer 36 is provided with holes H1 and H2 that penetrate through it. These holes H1 and H2, together with the embedded layer 36, penetrate the insulating layer 29 and reach the circuit board 200. The holes H1 and H2 have, for example, a rectangular planar shape, and multiple holes H1 and H2 are provided so as to surround the element region R1 (Figure 5). Hole H1 is located closer to the element region R1 than hole H2, and the side walls and bottom surface of hole H1 are covered with the conductive film 33. This hole H1 is for connecting the n-type semiconductor layer 24 (conductive film 33) and the wiring (wiring 46 described later) of the circuit board 200, and is provided penetrating the anti-reflective film 25, the embedded layer 36, and the insulating layer 29.

[0085] Hole H2 is located, for example, closer to the chip edge E than hole H1. This hole H2 penetrates the anti-reflective film 25, the embedding layer 36, and the insulating layer 29, and reaches the pad electrode (pad electrode 38 described later) of the circuit board 200. Electrical connection between the outside and the solid-state imaging device 1 is made through this hole H2. Holes H1 and H2 do not necessarily have to reach the circuit board 200. For example, holes H1 and H2 may reach the wiring of the insulating layer 29, and this wiring may be connected to the wiring 46 and pad electrode 38 of the circuit board 200. Holes H1 and H2 may also penetrate the adhesive layer B.

[0086] Holes and electrons generated in the n-type semiconductor film 21 are read out from the connecting electrode 31 and the n-type semiconductor layer 24. In order to perform this readout operation at high speed, it is preferable to set the distance between the connecting electrode 31 and the n-type semiconductor layer 24 to a distance sufficient for photoelectric conversion but not too far apart. That is, it is preferable to reduce the thickness of the light-receiving substrate 100. For example, the distance between the connecting electrode 31 and the n-type semiconductor layer 24 or the thickness of the light-receiving substrate 100 is 10 μm or less, more preferably 7 μm or less, and more preferably 5 μm or less.

[0087] The support substrate 41 of the circuit board 200 faces the light-receiving substrate 100 with a wiring layer 35 and an interlayer insulating layer 42 in between. This support substrate 41 is made of, for example, silicon (Si). Multiple transistors are provided near the surface of the support substrate 41 (the surface on the wiring layer 35 side). For example, a read-out circuit is configured for each pixel P using these multiple transistors. The wiring layer 35 has, for example, an interlayer insulating film 35A and an interlayer insulating film 35B in that order from the light-receiving substrate 100 side, and these interlayer insulating films 35A and 35B are provided in a laminated manner. For example, a connection layer 43 and a dummy connection layer 43D are provided in the interlayer insulating film 35A. The interlayer insulating layer 42 is provided facing the light-receiving substrate 100 with the wiring layer 35 in between. For example, a pad electrode 38 and multiple wirings 46 are provided in this interlayer insulating layer 42. The interlayer insulating films 35A and 35B are made of, for example, an inorganic insulating material. Examples of these inorganic insulating materials include silicon nitride (SiN), aluminum oxide (Al2O3), silicon dioxide (SiO2), and hafnium oxide (HfO2).

[0088] The connecting layer 43 is for electrically connecting the connecting electrode 31 and the wiring 46, and is provided in the element region R1 for each pixel P. This connecting layer 43 is in contact with the bump electrode 32 at the bonding surface S2 of the light-receiving substrate 100. Adjacent connecting layers 43 are electrically isolated by an interlayer insulating film 35A.

[0089] The dummy connection layer 43D, provided in the peripheral region R2, is in contact with the dummy electrode 32D at the bonding surface S2 of the light-receiving substrate 100. This dummy connection layer 43D is formed, for example, in the same process as the connection layer 43. The connection layer 43 and the dummy connection layer 43D are made of, for example, copper (Cu) pads and are exposed on the surface of the circuit board 200 facing the light-receiving substrate 100. That is, for example, CuCu bonding is made between the bump electrode 32 and the connection layer 43, and between the dummy electrode 32D and the dummy connection layer 43D. As will be described in detail later, this makes it possible to miniaturize the pixels P.

[0090] The wiring 46 connected to the bump electrode 32 is connected to a transistor provided near the surface of the support substrate 41, so that the connection electrode 31 and the readout circuit are connected for each pixel P. The wiring 46 connected to the conductive film 33 via the hole H1 is connected to, for example, a predetermined potential. In this way, one side of the charge generated in the n-type semiconductor film 21 (for example, a hole) is read out from the connection electrode 31 to the readout circuit via the bump electrode 32 and the connection layer 43, and the other side of the charge generated in the n-type semiconductor film 21 (for example, an electron) is discharged from the n-type semiconductor layer 24 to a predetermined potential via the conductive film 33.

[0091] The pad electrode 38 provided in the peripheral region R2 is for making an electrical connection to the outside. Near the chip end E of the solid-state imaging device 1, a hole H2 is provided that penetrates the light-receiving substrate 100 and reaches the pad electrode 38, and an electrical connection to the outside is made through this hole H2. The connection is made by methods such as wire bonding or bump bonding. For example, a predetermined potential may be supplied from an external terminal located in the hole H2 to the n-type semiconductor layer 24 via the wiring 46 and conductive film 33 of the hole H2. As a result of photoelectric conversion in the n-type semiconductor film 21, the signal voltage read from the connection electrode 31 may be read to a readout circuit on the support substrate 41 via the bump electrode 32 and the connection layer 43, and output to an external terminal located in the hole H2 via this readout circuit. The signal voltage may be output to the external terminal via the readout circuit and other circuits included in the circuit board 200, for example. Other circuits include signal processing circuits and output circuits.

[0092] The thickness of the circuit board 200 is preferably greater than the thickness of the light-receiving substrate 100. For example, the thickness of the circuit board 200 is preferably twice, more preferably five times, more preferably ten times, greater than the thickness of the light-receiving substrate 100. Alternatively, the thickness of the circuit board 200 may be, for example, 100 μm or more, 150 μm or more, or 200 μm or more. The mechanical strength of the solid-state imaging device 1 is ensured by the circuit board 200 having such a relatively large thickness. Note that the circuit board 200 may include only one layer of support substrate 41 for forming the circuit, or it may further include substrates such as support substrates in addition to the support substrate 41 for forming the circuit.

[0093] 2.4 Joint structure example Next, an example of the bonding structure of the solid-state imaging device 1 will be described. Figure 7 is a cross-sectional view showing an example of the bonding structure of the first embodiment. In Figure 7, each sensor pixel 11 in the pixel array section 10 is divided into normal pixels 11a or charge-emitting pixels 11b depending on the control of the reset transistor RST. However, since the pixel structure is the same for both normal pixels 11a and charge-emitting pixels 11b, they will simply be described as sensor pixels 11. Note that the charge-emitting pixels 11b are located on the outermost side of the pixel array section 10.

[0094] The pixel signal generation circuit 45 for each sensor pixel 11, consisting of a transfer transistor TRG, an emission transistor OFG, a floating diffusion transistor FD, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL, is formed for each pixel on a circuit board 200 made of a single-crystal material such as single-crystal silicon (Si). Note that in Figure 7, the symbols of the transfer transistor TRG, emission transistor OFG, floating diffusion transistor FD, reset transistor RST, amplification transistor AMP, and selection transistor SEL formed on the circuit board 200 are omitted.

[0095] On the upper side of the circuit board 200, which is the light incident side, an n-type semiconductor film 21, which will serve as a photodiode PD, is formed over the entire surface of the pixel array portion 10. The n-type semiconductor film 21 can be InGaP, InAlP, InGaAs, InAlAs, or a compound semiconductor with a chalcopyrite structure. Compound semiconductors with a chalcopyrite structure are materials that can obtain a high light absorption coefficient and high sensitivity over a wide wavelength range, and are therefore preferably used as n-type semiconductor films 21 for photoelectric conversion. Such compound semiconductors with a chalcopyrite structure are composed of elements surrounding group IV elements such as Cu, Al, Ga, In, S, and Se, and examples include CuGaInS mixed crystals, CuAlGaInS mixed crystals, and CuAlGaInSSe mixed crystals.

[0096] Furthermore, in addition to the compound semiconductors mentioned above, amorphous silicon (Si), germanium (Ge), quantum dot photoelectric conversion films, organic photoelectric conversion films, and other materials can also be used for the n-type semiconductor film 21.

[0097] In this embodiment, an InGaAs compound semiconductor is used as the n-type semiconductor film 21.

[0098] On the lower side of the n-type semiconductor film 21, which faces the circuit substrate 200, high-density p-type semiconductor layers 22 constituting the pixel electrodes are formed for each pixel. Between the high-density p-type semiconductor layers 22 formed for each pixel, n-type semiconductor layers 23 are formed, for example, of a compound semiconductor such as InP, to serve as pixel isolation regions that separate each sensor pixel 11. In addition to functioning as a pixel isolation region, these n-type semiconductor layers 23 also have the role of preventing dark current.

[0099] On the other hand, on the upper side of the n-type semiconductor film 21, which is the light incident side, a higher-density n-type semiconductor layer 24 is formed using a compound semiconductor such as InP, which is used as a pixel separation region. This high-density n-type semiconductor layer 24 functions as a barrier layer to prevent the backflow of charge generated in the n-type semiconductor film 21. For the material of the high-density n-type semiconductor layer 24, compound semiconductors such as InGaAs, InP, and InAlAs can be used, for example.

[0100] An anti-reflective film 25 is formed on the high-concentration n-type semiconductor layer 24, which acts as a barrier layer. For example, silicon nitride (SiN), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), tantalum oxide (Ta2Ta5), titanium oxide (TiO2), etc., can be used as the material for the anti-reflective film 25.

[0101] Either the high-concentration n-type semiconductor layer 24 or the anti-reflective film 25 functions as the upper electrode of the electrodes that sandwich the n-type semiconductor film 21 from above and below, and a predetermined voltage Va is applied to the high-concentration n-type semiconductor layer 24 or the anti-reflective film 25 as the upper electrode.

[0102] A color filter 26 and an on-chip lens 27 are further formed on the anti-reflective coating 25. The color filter 26 is a filter that transmits light (wavelength light) of either R (red), G (green), or B (blue), and is arranged in a so-called Bayer array in the pixel array section 10, for example.

[0103] A passivation layer 28 and an insulating layer 29 are formed beneath the high-density p-type semiconductor layer 22 that constitutes the pixel electrode and the n-type semiconductor layer 23 that serves as the pixel isolation region. The connecting electrode 31 and connecting layer 43 and the bump electrode 32 are formed to penetrate the passivation layer 28 and the insulating layer 29. The connecting electrode 31 and connecting layer 43 and the bump electrode 32 electrically connect the high-density p-type semiconductor layer 22 that constitutes the pixel electrode and the floating diffusion FD that accumulates charge.

[0104] The normal pixels 11a and the charge-emitting pixels 11b are configured as described above and have the same pixel structure.

[0105] However, the control method of the reset transistor RST differs between the normal pixel 11a and the charge-emitting pixel 11b.

[0106] In a normal pixel 11a, the reset transistor RST is switched on and off based on the reset signal RST, depending on the charge generation period (light reception period) by the photodiode PD and the reset period of the floating diffusion FD potential before the start of light reception. However, in a charge emission pixel 11b, the reset transistor RST is always controlled to be ON. As a result, the charge generated by the photodiode PD is discharged to ground, and a constant voltage Va is always applied to the charge emission pixel 11b.

[0107] 2.5 Packaging of Solid State Imaging Devices Next, the packaging of the solid-state imaging device 1 described above will be explained. Figure 8 is a plan view showing an example of the configuration of the sensor package (also called the imaging device) according to the first embodiment. Figure 9 is a cross-sectional view showing an example of the configuration of the sensor package according to the first embodiment. Note that Figure 9 shows a cross-section obtained by cutting Figure 8 through the XZ plane passing through the BB line.

[0108] As shown in Figures 8 and 9, the sensor package 1100 comprises a package 50 and a lid 60 with a sealing glass (an example of a lid) attached to the upper surface 50a of the package 50. The package 50 comprises a package substrate 70, a Peltier element 80, a ceramic interposer substrate 90 (also called a support substrate), and a solid-state imaging device 1. First, the configuration of the package 50 will be described.

[0109] Figure 10 is an exploded cross-sectional view showing an example of the configuration of a sensor package according to the first embodiment. The package substrate 70 is a multilayer substrate made of ceramic such as alumina (aluminum oxide), and is, for example, a PGA (Pin Grid Array) substrate. As shown in Figure 10, the package substrate 70 has a first surface (for example, an upper surface 70a) and a second surface (for example, a lower surface 70b) located on the opposite side of the first surface. Multiple wirings are arranged in multiple layers inside the package substrate 70 located between the upper surface 70a and the lower surface 70b. These wirings are connected to multiple terminals (for example, pin-shaped terminals 73) provided on the lower surface 70b of the package substrate 70.

[0110] Figure 11 is a plan view showing an example of the configuration of the upper surface of a package substrate according to the first embodiment. As shown in Figures 10 and 11, a cavity 71 is provided on the upper surface 70a of the package substrate 70. The cavity 71 has a first recess 111 and a second recess 112 (an example of a recess) provided on the bottom surface 111a of the first recess 111. The shape of the first recess 111 and the second recess 112 in plan view is, for example, rectangular. The diameter of the opening surface of the first recess 111 is larger than that of the second recess 112.

[0111] A Peltier element 80, which serves as a temperature control element, is placed in the second recess 112. For example, the Peltier element 80 is attached to the bottom surface 112a of the second recess 112 via an adhesive 51 (see Figure 9). The upper surface of the Peltier element 80 placed in the second recess 112 (for example, the upper surface 85a of the second ceramic substrate 85, which will be described later) is at the same height as, or approximately the same height as, the bottom surface 111a of the first recess 111.

[0112] The bottom surface 112a of the second recess 112 is provided with pin-shaped terminals 72 for connecting to the lead wires of the Peltier element 80. There are two pin-shaped terminals 72. Of the two pin-shaped terminals 72, one is connected to the positive lead wire of the Peltier element 80, and the other is connected to the negative lead wire of the Peltier element 80.

[0113] Furthermore, the external connection terminals can be replaced with ball terminals or land terminals instead of the pin-shaped terminals 73.

[0114] As shown in Figures 9 to 11, a seal ring 75 is provided on the upper surface 70a side of the outer periphery of the package substrate 70. In plan view, the seal ring 75 is continuously provided so as to surround the cavity 71 of the package substrate 70. The seal ring 75 is the part that is joined to the metal part 63 of the lid 60 with seal glass, which will be described later. The seal ring 75 is, for example, an iron (Fe)-nickel (Ni)-cobalt (Co) alloy (so-called Kovar) and has been surface-treated by plating with Ni and gold (Au), etc.

[0115] Figure 12 is a plan view illustrating the positional relationship between the package substrate and the ceramic interposer substrate according to the first embodiment. As shown in Figure 9, the ceramic interposer substrate 90 is attached to the bottom surface 111a of the first recess 111 and the Peltier element 80 via adhesive 51 on its lower surface 90b side. As shown in Figures 9 and 12, the ceramic interposer substrate 90 is positioned to completely cover the opening surface of the second recess 112.

[0116] Multiple bonding pads 74 are provided on the bottom surface 111a of the first recess 111, in the region exposed from below the ceramic interposer substrate 90. Multiple bonding pads 91 are also provided on the lower surface 90b of the ceramic interposer substrate 90. At least some of the multiple bonding pads 91 are connected to the bonding pads 74 via wires 54. At least some of the multiple bonding pads 91 are also connected to a bonding pad 92, which is an external terminal of the solid-state imaging device 1, via wires 55. Alternatively, both wires 54 and 55 may be connected to a single bonding pad 91. The wires 54 and 55 are, for example, gold wires.

[0117] A bonding pad 92 is provided on the outer peripheral region of the upper surface 93a side of the solid-state imaging device 1. The lower surface 93b side of the solid-state imaging device 1 is attached to the lower surface 90b side of the ceramic interposer substrate 90 via adhesive 51.

[0118] Figure 13 is a cross-sectional view showing an example of the configuration of a Peltier element according to the first embodiment. As shown in Figure 13, the Peltier element 80 includes a first ceramic substrate 81, a first copper electrode 82 provided on the first ceramic substrate 81, a second ceramic substrate 85 facing the first ceramic substrate 81, a second copper electrode 86 provided on the second ceramic substrate 85, a P-type thermoelectric semiconductor 87, and an N-type thermoelectric semiconductor 88. The P-type thermoelectric semiconductor 87 and the N-type thermoelectric semiconductor 88 are respectively arranged between the first ceramic substrate 81 and the second ceramic substrate 85. One end of the P-type thermoelectric semiconductor 87 and the N-type thermoelectric semiconductor 88 are connected to the first copper electrode 82, and the other end is connected to the second copper electrode 86. The P-type thermoelectric semiconductor 87 and the N-type thermoelectric semiconductor 88 are alternately connected in series via the first copper electrode 82 and the second copper electrode 86.

[0119] As shown in Figure 13, when a DC current is passed through the N-type thermoelectric semiconductor 88 of the Peltier element 80, the second ceramic substrate 85 absorbs heat T1, and the first ceramic substrate 81 releases heat T2. Since the second ceramic substrate 85 is attached to the ceramic interposer substrate 90 via adhesive 51, and the first ceramic substrate 81 is attached to the package substrate 70 via adhesive 51, the Peltier element 80 can dissipate heat generated by the solid-state imaging device 1, etc., from the ceramic interposer substrate 90 to the package substrate 70. In other words, the cooling function can be controlled by changing the amount of current flowing through the Peltier element.

[0120] Next, the configuration of package 50 will be described. As shown in Figures 8 to 10, the lid 60 with sealing glass has a sealing glass 61, a ceramic frame 62 provided on the lower surface 61b side of the outer periphery of the sealing glass 61, and a metal part 63 provided on the lower surface 62b side of the ceramic frame 62. The sealing glass 61 and the ceramic frame 62 are joined to each other with, for example, low-melting-point glass. The ceramic frame 62 and the metal part 63 are joined to each other with, for example, Ag-Cu brazing material.

[0121] The metal part 63 is a portion that is joined to the seal ring 75 of the package substrate 70 by means of seam welding, for example. The metal part 63 is made of the same material as the seal ring 75, for example, an iron (Fe)-nickel (Ni)-cobalt (Co) alloy (so-called Kovar) with a surface treatment by plating with Ni and gold (Au). The lid 60 with seal glass is joined to the upper surface 50a side of the package 50, and hermetically seals the upper surface 50a side of the package 50.

[0122] 2.6 Temperature Control Mechanism In a solid-state imaging device 1 that uses a photoelectric conversion material with a smaller bandgap energy than silicon, in other words, a material sensitive to light with wavelengths of approximately 1200 nm or more, as described above, it is necessary to provide a mechanism (temperature control mechanism) to cool the sensor chip or maintain it at a constant temperature in order to suppress the generation of dark current, which is noise.

[0123] However, in a configuration where a discrete thermistor element is attached to the solid-state imaging device 1, and a driver circuit located outside the package receives a temperature control signal generated based on the output from the thermistor element and controls the Peltier element based on the temperature control signal, there are challenges in terms of the accuracy of the measured sensor chip temperature, the robustness of the measured temperature, limitations on the number of terminals, and yield, as described above.

[0124] Therefore, in this embodiment, a thermometer circuit is placed inside the solid-state imaging device 1, and the driver circuit is configured to control the Peltier element in the package based on the output from this thermometer circuit. The driver circuit converts the input control signal into a current that is input to the Peltier element. This makes it possible to obtain advantages in terms of the accuracy of the measured sensor chip temperature, the robustness of the measured temperature, limitations on the number of terminals, and yield.

[0125] 2.7 Location of the temperature sensor (thermometer circuit) As shown in Figure 9, the thermometer circuit 120, which serves as a temperature sensor according to this embodiment, is fabricated, for example, on the circuit board 200 of the solid-state imaging device 1.

[0126] As shown in Figure 9, an AD conversion circuit 121 that converts the analog current or voltage value output from the thermometer circuit 120 into a digital value may be provided within the circuit board 200, and the system may be configured to output the digital value output from this AD conversion circuit 121. In this case, the ADC 40a within the horizontal selection circuit 40 may be used for the AD conversion circuit 121, or a dedicated ADC built into the circuit board 200 separately from the ADC 40a may be used.

[0127] Furthermore, the thermometer circuit 120 is not limited to the circuit board 200, but may be provided on the light-receiving board 100 side, for example.

[0128] 2.8 Example of a schematic configuration of an imaging system Next, we will describe, with some examples, an imaging system equipped with a temperature control mechanism according to this embodiment.

[0129] 2.8.1 Example of System Configuration 1 Figure 14 is a block diagram showing a schematic configuration example of an imaging system according to the first system configuration example of the first embodiment.

[0130] As shown in Figure 14, the imaging system 1000 according to the first system configuration example comprises a sensor package 1100 and a driver circuit 1300. The sensor package 1100 includes a solid-state imaging device 1 and a temperature control element 1400. Furthermore, as described above, the sensor package 1100 has a structure in which the solid-state imaging device 1 is housed in a cavity 71 formed by the package 50 and the lid 60 with sealing glass.

[0131] The temperature control element 1400 can utilize various temperature control devices, such as a cooling element like a Peltier element bonded to the outer surface of the sensor package 1100, a heat sink, an air cooler, or a water cooler. Furthermore, the temperature control element 1400 is positioned so as to overlap with at least a portion of the solid-state imaging device 1 in a plan view.

[0132] The solid-state imaging device 1 includes a pixel array section 10 containing sensor pixels 11, pixel drive lines 12, vertical signal lines 13, a system control circuit 16, a vertical drive circuit 20, a horizontal drive circuit 30, a thermometer circuit 120, and a register circuit 2000.

[0133] Since the thermometer circuit 120 is located within the solid-state imaging device 1, it is possible to directly measure the temperature of the solid-state imaging device 1 itself. This improves the accuracy of temperature measurement of the sensor chip. Furthermore, for example, since the analog value output from the thermometer circuit 120 is converted to a digital value by the AD conversion circuit 121 within the solid-state imaging device 1, it is possible to reduce the influence of noise on the measurement result detected by the thermometer circuit 120. This improves the robustness of the measured temperature.

[0134] The main heat-generating components are the horizontal drive circuit 30 and the system control circuit 16 on the circuit board 200. Therefore, as shown in Figure 14, the thermometer circuit 120 is placed near the main heat-generating components, such as the horizontal drive circuit 30 and the system control circuit 16.

[0135] Furthermore, the thermometer circuit 120 may be placed near the light-receiving substrate 100, which is intended for temperature control. However, if the thermometer circuit 120 includes a light-emitting element, superimposing the thermometer circuit 120 and the light-receiving substrate 100 may impair the uniformity of the sensitivity of the pixel array due to the light from the thermometer circuit 120. Therefore, the thermometer circuit 120 may be placed near the light-receiving substrate 100, but in an area that does not overlap with the light-receiving substrate 100.

[0136] Furthermore, the thermometer circuit 120 is preferably positioned in the substrate thickness direction of the solid-state imaging device 1 so as to overlap with the temperature control element 1400. This makes it possible to quickly detect the temperature controlled by the temperature control element 1400, thereby enabling more accurate temperature control.

[0137] Furthermore, the number of thermometer circuits 120 to be placed is not limited to one, but may be multiple. By distributing multiple thermometer circuits 120, the temperature of the solid-state imaging device 1 can be measured more accurately. If a material with high thermal conductivity, such as a silicon substrate, is used for the circuit board 200, sufficient measurement accuracy can be obtained even with a single thermometer circuit 120.

[0138] When multiple thermometer circuits 120 are arranged in a distributed manner, by arranging the multiple thermometer circuits 120 so as to surround the light-receiving substrate 100, it becomes possible to measure the temperature distribution of the light-receiving substrate 100, thereby enabling more accurate temperature control of the solid-state imaging device 1.

[0139] The system control circuit 16 acquires a temperature signal 3000 containing temperature data (temperature information) from the thermometer circuit 120 and outputs a temperature control signal 3200 generated based on the acquired temperature information to the driver circuit 1300. Alternatively, the temperature signal 3000 acquired by the system control circuit 16 may be a signal obtained by AD conversion of the signal output from the thermometer circuit 120 by the AD conversion circuit 121.

[0140] The system control circuit 16 may acquire temperature information registered in a register (not shown) from the thermometer circuit 120. In this case, the system control circuit 16 may access the register periodically (for example, 30 times / second) or as needed to acquire the temperature information registered in the register.

[0141] The driver circuit 1300 generates a temperature control element control signal 3300 based on the temperature control signal 3200 supplied from the system control circuit 16 and outputs it to the temperature control element 1400.

[0142] Generally, the power supply voltage that operates the driver circuit is higher than the power supply voltage that operates the internal circuitry of the sensor (solid-state imaging device). Therefore, the amount of heat generated by the driver circuit is greater than the amount of heat generated by the internal circuitry of the sensor (solid-state imaging device).

[0143] The driver circuit 1300 is located outside the sensor package 1100. This reduces the overall heat generated by the system and increases the voltage withstand margin of the sensor package.

[0144] The temperature control element 1400 performs temperature control based on the temperature control element control signal 3300 supplied from the driver circuit 1300. If the temperature control element 1400 is a Peltier element, temperature control is performed by adjusting the amount of current flowing through the Peltier element based on the temperature control element control signal 3300.

[0145] The register circuit 2000 stores information corresponding to the settings received from an external source. Information representing the settings is supplied to the system control circuit 16 as a register signal 3100. The system control circuit 16 may also generate a temperature control signal 3200 based on the register signal 3100.

[0146] 2.8.1.1 Temperature control signal Figure 15 is a diagram illustrating the temperature control signal. The temperature control signal is a PWM (pulse width modulation) signal in which the duty cycle of a constant-period oscillation signal is adjusted. If the period is denoted by time width T and the period during which the voltage is at a high level is denoted by time width H, the duty cycle is defined as shown in the equation in Figure 15. In other words, the duty cycle is adjusted by changing the time width H of the period during which the voltage is at a high level.

[0147] Such a signal is output from the system control circuit 16 in Figure 14 to the driver circuit 1300 as a temperature control signal 3200, and is used to control the temperature control element 1400. For example, the longer the period of high level and the larger the duty cycle, the greater the amount of heat absorbed by the temperature control element 1400.

[0148] 2.8.1.2 System Control Circuit Figure 16 is a block diagram showing an example of a system control circuit according to the first system configuration example of the first embodiment. As shown in Figure 16, the system control circuit 16 according to the first system configuration example of the first embodiment includes a temperature control signal generation circuit 2100 and a sensor state transition circuit 2200.

[0149] The temperature control signal generation circuit 2100 acquires a temperature signal 3000 containing temperature data (temperature information) from the thermometer circuit 120, and outputs a temperature control signal 3200 generated based on the acquired temperature information to the driver circuit 1300. By incorporating the temperature control signal generation circuit 2100 into the solid-state imaging device 1, the operation from acquiring temperature information to generating a temperature control signal (hereinafter referred to as temperature update) can be performed independently of the frame rate.

[0150] Furthermore, by incorporating multiple circuits necessary for temperature updates into the same solid-state imaging device 1, communication required for temperature control of the temperature control element can be accelerated. The temperature control signal generation circuit 2100 may be located within the solid-state imaging device 1 but outside the system control circuit 16, or it may be incorporated into the system control circuit 16 as shown in Figure 16. By incorporating the temperature control signal generation circuit 2100 into the system control circuit 16, an increase in circuit area can be suppressed.

[0151] The temperature control signal generation circuit 2100 may, as needed, access a register (not shown) in which temperature information periodically acquired from the thermometer circuit 120 is recorded, and acquire the temperature information. Alternatively, the recording of temperature information in the register may be performed in response to a request from the temperature control signal generation circuit 2100. In this case, the temperature control signal generation circuit 2100 accesses the register in which the temperature information is recorded and acquires the temperature information.

[0152] Furthermore, the temperature control signal generation circuit 2100 may acquire a sensor status signal 3110 containing sensor status information from the sensor status transition circuit 2200, and acquire temperature information from the thermometer circuit 120 based on the sensor status information. The sensor status information is information indicating the operating status of the sensor, such as the sensor readout state or the sensor readout pause state.

[0153] The sensor state transition circuit 2200 generates a sensor state signal 3110 based on a signal from the vertical drive circuit 20. The vertical drive circuit 20 is connected to the sensor state transition circuit 2200.

[0154] Furthermore, the sensor state transition circuit 2200 transitions the state of the sensor pixel 11 by switching the operation of the vertical drive circuit 20. Transitioning the state of the sensor pixel 11 means, for example, changing the current flowing through the pixel drive line 12 to transition from the sensor readout state to the sensor readout pause state. The sensor readout state is, for example, a state in which a voltage signal corresponding to the amount of light received at the sensor pixel 11 is read out via the vertical signal line 13.

[0155] The temperature control signal generation circuit 2100 includes a temperature information comparison circuit 2110, a temperature control mode selection circuit 2120, and a duty cycle adjustment circuit 2130. The temperature signal 3000 acquired from the thermometer circuit 120 is input to the temperature information comparison circuit 2110, and the register signal 3100 output from the register circuit 2000 is input to the temperature information comparison circuit 2110 and the temperature control mode selection circuit 2120.

[0156] The temperature information comparison circuit 2110 compares the target temperature with the temperature detected by the thermometer circuit 120 based on the temperature signal 3000, and generates a difference signal 3010 according to the comparison result. The difference signal 3010 includes, for example, information indicating the difference between the target temperature and the temperature detected by the thermometer circuit 120. This makes it possible to control the temperature detected by the thermometer circuit 120 so that it reaches an intended temperature, for example, a temperature at which the influence of the dark current described above is small.

[0157] The target temperature may be pre-set or set externally. The temperature information comparison circuit 2110 may perform a comparison based on the register signal 3100 containing information about the target temperature. This makes it possible to optimize the target temperature according to the operating environment of the solid-state imaging device 1.

[0158] The temperature control mode selection circuit 2120 acquires a sensor status signal 3110 from the sensor status transition circuit 2200 and a register signal 3100 from the register circuit 2000. Based on the sensor status signal 3110 and the register signal 3100, the temperature control mode selection circuit 2120 generates a mode selection signal 3130 and outputs it to the duty cycle adjustment circuit 2130. The mode selection signal 3130 includes information indicating the sensor operating state.

[0159] Furthermore, the temperature control mode selection circuit 2120 outputs a read control signal 3120, generated based on the sensor state, to the sensor state transition circuit 2200. The read control signal 3120 is, for example, an interrupt signal that changes the operating state of the sensor. The register signal 3100 that the temperature control mode selection circuit 2120 obtains from the register circuit 2000 may include information indicating the interval when temperature updates are performed continuously at regular intervals, and information indicating the start / end of the temperature control process.

[0160] The duty cycle adjustment circuit 2130 generates a temperature control signal 3200 by adjusting the duty cycle of the oscillation signal based on the difference signal 3010 from the temperature information comparison circuit 2110. More specifically, the duty cycle adjustment circuit 2130 generates the temperature control signal 3200 such that the duty cycle increases as the difference between the target temperature and the temperature detected by the thermometer circuit 120 increases. PWM control enables more power-efficient temperature control.

[0161] Furthermore, the duty cycle adjustment circuit 2130 may generate a temperature control signal 3200 in accordance with the mode selection signal 3130 obtained from the temperature control mode selection circuit 2120. The mode selection signal 3130 is a signal that indicates which of a plurality of modes is selected, including a mode in which the temperature is updated during a period when the sensor readout is paused (hereinafter referred to as the sensor readout pause period) and a mode in which the temperature is updated during a period when the sensor is readout (hereinafter referred to as the sensor readout period).

[0162] 2.8.1.3 First example of timing for acquiring temperature information Here, we will explain the timing of temperature updates in the system control circuit 16.

[0163] Figure 17A is a timing chart showing the first example of the timing for acquiring temperature information. The horizontal axis of Figure 17A represents time. The same applies to other timing charts described later. Figure 17A shows XVS and Temp Info.

[0164] XVS (Vertical Synchronization Signal) is a signal input to the system control circuit 16 from an external source, and it is a signal that remains at a high level for a predetermined period of time. The period from when XVS becomes high once until it becomes high again is the time required to process one frame (hereinafter referred to as the frame processing time). In Figure 17A, XVS becomes high once immediately after time t0, and then becomes high again immediately after time t3, and the time between these two points is the frame processing time.

[0165] The predetermined time from the moment XVS reaches a high level is the exposure time for the first row (the pixels of the first row) of the pixel array 10. After the predetermined time has elapsed, the exposure of the first row is completed, and the pixel signal based on the charge accumulated during exposure is read out. Subsequently, exposure and readout of each row of the pixel array 10 are performed in the forward direction at regular time intervals. In other words, the predetermined time from the moment XVS reaches a high level, which is the exposure time for the pixels of the first row, is a sensor readout pause period during which no pixel signals are read out.

[0166] Temp Info is temperature information acquired by the temperature control signal generation circuit 2100 from the thermometer circuit 120. Each time temperature information is acquired from the thermometer circuit 120, it is registered in a register (not shown) accessible by the temperature control signal generation circuit 2100. At the temperature update timing, for example, time t3, the temperature information registered in the register (not shown) is updated.

[0167] As shown in Figure 17A, for example, at time t0, the temperature control signal generation circuit 2100 acquires temperature information that the temperature detected by the thermometer circuit 120 (hereinafter referred to as the detected temperature) is 50°C, and generates a temperature control signal 3200 based on that temperature information. Next, at time t3, the temperature control signal generation circuit 2100 acquires temperature information that the detected temperature is 40°C, and generates a temperature control signal 3200 based on that temperature information.

[0168] In this way, temperature updates are performed continuously at a constant cycle. This enables temperature control that more accurately reflects the temperature of the solid-state imaging device 1.

[0169] Here, the temperature update interval (period) in Figure 17A is the same as the processing time for one frame. In other words, the reciprocal of the temperature update period is the same as the frame rate.

[0170] Let's explain Figure 17A in more detail. For example, suppose the target temperature is 20°C. During the period from time t0 to time t3, the temperature information comparison circuit 2110 generates a difference signal 3010 that indicates the difference of 30°C between the target temperature of 20°C and the detected temperature of 50°C. Based on the difference signal 3010, the duty cycle adjustment circuit 2130 generates a temperature control signal 3200 for the duty cycle corresponding to the difference of 30°C.

[0171] During the period from time t3 to time t6, the temperature information comparison circuit 2110 generates a difference signal 3010 that indicates the difference of 20°C between the target temperature of 20°C and the detected temperature of 40°C. Based on the difference signal 3010, the duty cycle adjustment circuit 2130 generates a temperature control signal 3200 for the duty cycle corresponding to the difference of 20°C.

[0172] Therefore, time t3 is the timing when the temperature control signal 3200 supplied to the driver circuit 1300 changes from a temperature control signal whose duty cycle is adjusted according to a difference of 30°C to a temperature control signal whose duty cycle is adjusted according to a difference of 20°C.

[0173] If the temperature control element 1400 is a Peltier element, the driver circuit 1300 adjusts the value of the current flowing through the Peltier element in accordance with the temperature control signal 3200. Therefore, at time t3, the value of the current flowing through the Peltier element, which is the temperature control element 1400, fluctuates in accordance with the change in the temperature control signal 3200. Here, the timing of the change in the value of the current flowing through the Peltier element and the timing of the change in the temperature control signal 3200 are considered to be approximately the same timing as the temperature update.

[0174] As described above, the period from the time when XVS reaches a high level to a predetermined time is the sensor readout pause period. In other words, the timing when the temperature control signal 3200 changes significantly is during the sensor readout pause period, not during the sensor readout period. This reduces the influence of magnetic field noise on the output image of the solid-state imaging device 1.

[0175] Figure 17B is a diagram illustrating the first example of the timing for acquiring temperature information. The vertical axis represents the temperature detected by the thermometer circuit 120, and the horizontal axis represents time. As the temperature is updated at the timings described above, the temperature detected by the thermometer circuit 120 decreases by 10°C at each of the times t3, t6, and t9, as shown in Figure 17B, until it reaches the target temperature of 20°C.

[0176] 2.8.1.4 Second example of the timing for acquiring temperature information Figure 18A is a timing chart showing a second example of the timing for acquiring temperature information. Figure 18A shows XVS and Temp Info.

[0177] In Figure 18A, XVS goes to a high level once immediately after time t0, and then goes to a high level again immediately after time t3. The time between these two points is the processing time for one frame. The time from time t0 to time t3 in Figure 18A is the same as, for example, the time from time t0 to time t3 in Figure 17A.

[0178] As shown in Figure 18A, for example, at time t0, the temperature control signal generation circuit 2100 acquires temperature information that the detected temperature is 50°C and generates a temperature control signal 3200 based on the temperature information. Next, at time t1, the temperature control signal generation circuit 2100 acquires temperature information that the detected temperature is 47°C and generates a temperature control signal 3200 based on the temperature information.

[0179] The temperature update cycle is shorter than the processing time of one frame. In other words, the reciprocal of the temperature update cycle is greater than the frame rate. In example A of Figure 18, the temperature is updated three times within the processing time of one frame.

[0180] Let's explain Figure 18A in more detail. For example, let's assume the target temperature is 20°C.

[0181] During the period from time t0 to time t1, the temperature information comparison circuit 2110 generates a difference signal 3010 indicating the difference of 30°C between the target temperature of 20°C and the detected temperature of 50°C. Based on the difference signal 3010, the duty cycle adjustment circuit 2130 generates a temperature control signal 3200 for the duty cycle corresponding to the 30°C difference.

[0182] During the period from time t1 to time t2, the temperature information comparison circuit 2110 generates a difference signal 3010 indicating the difference of 27°C between the target temperature of 20°C and the detected temperature of 47°C. Based on the difference signal 3010, the duty cycle adjustment circuit 2130 generates a temperature control signal 3200 for the duty cycle corresponding to the difference of 27°C.

[0183] Therefore, time t1 is the timing when the temperature control signal 3200 supplied to the driver circuit 1300 changes from a temperature control signal whose duty cycle is adjusted according to a difference of 30°C to a temperature control signal whose duty cycle is adjusted according to a difference of 27°C. Also, at time t1, the current value flowing through the Peltier element, which is the temperature control element 1400, changes in accordance with the change in the temperature control signal 3200.

[0184] As described above, the amount of change in the current value flowing through the Peltier element at the temperature update timing of A in Figure 18 (for example, time t1) is smaller than the amount of change in the current value flowing through the Peltier element at the temperature update timing of A in Figure 17 (for example, time t3).

[0185] When the current flowing through a Peltier element fluctuates, the larger the difference between the value before and after the fluctuation, the greater the influence of band noise generated by the current fluctuation. Therefore, as the temperature update period shortens, the above difference becomes smaller, and thus the influence of band noise decreases.

[0186] Figure 18B illustrates a second example of the timing for acquiring temperature information. As the temperature is updated at the timings described above, the temperature detected by the thermometer circuit 120 decreases by 3°C at each of the times t1 to t9, as shown in Figure 18B, until it reaches the target temperature of 20°C.

[0187] 2.8.1.5 Temperature control signal output from the duty cycle adjustment circuit Figure 19 is a diagram illustrating the temperature control signal output from the duty cycle adjustment circuit.

[0188] The PWM-P (first PWM signal) and PWM-N (second PWM signal) shown in Figure 19 are signals with adjusted duty cycles of an oscillating signal having a repetition frequency. The duty cycle resolution refers to the smallest pulse width that can be changed within one period to adjust the duty cycle.

[0189] The temperature control signal 3200 output from the duty cycle adjustment circuit 2130 may consist of a first PWM signal and a second PWM signal.

[0190] The first PWM signal is supplied to the gate of a PMOS transistor included in the half-bridge circuit within the driver circuit 1300. The second PWM signal is supplied to the gate of an NMOS transistor included in the half-bridge circuit within the driver circuit 1300. In this case, the first and second PWM signals may be supplied to each transistor via a boost converter or the like.

[0191] The deadband is the interval between the rising (or falling) edge timing of the ON pulse of the first PWM signal and the rising (or falling) edge timing of the ON pulse of the second PWM signal.

[0192] The first and second PWM signals are generated such that the rising edge timing of the ON pulse of the first PWM signal does not overlap with the rising edge timing of the ON pulse of the second PWM signal. The deadband in this case is, for example, 25 nsec.

[0193] This prevents the PMOS and NMOS transistors in the half-bridge circuit from turning ON at the same time, thus avoiding a short circuit where current flows directly from the power supply to ground.

[0194] 2.8.1.6 Example of a driver circuit Figure 20 shows an example of a driver circuit configuration.

[0195] The driver circuit 1300 includes a level shifter circuit 1310, a half-bridge circuit 1320, and a low-pass filter circuit 1330.

[0196] The level shifter circuit 1310 boosts the voltage levels of the first PWM signal and the second PWM signal supplied from the temperature control signal generation circuit 2100 to a voltage level that can be handled by the driver circuit 1300 (for example, 5V), and outputs the boosted signal to the half-bridge circuit 1320.

[0197] The half-bridge circuit 1320 outputs a signal to the low-pass filter circuit 1330 that corresponds to the voltage level of the signal supplied from the level shifter circuit 1310. The half-bridge circuit 1320 includes a PMOS transistor and an NMOS transistor.

[0198] The low-pass filter circuit 1330 performs D / A conversion on the signal supplied from the half-bridge circuit 1320, and outputs the D / A converted signal as a temperature control element control signal 3300 to the terminals of the temperature control element 1400.

[0199] 2.8.1.7 Flow of Temperature Control Process 1 Figure 21 is a diagram illustrating the temperature control process 1.

[0200] In step S301, the temperature information comparison circuit 2110 acquires temperature information from the thermometer circuit 120. The temperature information comparison circuit 2110 compares the detected temperature indicated by the temperature information with the target temperature and outputs a difference signal corresponding to the difference to the duty cycle adjustment circuit 2130.

[0201] In step S302, the duty cycle adjustment circuit 2130 generates a temperature control signal 3200 with an adjusted duty cycle based on the difference between the detected temperature and the target temperature, and outputs it to the temperature control element 1400. The temperature control element 1400 cools the solid-state imaging device 1 based on the temperature control signal 3200 supplied from the duty cycle adjustment circuit 2130.

[0202] For example, temperature control process 1 starts when a temperature control process 1 start signal is supplied from the register circuit 2000 to the temperature control signal generation circuit 2100, and ends when a temperature control process 1 end signal is supplied.

[0203] 2.8.1.8 Flowchart of Continuous Temperature Control Process Figure 22 is a diagram illustrating the continuous control process. The continuous control process is a process that continuously performs the temperature control process as described with reference to Figure 21.

[0204] As shown in Figure 22, first, in step S401, the temperature control signal generation circuit 2100 performs temperature control processing. The processing performed as temperature control processing can be any of the following: temperature control processing 1 (Figure 21), temperature control processing 2 (Figure 24), which will be described later, or temperature control processing 3 (Figure 26), which will be described later.

[0205] Next, in step S402, the temperature control mode selection circuit 2120 determines whether or not to terminate this operation based on the register signal 3100 from the register circuit 2000.

[0206] If it is determined that this operation should not be terminated (NO in step S402), in step S403, the temperature control signal generation circuit 2100 waits until the temperature update timing arrives. For example, when the temperature control signal generation circuit 2100 receives a register signal 3100 indicating the temperature update timing from the register circuit 2000, the process returns to step S401 and the temperature control process is executed.

[0207] On the other hand, when the temperature control mode selection circuit 2120 receives a continuous control processing end signal from the register circuit 2000, it is determined that this operation is finished (YES in step S402), and the process ends.

[0208] For example, continuous control processing is initiated when a continuous control processing start signal is sent from the register circuit 2000 to the temperature control signal generation circuit 2100.

[0209] 2.8.1.9 Third example of the timing for acquiring temperature information Figure 23A is a timing chart showing a third example of the timing for acquiring temperature information. Figure 23A shows the temperature update timing, Sensor_State, Temp_Info, and Duty_Ratio. Explanations that overlap with the above explanations are omitted as appropriate.

[0210] The temperature update timing is represented, for example, by a temperature update timing signal supplied from the register circuit 2000 to the temperature control mode selection circuit 2120. In example A of Figure 23, each of the times t1 to t5 is set as the temperature update timing.

[0211] The temperature control signal generation circuit 2100 performs a temperature update at the temperature update timing.

[0212] The temperature update timing may be set continuously at regular intervals. The regular interval (period) for temperature updates may be variable.

[0213] The fixed interval for temperature updates is set, for example, using a register circuit 2000. Furthermore, the temperature update period may be changed according to the temperature of the solid-state imaging device 1. For example, the larger the temperature change detected by the thermometer circuit 120, the shorter the temperature update period will be. This reduces fluctuations in the current flowing through the Peltier element and minimizes the influence of band noise, as the temperature is updated more frequently when the temperature of the solid-state imaging device 1 changes rapidly.

[0214] Sensor_State (sensor state information) is information indicating which of several states the operating state of the solid-state imaging device 1 is in, including the sensor readout state and the sensor readout paused state. The sensor readout state is, for example, the state in which a voltage signal corresponding to the amount of light received at the sensor pixel 11 is read out via the vertical signal line 13. The sensor state signal 3110 supplied from the sensor state transition circuit 2200 to the temperature control mode selection circuit 2120 includes the sensor state information.

[0215] In example A of Figure 23, for instance, at time t1, the operating state of the solid-state imaging device 1 transitions from the sensor readout state to the sensor readout pause state. Temperature updates are not performed during the sensor readout period, and temperature updates are performed continuously at regular intervals during the sensor readout pause period, which is the period after time t1.

[0216] As a result, the timing at which the PWM waveform of the temperature control signal 3200 changes significantly in conjunction with temperature updates falls within the readout pause period, thereby reducing the influence of magnetic field noise on the output image of the solid-state imaging device 1. If temperature updates were performed during the sensor readout period, the change in the PWM waveform of the temperature control signal 3200 would cause magnetic field noise to affect the output image, but this can be prevented. If temperature updates are also performed during the sensor readout period, the temperature update period during the sensor readout period is longer than the temperature update period during the sensor readout pause period. This further reduces the influence of magnetic field noise on the output image.

[0217] For example, during the sensor readout period from time t0 to time t1, the duty cycle adjustment circuit 2130 does not change the PWM waveform of the temperature control signal 3200. That is, during the sensor readout period, the duty cycle of the temperature control signal 3200 is maintained at 50%. This reduces the influence of magnetic field noise on the output image of the solid-state imaging device 1.

[0218] During the period from time t1 to time t2, which is the sensor readout pause period, the duty cycle adjustment circuit 2130 generates a temperature control signal 3200 with a duty cycle adjusted to 65% based on a comparison between a target temperature, for example, 20°C, and a detected temperature, 38°C. Similarly, during other periods of the sensor readout pause period, the duty cycle of the temperature control signal 3200 is adjusted based on a comparison between the target temperature and the detected temperature.

[0219] Figure 23B illustrates a third example of the timing for acquiring temperature information. As the temperature is updated at the timings described above during the sensor readout pause period, the temperature detected in the thermometer circuit 120 decreases by a predetermined amount at each of the times t1 to t5, as shown in Figure 23B, and approaches the target temperature.

[0220] 2.8.1.10 Flow of Temperature Control Process 2 Figure 24 is a flowchart illustrating temperature control process 2.

[0221] As shown in Figure 24, first, in step S501, the temperature control mode selection circuit 2120 receives the sensor state signal 3110 supplied from the sensor state transition circuit 2200 and acquires sensor state information.

[0222] Next, in step S502, the temperature control mode selection circuit 2120 determines whether the operating state of the solid-state imaging device 1 is in a sensor readout pause state or not, based on the acquired sensor state information.

[0223] If the operating state of the solid-state imaging device 1 is determined to be in a sensor readout pause state (YES in step S502), in step S503, the temperature information comparison circuit 2110 acquires temperature information. The temperature information comparison circuit 2110 compares the detected temperature indicated by the temperature information with the target temperature and outputs a difference signal corresponding to the difference to the duty cycle adjustment circuit 2130. The temperature information comparison circuit 2110 acquires temperature information from, for example, a register (not shown) or a thermometer circuit 120.

[0224] Next, in step S504, the duty cycle adjustment circuit 2130 generates a temperature control signal 3200 with an adjusted duty cycle based on the difference between the detected temperature and the target temperature, and outputs it to the temperature control element 1400. The temperature control element 1400 cools the solid-state imaging device 1 based on the temperature control signal 3200 supplied from the duty cycle adjustment circuit 2130.

[0225] If it is determined that the operating state of the solid-state imaging device 1 is not in the sensor readout pause state (NO in step S502), the process returns to step S501 and the subsequent operations are executed. In other words, if the sensor readout state is active, the temperature is not updated.

[0226] For example, temperature control process 2 starts when a temperature control process 2 start signal is supplied from the register circuit 2000 to the temperature control signal generation circuit 2100, and ends when a temperature control process 2 end signal is supplied.

[0227] 2.8.1.11 Fourth example of the timing for acquiring temperature information Figure 25 illustrates a fourth example of the timing for acquiring temperature information. Explanations that overlap with those described above will be omitted as appropriate.

[0228] The read control signal is a signal supplied from the temperature control mode selection circuit 2120 to the sensor state transition circuit 2200, and includes information indicating whether or not to temporarily suspend the read operation during the sensor read period.

[0229] For example, a read control signal value of 0 indicates that the read operation is temporarily suspended. When the read operation is temporarily suspended during the sensor readout period, the read control signal value switches from 1 to 0. In response to a read control signal of value 0 being supplied from the temperature control mode selection circuit 2120, the sensor state transition circuit 2200 transitions the state of the sensor pixel 11 to temporarily suspend the read operation.

[0230] In the example shown in Figure 25, the sensor state transition circuit 2200 temporarily stops the read operation during the period from time t1 to time t2. Then, during the period from time t1 to time t2, when the sensor read period transitions to the sensor readout pause period, the temperature is updated by the temperature information comparison circuit 2110 or the like.

[0231] For example, during the period from time t1 to time t2, which is a sensor readout pause period, the duty cycle adjustment circuit 2130 generates a temperature control signal 3200 with a duty cycle adjusted to 65% based on a comparison between a target temperature, for example, 20°C, and a detected temperature, 36°C. Subsequently, the duty cycle of the temperature control signal 3200 is maintained at 65%.

[0232] In response to the reading control signal of value 1 being supplied from the temperature control mode selection circuit 2120, the sensor state transition circuit 2200 restarts the reading operation from time t2.

[0233] In this way, if the sensor temperature rises rapidly during the sensor readout period and a temperature update is necessary, the temperature update is performed without waiting for the end of the sensor readout period, ensuring that it does not overlap with the readout period. This reduces the generation of dark current. The mode in which the temperature is updated during the sensor readout period or during the sensor readout pause period is selected by setting a predetermined value in the register circuit 2000.

[0234] 2.8.1.12 Flow of Temperature Control Process 3 Figure 26 is a flowchart illustrating temperature control process 3.

[0235] As shown in Figure 26, first, in step S601, the temperature control signal generation circuit 2100 determines whether the amount of change in the detected temperature per unit time exceeds a predetermined threshold. Step S601 is a step to determine whether the temperature of the solid-state imaging device 1 has risen rapidly. In step S601, the determination of whether the temperature of the solid-state imaging device 1 has risen rapidly may be made based on data from a thermometer (not shown) outside the sensor package 1100 or data from other sensors.

[0236] If the change in detected temperature per unit time exceeds a predetermined threshold (YES in step S601), in step S602, the temperature control mode selection circuit 2120 receives the sensor status signal 3110 supplied from the sensor status transition circuit 2200 and acquires sensor status information. If the change in detected temperature per unit time does not exceed the predetermined threshold (NO in step S601), the process returns to step S601 and the subsequent operations are performed.

[0237] After acquiring sensor status information in step S602, in step S603, the temperature control mode selection circuit 2120 determines whether the operating state of the solid-state imaging device 1 is in the sensor readout state or not, based on the acquired sensor status information.

[0238] If the operating state of the solid-state imaging device 1 is determined to be the sensor readout state (YES in step S603), in step S604, the temperature control mode selection circuit 2120 sends a readout stop signal to the sensor state transition circuit 2200 to temporarily stop the sensor readout. The state of the sensor pixel 11 transitions to a state in which the readout operation is temporarily stopped.

[0239] Next, in step S605, the temperature information comparison circuit 2110 acquires temperature information. The temperature information comparison circuit 2110 compares the detected temperature indicated by the temperature information with the target temperature and outputs a difference signal corresponding to the difference to the duty cycle adjustment circuit 2130.

[0240] Next, in step S606, the duty cycle adjustment circuit 2130 generates a temperature control signal 3200 with an adjusted duty cycle based on the difference between the detected temperature and the target temperature, and outputs it to the temperature control element 1400. The temperature control element 1400 cools the solid-state imaging device 1 based on the temperature control signal 3200 supplied from the duty cycle adjustment circuit 2130.

[0241] Next, in step S607, the temperature control mode selection circuit 2120 transmits a readout start signal to the sensor state transition circuit 2200 to initiate sensor readout. The state of the sensor pixel 11 transitions to the state in which the readout operation has resumed.

[0242] On the other hand, if it is determined that the operating state of the solid-state imaging device 1 is not in the sensor readout pause state (NO in step S603), then the processes in steps S608 and S609 are executed in order. The processes in steps S608 and S609 are the same as the processes in steps S605 and S606, respectively.

[0243] For example, temperature control processing 3 starts when a temperature control signal 3 start signal is supplied from the register circuit 2000 to the temperature control signal generation circuit 2100, and ends when a temperature control signal 3 end signal is supplied.

[0244] 2.8.1.13 Test External Terminals Figure 27 is a diagram illustrating the external terminals for testing.

[0245] The solid-state imaging device 1 includes a pixel array section 10 including sensor pixels 11, a system control circuit 16 including a temperature control signal generation circuit 2100, a horizontal drive circuit 30, a thermometer circuit 120, a first multiplexer circuit 2300-1, a second multiplexer circuit 2300-2, a first test external terminal 2400-1, and a second test external terminal 2400-2. The first multiplexer circuit 2300-1 is provided between the system control circuit 16 and the first test external terminal 2400-1, and the second multiplexer circuit 2300-2 is provided between the system control circuit 16 and the second test external terminal 2400-2.

[0246] When the thermometer circuit 120 and the temperature control signal generation circuit 2100 are incorporated into the solid-state imaging device 1, the signal output from the solid-state imaging device 1 that is related to the control of the temperature control element 1400 is the temperature control signal 3200, which is a 2-bit signal.

[0247] By integrating the thermometer circuit 120 and the temperature control signal generation circuit 2100 into the solid-state imaging device 1, interfaces such as I2C (Inter-Integrated Circuit) and SPI (Serial Peripheral Interface) become unnecessary for controlling the temperature control element. This improves the communication delay for controlling the temperature control element 1400. For example, if the temperature control signal generation circuit 2100 is located outside the solid-state imaging device 1, the signal output from the solid-state imaging device 1 and related to the control of the temperature control element 1400 is transmitted via serial communication and becomes a signal with more than 2 bits. In other words, by integrating the temperature control signal generation circuit 2100 into the solid-state imaging device 1, it becomes unnecessary to use such a high-bit signal for controlling the temperature control element. Also, if the temperature control signal generation circuit 2100 is located outside the solid-state imaging device 1, serial communication for acquiring temperature information may be performed during the sensor readout period, which may cause noise in the output image due to logic power supply fluctuations. Therefore, serial communication is performed during the V-blanking period (vertical blanking period), which is the sensor readout pause period. In other words, by incorporating the temperature control signal generation circuit 2100 into the solid-state imaging device 1, the temperature control element 1400 can be controlled using the detected temperature independently of the frame rate.

[0248] Furthermore, as shown in Figure 27, the temperature control signal 3200 is supplied from the system control circuit 16 to the driver circuit 1300 via an external terminal.

[0249] At this time, the temperature control signal 3200 is output via the bonding pad 92 of the solid-state imaging device 1. The bonding pad 92 that outputs the temperature control signal 3200 may also be an external test terminal.

[0250] The external terminals for testing are external terminals for testing whether the circuits in the solid-state imaging device operate normally during the manufacturing process of the solid-state imaging device, and are terminals generally provided in the solid-state imaging device. Therefore, by using the external terminals for testing for the output of the temperature control signal 3200, there is no need to newly add external terminals. As a result, the solid-state imaging device can be made smaller.

[0251] The external terminals for testing are connected to the output terminals of the multiplexer circuit. The input terminals of the multiplexer circuit are connected to the temperature control signal generation circuit 2100 in the system control circuit 16 and other circuits (for example, the thermometer circuit 120) included in the solid-state imaging device 1. The multiplexer circuit outputs a selected signal among the input plurality of signals.

[0252] The first external terminal for testing 2400-1 and the second external terminal for testing 2400-2 may be arranged adjacent to each other. Since the external terminals for testing are adjacent, the wiring delay difference due to the wiring length can be reduced. When the influence of the wiring delay difference occurs in the control signals PWM-P and PWM-N, it may become impossible to ensure the dead band described above. Therefore, by reducing the wiring delay difference, it is possible to suppress the risk of the through-current flowing.

[0253] 2.8.2 Second System Configuration Example (Multiple Temperature Control Elements) FIG. 28 is a block diagram showing an example of a system control circuit according to the first system configuration example of the second embodiment.

[0254] As shown in FIG. 28, the imaging system 1000 according to the first system configuration example of the second embodiment includes a sensor package 1100, a first driver circuit 1300A, and a second driver circuit 1300B.

[0255] The sensor package 1100 includes the solid-state imaging device 1, a first temperature control element 1400A, and a second temperature control element 1400B. That is, in this example, a plurality of temperature control elements are provided in the sensor package 1100.

[0256] The sensor package 1100 includes multiple temperature control elements, which improves the cooling efficiency of the solid-state imaging device 1.

[0257] The solid-state imaging device 1 includes a pixel array section 10 containing sensor pixels 11, a pixel drive line 12, a vertical signal line 13, a system control circuit 16, a vertical drive circuit 20, a horizontal drive circuit 30, a first thermometer circuit 120A, a second thermometer circuit 120B, and a register circuit 2000.

[0258] This example describes a sensor package having two thermometer circuits and two temperature control elements, but the sensor package may have two or more thermometer circuits and two or more temperature control elements. When using multiple temperature control elements, for example, the number of temperature control signal generation circuits is the same as the number of temperature control elements. Also, the number of output PADs is twice the number of temperature control signal generation circuits, and the number of driver circuits is the same as the number of temperature control elements.

[0259] Figure 28 is a plan view of the sensor package 1100.

[0260] In the example shown in Figure 28, the first temperature control element 1400A is positioned to cool the left side of the solid-state imaging device 1, overlapping with approximately the left half of the solid-state imaging device 1. On the other hand, the second temperature control element 1400B is positioned to cool the right side of the solid-state imaging device 1, overlapping with approximately the right half of the solid-state imaging device 1. The first thermometer circuit 120A is positioned to overlap with the first temperature control element 1400A. The second thermometer circuit 120B is positioned to overlap with the second temperature control element 1400B.

[0261] In other words, each temperature control element is controlled according to the temperature information of the area corresponding to the arrangement of each temperature control element. This reduces variations in temperature changes within the solid-state imaging device.

[0262] The system control circuit 16 acquires a temperature signal 3000A containing first temperature data (temperature information) from the first thermometer circuit 120A, and a temperature signal 3000B containing second temperature data (temperature information) from the second thermometer circuit 120B. The first temperature control signal 3200A, generated based on the temperature information acquired from the first thermometer circuit 120A, is output to the first driver circuit 1300A. The second temperature control signal 3200B, generated based on the temperature information acquired from the second thermometer circuit 120B, is output to the second driver circuit 1300B.

[0263] The first driver circuit 1300A generates a first temperature control element control signal 3300A based on a first temperature control signal 3200A supplied from the system control circuit 16 and outputs it to the first temperature control element 1400A. The second driver circuit 1300B generates a second temperature control element control signal 3300B based on a second temperature control signal 3200B supplied from the system control circuit 16 and outputs it to the second temperature control element 1400B.

[0264] 2.8.2.1 System Control Circuit Figure 29 is a block diagram showing an example of a system control circuit according to the first system configuration example of the second embodiment.

[0265] As shown in Figure 29, the system control circuit 16 according to the first system configuration example of the second embodiment includes a first temperature control signal generation circuit 2100A, a second temperature control signal generation circuit 2100B, and a sensor state transition circuit 2200.

[0266] The circuit configuration, in which the sensor state transition circuit 2200 is shared by multiple temperature control signal generation circuits, suppresses an increase in circuit area.

[0267] The first temperature control signal generation circuit 2100A acquires a first temperature signal 3000A containing first temperature data (first temperature information) from the first thermometer circuit 120A, and outputs a first temperature control signal 3200A generated based on the acquired first temperature information to the first driver circuit 1300A.

[0268] The second temperature control signal generation circuit 2100B acquires a second temperature signal 3000B including second temperature data (second temperature information) from the second thermometer circuit 120B, and outputs a second temperature control signal 3200B generated based on the acquired second temperature information to the second driver circuit 1300B.

[0269] The first temperature control signal generation circuit 2100A includes a first temperature information comparison circuit 2110A, a first Duty ratio adjustment circuit 2130A, and a first temperature control mode selection circuit 2120A.

[0270] The second temperature control signal generation circuit 2100B includes a second temperature information comparison circuit 2110B, a second Duty ratio adjustment circuit 2130B, and a second temperature control mode selection circuit 2120B.

[0271] Thus, the first temperature control signal generation circuit 2100A and the second temperature control signal generation circuit 2100B are each provided with the same configuration as the configuration of the temperature control signal generation circuit 2100 described with reference to FIG. 16 and the like.

[0272] The register circuit 2000 outputs a first register signal 3100A and a second register signal 3100B. That is, the solid-state imaging device 1 can perform temperature updates by the first temperature control signal generation circuit 2100A and temperature updates by the second temperature control signal generation circuit 2100B at different timings.

[0273] 2.8.2.2 External Terminals FIG. 30 is a diagram for explaining external terminals according to a first system configuration example of the second embodiment.

[0274] As shown in FIG. 30, the sensor package 1100 includes the solid-state imaging device 1, a first temperature control element 1400A, and a second temperature control element 1400B.

[0275] The solid-state imaging device 1 includes a pixel array section 10 containing sensor pixels 11, a pixel drive line 12, a vertical signal line 13, a system control circuit 16, a vertical drive circuit 20, a horizontal drive circuit 30, a first thermometer circuit 120A, a second thermometer circuit 120B, a register circuit 2000, a first external terminal 2400-1A, a second external terminal 2400-2A, a third external terminal 2400-1B, and a fourth external terminal 2400-2B.

[0276] Figure 30 is a plan view of the sensor package 1100.

[0277] The first thermometer circuit 120A, the first external terminal 2400-1A, and the second external terminal 2400-2A are arranged so as to overlap with the first temperature control element 1400A in a plan view. The second thermometer circuit 120B, the third external terminal 2400-1B, and the fourth external terminal 2400-2B are arranged so as to overlap with the second temperature control element 1400B in a plan view.

[0278] As shown in Figure 30, the types, number, and density of circuits arranged in the first region corresponding to the first temperature control element 1400A within the solid-state imaging device 1 differ from the types, number, and density of circuits arranged in the second region corresponding to the second temperature control element 1400B. In other words, the degree to which the temperature rises in the first region differs from the degree to which the temperature rises in the second region. Generally, the greater the heat generated by the arranged circuits and the higher the density of the arranged circuits, the greater the degree of temperature rise.

[0279] In Figure 30, the first region corresponding to the first temperature control element 1400A has a more densely packed circuit layout compared to the second region corresponding to the second temperature control element 1400B. Therefore, the register circuit 2000 sets the temperature update period corresponding to the control of the first temperature control element 1400A to be shorter than the temperature update period corresponding to the control of the second temperature control element 1400B. This reduces the amount of heat generated by the solid-state imaging device.

[0280] 2.8.2.3 Thermometer circuit Figure 31 is a circuit diagram showing an example of a thermometer circuit. As shown in Figure 31, a silicon diode can be used in the thermometer circuit 120, for example.

[0281] Silicon diodes have a forward voltage (equivalent to film voltage) Vf with a temperature coefficient of -2mV / °C, and Vf decreases linearly as the temperature rises. This gives them the advantage of being able to easily determine the temperature from the Vf voltage value. Furthermore, this characteristic allows for calibration during the manufacturing of the solid-state imaging device 1. In addition, since silicon diodes can be formed using the same process as each transistor in the pixel circuit 14, there is no need to add a new step for forming the thermometer circuit 120, thus reducing the complexity of the manufacturing process.

[0282] However, the thermometer circuit 120 according to this embodiment is not limited to silicon diodes, and various temperature sensors that can be fabricated on the circuit board 200 can be used, such as semiconductor temperature sensors like PNP transistors.

[0283] While embodiments of this disclosure have been described above, the technical scope of this disclosure is not limited to the embodiments described above, and various modifications are possible without departing from the spirit of this disclosure. Furthermore, components from different embodiments and modifications may be combined as appropriate.

[0284] 2.8.3 Example of System Configuration 3 Figure 32 is a block diagram showing a schematic configuration example of an imaging system according to the first system configuration example of the third embodiment. As shown in Figure 32, the imaging system 1000 according to the first system configuration example comprises the sensor package 1100 described above, an FPGA (Field-Programmable Gate Array) 1200, and a driver circuit 1300.

[0285] As described above, the sensor package 1100 has a structure that houses the solid-state imaging device 1 within a cavity 71 formed by the package 50 and the lid 60 with sealing glass.

[0286] The FPGA 1200 is, for example, a control device for controlling the solid-state imaging device 1, and inputs control signals for controlling the solid-state imaging device 1 to the solid-state imaging device 1 inside the package 50 via pin terminals. As mentioned above, I2C (Inter-Integrated Circuit) or SPI (Serial Peripheral Interface) can be used as the interface connecting the FPGA 1200 and the solid-state imaging device 1. Alternatively, an information processing device such as an ISP (Image Signal Processor) may be used instead of the FPGA 1200.

[0287] The temperature data (detection result) detected by the thermometer circuit 120 of the solid-state imaging device 1 and converted to a digital value by the AD conversion circuit 121 is output to the FPGA 1200 outside the package via an interface such as I2C or SPI connecting the FPGA 1200 and the solid-state imaging device 1. Therefore, in this embodiment, dedicated lines or terminals for outputting temperature data to the outside of the package can be omitted.

[0288] The driver circuit 1300 is configured to control the Peltier element 80 in the sensor package 1100 according to a control signal from the FPGA 1200, for example. Specifically, the driver circuit 1300 generates an analog signal to be supplied to the Peltier element 80 according to the control signal from the FPGA 1200 and supplies this signal to the Peltier element 80 in the sensor package 1100 via the pin terminal 73.

[0289] With the above configuration, since the thermometer circuit 120 is located inside the solid-state imaging device 1, it becomes possible to directly measure the temperature of the solid-state imaging device 1 itself. This makes it possible to improve the accuracy of the measured sensor chip temperature.

[0290] Furthermore, for example, since the analog value output from the thermometer circuit 120 is converted to a digital value by the AD conversion circuit 121 in the solid-state imaging device 1, it is possible to reduce the influence of noise on the measurement result detected by the thermometer circuit 120. This makes it possible to improve the robustness of the measured temperature.

[0291] Furthermore, by converting the measurement results into digital values, it becomes possible to output the measurement results to the outside of the sensor package 1100 using control signals such as I2C or SPI. This eliminates the need to provide a dedicated terminal for outputting the measurement results outside the sensor package 1100. As a result, it becomes possible to output the measurement results externally without being limited by the number of terminals on the sensor package 1100.

[0292] Furthermore, since it does not involve attaching a separate component, such as a discrete thermistor element, to the solid-state imaging device 1, it is possible to suppress yield reductions due to defects in the thermistor element or improper installation.

[0293] 2.8.3.1 Example Configuration of a Solid State Imaging Device Figure 33 is a layout diagram illustrating the arrangement of a thermometer circuit according to the first example of the third embodiment. In the layout illustrated in Figure 33, the main heat-generating parts are the horizontal circuit 40A and the system control circuit 16 on the circuit board 200. Therefore, in the first example, as shown in Figure 33, the thermometer circuit 120 is arranged around the horizontal circuit 40A and the system control circuit 16, which are the main heat-generating parts.

[0294] The horizontal circuit 40A is a circuit that includes the horizontal drive circuit 30 and the horizontal selection circuit. In the horizontal selection circuit, for example, an ADC and a switching element are provided for each pixel row (or vertical signal line 13) of the pixel array section 10. The output of the PLL circuit 131 is supplied to the system control circuit 16 and the horizontal circuit 40A. The output of the system control circuit 16 to the vertical drive circuit 20 is also supplied to the bias circuit 132.

[0295] Furthermore, the number of thermometer circuits 120 to be placed is not limited to one, but may be multiple, as shown in Figure 33. By distributing multiple thermometer circuits 120, it becomes possible to measure the temperature of the solid-state imaging device 1 more accurately. However, if a material with high thermal conductivity, such as a silicon substrate, is used for the circuit board 200, sufficient accuracy can be obtained even with a single thermometer circuit 120.

[0296] Furthermore, terminal 133, which is used to input control signals to the solid-state imaging device 1 and to output image data generated by the solid-state imaging device 1, is also connected to the thermometer circuit 120 or the AD conversion circuit 121 connected thereto, or a register that holds the temperature data generated by the AD conversion circuit 121. This may be the same in other examples described later.

[0297] Figure 34 shows an example of the input and output of the solid-state imaging device 1.

[0298] The solid-state imaging device 1 also has register circuits A and B within the system control circuit 16, making it possible to average multiple measurement results.

[0299] The averaging of multiple measurement results will now be explained. First, the solid-state imaging device 1 receives a control signal output from FPGA 1200, which sets the thermometer update register. Once the thermometer update register is set, the system control circuit 16 accesses the thermometer circuit 120 and updates the thermometer output value (reads the thermometer output value).

[0300] At this time, the system control circuit 16 accesses the thermometer circuit 120 multiple times and averages the multiple thermometer output values ​​read from the thermometer circuit 120. The data representing the thermometer output value obtained by averaging is stored in the register circuit B.

[0301] Next, the data stored in register circuit B is transferred to register circuit A, which is a register for external output. The data transferred to register circuit A is then output to the outside of the solid-state imaging device 1 using a control signal.

[0302] This makes it possible to suppress temperature variations in the time direction caused by noise and quantization errors (errors during AD conversion) generated in the internal circuit, thereby improving the measurement accuracy of the thermometer circuit 120.

[0303] An external terminal for receiving the sensor control signal may be provided separately from terminal 133, and the signal from register circuit A may be output via the external terminal for receiving the sensor control signal. This means that the external terminal is shared by both the sensor control signal and the signal from register circuit A, reducing the terminal's footprint and enabling miniaturization of the sensor.

[0304] Furthermore, the solid-state imaging device 1 may also be equipped with an external terminal for outputting a signal from register circuit A, in addition to the external terminal for receiving sensor control signals. This makes it possible to output the signal from register circuit A independently.

[0305] Furthermore, in averaging multiple measurement results, multiple averaging modes may be provided, each with a different number of measurement results to be averaged. Switching between averaging modes is performed, for example, by changing the number of accesses from the system control circuit 16 to the thermometer circuit 120.

[0306] If the solid-state imaging device 1 has multiple thermometer circuits 120, it is possible to provide a number of register circuits B, an averaging circuit, and a register circuit A equal to the number of thermometer circuits 120.

[0307] Furthermore, if the solid-state imaging device 1 has multiple thermometer circuits 120, a selection circuit such as a multiplexer can be placed between the multiple register circuits B and register circuit A. This ensures that only the selected thermometer output value from among the multiple thermometer output values ​​detected by the multiple thermometer circuits 120 is transferred to register circuit A.

[0308] The selection circuit may include a comparison circuit. The solid-state imaging device 1 can select, for example, the signal showing the highest thermometer output value from among the multiple thermometer output values ​​detected by the multiple thermometer circuits 120 and transfer it to register A.

[0309] Furthermore, the effects described in each embodiment of this specification are merely illustrative and not limiting, and other effects may also occur.

[0310] 3. Examples of applications to mobile devices The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein may be implemented as a device mounted on any type of mobile vehicle, such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, drone, ship, or robot.

[0311] Figure 35 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0312] The vehicle control system 12000 comprises multiple electronic control units connected via a communication network 12001. In the example shown in Figure 35, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0313] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0314] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0315] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0316] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0317] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0318] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking system based on information from inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0319] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0320] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12030 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0321] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 35, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0322] Figure 36 shows an example of the installation position of the imaging unit 12031.

[0323] In Figure 36, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0324] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0325] Figure 36 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0326] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0327] For example, the microcomputer 12051, based on distance information obtained from imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to vehicle 12100). In particular, it can extract the nearest object on the vehicle 12100's path that is traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0328] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, heavy vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0329] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0330] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein can be applied to the imaging unit 12031 of the configuration described above. By applying the technology described herein to the imaging unit 12031, the degradation of image quality of the captured image is reduced, and a more easily viewable image can be obtained, thereby reducing driver fatigue.

[0331] <Examples of configuration combinations> This technology can also be configured as follows:

[0332] (1) A photoelectric conversion unit constructed using a material with a smaller bandgap energy than silicon, A circuit board joined to the photoelectric conversion unit Equipped with, The aforementioned circuit board is A pixel signal generation circuit that generates a pixel signal with a voltage value corresponding to the charge generated in the photoelectric conversion unit, A thermometer circuit for detecting the temperature of the circuit board, A temperature control signal generation circuit acquires temperature information indicating the temperature detected by the thermometer circuit and generates a temperature control signal based on the acquired temperature information. has Solid-state imaging device. (2) The circuit board further comprises a system control circuit that drives the pixel signal generation circuit, The temperature control signal generation circuit is incorporated into the system control circuit. The solid-state imaging device described in (1) above. (3) The temperature control signal generation circuit generates the temperature control signal according to the result of comparing the target temperature with the detected temperature indicated by the temperature information. The solid-state imaging device described in (1) or (2) above. (4) The temperature control signal generation circuit performs a comparison between the target temperature and the detected temperature each time the temperature information is acquired. The solid-state imaging device described in (3) above. (5) The temperature control signal generation circuit generates the temperature control signal with its duty cycle adjusted according to the comparison result between the target temperature and the detected temperature. The solid-state imaging device described in (3) or (4) above. (6) The temperature control signal is a PWM signal. A solid-state imaging device according to any one of (1) to (5) above. (7) The aforementioned temperature information is acquired continuously at a constant interval. A solid-state imaging device according to any one of (1) to (6) above. (8) The reciprocal of the aforementioned period is equal to the frame rate. The solid-state imaging device described in (7) above. (9) The reciprocal of the aforementioned period is greater than the frame rate. The solid-state imaging device described in (7) above. (10) The aforementioned period is variable. The solid-state imaging device described in (7) above. (11) The period is changed according to the temperature of the solid-state imaging device. The solid-state imaging device described in (10) above. (12) The period is shorter the larger the change in temperature detected by the thermometer circuit. The solid-state imaging device described in (11) above. (13) It further has a register circuit, The period is set using the register circuit. A solid-state imaging device according to any one of (10) to (12) above. (14) The temperature control signal generation circuit acquires sensor operating state information and generates the temperature control signal based on the sensor operating state information. A solid-state imaging device according to any one of (1) to (13) above. (15) The temperature control signal generation circuit acquires the temperature information during the sensor readout pause period. The solid-state imaging device described in (14) above. (16) The temperature control signal generation circuit does not acquire the temperature information during the sensor readout period. The solid-state imaging device described in (15) above. (17) The temperature control signal generation circuit temporarily stops sensor reading and then acquires the temperature information if the amount of temperature change detected by the thermometer circuit during the sensor reading period is greater than a threshold. The solid-state imaging device described in (16) above. (18) Temperature information is acquired continuously at regular intervals. The period during the sensor readout period is longer than the period during the sensor readout pause period. The solid-state imaging device described in (15) above. (19) It also has external test terminals, The temperature control signal generation circuit is electrically connected to the test external terminal. A solid-state imaging device according to any one of (1) to (18) above. (20) Equipped with a multiplexer, Multiple circuits within the circuit board, including the temperature control signal generation circuit, are connected to the input terminal of the multiplexer. The test external terminal is connected to the output terminal of the multiplexer. The solid-state imaging device described in (19) above. (twenty one) A photoelectric conversion unit constructed using a material with a smaller bandgap energy than silicon, A circuit board joined to the photoelectric conversion unit Equipped with, The aforementioned circuit board is A pixel signal generation circuit that generates a pixel signal with a voltage value corresponding to the charge generated in the photoelectric conversion unit, A first thermometer circuit for detecting the temperature of the circuit board, A second thermometer circuit for detecting the temperature of the circuit board, A first temperature control signal generation circuit that acquires first temperature information indicating the temperature detected by the first thermometer circuit and generates a first temperature control signal based on the acquired first temperature information, A second temperature control signal generation circuit acquires second temperature information indicating the temperature detected by the second thermometer circuit and generates a second temperature control signal based on the acquired second temperature information. has Solid-state imaging device. (twenty two) The first temperature information and the second temperature information are acquired periodically and continuously. The period for acquiring the first temperature information is different from the period for acquiring the second temperature information. The solid-state imaging device described in (21) above. (twenty three) The system includes a control circuit or horizontal drive circuit that includes the first temperature control signal generation circuit and the second temperature control signal generation circuit, The first thermometer circuit is positioned closer to the system control circuit or horizontal drive circuit than the second thermometer circuit. The period for acquiring the first temperature information is shorter than the period for acquiring the second temperature information. The solid-state imaging device described in (22) above. (twenty four) The solid-state imaging device described in (1) above, A cooling element is arranged so as to overlap with at least a portion of the solid-state imaging device in a plan view. A package containing [something]. (twenty five) The solid-state imaging device described in (1) above, A cooling element is arranged so as to overlap with the solid-state imaging device in a plan view, Based on the temperature control signal, a driver circuit controls the cooling element. An imaging system having [a certain feature]. (26) The solid-state imaging device described in (22) above, A first cooling element is positioned so as to overlap with the solid-state imaging device, A second cooling element is positioned so as to overlap with the solid-state imaging device but not with the first cooling element, A first driver circuit that controls the first cooling element based on the first temperature control signal, A second driver circuit controls the second cooling element based on the second temperature control signal. It has, The first thermometer circuit is positioned to overlap with the first cooling element. The second thermometer circuit is positioned to overlap with the second cooling element. Imaging system. (27) The first temperature control signal generation circuit is arranged to overlap with the first cooling element. The second temperature control signal generation circuit is arranged to overlap with the second cooling element. The imaging system described in (26) above. (28) A photoelectric conversion unit constructed using a material with a smaller bandgap energy than silicon, A circuit board joined to the photoelectric conversion unit Equipped with, The aforementioned circuit board is A pixel signal generation circuit that generates a pixel signal with a voltage value corresponding to the charge generated in the photoelectric conversion unit, A thermometer circuit for detecting the temperature of the circuit board, A system control circuit that acquires multiple temperature information records indicating the temperature detected by the thermometer circuit and performs averaging of the multiple temperatures. has Solid-state imaging device. (29) A photoelectric conversion unit constructed using a material with a smaller bandgap energy than silicon, A circuit board joined to the photoelectric conversion unit Equipped with, The aforementioned circuit board is A pixel signal generation circuit that generates a pixel signal with a voltage value corresponding to the charge generated in the photoelectric conversion unit, Multiple thermometer circuits for detecting the temperature of the circuit board, A system control circuit that acquires temperature information indicating the temperatures detected by the multiple thermometer circuits and performs averaging of the multiple temperatures. has Solid-state imaging device. [Explanation of Symbols]

[0333] 1. Solid-state imaging device 10 Pixel array section 11, 11R, 11G, 11B sensor pixels 12 pixel drive lines 13 Vertical signal lines 14 Pixel Circuit 15. Readout Circuit 16 System Control Circuits 17. Film Voltage Control Unit 18 Voltage Generation Circuit 20 Vertical drive circuit 21 n-type semiconductor film (InGaAs) 21A Semiconductor layer 22 p-type semiconductor layer 22A Diffusion region 23 n-type semiconductor layer 24 n-type semiconductor layer 25 Anti-reflective coating 26 Color Filters 26R, 26G, 26B filters 27 On-chip lenses 28 Passivation Layer 29 Insulating layer 29A, 29B, 35A, 35B Interlayer insulating film 30 Horizontal drive circuit 31 Connecting electrodes 32 Bump electrodes 32D dummy electrode 33 Conductive film 35 wiring layer 36. Embedding layer 37H opening 38 Pad electrodes 40 Horizontal Selection Circuit 40A horizontal circuit 40a ADC 40b Switching element 40c horizontal signal line 41 Support substrate 42 Interlayer insulating layer 43 Connectivity Layer 43D Dummy Connecting Layer 44 Readout electrodes 45-pixel signal generation circuit 46 Wiring 50 packages 51 Adhesive 54, 55 wires 60 lid with sealed glass 61 Seal Glass 62 Ceramic frame 63 Metal parts 70 Package substrates 71 Cavity 72, 73 Pin-shaped terminals 74, 91, 92 Bonding pads 75 Seal rings 80 Peltier elements 81. First ceramic substrate 82 Cuprous electrode 85. Second ceramic substrate 86 Cupric electrode 87 P-type thermoelectric semiconductor 88 N-type thermoelectric semiconductor 90 Ceramic interposer substrate 100 Light-receiving substrate (InGaAs substrate) 100A light receiving surface 120 Thermometer circuit 121 AD Conversion Circuit 133 terminals 200 circuit boards 200A Pixel signal generation circuit area 200B peripheral circuit area 1000 Imaging System 1100 Sensor Package 1300 driver circuit 1400 temperature control elements AMP (amplifying transistor) FD Floating Diffusion OFG emission transistor PD photodiode RST Reset Transistor SEL Select Transistor TRG Transfer Transistor

Claims

1. A photoelectric conversion unit constructed using a material with a smaller bandgap energy than silicon, A circuit board joined to the photoelectric conversion unit Equipped with, The aforementioned circuit board is A pixel signal generation circuit that generates a pixel signal with a voltage value corresponding to the charge generated in the photoelectric conversion unit, A thermometer circuit for detecting the temperature of the circuit board, A temperature control signal generation circuit acquires temperature information indicating the temperature detected by the thermometer circuit and generates a temperature control signal, which is a PWM signal, based on the acquired temperature information. It has, The temperature control signal generation circuit maintains the duty cycle of the temperature control signal during the readout period of the pixel signal by the pixel signal generation circuit, and updates the duty cycle during the pause period for reading the pixel signal, thereby reducing the influence of magnetic field noise on the pixel signal during the readout period. Solid-state imaging device.

2. The circuit board further comprises a system control circuit that drives the pixel signal generation circuit, The temperature control signal generation circuit is incorporated into the system control circuit. The solid-state imaging apparatus according to claim 1.

3. The temperature control signal generation circuit generates the temperature control signal according to the result of comparing the target temperature with the detected temperature indicated by the temperature information. The solid-state imaging apparatus according to claim 1.

4. The temperature control signal generation circuit generates the temperature control signal with its duty cycle adjusted according to the comparison result between the target temperature and the detected temperature. The solid-state imaging apparatus according to claim 3.

5. The aforementioned temperature information is acquired continuously at a constant interval. The solid-state imaging apparatus according to claim 1.

6. The reciprocal of the aforementioned period is equal to the frame rate. The solid-state imaging apparatus according to claim 5.

7. The reciprocal of the aforementioned period is greater than the frame rate. The solid-state imaging apparatus according to claim 5.

8. The aforementioned period is variable. The solid-state imaging apparatus according to claim 5.

9. The period is changed according to the temperature of the solid-state imaging device. The solid-state imaging apparatus according to claim 8.

10. The period is shorter the larger the change in temperature detected by the thermometer circuit. The solid-state imaging apparatus according to claim 9.

11. It further has a register circuit, The period is set using the register circuit. The solid-state imaging apparatus according to claim 8.

12. It also has external test terminals, The temperature control signal generation circuit is electrically connected to the test external terminal. The solid-state imaging apparatus according to claim 1.

13. Equipped with a multiplexer, Multiple circuits within the circuit board, including the temperature control signal generation circuit, are connected to the input terminal of the multiplexer. The test external terminal is connected to the output terminal of the multiplexer. The solid-state imaging apparatus according to claim 12.

14. A solid-state imaging device according to claim 1, A cooling element is arranged so as to overlap with at least a portion of the solid-state imaging device in a plan view. A package containing [something].

15. A solid-state imaging device according to claim 1, A cooling element is arranged so as to overlap with the solid-state imaging device in a plan view, Based on the temperature control signal, a driver circuit controls the cooling element. An imaging system having [a certain feature].

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