Silicon carbide semiconductor device and method for manufacturing a silicon carbide semiconductor device
By employing an alloy layer with differential aluminum concentrations and a barrier layer with varying thicknesses, the silicon carbide semiconductor device reduces contact resistance, enhancing its operational efficiency.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- MITSUMI ELECTRIC CO LTD
- Filing Date
- 2022-10-13
- Publication Date
- 2026-07-01
AI Technical Summary
Conventional silicon carbide semiconductor devices face high contact resistance between the p-type semiconductor region and the NiSi film, necessitating a reduction in this resistance to enhance device performance.
The silicon carbide semiconductor device incorporates an alloy layer with varying aluminum concentrations on p-type and n-type semiconductor regions, coupled with a barrier layer of differing thicknesses to facilitate ohmic bonding, thereby reducing contact resistance.
This configuration effectively lowers the contact resistance between the p-type and n-type semiconductor regions, improving the overall performance of the semiconductor device.
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Abstract
Description
Technical Field
[0001] The present disclosure relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.
Background Art
[0002] As one of the silicon carbide semiconductor devices, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) provided with a NiSi film that forms an ohmic contact with a p-type semiconductor region and an n-type semiconductor region has been disclosed.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] In a conventional silicon carbide semiconductor device provided with a NiSi film, it is required to reduce the contact resistance between the p-type semiconductor region and the NiSi film.
[0005] An object of the present disclosure is to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can reduce the contact resistance between a p-type semiconductor region and an n-type semiconductor region and an alloy layer.
Means for Solving the Problems
[0006] The silicon carbide semiconductor device of the present disclosure comprises: a silicon carbide substrate having a first main surface in which a p-type semiconductor region and an n-type semiconductor region are exposed; an alloy layer provided on the first main surface and containing nickel, silicon, and aluminum; a barrier layer provided on the alloy layer; and an electrode provided on the barrier layer and containing aluminum, wherein the alloy layer has a first alloy region provided on the p-type semiconductor region and a second alloy region provided on the n-type semiconductor region, the aluminum concentration in the first alloy region is higher than the aluminum concentration in the second alloy region; and the barrier layer has a first barrier region provided on the first alloy region and a second barrier region provided on the second alloy region, the thickness of the first barrier region is thinner than the thickness of the second barrier region. [Effects of the Invention]
[0007] According to this disclosure, it is possible to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can reduce the contact resistance between the p-type semiconductor region, the n-type semiconductor region and the alloy layer. [Brief explanation of the drawing]
[0008] [Figure 1] Figure 1 is a plan view showing a silicon carbide semiconductor device according to an embodiment. [Figure 2] Figure 2 is a cross-sectional view showing a silicon carbide semiconductor device according to an embodiment of this invention. [Figure 3] Figure 3 is a cross-sectional view showing a silicon carbide semiconductor device according to an embodiment of the present invention. [Figure 4] Figure 4 is a cross-sectional view showing a silicon carbide semiconductor device according to an embodiment. [Figure 5] Figure 5 is a cross-sectional view showing a silicon carbide semiconductor device according to an embodiment of this invention. [Figure 6] Figure 6 is a plan view showing a silicon carbide semiconductor device according to a modified embodiment. [Figure 7] Figure 7 is a cross-sectional view showing a silicon carbide semiconductor device according to a modified embodiment. [Figure 8]Figure 8 is a cross-sectional view showing a silicon carbide semiconductor device according to a modified embodiment. [Figure 9] Figure 9 is a cross-sectional view showing a silicon carbide semiconductor device according to a modified embodiment. [Figure 10] Figure 10 is a cross-sectional view (part 1) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 11] Figure 11 is a cross-sectional view (part 2) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 12] Figure 12 is a cross-sectional view (part 3) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 13] Figure 13 is a cross-sectional view (part 4) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 14] Figure 14 is a cross-sectional view (part 5) showing a method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Modes for carrying out the invention]
[0009] The implementation methods are described below.
[0010] [Description of Embodiments in this Disclosure] The embodiments of this disclosure are first listed and described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description of them is not repeated.
[0011] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure comprises: a silicon carbide substrate having a first main surface on which a p-type semiconductor region and an n-type semiconductor region are exposed; an alloy layer provided on the first main surface and containing nickel, silicon, and aluminum; a barrier layer provided on the alloy layer; and an electrode provided on the barrier layer and containing aluminum, wherein the alloy layer has a first alloy region provided on the p-type semiconductor region and a second alloy region provided on the n-type semiconductor region, the aluminum concentration in the first alloy region is higher than the aluminum concentration in the second alloy region; and the barrier layer has a first barrier region provided on the first alloy region and a second barrier region provided on the second alloy region, the thickness of the first barrier region is thinner than the thickness of the second barrier region. In this case, the first alloy region with a high aluminum concentration is ohmic bonded with the p-type semiconductor region, and the second alloy region with a low aluminum concentration is ohmic bonded with the n-type semiconductor region. Therefore, the contact resistance between the p-type semiconductor region and the n-type semiconductor region and the alloy layer can be reduced.
[0012] [2] A silicon carbide semiconductor device according to another aspect of the present disclosure comprises: a silicon carbide substrate having a first main surface on which a p-type semiconductor region and an n-type semiconductor region are exposed; an alloy layer provided on the first main surface; a barrier layer provided on the alloy layer; and an electrode containing aluminum provided on the barrier layer, wherein the alloy layer has a first alloy region provided on the p-type semiconductor region and containing nickel, silicon, and aluminum; and a second alloy region provided on the n-type semiconductor region and containing nickel, silicon, and not aluminum; and the barrier layer has a first barrier region provided on the first alloy region and a second barrier region provided on the second alloy region, wherein the thickness of the first barrier region is thinner than the thickness of the second barrier region. In this case, the first alloy region containing aluminum is ohmic bonded with the p-type semiconductor region, and the second alloy region not containing aluminum is ohmic bonded with the n-type semiconductor region. Therefore, the contact resistance between the p-type semiconductor region and the n-type semiconductor region and the alloy layer can be reduced.
[0013] In [3], [1] or [2], the first barrier region and the second barrier region have a laminated structure of a titanium film and a titanium nitride film, and the thickness of the titanium nitride film in the first barrier region may be thinner than the thickness of the titanium nitride film in the second barrier region. In this case, while diffusing aluminum into the alloy layer on the p-type semiconductor region, it is easy to suppress the diffusion of aluminum into the alloy layer on the n-type semiconductor region.
[0014] 〔4〕 A method for manufacturing a silicon carbide semiconductor device according to another aspect of the present disclosure includes a step of preparing a silicon carbide substrate having a first main surface on which a p-type semiconductor region and an n-type semiconductor region are exposed, a step of forming an alloy layer containing nickel and silicon on the p-type semiconductor region and the n-type semiconductor region, a step of forming a barrier layer on the alloy layer, a step of etching at least a part of the barrier layer formed on the p-type semiconductor region, and a step of diffusing aluminum into at least the alloy layer formed on the p-type semiconductor region by forming an aluminum-containing electrode on the barrier layer after the etching step. In this case, a silicon carbide semiconductor device in which an alloy region having a high aluminum concentration forms an ohmic contact with the p-type semiconductor region and an alloy region having a low aluminum concentration or containing no aluminum forms an ohmic contact with the n-type semiconductor region can be manufactured. Therefore, the contact resistance between the p-type semiconductor region, the n-type semiconductor region, and the alloy layer can be reduced.
[0015] 〔5〕 In [4], the barrier layer has a laminated structure of a titanium film and a titanium nitride film, and in the etching step, the titanium nitride film may be etched without etching the titanium film. In this case, while diffusing aluminum into the alloy layer on the p-type semiconductor region, it is easy to suppress the diffusion of aluminum into the alloy layer on the n-type semiconductor region.
[0016] 〔6〕 In [4] or [5], the diffusing step may include a step of forming an aluminum film on the barrier layer and a step of heat-treating the aluminum film after the forming step. In this case, the diffusion of aluminum into the barrier layer and the alloy layer is promoted.
[0017] [7] In [4] or [5], the diffusion step may include the step of forming an aluminum film on the barrier layer and the step of cooling the aluminum film during the film formation step. In this case, cracks will form in the parts of the barrier layer that are thin, making it easier for the aluminum to diffuse into the barrier layer. This promotes the diffusion of aluminum into the alloy layer on the p-type semiconductor region.
[0018] [Details of the embodiments of this disclosure] The embodiments of this disclosure will be described in detail below, but this disclosure is not limited to these embodiments.
[0019] (Silicon carbide semiconductor device) Referring to Figures 1 to 5, an embodiment of the silicon carbide semiconductor device will be described. Figure 1 is a plan view showing the silicon carbide semiconductor device according to the embodiment. Figures 2 to 5 are cross-sectional views showing the silicon carbide semiconductor device according to the embodiment. Figure 2 corresponds to a cross-sectional view along line II-II in Figure 1. Figure 3 corresponds to a cross-sectional view along line III-III in Figure 1. Figure 4 corresponds to a cross-sectional view along line IV-IV in Figure 1. Figure 5 is an enlarged view of a part of Figure 4.
[0020] As shown in Figures 1 to 5, the silicon carbide semiconductor device according to this embodiment is a so-called trench-type MOSFET 100. The MOSFET 100 mainly comprises a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, and a drain electrode 70.
[0021] The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 located on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, polytype 4H hexagonal silicon carbide. The silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has an n-type structure.
[0022] In this embodiment, a field-effect transistor is formed on the silicon carbide substrate 10 as an example of a semiconductor device. The silicon carbide epitaxial layer 40 mainly consists of a drift region 11, a body region 12, a source region 13, and a contact region 18.
[0023] The drift region 11 contains n-type impurities such as nitrogen or phosphorus (P), and has an n-type configuration.
[0024] The body region 12 is provided on the drift region 11. The body region 12 contains p-type impurities such as aluminum (Al) and has a p-type composition.
[0025] The source region 13 is provided on the body region 12 such that it is separated from the drift region 11 by the body region 12. The source region 13 contains n-type impurities such as nitrogen or phosphorus and has an n-type semiconductor structure. The source region 13 constitutes the first main surface 1. The source region 13 is an example of an n-type semiconductor region.
[0026] The contact region 18 contains p-type impurities, such as aluminum, and has a p-type structure. The contact region 18 constitutes the first main surface 1. The contact region 18 penetrates the source region 13 and is in contact with the body region 12. The contact region 18 is an example of a p-type semiconductor region.
[0027] Multiple gate trenches 5 are provided on the first main surface 1. The gate trenches 5 extend in a first direction parallel to the first main surface 1, for example, and the multiple gate trenches 5 are arranged in a second direction. The gate trenches 5 have a bottom surface 4 consisting of a drift region 11. The bottom surface 4 is, for example, a plane parallel to the second main surface 2. The gate trenches 5 have side surfaces 3 that penetrate the contact region 18, the source region 13, and the body region 12 and connect to the bottom surface 4. The side surfaces 3 are, for example, perpendicular to the plane containing the bottom surface 4.
[0028] The gate insulating film 81 is in contact with the side surface 3 and the bottom surface 4. The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of a material containing, for example, silicon dioxide. The gate insulating film 81 is in contact with the drift region 11 at the bottom surface 4. The gate insulating film 81 is in contact with the contact region 18, the source region 13, the body region 12, and the drift region 11 at the side surface 3.
[0029] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon containing conductive impurities. The gate electrode 82 is positioned inside the gate trench 5.
[0030] The interlayer insulating film 83 is in contact with the gate insulating film 81 and the gate electrode 82. The interlayer insulating film 83 is made of a material containing, for example, silicon dioxide. Contact holes 90 are formed in the interlayer insulating film 83 at regular intervals in a second direction. The contact holes 90 are arranged such that the gate trench 5 is located between adjacent contact holes 90 in the second direction. The contact holes 90 extend in a first direction. The source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 through the contact holes 90.
[0031] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 is electrically insulated from the gate electrode 82 by an interlayer insulating film 83. The source electrode 60 has an alloy layer 61, a metal layer 62, a barrier layer 63, and a source wiring 64.
[0032] The alloy layer 61 is provided within the contact hole 90. The alloy layer 61 is provided on the first main surface 1. On the first main surface 1, the alloy layer 61 is in contact with the source region 13 and the contact region 18. The alloy layer 61 is connected to the silicon carbide substrate 10 through the contact hole 90. The alloy layer 61 has a first alloy region 61a and a second alloy region 61b.
[0033] The first alloy region 61a is in contact with the contact region 18. The first alloy region 61a is ohmic-bonded to the contact region 18. The first alloy region 61a is composed of a material containing, for example, nickel (Ni), silicon (Si), and aluminum. The first alloy region 61a is formed of, for example, a NiSiAl alloy.
[0034] The second alloy region 61b is in contact with the source region 13. The second alloy region 61b is ohmic-jointed with the source region 13. The second alloy region 61b is composed of a material containing, for example, nickel, silicon, and aluminum. The second alloy region 61b is formed of, for example, a NiSiAl alloy. The second alloy region 61b may be composed of a material containing nickel and silicon but not aluminum. The second alloy region 61b may be formed of, for example, a NiSi alloy.
[0035] The aluminum concentration in the first alloy region 61a is higher than that in the second alloy region 61b. In this case, the first alloy region 61a, with its higher aluminum concentration, forms an ohmic bond with the contact region 18, while the second alloy region 61b, with its lower aluminum concentration, forms an ohmic bond with the source region 13. This reduces the contact resistance between the contact region 18 and the source region 13 and the alloy layer 61.
[0036] The metal layer 62 covers the upper and side surfaces of the interlayer insulating film 83. The metal layer 62 is formed of, for example, a Ni film.
[0037] The barrier layer 63 is provided on the alloy layer 61 and the metal layer 62. The barrier layer 63 covers the alloy layer 61 and the metal layer 62. The barrier layer 63 is in contact with the alloy layer 61 and the metal layer 62. The barrier layer 63 has a first barrier region 63a, a second barrier region 63b, and a third barrier region 63c.
[0038] The first barrier region 63a is provided on the first alloy region 61a. The first barrier region 63a is in contact with the first alloy region 61a. The first barrier region 63a has a laminated structure of a titanium film 63d and a titanium nitride film 63e, for example, as shown in Figure 5. The first barrier region 63a may also consist only of a titanium film 63d, without including a titanium nitride film 63e.
[0039] The second barrier region 63b is provided on the second alloy region 61b. The second barrier region 63b is in contact with the second alloy region 61b. The second barrier region 63b has a laminated structure of a titanium film 63f and a titanium nitride film 63g, as shown in Figure 5, for example. The thickness of the titanium film 63f in the second barrier region 63b may be, for example, 5 nm. The thickness of the titanium nitride film 63g in the second barrier region 63b may be, for example, 100 nm.
[0040] The thickness of the first barrier region 63a is thinner than the thickness of the second barrier region 63b. The thickness of the titanium nitride film 63e within the first barrier region 63a may be thinner than the thickness of the titanium nitride film 63g within the second barrier region 63b. In this case, it is easier to diffuse aluminum into the first alloy region 61a while suppressing the diffusion of aluminum into the second alloy region 61b. The ratio of the thickness of the first barrier region 63a to the thickness of the second barrier region 63b may be, for example, 1:2 to 1:10.
[0041] The third barrier region 63c is provided on the metal layer 62. The third barrier region 63c covers the metal layer 62. The third barrier region 63c has, for example, a laminated structure of a titanium film and a titanium nitride film.
[0042] The source wiring 64 is provided on top of the barrier layer 63. The source wiring 64 covers the barrier layer 63. The source wiring 64 is in contact with the barrier layer 63. The source wiring 64 is made of a material that includes, for example, aluminum. The source wiring 64 is an example of an electrode.
[0043] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 on the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing, for example, nickel silicide. The drain electrode 70 may be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 is ohmic bonded to the silicon carbide single crystal substrate 50.
[0044] As described above, according to the MOSFET 100 of the embodiment, a p-type contact region 18 and an n-type source region 13 are formed on the silicon carbide substrate 10. A first alloy region 61a with a high aluminum concentration is provided on the contact region 18, and a second alloy region 61b with a low aluminum concentration is provided on the source region 13. In this case, the first alloy region 61a with a high aluminum concentration is ohmic-bonded to the contact region 18, and the second alloy region 61b with a low aluminum concentration is ohmic-bonded to the source region 13. Therefore, the contact resistance between the contact region 18 and the source region 13 and the alloy layer 61 can be reduced.
[0045] The aluminum concentrations in the first alloy region 61a and the second alloy region 61b can be measured, for example, by energy dispersive X-ray spectroscopy (EDX).
[0046] In the above embodiment, the case in which the silicon carbide semiconductor device is a so-called trench-type MOSFET 100 was described, but it is not limited to this. For example, the silicon carbide semiconductor device may be a so-called planar-type MOSFET 200.
[0047] Figure 6 is a plan view showing a silicon carbide semiconductor device according to a modified embodiment. Figures 7 to 9 are cross-sectional views showing a silicon carbide semiconductor device according to a modified embodiment. Figure 7 corresponds to a cross-sectional view along line VII-VII in Figure 6. Figure 8 corresponds to a cross-sectional view along line VIII-VIII in Figure 6. Figure 9 corresponds to a cross-sectional view along line IX-IX in Figure 6.
[0048] As shown in Figures 6 to 9, the MOSFET 200 does not have a gate trench 5 on the first main surface 1 of the silicon carbide substrate 10, and the gate insulating film 81 and gate electrode 82 are formed on the first main surface 1 in that order.
[0049] MOSFET200 has a silicon carbide substrate 10. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide epitaxial layer 40 has a drift region 11, a p region 15, and an n region 16. The p region 15 and the n region 16 are exposed on the first main surface 1. The p region 15 is an example of a p-type semiconductor region. The n region 16 is an example of an n-type semiconductor region. Other configurations of MOSFET200 may be the same as those of MOSFET100.
[0050] The MOSFET200 according to a modified embodiment also exhibits the same effects and advantages as the MOSFET100 according to the embodiment.
[0051] (Manufacturing method for silicon carbide semiconductor devices) A method for manufacturing the MOSFET 100 according to the embodiment will now be described. Figures 10 to 14 are cross-sectional views showing the method for manufacturing the MOSFET 100 according to the embodiment. Figures 10 to 14 correspond to cross-sectional views along the line IV-IV in Figure 1.
[0052] First, a silicon carbide substrate 10 is prepared, having a first main surface 1 in which the source region 13 and the contact region 18 are exposed, as shown in Figure 10.
[0053] The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 located on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide epitaxial layer 40 mainly has a drift region 11, a body region 12, a source region 13, and a contact region 18. The first main surface 1 is provided with a plurality of gate trenches 5 (Figures 2 and 3). Each gate trench 5 is provided with a gate insulating film 81, a gate electrode 82, and an interlayer insulating film 83 (Figures 2 and 3).
[0054] Next, as shown in Figure 11, a metal film (not shown) for the alloy layer 61 that contacts the source region 13 and the contact region 18 is formed on the first main surface 1, and a metal film for the drain electrode 70 that contacts the silicon carbide single crystal substrate 50 is formed on the second main surface 2. The metal film for the alloy layer 61 and the metal film for the drain electrode 70 are formed, for example, by sputtering. The metal film for the alloy layer 61 and the metal film for the drain electrode 70 are made of a material containing nickel, for example.
[0055] Next, alloying annealing is performed. The metal film for the alloy layer 61 and the metal film for the drain electrode 70 are held at a temperature of, for example, 900°C to 1100°C for about 5 minutes. As a result, at least a portion of the metal film for the alloy layer 61 and at least a portion of the metal film for the drain electrode 70 react with the silicon contained in the silicon carbide substrate 10 and silicide. This forms the alloy layer 61 which is ohmic bonded to the source region 13 and the contact region 18, and the drain electrode 70 which is ohmic bonded to the silicon carbide single crystal substrate 50.
[0056] Next, as shown in Figure 12, a barrier layer 63 is formed on the alloy layer 61. The barrier layer 63 is formed, for example, by sputtering. The barrier layer 63 has a laminated structure of, for example, a titanium film formed on the alloy layer 61 and a titanium nitride film formed on the titanium film.
[0057] Next, as shown in Figure 13, a resist pattern 30 having an opening 30a is formed on the contact region 18. Specifically, a photoresist is applied to the contact region 18, and exposure and development are performed using an exposure apparatus to form a resist pattern 30 having an opening 30a. After this, at least a portion of the barrier layer 63 in the opening 30a of the resist pattern 30 is removed by etching, such as by reactive ion etching (RIE). As a result, a thin barrier layer 63 (first barrier region 63a) is formed on the contact region 18, and a thicker barrier layer 63 (second barrier region 63b) is formed on the source region 13. In etching the barrier layer 63, a portion of the titanium nitride film is removed by etching without etching the titanium film. In this case, when forming the source wiring 64, it is easier to diffuse aluminum into the alloy layer 61 on the contact region 18 while suppressing the diffusion of aluminum into the alloy layer 61 on the source region 13. In etching the barrier layer 63, the titanium nitride film and a portion of the titanium film may also be etched. After this, the resist pattern 30 is removed using an organic solvent or the like.
[0058] Next, as shown in Figure 14, source wiring 64 is formed. Specifically, source wiring 64 is formed to cover the barrier layer 63. Source wiring 64 is formed, for example, by sputtering. Source wiring 64 is formed, for example, while heating the barrier layer 63. Source wiring 64 is made of a material containing aluminum, for example. The conditions for forming source wiring 64 are that the aluminum contained in source wiring 64 diffuses into the alloy layer 61 on the contact region 18.
[0059] The thickness of the first barrier region 63a is thinner than the thickness of the second barrier region 63b. In this case, aluminum diffuses easily into the region of the alloy layer 61 that is in contact with the first barrier region 63a, while it does not diffuse easily into the region of the alloy layer 61 that is in contact with the second barrier region 63b. Therefore, a NiSiAl alloy with a high aluminum concentration is formed in the region of the alloy layer 61 that is in contact with the first barrier region 63a, and a NiSiAl alloy with a low aluminum concentration or a NiSi alloy that does not contain aluminum is formed in the region of the alloy layer 61 that is in contact with the second barrier region 63b. In this way, a first alloy region 61a with a high aluminum concentration is formed on the contact region 18, and a second alloy region 61b with a low aluminum concentration is formed on the source region 13.
[0060] After the source wiring 64 is formed on the barrier layer 63, the source wiring 64 may be heat-treated at a temperature of, for example, 400°C to 500°C. In this case, the diffusion of aluminum into the barrier layer 63 and the alloy layer 61 is promoted.
[0061] When forming the source wiring 64, the source wiring 64 may be cooled during the film deposition process. In this case, cracks may form in the first barrier region 63a where the barrier layer 63 is thin, making it easier for aluminum to diffuse into the first barrier region 63a. This promotes the diffusion of aluminum into the alloy layer 61 (first alloy region 61a) on the contact region 18. For example, a source wiring 64 with half the target film thickness may be formed, then the source wiring 64 may be air-cooled, and then a source wiring 64 with the remaining half the target film thickness may be formed.
[0062] In this way, the silicon carbide semiconductor device 100 according to the embodiment can be manufactured.
[0063] As described above, according to the manufacturing method of the silicon carbide semiconductor device 100 according to the embodiment, first, at least a portion of the barrier layer 63 formed on the contact region 18 is etched. Next, by forming source wiring 64 on the barrier layer 63, aluminum is diffused into at least the alloy layer 61 formed on the contact region 18. In this case, a silicon carbide semiconductor device can be manufactured in which the first alloy region 61a with a high aluminum concentration is ohmic bonded with the contact region 18, and the second alloy region 61b with a low aluminum concentration or no aluminum is ohmic bonded with the source region 13. Therefore, the contact resistance between the contact region 18 and the source region 13 and the alloy layer 61 can be reduced.
[0064] Although embodiments have been described in detail above, the invention is not limited to any particular embodiment, and various modifications and changes are possible within the scope described in the claims. [Explanation of Symbols]
[0065] 1. First main surface 2. Second main surface 3 Sides 4. Bottom 5 Gate Trench 10 Silicon carbide substrate 11. Drift Region 12 Body Region 13 Source Area 15 p region 16 n-region 18 Contact Area 30 Resist Patterns 30a opening 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 source electrodes 61 Alloy layer 61a 1st alloy region 61b 2nd alloy region 62 Metal layer 63 Barrier layer 63a First barrier region 63b Second barrier region 63c Third barrier area 63d titanium film 63e Titanium Nitride Film 63f titanium film 63g Titanium Nitride Film 64 Source Wiring 70 Drain electrode 81 Gate Insulator 82 Grid gate 83 Interlayer insulating film 90 Contact Holes 100 Silicon Carbide Semiconductor Devices
Claims
1. A silicon carbide substrate having a first main surface in which a p-type semiconductor region and an n-type semiconductor region are exposed, An alloy layer comprising nickel, silicon, and aluminum is provided on the first main surface, A barrier layer provided on the alloy layer, An electrode containing aluminum is provided on the barrier layer, Equipped with, The alloy layer has a first alloy region provided on the p-type semiconductor region and a second alloy region provided on the n-type semiconductor region. The concentration of aluminum in the first alloy region is higher than the concentration of aluminum in the second alloy region. The barrier layer has a first barrier region provided on the first alloy region and a second barrier region provided on the second alloy region. The thickness of the first barrier region is thinner than the thickness of the second barrier region. Silicon carbide semiconductor device.
2. A silicon carbide substrate having a first main surface in which a p-type semiconductor region and an n-type semiconductor region are exposed, An alloy layer provided on the first main surface, A barrier layer provided on the alloy layer, An electrode containing aluminum is provided on the barrier layer, Equipped with, The aforementioned alloy layer is A first alloy region containing nickel, silicon, and aluminum is provided on the aforementioned p-type semiconductor region, A second alloy region is provided on the aforementioned n-type semiconductor region, and contains nickel and silicon but does not contain aluminum. It has, The barrier layer has a first barrier region provided on the first alloy region and a second barrier region provided on the second alloy region. The thickness of the first barrier region is thinner than the thickness of the second barrier region. Silicon carbide semiconductor device.
3. The first barrier region and the second barrier region have a laminated structure of a titanium film and a titanium nitride film. The thickness of the titanium nitride film in the first barrier region is thinner than the thickness of the titanium nitride film in the second barrier region. A silicon carbide semiconductor device according to claim 1 or claim 2.
4. A step of preparing a silicon carbide substrate having a first main surface in which a p-type semiconductor region and an n-type semiconductor region are exposed, A step of forming an alloy layer containing nickel and silicon on the p-type semiconductor region and the n-type semiconductor region, A step of forming a barrier layer on the alloy layer, A step of etching at least a portion of the barrier layer formed on the p-type semiconductor region, After the etching step, the process involves forming an electrode containing aluminum on the barrier layer, thereby diffusing aluminum into the alloy layer formed on at least the p-type semiconductor region. Having, A method for manufacturing silicon carbide semiconductor devices.
5. The barrier layer has a laminated structure of a titanium film and a titanium nitride film. In the etching step, the titanium nitride film is etched without etching the titanium film. A method for manufacturing a silicon carbide semiconductor device according to claim 4.
6. The aforementioned diffusion step is, A step of forming an aluminum film on the barrier layer, The process of heat-treating the aluminum film after the film formation process, Having, A method for manufacturing a silicon carbide semiconductor device according to claim 4 or claim 5.
7. The aforementioned diffusion step is, A step of forming an aluminum film on the barrier layer, The process of forming the aforementioned film includes a step of cooling the aluminum film during the process, Having, A method for manufacturing a silicon carbide semiconductor device according to claim 4 or claim 5.