Method for adjusting the temperature conditions of an epitaxy process.

Abstract

The method includes the steps of: a) selecting a type of test substrate having a thickness 20%-40% less than normal for a given substrate diameter and / or having an interstitial oxygen concentration less than 10 ppma and / or including an SOI stack including a dielectric layer and a thin film of monocrystalline silicon having a thickness of 300 nm or less; b) fixing initial temperature conditions, said conditions defining the temperatures to be applied to the two regions; c) forming a layer on the selected type of test substrate by applying an epitaxy process at the initial temperature conditions and then measuring the slip-line defects; d) fixing the new temperature conditions by varying the temperature applied to the two regions of the substrate; f) comparing the amount of slip-line defects measured on the test structure and selecting the temperature conditions that generate the least amount of slip-line defects.

Description

Technical Field

[0001] (Field of the Invention) The present invention relates to a setting method for adjusting temperature conditions for obtaining minimum thermal stress before processing a receiving substrate. This preset ensures the quality of the substrate at the end of the epitaxy process and guarantees the optimal use of the associated epitaxy apparatus.

[0002] (Technical Context of the Invention) Epitaxy methods for growing layers containing silicon are commonly used in the fields of semiconductor materials and microelectronics. Associated apparatuses typically incorporate an epitaxy chamber in which the atmosphere (nature of the gas and pressure) and temperature are controlled and the substrate to be processed is held on a support.

[0003] With the increase in the diameter of processed substrates (200 mm, 300 mm, and even 450 mm) accompanied by densification of elements per substrate, defects generated during manufacturing steps (and thus particularly during epitaxy) must be carefully controlled and limited as much as possible. Defects such as slip lines are particularly important because they can affect large areas of the substrate, and those defects are typically defects generated during high-temperature heat treatment to which epitaxy growth belongs.

[0004] Typically, it is normal to determine the process window (especially regarding temperature conditions) for a given epitaxy process, which is typically constituted by the formation of a useful layer on a receiving substrate. The characteristics of the receiving substrate to be processed and the useful layer to be formed (composition, thickness, crystal structure, and quality) are defined to obtain a given structure at the end of the epitaxy process. Processing the receiving substrate within the process window makes it possible to obtain an adapted final structure with respect to the dimensional characteristics of the useful layer as well as with respect to the overall quality (amount of defects not exceeding the specified limits), as shown in FIG. 1.

[0005] Generally, this process window is checked periodically by processing test substrates between batches of acceptor substrates.

[0006] Sometimes, the definition of the process window is not precise enough to ensure uniform behavior of all acceptor substrates. In fact, since the physical properties of acceptor substrates can vary within the same batch or between consecutive batches, it is not uncommon to observe quality variations among final structures, even when epitaxy is applied in a similar manner within the process window. Quality variations, in particular, can lead to the uncontrollable appearance of slip lines in some structures. In addition to yield loss, such variations result in interruptions in the use of epitaxy equipment requiring further adjustments, thus reducing the uptime of the epitaxy equipment.

[0007] (Purpose of the invention) The present invention proposes a solution to correct the above-mentioned problems. The present invention relates to a setup method for an epitaxy process intended to form a useful layer on a receiving substrate in an epitaxy apparatus, the setup method being performed before processing the receiving substrate to adjust the temperature conditions of the epitaxy process so that thermal stress on the substrate to be processed is minimized. The setup method ensures high reproducibility of the behavior of the receiving substrate after the epitaxy process is applied, particularly with respect to the absence (or very low occurrence) of slip line defects on the final structure.

[0008] (Brief description of the invention) The present invention proposes a setup method for an epitaxy process intended to form a useful layer on a receiving substrate within an epitaxy apparatus, wherein the layer and the substrate contain silicon. The setup method is performed before processing the receiving substrate, and the setup method is a) A thickness of 725 microns and 775 microns, which are 20% to 40% smaller than the normal thickness for a given substrate diameter, and / or a thickness of 725 microns and 775 microns, which are the normal thicknesses for diameters of 200 mm and 300 mm, respectively. Having an interstitial oxygen concentration of less than 10 ppm (ASTM'79), and / or The SOI laminate includes a dielectric layer and a thin film of single-crystal silicon with a thickness of 300 nm or less. a)) a))))))))))))))))))))))))))))))))) c) To obtain an initial test structure, a useful layer is formed on a selected type of test substrate by applying an epitaxy process under initial temperature conditions, and then slip line defects are measured on the initial test structure. d) A step of fixing new temperature conditions by changing the temperature applied to at least two regions of the substrate compared to the initial temperature conditions, e) To obtain a new test structure, a useful layer is formed on a new test substrate of a selected type by applying an epitaxy process under new temperature conditions, and then slip line defects are measured on the new test structure. f) The process includes comparing the measured amount of slipline defects on multiple test structures and selecting the temperature conditions for the epitaxy process that generate the fewest slipline defects. Other advantages and non-limiting features of the present invention, as interpreted individually or in any technically feasible combination, Steps d) and e) are repeated once or more times under other new temperature conditions before step f). The epitaxy apparatus is equipped with multiple epitaxy chambers. Steps b) and d) are performed in parallel, not sequentially, and each of these steps is applied to a different epitaxy chamber, and then Steps c) and e) are carried out in parallel, with the initial and new test substrates placed in the different chambers. Steps d) and e) are repeated once or multiple times after step f) under other new temperature conditions, and then step f) is repeated. Steps d) and e) are repeated between 2 and 5 times. Slip line defects are measured using a surface scanning optical tool. The target is narrowed to address slip line defects of less than 20 mm, and preferably less than 5 mm in cumulative slip line length. The temperature conditions define the temperature applied to the central and peripheral regions of the substrate being processed within the epitaxy apparatus. The temperature conditions define the temperature offset(s) applied between the central region of the substrate being processed in the epitaxy apparatus and the three peripheral regions. Between the initial temperature conditions and the new temperature conditions, the temperature fluctuation applied to at least two regions of the substrate ranges from -30°C to +30°C. The epitaxy process involves a pressure between ultra-high vacuum and atmospheric pressure, and a temperature between 600°C and 1200°C, in an atmosphere containing at least one gas selected from TCS, DCS, SiH4, SiCl4, Si2H4, Si3H8, and GeH4. The useful layer formed during the epitaxy process is made of silicon and has a thickness between 0.3 microns and 30 microns. The useful layer formed during the epitaxy process is made of silicon germanium and has a thickness between 50 nm and 1000 nm.

[0009] The present invention also relates to an epitaxy method that carries out an epitaxy process intended to form a useful layer on a receiving substrate in an epitaxy apparatus, wherein the layer and the substrate contain silicon, the setting method described above is performed before processing the receiving substrate, and the receiving substrate is an SOI substrate. [Brief explanation of the drawing]

[0010] Other features and advantages of the present invention will be revealed in the following detailed description of the invention with reference to the attached figures. [Figure 1]A graph showing a typical process window for an epitaxy process, for example, the temperature conditions are adjusted as a function of the defects obtained on the test wafer. [Figure 2] A map showing the defect level (slip line defect) of the structure obtained from step c) of the setting method according to the present invention. [Figure 3] A map showing the defect level of the structure obtained after step e) of the setting method according to the present invention. [Figure 4] A comparison between the conventional process window and the narrow process window determined by using the setting method according to the present invention is shown. [Figure 5] An embodiment of the setting method according to the present invention is shown. [[ID=IS=13]] [Figure 6] Another embodiment of the setting method according to the present invention is shown.

Mode for Carrying Out the Invention

[0011] (Detailed Description of the Invention) The present invention relates to a setting method for an epitaxy process intended to form a useful layer on a receiving substrate in an epitaxy apparatus, wherein the layer and the substrate contain silicon.

[0012] The receiving substrate is made of single crystal silicon or mostly formed of single crystal silicon. In particular, the receiving substrate can be a silicon-on-insulator substrate (SOI) in which the silicon top layer has a thickness ranging from 0.1 to 2.0 microns, the embedded silicon oxide has a thickness ranging from 0.05 to 5.0 microns, and the base wafer is formed of silicon.

[0013] The receiving substrate can take the form of a circular wafer with a standard size, for example, having a diameter of 200 mm or 300 mm, or even 450 mm, as is common in the field of microelectronics. The substrate has a normal thickness for a given diameter, typically 725 microns, 775 microns, and 925 microns being the normal thicknesses for diameters of 200 mm, 300 mm, and 450 mm, respectively.

[0014] The useful layer constructed by epitaxial growth on the top of the receiving substrate can be made of polycrystalline silicon or single-crystalline silicon with a thickness ranging from 0.3 microns to 30 microns. 1E13 / cm 3 ~ about 1E19 / cm 3 It may be p-type or n-type doped.

[0015] Alternatively, the useful layer can be made of silicon germanium with a thickness ranging from 50 nm to 1000 nm.

[0016] The epitaxy process to which the setting method of the present invention is applied is based on chemical vapor deposition technology (CVD). Typically, it includes temperatures ranging from 600 °C (SiGe) or 900 °C (Si) belonging to the high-temperature range to about 1200 °C. Depending on the properties of the target useful layer, the atmosphere may contain at least one gas selected from TCS (trichlorosilane), DCS (dichlorosilane), SiH4 (silane), SiCl4 (silicon tetrachloride), Si2H4 (disilane), Si3H8 (trisilane), GeH4 (germanium), and the pressure during the epitaxy process may be selected between ultra-high vacuum and atmospheric pressure.

[0017] The setting procedure is performed before processing the receiving substrate to determine a precise and preferred process window, i.e., a process window that minimizes the thermal stress observed in the substrate during epitaxial growth in the relevant epitaxy apparatus. Slip line defects are known to be induced by thermal stress applied to the substrate during high-temperature heat treatment. The preferred process window is determined, in particular, to avoid or highly limit the appearance of such defects.

[0018] The setup method first includes step a) selecting a type of silicon-based test substrate that has physical and structural characteristics that are highly sensitive to slipline failure.

[0019] The first type of test substrate corresponds to a silicon-based wafer having a thickness that is 20% to 40% less than the normal thickness of a wafer of the same diameter. For example, for a 200 mm diameter test substrate, the thickness would be selected between 450 and 550 microns, and for a 300 mm diameter test substrate, the thickness would be selected between 500 and 600 microns. The test substrate may be undoped or heavily doped, P-type or N-type. Heavily doped means 1 × 10⁻⁶. 18 / cm 3 This means a higher dopant concentration.

[0020] The applicant has demonstrated that the thickness range selected for the test substrate according to the first type is particularly suitable for improving the process window of the epitaxy process. In fact, smaller thicknesses of the treated substrate increase the appearance of slip lines due to their increased sensitivity to thermal stress. Nevertheless, the thickness is maintained at 60% or more of the normal thickness to avoid side effects such as fracture caused by thermal stress or mechanical handling challenges.

[0021] According to the second type, the test substrate should be 10 ppm (ASTM'79) (i.e., 5E17 Oi / cm²). 3 This is a silicon-based wafer having an interstitial oxygen concentration of less than ).

[0022] The low interstitial oxygen content in the test substrate reduces dislocation adhesion due to oxygen precipitation in silicon, thereby promoting the formation of slip lines during high-temperature processing.

[0023] The third type of test substrate corresponds to a silicon-based wafer having an SOI (Silicon Oxide) laminate on its front surface, the SOI laminate comprising an embedded dielectric layer and a thin top layer of single-crystal silicon with a thickness of 300 nm or less. Typically, the dielectric layer, made of silicon oxide, can have a thickness between 0.5 and 5.0 microns.

[0024] The presence of SOI laminates on a silicon wafer can add to the level of mechanical stress on the test substrate, further increasing its sensitivity to the appearance of slipline defects. The thin top layer of the SOI laminate may also further increase slipline sensitivity due to thermal stress.

[0025] Other types of test substrates can be selected in step a) of the setup method, and by this method, the test substrates exist in any combination of the characteristics of the first, second, and third types. The most accurate process window may be determined from test substrates including thin thickness (first type), low interstitial oxygen content (second type), and SOI laminates (third type) having a thin layer with a thickness of 300 nm or less on its front surface.

[0026] It should be noted that the characteristics of the test substrate are independent of the characteristics of the receiving substrate being processed. The type of test substrate is selected only in relation to its sensitivity to thermal stress, and whatever the properties of those receiving substrates may be, it will help to determine as accurately as possible the temperature conditions for the epitaxy process that will generate the minimum stress on the receiving substrate. In a preferred embodiment, the test substrate(s) used in the setup method are different and independent of the receiving substrate(s) to which the epitaxy process is applied as a whole.

[0027] The setting method then includes step b) fixing an initial temperature condition Ti, which determines the temperature applied to at least two regions of the substrate being processed in the epitaxy apparatus during the epitaxy process.

[0028] Depending on the apparatus, the heating means and their arrangement around the substrate being processed can differ. The heating means is typically based on a lamp system configured to heat the inner (center) and outer (peripheral) regions of the processed substrate, such as the Centura® tool from Applied Materials. Alternatively, the lamp system can be configured to separately offset the temperatures of the three edge regions (referred to as the front, side, and back) of the processed substrate compared to the temperature of the center region, as is the case with the Epsilon® tool from ASM.

[0029] The initial temperature condition Ti may be selected within the available process window, or according to process conditions already used for a pre-treated receiving substrate, or according to the latest optimized process conditions. While the latest optimized process has already been tuned, it should be noted that the minimum stress process conditions may change due to tool drift over time or periodic maintenance.

[0030] Referring to Figure 4, the initial temperature condition Ti can be adopted, for example, at the center of a conventional process window. Note that this conventional process window is conventionally determined directly by using a standard wafer with normal thickness and physical properties, or by using a receptacle substrate. This second option is costly and, naturally, highly dependent on the characteristics of the receptacle substrate.

[0031] The setting method then includes step c) forming a useful layer on a selected type of test substrate by applying an epitaxy process at an initial temperature condition Ti. This leads to obtaining an initial test structure comprising the test substrate and the epitaxy-grown useful layer on top thereof.

[0032] Next, step c) includes measuring slip line defects on the initial test structure.

[0033] Slip line defects are measured using surface scanning optical tools, such as the SP series equipment manufactured by KLA.

[0034] Figure 2 shows an example of a measurement map highlighting slipline defects around the test structure. The amount of such defects is preferentially evaluated as a result of the cumulative length of sliplines across the wafer, ultimately considered to be edge exclusions ranging from 0.5 to 5 mm. In Figure 2, the test structure has a diameter of 200 mm, and the cumulative length of sliplines is approximately 5 × 10⁻⁶. 3 It is mm.

[0035] When the test structure exhibits a large number of slipline defects as shown in Figure 2, it is predicted that the relevant temperature condition Ti of the epitaxy process after step c) of the setup method will not enable stable and reproducible behavior of the acceptor substrate over time, even if a portion of the final structure (the acceptor substrate on which the useful layer has been grown) no longer exhibits any slipline defects. Since different types of test substrates are highly sensitive to slipline defects, the setup method can identify temperature conditions within a conventional process window that can induce excessively high thermal stress in the treated substrate, and such levels of thermal stress make the acceptor substrate susceptible to damage in at least a portion due to variations in the physical properties within or between batches of acceptor substrates.

[0036] The next step in the setup procedure, d), is to fix a new temperature condition Tn by changing the temperature applied to at least two regions of the processed substrate compared to the initial temperature condition Ti.

[0037] It is advantageous that the temperature variation applied to at least two regions of the processed substrate between the initial temperature condition Ti and the new temperature condition Tn ranges from -30°C to +30°C.

[0038] This temperature control between different regions of the processed substrate affects the thermal stress applied to the substrate during epitaxial growth.

[0039] The setting method then includes step e) forming a useful layer on a new test substrate of a selected type by applying an epitaxy process at a new temperature condition Tn. Step e) leads to obtaining a new test structure including the new test substrate and the useful layer grown on top of it. Slip line defects are then measured on the structure using the same tools and methods as in step c).

[0040] Figure 3 shows the measurement map of the new test structure. It is immediately clear that the amount of slip lines has decreased dramatically. Ideally, the target cumulative length of slip lines on the test structure should be less than 20 mm, or even less than 5 mm.

[0041] Step f) of the setup procedure involves comparing the amount of slipline defects measured on the (initial and new) test structures and selecting the temperature conditions for the epitaxy process that generate the fewest slipline defects. The fewest defects ideally correspond to the target cumulative slipline length mentioned above, with the ultimate goal being zero defects.

[0042] If the initial and new test structures do not exhibit the correct level of defects, the setting method is to repeat steps d) and e) once or more for other new temperature conditions Tn', Tn'', Tn'''', etc., after step f). Then, of course, step f) is repeated and compared with the resulting new test structures.

[0043] The setup method may include repeating steps d) and e) once or more times with other new temperature conditions Tn', Tn'', Tn''', etc., before performing step f). The step of comparing the amount of slipline defects is then applied to a set of prepared test structures.

[0044] This is typically possible when the epitaxy apparatus includes multiple epitaxy chambers, each capable of setting different, independent temperature conditions. Therefore, steps b) and d) are performed in parallel rather than sequentially, with each step applied to a different epitaxy chamber. For example, if five chambers are available, step b) will be applied to the first chamber, step d) with the first new temperature condition Tn will be applied to the second chamber, step d) with the second new temperature condition Tn' will be applied to the third chamber, and so on. Thus, a total of five (initial and new) temperature conditions will be fixed in five different chambers.

[0045] Next, steps c) and e) are carried out in parallel, and the initial and new test substrates are placed in the different chambers.

[0046] In step f), the initial test structure treated under the initial temperature condition Ti, and four new test structures treated under individual temperature conditions Tn, Tn', Tn'', and Tn'''' are available for comparison of the amount of slipline.

[0047] Figure 4 shows the narrow process window identified thanks to the setting method of the present invention. This process window corresponds to temperature conditions that result in no slipline defects or only slight slipline defects using one type of highly sensitive test structure defined in the present invention. These temperature conditions ensure very high reproducibility and stability of the behavior of the receiving substrate when processed according to the epitaxy process.

[0048] It is advantageous to repeat steps d) and e) 2 to 5 times before or after step f).

[0049] The epitaxy process based on the temperature conditions selected in step f) can then be carried out in a batch of acceptor substrates.

[0050] Example 1: The epitaxy apparatus is a Centura® tool. The epitaxy process aims to grow a usable silicon layer with a thickness of 20 microns. A bake at 1100°C for 30 seconds is applied at the start of the process, followed by epitaxial growth at 1100°C for 10 minutes.

[0051] The power of the heating system lamp is, Thanks to the internal lamp, the temperature applied to the central region of the substrate being processed, and Thanks to the external lamp, the temperature applied to the peripheral area of ​​the substrate It can be independently adjusted to determine [the value].

[0052] The heating system includes upper and lower lamps facing the front and back of the substrate, respectively, for the central (inner) region and the peripheral (outer) region.

[0053] The baseline conditions are set as follows in this specification. The power ratio of the bottom lamps (inner and outer) is 60%, meaning that the ratio of bottom power to total lamp power is 0.6. The power ratio of the upper inner lamp is 70%, meaning that the ratio of the upper inner lamp power to the total upper lamp power is 0.7. The power ratio of the bottom inner lamp is 45%, which means that the ratio of the bottom inner lamp power to the total bottom lamp power is 0.45.

[0054] The type of test substrate selected for the setup method corresponds to the first type already described. In particular, for 200 mm silicon wafers, a 500 micron thick, heavily boron-doped type (20 lm / cm) is used as the test substrate. Note that other types could also be selected as alternatives.

[0055] The table in Figure 5 shows the various temperature conditions fixed and applied to the test substrate in the first embodiment. Steps d) and e) were performed five times under five new temperature conditions Tn, Tn', Tn'', Tn''', and Tn''''. Temperature variations between different temperature conditions are controlled by increasing or decreasing the percentage of internal power provided by the top and bottom lamps. In this example, the internal power percentage varies from +10% to -25%, similar to the top and bottom lamps.

[0056] This results in an increase or decrease in the temperature difference between the inner and outer zones (i.e., between the central and peripheral regions of the processed substrate). The temperature difference associated with variations in the inner power ratio typically ranges from 3°C to 30°C.

[0057] Please note that the internal power ratio may vary at the top and bottom using different methods.

[0058] After forming useful layers on the initial test structure and five new test structures under the relevant temperature conditions, step f) reveals the presence of slip lines on the initial test substrate and the three other test structures (as shown in the table in Figure 5). The two test structures treated under the temperature conditions referred to as Tn''' and Tn'''' show no slip lines.

[0059] The configuration method allows for the setting of a process window narrower than the conventional process window for the target epitaxy process, and the associated temperature conditions ensure minimal thermal stress on the substrate being processed. Any receiving substrate can then be safely processed within the narrow process window defined by the configuration method.

[0060] Example 2: The epitaxy apparatus is an Epsilon® tool. The epitaxy process aims to grow a usable silicon layer 20 microns thick. A bake at 1100°C for 30 seconds is applied at the start of the process, followed by epitaxial growth at 1100°C for 10 minutes.

[0061] The lamp power of the heating system can be independently adjusted to establish a temperature offset between the central region of the substrate being processed and three edge regions, referred to as the front, side, and rear, and located at 12 o'clock, 3 o'clock, and 6 o'clock, respectively, on the edges of the wafer.

[0062] The baseline conditions are defined as follows in this specification. The core temperature is set to 1100°C. The front offset is -25°C, which corresponds to a front temperature of 1075°C. The side offset is -15°C, which corresponds to a side temperature of 1085°C. The rear offset is -50°C, which corresponds to a rear temperature range of 1050°C.

[0063] The type of test substrate selected for the setup method corresponds to the second type described above. In particular, a 200 mm silicon wafer with a thickness of 725 microns and a low interstitial oxygen content is used as the test substrate. Note that other types could also be selected as alternatives.

[0064] The table in Figure 6 shows the various temperature conditions fixed and applied to the test substrate in the second embodiment. Steps d) and e) were performed five times under five new temperature conditions, such as Tn, Tn'. The temperature change between different temperature conditions was controlled by increasing or decreasing the offset between the central region and the three edge regions.

[0065] In this example, as with all three peripheral regions, the offset varies from +5°C to -20°C. Note that the offset can be modified in different ways for the three edge regions, and therefore the three edge regions are controlled separately. For example, the offsets for the front, side, and rear regions could be selected at -10°C, -5°C, and -7°C, respectively, to fine-tune the temperature conditions that allow for lower thermal stress.

[0066] After forming useful layers on the initial test structure and five new test structures under the relevant temperature conditions, step f) reveals the presence of slip lines on the initial test structure and three other test structures (as shown in the table in Figure 6). Two test structures treated under the temperature conditions designated Tn''' and Tn'''' show no slip lines.

[0067] In this second embodiment, similarly, the setting method allows for the establishment of a process window narrower than the conventional process window for the target epitaxy process, and the associated temperature conditions ensure minimal thermal stress on the substrate being processed. Any receiving substrate can then be safely processed within the narrow process window established by the setting method.

[0068] Naturally, the present invention is not limited to the embodiments described, and a variety of realizations can be added without exceeding the scope of the invention as defined by the claims.

Claims

1. A setup method for an epitaxy process intended to form a useful layer on a receiving substrate within an epitaxy apparatus, wherein the layer and the substrate comprise silicon, the setup method is performed before processing the receiving substrate, and the setup method is a) Thicknesses that are 20% to 40% smaller than the normal thickness for a given substrate diameter, such as 725 microns and 775 microns, which are the normal thicknesses for diameters of 200 mm and 300 mm, respectively, and / or Having an interstitial oxygen concentration of less than 10 ppma (ASTM '79), and / or The SOI laminate includes a dielectric layer with a thickness in the range of 0.5 to 5.0 microns and a thin film of single-crystal silicon with a thickness of 300 nm or less. The steps include selecting a type of test substrate from among silicon-based wafers that is different from the receiving substrate, b) A step of fixing initial temperature conditions, wherein the conditions are defined as temperatures applied to at least two regions of the substrate to be processed in the epitaxy apparatus, c) A step of forming the useful layer on the selected type of test substrate by applying the epitaxy process under the initial temperature conditions to obtain an initial test structure, and then measuring slip line defects on the initial test structure, d) A step of fixing new temperature conditions by changing the temperature applied to the at least two regions of the substrate being processed in the epitaxy apparatus, compared to the initial temperature conditions; e) A step of forming the useful layer on a new test substrate of the selected type by applying the epitaxy process under the new temperature conditions to obtain a new test structure, and then measuring slip line defects on the new test structure, f) A step of comparing the measured amount of slip line defects on multiple test structures and selecting the temperature conditions of the epitaxy process that generate the fewest slip line defects. Instructions for setting it up, including the setup method.

2. The setting method according to claim 1, wherein steps d) and e) are repeated once or more times under other new temperature conditions before step f).

3. The epitaxy apparatus comprises multiple epitaxy chambers, Steps b) and d) are performed in parallel, not sequentially, and each of these steps is applied to a different epitaxy chamber, and then Steps c) and e) are carried out in parallel, and the initial and new test substrates are placed in the different chambers. The setting method according to claim 1 or 2.

4. Steps d) and e) are repeated once or multiple times after step f) under other new temperature conditions. Next, step f) is repeated. The setting method according to claim 1.

5. The setting method according to any one of claims 2 to 4, wherein steps d) and e) are repeated between 2 and 5 times.

6. The setting method according to any one of claims 1 to 5, wherein the measurement of the slip line defect is performed using a surface scanning optical tool.

7. The setting method according to claim 6, wherein the target is narrowed down so that the amount of slip line defects corresponds to a cumulative slip line length of less than 20 mm, preferably less than 5 mm.

8. The setting method according to any one of claims 1 to 7, wherein the temperature conditions determine the temperature applied to the central and peripheral regions of the substrate processed in the epitaxy apparatus.

9. The setting method according to any one of claims 1 to 7, wherein the temperature conditions determine the temperature offset(s) applied between the central region and three peripheral regions of the substrate processed in the epitaxy apparatus.

10. The setting method according to any one of claims 1 to 9, wherein the change in temperature applied to at least two regions of the substrate between the initial temperature condition and the new temperature condition ranges from -30°C to +30°C.

11. The epitaxy process is TCS, DCS, SiH ４ SiCl ４ Si ２ H ４ Si ３ H ８ GeH ４ A setting method according to any one of claims 1 to 10, comprising an atmosphere containing at least one gas selected from, a pressure between ultra-high vacuum and atmospheric pressure, and a temperature between 600°C and 1200°C.

12. The setting method according to any one of claims 1 to 11, wherein the useful layer formed during the epitaxy process is made of silicon and has a thickness between 0.3 microns and 30 microns.

13. The setting method according to any one of claims 1 to 11, wherein the useful layer formed during the epitaxy process is made of silicon germanium and has a thickness between 50 nm and 1000 nm.

14. An epitaxy method for performing an epitaxy process intended to form a useful layer on a receiving substrate within an epitaxy apparatus, wherein the layer and the substrate contain silicon, and the setting method described in any one of claims 1 to 13 is performed before processing the receiving substrate, and the receiving substrate is an SOI substrate.

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