Method for averaging bit error rates in data storage devices and fractional bit cell memory

Abstract

This invention provides a data storage device and method for averaging bit error rates in fractional bit cell memory, as well as a method for storing entangled logical pages of data. [Solution] The data storage device 100 includes a memory that stores a fraction (i.e., a non-integer) number of bits per memory cell. A word line in the memory has different sets of memory cells, and the stored bits are inferred by reading pairs of memory cells stored across different sets. To average the bit error rate, different program verification levels are used in each set, which are provided by using voltage (VCGR) shifts to different control gates or by changing the sense amplifier capacitor integration time.

Description

Technical Field

[0001] Bits per cell (BPC) refers to the number of bits that can be stored in a non-volatile memory (NVM) cell. Usually, BPC is an integer such as 4 bits per cell. While cost savings are provided, using 4 bits per cell can potentially degrade performance.

Brief Description of the Drawings

[0002] [Figure 1A] It is a block diagram of a data storage device according to an embodiment. [Figure 1B] It is a block diagram illustrating a memory module according to an embodiment. [Figure 1C] It is a block diagram illustrating a hierarchical memory system according to an embodiment. [Figure 2A] It is a block diagram illustrating the components of a controller of a data storage device illustrated in FIG. 1A according to an embodiment. [Figure 2B] It is a block diagram illustrating the components of a data storage device illustrated in FIG. 1A according to an embodiment. [Figure 3] It is a block diagram of a host and a data storage device according to an embodiment. [Figure 4A] It is a diagram of an independent memory cell according to an embodiment. [Figure 4B] It is a diagram of an entangled memory cell according to an embodiment. [Figure 5] It is a flowchart of a method according to an embodiment for writing to memory with an integer number of bits per cell. [Figure 6] It is a flowchart of a method according to an embodiment for writing to memory with a non-integer number of bits per cell. [Figure 7] It is a graph of an embodiment without using BER averaging of the average BER with respect to the bit error rate (BER) per page. [Figure 8] This is a graph of one embodiment using BER averaging, where the average BER is the BER per page. [Figure 9] This is a graph of one embodiment of the DAC (Digital Calculation) with respect to the charge voltage distribution (CVD), without using averaging. [Figure 10] This is a graph of one embodiment using averaging of DAC against CVD. [Figure 11] This is a graph of the actual BER relative to the BER in one embodiment. [Figure 12] This is a flowchart of one embodiment of a method for BER averaging in fractional bit cell memory. [Figure 13] This is a flowchart of one embodiment of a method for extracting a read threshold. [Figure 14] This is a flowchart of one embodiment of a method for performing readout threshold calibration. [Figure 15] This is a flowchart of one embodiment of a method for calibrating the read threshold in fractional bit cell memory. [Modes for carrying out the invention]

[0003] The following embodiments relate, in general, to data storage devices and methods for bit error rate averaging in fractional bit cell memory. In one embodiment, a data storage device is provided comprising a memory and one or more processors. The memory comprises a word line having first and second sets of memory cells. One or more processors are configured to perform bit error rate (BER) averaging by individually or in combination programming the memory cells in the first and second sets of memory cells to store non-integer bits in each of the programmed memory cells, and by using different program verification levels in the first and second sets of memory cells.

[0004] In another embodiment, a method is provided that is performed in a data storage device including a memory including a word line, the word line comprising first and second sets of memory cells. The method includes the steps of programming a fraction of bits per memory cell into the memory cells in the first and second sets of memory cells, and averaging the bit error rate between the first and second sets of memory cells by using different program verification levels within the first and second sets of memory cells.

[0005] In yet another embodiment, a data storage device is provided which includes a memory comprising first and second sets of memory cells, and means for averaging the bit error rate (BER) by verifying the programming of the memory cells in the first and second sets of memory cells using different program verification levels when storing non-integer bits in each of the programmed memory cells.

[0006] In one embodiment, a data storage device is provided comprising memory and one or more processors. The memory comprises a word line, the word line comprising first and second sets of memory cells. One or more processors are configured to individually or in combination to program a plurality of entangled pages of data in the first and second sets of memory cells, wherein a read threshold is shared among at least some of the plurality of entangled pages, and to calibrate a read threshold of one of the plurality of entangled pages.

[0007] Another embodiment provides a method to be performed in a data storage device including memory, where pages of data are stored between first and second sets of fractional bit cell (bits per cell, BPC) memory cells. The method includes fixing some read thresholds for a page of data and scanning other read thresholds for a page of data; performing a bit error rate estimation scan on the page of data to generate optimized scanned read thresholds; fixing the optimized scanned read thresholds and scanning previously fixed read thresholds; calibrating the previously fixed read thresholds; and outputting a set of calibrated read thresholds for the page of data.

[0008] In yet another embodiment, a data storage device is provided comprising a memory having first and second sets of memory cells configured to store a plurality of entangled pages, and means for calibrating a read threshold for one of the plurality of entangled pages.

[0009] Other embodiments are also possible, and each embodiment can be used individually or in combination. Accordingly, various embodiments are described herein with reference to the accompanying drawings.

[0010] Embodiment The following embodiments relate to data storage devices (DSDs). As used herein, “data storage device” refers to a non-volatile device that stores data. Examples of DSDs include, but are not limited to, hard disk drives (HDDs), solid state drives (SSDs), tape drives, and hybrid drives. Illustrative details of DSDs are provided below.

[0011] Examples of data storage devices suitable for use in implementing aspects of these embodiments are shown in Figures 1A and 1C. Note that these are examples only, and other implementations may be used. Figure 1A is a block diagram illustrating a data storage device 100 according to one embodiment. Referring to Figure 1A, the data storage device 100 in this example includes a controller 102 coupled to a non-volatile memory which may consist of one or more non-volatile memory dies 104. As used herein, the term die refers to a collection of non-volatile memory cells and associated circuits for managing the physical operation of those non-volatile memory cells, formed on a single semiconductor substrate. The controller 102 interfaces with a host system and transmits command sequences for read, program, and erase operations to the non-volatile memory dies 104. Also as used herein, the phrases “communicate with” or “coupled with” may mean directly communicating / coupled, or indirectly communicating / coupled through one or more components, which may or may not be illustrated or described herein. The communication / coupled may be wired or wireless.

[0012] The controller 102 (which may be a non-volatile memory controller (e.g., a flash, resistive random-access memory (ReRAM), phase-change memory (PCM), or magnetoresistive random-access memory (MRAM) controller)) may include, individually or in combination, one or more components configured to perform certain functions, including but not limited to those described herein and illustrated in the flowcharts. For example, as shown in Figure 2A, the controller 102 may include one or more processors 138 configured individually or in combination to perform functions, including but not limited to those described herein and illustrated in the flowcharts, by executing computer-readable program code stored in one or more non-temporary memories 139 (e.g., random access memory (RAM) 116 or read-only memory (ROM) 118) inside and / or outside the controller 102. As another example, one or more components may include, but are not limited to, circuitry such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0013] In one exemplary embodiment, the non-volatile memory controller 102 is a device that manages data stored in non-volatile memory and communicates with a host, such as a computer or electronic device having any suitable operating system. In addition to the specific functions described herein, the non-volatile memory controller 102 may have a variety of other functions. For example, the non-volatile memory controller may format the non-volatile memory to ensure that the memory is functioning properly, map out faulty non-volatile memory cells, and allocate spare cells to replace future failed cells. Some portions of the spare cells may be used to operate the non-volatile memory controller and hold firmware (and / or other metadata used for housekeeping and tracking) to implement other features. While operating, the host can communicate with the non-volatile memory controller when it needs to read data from or write data to the non-volatile memory. If the host provides a logical address from which data is read / written, the non-volatile memory controller can translate the logical address received from the host into a physical address in the non-volatile memory. Non-volatile memory controllers can also perform a variety of memory management functions, including, but are not limited to, wear leveling (distributing writes to avoid wearing out specific blocks of memory that would otherwise be repeatedly written to) and garbage collection (moving only valid pages of data to new blocks after a block is full, so that full blocks can be erased and reused).

[0014] The non-volatile memory die 104 can include any suitable non-volatile storage medium including resistive change random access memory (ReRAM), magnetic random access memory (MRAM), phase change memory (PCM), NAND flash memory cells, and / or NOR flash memory cells. The memory cells can be in the form of solid state (e.g., flash) memory cells and can be one-time programmable, multi-time programmable, or many-time programmable. The memory cells can also be single-level cells (SLC), multiple-level cells (MLC) (e.g., dual-level cells, triple-level cells (TLC), quad-level cells (QLC), etc.), or other memory cell level technologies known currently or developed later can be used. Also, the memory cells can be manufactured in a two-dimensional or three-dimensional manner.

[0015] The interface between the controller 102 and the non-volatile memory die 104 can be any suitable flash interface such as toggle mode 200, 400, or 800. In one embodiment, the data storage device 100 can be a card-based system such as a secure digital (SD) or micro secure digital (micro SD) card. In another embodiment, the data storage device 100 can be part of an embedded data storage device.

[0016] In the example illustrated in Figure 1A, the data storage device 100 (sometimes referred to herein as a storage module) includes a single channel between the controller 102 and the non-volatile memory die 104; however, the subject matter described herein is not limited to having a single memory channel. For example, in some architectures (such as those shown in Figures 1B and 1C), depending on the capabilities of the controller, two, four, eight or more memory channels may exist between the controller and the memory device. In any of the embodiments described herein, even if a single channel is shown in the drawings, two or more channels may exist between the controller and the memory die.

[0017] Figure 1B illustrates a storage module 200 including a plurality of non-volatile data storage devices 100. Thus, the storage module 200 may include a host and a storage controller 202 that interfaces with a data storage device 204 containing the plurality of data storage devices 100. The interface between the storage controller 202 and the data storage devices 100 may be a bus interface such as a serial advanced technology attachment (SATA), peripheral component interconnect express (PCIe) interface, double-data-rate (DDR) interface, or serial attached small-scale compute interface (SAS / SCSI). In one embodiment, the storage module 200 may be a solid-state drive (SSD) or a non-volatile dual in-line memory module (NVDIMM), as found in server PCs or portable computing devices such as laptop computers and tablet computers.

[0018] FIG. 1C is a block diagram illustrating a hierarchical memory system. The hierarchical memory system 250 includes a plurality of memory controllers 202, each of which controls a respective data storage device 204. A host system 252 can access the memory within the memory system 250 via a bus interface. In one embodiment, the bus interface can be a Non-Volatile Memory Express (NVMe) or Fibre Channel over Ethernet (FCoE) interface. In one embodiment, the system illustrated in FIG. 1C can be a rack-mountable mass storage system accessible by a plurality of host computers, such as seen in a data center or other location where large-scale storage is required.

[0019] Referring again to FIG. 2A, the controller 102 in this example also includes a front-end module 108 that interface-connects with a host, a back-end module 110 that interface-connects with one or more non-volatile memory dies 104, and various other components or modules, such as, but not limited to, a buffer manager / bus controller module that manages buffers in the RAM 116 and controls the internal bus arbitration of the controller 102. The module can include one or more processors or components, as discussed above. The ROM 118 can store system boot code. In FIG. 2A, it is illustrated as being located separately from the controller 102, but in other embodiments, one or both of the RAM 116 and the ROM 118 can be located within the controller 102. In still other embodiments, portions of the RAM 116 and the ROM 118 can be located both within and outside the controller 102.

[0020] The front-end module 108 includes a host interface 120 and a physical layer interface (PHY) 122 that provide an electrical interface with the host or a next-level storage controller. The choice of host interface 120 may depend on the type of memory being used. Examples of host interface 120 include, but are not limited to, SATA, SATA Express, serially attached small computer system interface (SAS), Fibre Channel, universal serial bus (USB), PCIe, and NVMe. The host interface 120 typically facilitates the transfer of data, control signals, and timing signals.

[0021] The backend module 110 includes an error correction code (ECC) engine 124 that encodes data bytes received from the host and decodes and error-corrects data bytes read from the non-volatile memory. The command sequencer 126 generates command sequences, such as program and erase command sequences, which are sent to the non-volatile memory die 104. The RAID (Redundant Array of Independent Drive) module 128 manages the generation of RAID parity and the recovery of failed data. RAID parity can be used as an additional level of integrity protection for data written to the memory device 104. In some cases, the RAID module 128 may be part of the ECC engine 124. The memory interface 130 provides command sequences to the non-volatile memory die 104 and receives status information from the non-volatile memory die 104. In one embodiment, the memory interface 130 may be a double data rate (DDR) interface, such as a toggle mode 200, 400, or 800 interface. In this example, the controller 102 also includes a media management layer 137 and a flash control layer 132 that controls the overall operation of the backend module 110.

[0022] The data storage device 100 also includes other discrete components 140, such as an external electrical interface, external RAM, resistors, capacitors, or other components that can interface with the controller 102. In an alternative embodiment, one or more of the physical layer interface 122, RAID module 128, media management layer 138, and buffer management / bus controller are optional components that are not required for the controller 102.

[0023] Figure 2B is a block diagram illustrating the components of the non-volatile memory die 104 in more detail. The non-volatile memory die 104 includes peripheral circuits 141 and a non-volatile memory array 142. The non-volatile memory array 142 includes non-volatile memory cells used to store data. The non-volatile memory cells may be any suitable non-volatile memory cells, including two-dimensional and / or three-dimensional ReRAM, MRAM, PCM, NAND flash memory cells and / or NOR flash memory cells. The non-volatile memory die 104 further includes a data cache 156 that caches data and address decoders 148, 150. In this example, the peripheral circuits 141 include a state machine 152 that provides status information to the controller 102. The peripheral circuits 141 may also comprise one or more components configured to perform certain functions, individually or in combination, including but not limited to the functions described herein and illustrated in the flowcharts. For example, as shown in Figure 2B, the memory die 104 may comprise one or more processors 168 configured individually or in combination to execute computer-readable program code stored in one or more non-temporary memories 169, stored in a memory array 142, or stored outside the memory die 104. As another example, one or more components may include, but are not limited to, circuitry such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0024] In addition to, or instead of, the one or more processors 138 (or more generally, components) in the controller 102 and the one or more processors 168 (or more generally, components) in the memory die 104, the data storage device 100 may comprise another set of one or more processors (or more generally, components). Generally, one or more processors (or more generally, components) in the data storage device 100, wherever they are located and how many there are, may be configured individually or in combination to perform a variety of functions, including, but not limited to, those described herein and illustrated in the flowcharts. For example, one or more processors (or components) may be located in the controller 102, the memory device 104, and / or elsewhere in the data storage device 100. Also, different functions may be performed using different processors (or components), or combinations of processors (or components). Furthermore, means for performing functions may be implemented using a controller comprising one or more components (e.g., the processors or other components described above).

[0025] Returning to Figure 2A, the flash control layer 132 (referred to herein as the flash translation layer, FTL) handles flash errors and interfaces with the host. In particular, the FTL, which may be an algorithm within the firmware, is responsible for the internal memory management and translates writes from the host into writes to memory 104. The FTL may be necessary because memory 104 may have limited durability, can only be written to in page units, and / or cannot be written to unless erased as a block. The FTL understands these potential limitations of memory 104, which may not be visible to the host. Therefore, the FTL attempts to translate writes from the host into writes to memory 104.

[0026] The FTL may include a logical-to-physical address (L2P) map (sometimes referred to herein as a table or data structure) and allocated cache memory. In this way, the FTL translates logical block addresses ("logical block addresses, LBAs") from the host to physical addresses in memory 104. The FTL may include, but is not limited to, power-off recovery (so that the data structures of the FTL can be recovered in the event of a sudden power loss) and wear leveling (so that wear across memory blocks is uniform to prevent excessive wear on some blocks, which would lead to a greater likelihood of failure).

[0027] Referring again to the drawings, Figure 3 is a block diagram of a host 300 and a data storage device 100 according to one embodiment. The host 300 can take any preferred form, including but not limited to a computer, mobile phone, tablet, wearable device, digital video recorder, surveillance system, etc. The host 300 in this embodiment (here, a computing device) comprises one or more processors 330 and one or more memories 340. In one embodiment, computer-readable program code stored in one or more memories 340 configures one or more processors 330 to perform operations described herein as being executed by the host 300. Thus, actions performed by the host 300 may be referred to herein as being performed by an application (computer-readable program code) running on the host 300. For example, the host 300 may be configured to send data (e.g., initially stored in the host's memory 340) to the data storage device 100 for storage in the memory 104 of the data storage device.

[0028] As mentioned above, bits per cell (BPC) refers to the number of bits that can be stored in a non-volatile memory (NVM) cell. Typically, BPC is an integer, such as 4 bits per cell ("X4"). While cost savings are provided, using 4 bits per cell (or 16 different states per cell) can degrade performance. To provide a trade-off between performance / reliability and cost savings, "fractional BPC" memory can be used, which has a non-integer number of bits per cell (e.g., 3.5 bits per cell ("X3.5")). In X3.5 memory, 56 kilobytes (KB) of data is written to a 16KB memory cell in a word line. In contrast, 48KB of data is written to memory with 3 bits per cell (X3), and 64KB of data is written to memory with 4 bits per cell (X4). Unlike X3 or X4 memory, mapping user data to various memory cell states is not straightforward in X3.5 memory, and different mappings can have different associated drawbacks.

[0029] Referring again to the diagrams, Figures 4A and 4B illustrate a bit-line pairing scheme used to map data and various memory cell states. In this scheme, a pair of sets of memory cells exists within a page. This pair may be independent or entangled, as shown in the examples in Figures 4A and 4B, respectively. As shown in these figures, there are two sets of memory cells on the same word line: an 8KB set of memory cells on the left side of the word line and an 8KB set of memory cells on the right side of the word line. There are four independent logical pages, each containing 32KB (4×8KB) consisting of either a left cell or a right cell only, and three other entangled logical pages (3×8KB) consisting of both left and right cells. Thus, 7 bits are stored across two memory cells. The pairs are made within the same page (different column addresses but the same block address). Independent pages have mappings that depend on only one cell, similar to X3 or X4 memory. Entangled pages combine read thresholds from two cells on the same word line. Decoding of entangled bits can be performed within the sense amplifier or within the data path.

[0030] Two cells are read, the page is read, and the bits are inferred. A logical function is applied to the read results from the two cells in order to read the entangled logical page. In this example, the first cell is read in state 8 (S8), and the second cell is read in state 4 (S4). A logical operation is then applied to both pages, and as a result, the bits are read.

[0031] Host data is written directly to logical pages. When reading data, it is desirable that different logical pages do not show significant differences in throughput and read latency. To achieve this, bit error rate (BER) averaging between logical pages can be used. BER averaging can be done by shifting states so that they are not at uniform intervals, as is done in X3 and X4 memory. In X3 and X4 memory, all memory cells in a word line can receive the same read threshold shift and write / verification threshold shift because there are no inherent differences between them. More specifically, the flash memory programming procedure may include executing multiple programming pulses. After each programming pulse, a set of verification operations is performed to check which cells have reached their target state and may be prohibited. Verification operations are performed by sensing at each verification level corresponding to the target state. Traditionally, the same verification level is applied to all cells in a word line.

[0032] However, in X3.5 memory, because pages are entangled, BER averaging cannot be achieved using simple verification-level optimizations as performed in X3 and X4 memory. The following embodiments provide novel methods for achieving BER averaging in X3.5 memory. These embodiments can improve BER averaging and reduce the maximum BER while minimizing the impact on write latency. In general, these embodiments provide several methods for optimizing BER averaging in non-volatile memory with entangled pages. These methods may rely on utilizing different aspects of entangled pages and memory systems.

[0033] In one embodiment, a novel verification method is provided for achieving BER averaging of entangled pages in memory using fractional BPCs. While X3.5 memory is used as an example to illustrate these embodiments, it should be understood that these embodiments may be used with any suitable memory having fractional BPCs, and X3.5 should not be read into the claims unless expressly stated. In one exemplary implementation, two different verification levels are used for pairs of entangled cells in the same word line that jointly store bits. Here, shifting the voltage to the control gate (VCGR) to different voltages is used for the verification level of each pair of entangled cells. This involves doubling the number of verification levels, which may result in slower write speeds. As an example, assume that cells 1 and 2 are entangled, cells 3 and 4 are entangled, and so on. Also, in all states, the verification level of odd-numbered cells is lower than the verification level of even-numbered cells. This procedure applies a set of validation behaviors with increasing validation levels, where odd cells are validated using odd VCGR levels, and then even cells are validated using higher even VCGR validation levels. This can be done in ascending order for all states using 22 validation levels (i.e., 11 validation levels for odd cells and 11 different levels for even cells) (for example, a total of 11 for X3.5).

[0034] The system proposed in this embodiment improves averaging but may lead to increased write latency due to the increased number of write / verification pulses. Because the write thresholds are different, the read thresholds for entangled cells are also different. This may require separate calibration of each read threshold, each with its own calibration scheme for the left and right cells. However, when calibrating entangled pages, there are read thresholds shared between different logical pages.

[0035] In another embodiment, instead of changing the VCGR, a change in the sense amplifier (SA) capacitor integration time may be used to reduce write latency while maintaining a doubling of the number of verification levels to accommodate the best BER averaging. Modulating the capacitor integration time can produce similar results to VCGR modulation without requiring actual changes to the VCGR, which can lead to greater latency. Using the same VCGR with multiple capacitor integration times can result in faster verification times, leading to higher programming speeds.

[0036] The proposed method can be combined with a Quick Pass Write (QPW) approach, in which a memory cell exhibits a high programming pulse (faster programming) until it reaches a first verification level lower than the final verification level of its target state. Once the cell passes the lower verification level, its bit line voltage is adjusted so that subsequent programming pulses result in smaller threshold voltage (Vt) increments (slower programming) to improve accuracy and narrow the charge voltage distribution (CVD). The QPW scheme can be generalized to use four verification levels per state: slow odd cells, fast odd cells, slow even cells, and fast even cells. These verification levels can be adjusted directly via VCGR or indirectly via SA capacitor integral time modulation.

[0037] Figures 5 and 6 illustrate the comparison between writing a non-fractional BPC (Figure 5) and writing a fractional BPC (Figure 6). As shown in the flowchart 700 of Figure 5, when the following state is written to memory with a non-fractional BPC, the controller 102 of the data storage device 100 changes the VCGR (710) and performs a fast QPW step to change the capacitor integration time (720). Next, the controller 102 applies a write pulse (730) and performs a slow QPW step to change the capacitor integration time (740). After several pulses, the controller 102 checks the verification level to determine whether the programming was successful (750).

[0038] As shown in the flowchart 800 of Figure 6, when the following state is written to memory in fractional BPC, the controller 102 of the data storage device 100 changes VCGR (805) and performs a fast QPW step to change the capacitor integration time for the left cell (810). Next, the controller 102 applies a write pulse (815) and performs a fast QPW step to change the capacitor integration time for the right cell (820). Then, the controller 102 applies a write pulse (825) and performs a slow QPW step to change the capacitor integration time for the left cell (830). Then, the controller 102 applies a write pulse (835) and performs a slow QPW step to change the capacitor integration time for the right cell (840) and applies an additional write pulse (845). After several pulses, the controller 102 checks the verification level to determine whether the programming was successful (855).

[0039] Averaging BER by shifting memory states may lead to an increase in the average BER but a decrease in the maximum BER. Figures 7 and 8 illustrate the effects of using different BER averaging methods. More specifically, Figure 7 is a graph of the average BER against the bit error rate (BER) per page in one embodiment without BER averaging, and Figure 8 is a graph of the average BER against the BER per page in one embodiment with BER averaging. In these graphs, the X-axis is the average BER and the Y-axis is the BER per page. Averaging is not shown in Figure 7. It is clear that each page makes a different contribution, and independent pages (pages 0-3) with more read thresholds (not entangled) contribute more to the BER. Figure 8 shows the averaged BER against a given average BER point.

[0040] This averaging can also be seen when looking at the CVD of the X3.5 word line. Figure 9 is a graph of one embodiment of the DAC against the charge voltage distribution (CVD) without averaging, and Figure 10 is a graph of one embodiment of the DAC against the CVD with averaging. As shown in these graphs, averaging effectively shifts the state center (and readout threshold). In both cases, it should be noted that higher voltage states are shorter, not averaged out, due to the X3.5 structure.

[0041] These graphs show that averaging can be achieved for a given average BER point. However, when the BER is lower and (more importantly) higher, the BER is no longer averaged across pages. However, there are other properties of entangled pages that can be used to one's advantage. Due to the definition of page #5, sensing the soft bit (SB) is not as straightforward as with independent pages. More logical operations may be performed to obtain the exact SB, which can require more time and computational complexity.

[0042] To mitigate this, inaccurate SBs can be detected for entangled pages. For example, if soft bit read (SBR) using only NAND is required for page 2, there may be some cells that are unnecessarily flagged by the SB. Decoding with inaccurate SBs reduces the correction capability by a certain margin. Figure 11 shows the correction capability with inaccurate SBs for entangled page 5, with the X-axis representing the actual BER measured at the input to the decoder.

[0043] When designing this system, BER averaging can be calibrated so that pages corresponding to inaccurate SBs are less likely to achieve a higher BER. This BER averaging operation can be tailored to the logical mapping to make the most of BER imbalances. In other words, BER averaging can take into account differences in decoding quality between pages (for example, page 5 has lower decoding ability due to suboptimal SB sensing). Specifically, in the example above, averaging can induce a lower BER on page 5 (due to its degraded correction ability) at the expense of slightly higher BERs on other pages.

[0044] In another embodiment, if the BER is not sufficiently averaged across logical pages, more critical data may be written to "more secure" logical pages. This data may include, for example, firmware headers, critical metadata, security keys, calculation results, and other objects that are more important than ordinary data.

[0045] There are several advantages associated with these embodiments. For example, these embodiments can be used to improve BER averaging in X3.5 memory and other “fractional BPC” memory. This avoids performance degradation, reduced correction capability, and increased power consumption that may occur if BER averaging between pages fails. In one exemplary implementation, these advantages can be achieved by using the method described in flowchart 1500 of Figure 12. As shown in Figure 12, this method involves causing a BER averaging system (implemented, for example, in controller 102) to consider logical page characteristics such as SB efficiency in a given input BER (1510). The BER averaging system then sets the verification levels of the left and right cells in such a way that it takes into account a certain imbalance in order to favor lower SB efficiency (1520). The BER averaging system then uses the acquired verification levels in its operation (1530).

[0046] Another embodiment relates to read threshold calibration. While the read thresholds of independent pages can be calibrated without any modification, there are some challenges in calibrating the read thresholds of specific entangled logical pages because the read thresholds of some pages are shared among different logical pages.

[0047] The following embodiments can be used to address read threshold calibration of entangled pages, which can improve the quality of the acquired read threshold and enable a reduction in the BER. As a result, throughput can be improved and power consumption and read latency can be reduced. Furthermore, by directly minimizing the BER (for example, by using a BER Estimation Scan (BES)), it can be more advantageous than other calibration methods, such as those based on Valley Search (VS).

[0048] In general, these embodiments can be used to calibrate the read thresholds of several entangled pages. Different options for performing the calibration can be used, along with different trade-offs between those options. The following paragraphs describe options for handling read threshold calibration according to entanglement.

[0049] Read threshold calibration of entangled cells with the same read threshold. In one embodiment, the read threshold is equal between the left and right cells. This is the easiest configuration to manage because there is no need to distinguish between left and right cell read threshold calibrations. In this design, if the logical mapping includes the same threshold from both the left and right cells, calibration can be performed using a BER Estimation Scan (BES) as if only one read threshold existed. More specifically, the scan can be performed by applying multiple read operations around a single read threshold.

[0050] For each of these read operations, entangled bits are generated by applying logical operations in memory 104, and the read page is transferred to controller 102 for BER estimation. BER estimation can be performed by calculating the corresponding syndrome weights for the read page (i.e., by counting the number of unsatisfied parity check equations). This can also be done by using an existing BES engine in a single read threshold mode without requiring hardware changes.

[0051] Read threshold calibration of entangled cells with different read thresholds In another embodiment, a read threshold calibrated based on other pages shared with the target entangled page is used to read the entangled page.

[0052] The flowchart 1600 in Figure 13 summarizes this embodiment. As shown in Figure 13, in this embodiment, read threshold calibration of page 5 is required (1610). Controller 102 calibrates the read threshold of page 4 (1620), and then calibrates the read threshold of page 6 (1630). Controller 102 then extracts the relevant read threshold for page 5 (1640).

[0053] Full scan In the full scan approach, to calibrate an entangled page containing N read thresholds, the controller 102 can perform M^N reads, where M is the desired scan resolution around each read threshold. For each of the M^N reads, the controller 102 can compute the entangled page in the memory die 104 and perform a BER estimation on it. The combination of read thresholds with the minimum syndrome weights can be selected as optimal. For example, consider page 5 containing N=2 read thresholds and assume a scan resolution of M=7 is required. The controller 102 can perform 7^2 normal read operations (where entanglement occurs in the memory die 104) and perform a BER estimation for each of the 49 options. This may be prohibited due to the large number of sense operations and corresponding latency.

[0054] Emulated scan In the emulated scan approach, memory 104 performs only M normal read operations (each operation involving sensing at N read thresholds), and the remaining processing is performed by controller 102. Similar to normal BES operation, the voltage bin of each cell can be obtained by analyzing M read pages (i.e., the voltage bin of each cell can be estimated from its M read bits). Once the voltage bin of each cell is determined, the read results of the cell can be emulated under each of M^N read level combinations. From the emulated read results of each of the two entangled cells, the entangled bits are calculated, which determines the entangled page. Finally, BER estimation is performed on the emulated entangled page. The read threshold combination corresponding to the minimum BER estimation among the M^N combinations is determined as optimal.

[0055] In this approach, only M read operations are performed to emulate M^N possible entangled pages, thus significantly reducing sensing latency (compared to an actual scan). In some implementations, the emulated scan may require a dedicated ASIC (i.e., dedicated BES logic) for X3.5 memory mapping to perform the entangled page calculations.

[0056] In entangled pages with several thresholds, it is possible to fix some read thresholds and run BES on the remaining read thresholds. Read threshold calibration is independent, but the syndrome weight calculation used in BES depends on the position of all read thresholds on the logical page. If the fixed read thresholds are completely off, it will hinder subsequent BES processing performed in this manner. However, if the fixed read thresholds are close enough to the optimal read thresholds, the BES on the remaining thresholds can proceed to find the optimal read thresholds and then run BES on the previously fixed read thresholds.

[0057] In one embodiment, one of the thresholds of an entangled page is fixed, and BES is performed on the other read thresholds. This process can then be reversed, resulting in the previously fixed read threshold also being optimized by BES. This option allows the use of existing ASICs for conventional memory (with conventional BES engines). For example, consider page 5. R3 may be fixed, and a single threshold scan may be performed near R7 and the corresponding single threshold BES. Then R7 may be fixed according to the BES result, a single threshold scan may be performed near R3, followed by a single threshold BES operation.

[0058] In another embodiment, after calibrating page 4, the BER index can be read to determine whether page 5 can now be read successfully, or whether page 6 needs to be calibrated before reading page 5 again. It should be noted that calibrating all read thresholds for the page that failed to read is beneficial, but does not necessarily have to be done "online" while host 300 is waiting for the requested data. Furthermore, in one embodiment, the data on page 5 may be read after calibrating page 4, and the calibration of the remaining read thresholds that depend on page 6 may be completed at a later point during background operation.

[0059] Figure 14 provides a flowchart 1700 illustrating these processes. As shown in Figure 14, an urgent read threshold calibration for page 5 is required (1710). After the read threshold for page 4 has been calibrated (1720), the controller 102 determines whether there is an indicator that the partial read threshold correction is sufficient (e.g., whether the partial read threshold calibration calibrates the read thresholds shared with page 5) (1730). If the partial read threshold correction is insufficient, the read thresholds for page 6 (including other remaining uncalibrated read thresholds for page 5) are also calibrated (1740), and the read thresholds relevant to page 5 are extracted (1750). However, if the partial read threshold correction is sufficient, the read thresholds relevant to page 5 are extracted without additional calibration (1760), and the calibration of the remaining page 5 read thresholds is scheduled during background operation time (1770). In a typical configuration, it may be necessary to configure a scheme based on selected logical mappings for all states so that an appropriate read threshold calibration scheme can be selected.

[0060] As mentioned above, when the same read threshold is used for both the left and right cells, BER averaging across pages is not optimal. Also, as mentioned above, for optimal BER averaging, the left and right cells of an entangled page may use different validation levels and therefore require different read thresholds when reading the entangled page. In this case, even if the entangled page contains a single threshold, it effectively contains two read thresholds because the thresholds of some cells are not identical. Therefore, when such BER averaging is used, a single-threshold entangled page effectively becomes a page with multiple read thresholds, and thus the method described above can also be used in this case.

[0061] There are several advantages associated with these embodiments. For example, these embodiments can improve the read threshold calibration of X3.5 memory or other fractional-bit memory in that well-calibrated read thresholds can improve performance and reduce power consumption. Also, the process of read threshold calibration itself can be limited in length, and these embodiments can be used to reduce latency. In one exemplary implementation, these advantages can be achieved by using the method described in flowchart 1800 of Figure 15. As shown in Figure 15, after the start of read threshold calibration of entangled thresholds (1810), memory 104 fixes some read thresholds (while scanning other read thresholds) and passes the read page to controller 102 (1820). Controller 102 operates a standard BES on the read page and optimizes the scanned read thresholds (1830). Memory 104 fixes the optimized read thresholds and scans the previously fixed read thresholds (1840). Next, the controller 102 calibrates the previously fixed read thresholds and outputs the full set of calibrated read thresholds (1850).

[0062] Finally, as mentioned above, any suitable type of memory can be used. Semiconductor memory devices include volatile memory devices such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, non-volatile memory devices such as resistive random access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"), as well as other semiconductor elements capable of storing information. Each type of memory device may have a different configuration. For example, flash memory devices may be configured in a NAND or NOR configuration.

[0063] Memory devices can be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity switching memory elements such as antifuses and phase-change materials, and optionally steering elements such as diodes. Furthermore, as a non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements with charge storage regions such as floating gates, conductive nanoparticles, or charge-storage dielectric materials.

[0064] Multiple memory elements may be configured to be connected in series or so that each element is individually accessible. As a non-limiting example, a flash memory device with a NAND configuration (NAND memory) typically includes memory elements connected in series. A NAND memory array may be configured such that the array consists of multiple memory strings, each string consisting of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible (e.g., a NOR memory array). NAND and NOR memory configurations are examples, and memory elements may be configured in other ways.

[0065] Semiconductor memory elements located within and / or on the substrate may be arranged in two or three dimensions, such as in a two-dimensional memory structure or a three-dimensional memory structure.

[0066] In a two-dimensional memory structure, semiconductor memory elements are arranged on a single plane or at the single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged on a plane (e.g., the xz plane) that extends substantially parallel to the main surface of the substrate supporting the memory elements. The substrate may be a wafer on which layers of memory elements are formed, either above or within it, or a carrier substrate to which the memory elements are attached after they have been formed. In non-limiting embodiments, the substrate may include a semiconductor such as silicon.

[0067] Memory elements may be arranged in an ordered array, such as multiple rows and / or columns, at the level of a single memory device. However, memory elements may be arranged in an irregular or non-orthogonal configuration. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0068] A three-dimensional memory array is arranged such that memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in the x, y, and z directions, where the y direction is substantially perpendicular to the main surface of the substrate, and the x and z directions are substantially parallel to the main surface of the substrate).

[0069] As a non-limiting embodiment, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory devices. As another non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns substantially perpendicular to the main plane of the substrate, i.e., extending in the y-direction) where each column has multiple memory elements within each column. The columns may be arranged in a two-dimensional configuration, e.g., in the xz plane, resulting in a three-dimensional arrangement of memory elements having elements on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also constitute a three-dimensional memory array.

[0070] As a non-restrictive example, in a three-dimensional NAND memory array, memory elements may be joined together to form a NAND string within a single horizontal (e.g., xz) memory device level. Alternatively, memory elements may be joined together to form a vertical NAND string that spans multiple horizontal memory device levels. Other three-dimensional configurations can be envisioned where some NAND strings contain memory elements within a single memory level, and others contain memory elements that span multiple memory levels. Three-dimensional memory arrays can further be designed in NOR and ReRAM configurations.

[0071] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed on a single substrate. If necessary, the monolithic three-dimensional memory array may further have one or more memory layers, at least partially, within a single substrate. In non-limiting embodiments, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layers constituting each memory device level of the array are typically formed on layers of memory device levels beneath the array. However, adjacent memory device level layers in a monolithic three-dimensional memory array may be shared, or there may be intervening layers between the memory device levels.

[0072] In this case as well, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device having multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrates may be thinned or removed from the memory device levels before stacking, but since the memory device levels are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0073] Related circuitry is typically required for the operation of memory elements and for communication with them. As a non-limiting example, a memory device may have circuitry used to control and drive memory elements to achieve functions such as programming and reading. This related circuitry may be on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for memory read / write operations may be located on a separate controller chip and / or on the same substrate as the memory elements.

[0074] Those skilled in the art will recognize that the present invention is not limited to the two-dimensional and three-dimensional structures described, but encompasses all relevant memory structures within the spirit and scope of the invention, as described herein and understood by those skilled in the art.

[0075] The above detailed description is intended to be understood not as a definition of the present invention, but as an illustrative example of selected forms that the invention may take. Only the following claims, including all equivalents, are intended to define the scope of the claimed invention. Finally, it should be noted that any aspect of the embodiments described herein may be used individually or in combination with others.

Claims

1. A data storage device, A memory having a word line, wherein the word line comprises a first and second set of memory cells, A system comprising one or more processors, wherein the one or more processors can be operated individually or in combination. Program the memory cells in the first and second sets of memory cells, and store a non-integer bit in each of the programmed memory cells. A data storage device configured to perform bit error rate (BER) averaging by using different program verification levels in the first and second sets of memory cells.

2. The data storage device according to claim 1, which provides the different program verification levels by using voltage (VCGR) shifts to different control gates.

3. The data storage device according to claim 1, wherein the sense amplifier capacitor integration time is changed to provide the different program verification levels.

4. The data storage device according to claim 1, wherein one or more processors are further configured to increase the program verification level in ascending order when programming a memory cell.

5. The data storage device according to claim 1, wherein one or more processors are further configured to store data-entangled logical pages in the first and second sets of memory cells, individually or in combination.

6. The data storage device according to claim 1, wherein one or more processors are further configured to perform a quick-path write operation after their respective verification levels have been met, thereby providing a lower voltage threshold for each consecutive programming pulse.

7. The data storage device according to claim 1, wherein one or more processors are further configured to move data in response to a determination that BER averaging was unsuccessful.

8. The aforementioned one or more processors, individually or in combination, The programmed memory cell is read, The data storage device according to claim 1, further configured to apply a logical function to the result to infer the bits stored in the programmed memory cell.

9. The data storage device according to claim 1, wherein one or more processors are further configured to set the program verification levels in the first and second sets of memory cells based on the determined soft bit efficiency values.

10. The data storage device according to claim 1, wherein one or more processors are further configured to individually or in combination to calibrate the read thresholds of the first and second sets of memory cells to different levels.

11. The data storage device according to claim 1, wherein the memory comprises a three-dimensional memory.

12. A data storage device having a memory with a word line, wherein the word line comprises a first and second set of memory cells, A fraction of bits per memory cell is programmed into the memory cells in the first and second sets of memory cells. A method for averaging the bit error rate between the first and second sets of memory cells by using different program verification levels within the first and second sets of memory cells.

13. The method according to claim 12, further comprising providing the different program verification levels by using voltage (VCGR) shifts to different control gates.

14. The method according to claim 12, further comprising changing the integration time of the sense amplifier capacitor to provide the different program verification levels.

15. The method according to claim 12, further comprising increasing the program verification level in ascending order when programming the memory cell.

16. The method according to claim 12, further comprising storing data-entangled logical pages in the first and second sets of memory cells.

17. The method according to claim 12, further comprising performing a quick-path write operation after each verification level has been met to provide a lower voltage threshold for each consecutive programming pulse.

18. The method according to claim 12, further comprising moving the data in response to a determination that the averaging of the bit error rate was unsuccessful.

19. The method according to claim 12, further comprising setting the program verification levels in the first and second sets of memory cells based on the determined soft bit efficiency values.

20. A data storage device, A memory comprising a first and second set of memory cells, A data storage device comprising: means for averaging the bit error rate (BER) by verifying the programming of the memory cells in the first and second sets of memory cells using different program verification levels when programming the memory cells in the first and second sets and storing non-integer bits in each of the programmed memory cells.

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