Power conversion circuit and power conversion method

Abstract

In order to further reduce the loss of a three-level circuit formed from a multi-gate IGBT and a MOS gate diode, the present invention comprises: a first unit circuit and a fourth unit circuit each of which are formed from a semiconductor element having a pair of main terminals and a plurality of control terminals and a diode with a control terminal connected in anti-parallel to the semiconductor element; and a second unit circuit and a third unit circuit each of which are formed from a semiconductor element having a pair of main terminals and a plurality of control terminals and a diode connected in anti-parallel to the semiconductor element. The first unit circuit, the second unit circuit, the third unit circuit, and the fourth unit circuit are connected in series in the stated order. The positive side terminal of the first unit circuit is connected to a positive power supply line, and the negative side terminal of the fourth unit circuit is connected to a negative power supply line. The intermediate potential between the positive power supply line and the negative power supply line is set as a neutral point terminal, and a connection point between the second unit circuit and the third unit circuit is set as an input / output terminal for one AC phase. The present invention comprises: a first clamp diode with a control terminal the cathode of which is connected to a connection point between the first unit circuit and the second unit circuit and the anode of which is connected to the neutral point terminal; and a second clamp diode with a control terminal the cathode of which is connected to the neutral point terminal and the anode of which is connected to a connection point between the third unit circuit and the fourth unit circuit.

Description

Technical Field

[0001] The present invention relates to a power conversion circuit and a power conversion method constituting a power conversion device, and is particularly suitable for a power conversion device composed of a power semiconductor device having a diode provided with a gate control terminal.

Background Art

[0002] Since the IGBT was introduced as a power semiconductor device for power conversion devices, its performance has been continuously improved, and high voltage withstand, high output, and low loss have been promoted. However, the improvement of its performance is approaching its limit.

[0003] Therefore, in recent years, in order to further improve performance, instead of Si (silicon) which has been used as the element material so far, so-called wide-bandgap semiconductors such as SiC (silicon carbide) and GaN (gallium nitride) have been used as next-generation semiconductor materials, and elements such as MOSFETs using these have been developed and are gradually becoming popular. However, wide-bandgap semiconductor devices have higher material costs and manufacturing costs than conventional Si IGBTs, which is a major problem for further widespread use.

[0004] Therefore, as a technology for reducing the loss of IGBTs without using these expensive materials, multi-gate IGBTs have been devised and their development is underway. The multi-gate IGBT has an auxiliary gate electrode for controlling the carrier concentration inside the IGBT, and by switching the on and off of the auxiliary gate electrode, the loss during current interruption (turn-off) is reduced.

[0005] Specifically, when the IGBT is on, that is, when the collector-emitter is in a conducting state, sufficient carriers (charges) are supplied into the IGBT by turning on all the gate electrodes, reducing the on-resistance and reducing the conduction loss. On the other hand, when turning off the current, the carriers accumulated in the IGBT are reduced by turning off the auxiliary gate electrode in advance a certain time before turning off, reducing the turn-off loss.

[0006] The aforementioned technique of reducing losses using an auxiliary gate electrode can be applied not only to switching elements such as IGBTs, but also to freewheeling diodes in inverter circuits. In the case of these diodes, as with multi-gate IGBTs, it is possible to reduce both conduction losses and switching losses by controlling the carrier concentration according to the conduction or switching state.

[0007] To achieve this, a diode with a MOS (Metal-Oxide-Semiconductor) gate has been devised and is currently under development. A MOS gate diode has a MOS gate electrode that controls the carrier concentration inside the diode, and by switching the MOS gate electrode on and off, it reduces losses during diode interruption (recovery).

[0008] Patent Document 1 discloses an example in which a gate-controllable MOS gate diode is applied to a clamp diode, thereby reducing the loss of the clamp diode. Here, the freewheel diode disclosed in Patent Document 1 is a conventional diode without gate control.

[0009] In this case, in order to drive the MOS gate diode, it is necessary to provide the diode with a gate command in addition to the IGBT gate command. Patent Document 1 discloses a method in which, for a MOS gate diode connected in antiparallel to an IGBT, the gate command for the IGBT generated by the higher-level controller is input to the gate driver, and the gate driver generates the gate command for the diode. [Prior art documents] [Patent Documents]

[0010] [Patent Document 1] Japanese Patent Publication No. 2018-14880 [Patent Document 2] Japanese Patent Publication No. 2021-90026 [Overview of the Initiative] [Problems that the invention aims to solve]

[0011] As a result of diligent research into further reducing losses in a 3-level circuit using multi-gate IGBTs and MOS-gate diodes, the inventors of this invention have obtained the following findings.

[0012] Patent Document 1 discloses an example in which a gate-controllable MOS gate diode is applied to a clamp diode to avoid excessive load on electrical elements within an inverter due to large surge currents. It also discloses reducing switching losses at a branch of the inverter by discharging the diode before switching on that branch. However, freewheeling diodes are conventional diodes without gate control, and reducing the losses of freewheeling diodes has not been considered.

[0013] Furthermore, the higher-level controller of a conventional 3-level circuit using IGBTs generates drive command signals for the four IGBTs. In contrast, to reduce the losses of all elements in a 3-level circuit using multi-gate IGBTs and MOS gate diodes, gate commands are required not only for the four series-connected multi-gate IGBTs and MOS gate diodes, but also for the MOS gate diodes used as clamp diodes. This necessitates the higher-level controller adding and outputting two additional gate commands. Therefore, when changing the IGBTs and diodes that make up a conventional 3-level circuit to multi-gate IGBTs and MOS gate diodes, the higher-level controller also needed to be changed.

[0014] Furthermore, the need to add a gate driver board to drive the clamp diodes also increased the size, weight, and cost of the device.

[0015] Therefore, in order to solve the above problems, the present invention aims to further reduce the losses of a 3-level circuit consisting of a multi-gate IGBT and a MOS-gate diode. Preferably, the aim is to provide a low-loss 3-level circuit system that is compatible with conventional 3-level circuit systems. [Means for solving the problem]

[0016] To solve the above problems, one of the power conversion circuits for one phase of a typical power conversion device that converts DC and AC according to the present invention comprises a first unit circuit and a fourth unit circuit composed of a semiconductor element having a pair of main terminals and a plurality of control terminals and a diode with a control terminal connected in antiparallel to the semiconductor element, and a second unit circuit and a third unit circuit composed of a semiconductor element having a pair of main terminals and a plurality of control terminals and a diode connected in antiparallel to the semiconductor element, and the first unit circuit to the fourth unit circuit are connected in series in the order of the first unit circuit, the second unit circuit, the third unit circuit and the fourth unit circuit, The positive terminal of the first unit circuit is connected to a positive power supply line, the negative terminal of the fourth unit circuit is connected to a negative power supply line, the midpoint potential between the potentials of the positive and negative power supply lines is used as the neutral point terminal, the connection point between the second and third unit circuits is used as an input / output terminal for one phase of AC, and the first clamp diode with a control terminal has its cathode connected to the connection point between the first and second unit circuits and its anode connected to the neutral point terminal, and the second clamp diode with a control terminal has its cathode connected to the neutral point terminal and its anode connected to the connection point between the third and fourth unit circuits. Preferably, the system includes a first driver for driving and controlling the semiconductor elements and diodes with control terminals that constitute a first unit circuit, a second driver for driving and controlling the semiconductor elements and second clamp diodes with control terminals that constitute a second unit circuit, a third driver for driving and controlling the semiconductor elements and first clamp diodes with control terminals that constitute a third unit circuit, and a fourth driver for driving and controlling the semiconductor elements and diodes with control terminals that constitute a fourth unit circuit. Furthermore, the second driver drives and controls the second clamp diodes with control terminals via an insulating element, and the third driver drives and controls the first clamp diodes with control terminals via an insulating element. [Effects of the Invention]

[0017] According to the present invention, by providing gates to all freewheeling diodes and clamp diodes corresponding to the current paths in which recovery losses occur, it is possible to reduce recovery losses regardless of the current path taken between the positive or negative terminal and the input / output terminals, and between the neutral terminal and the input / output terminals, including commutation (covering all patterns in which recovery losses occur in a 3-level circuit). Preferably, by applying low-loss multi-gate IGBTs and MOS gate diodes to the 3-level circuit without changing the higher-level controller that controls the 3-level circuit, recovery losses can be reduced regardless of the current path taken, including commutation, and the system can be easily made lower in terms of losses. Furthermore, since there is no need to add a gate driver board, the size of the device can be kept the same as the conventional system, and it is possible to mount multi-gate IGBTs and MOS gate diodes without design changes. This is expected to shorten the time required for development, design, and replacement work. Other issues, structures, and effects not mentioned above will be clarified by the following explanation of the implementation methods. [Brief explanation of the drawing]

[0018] [Figure 1]It is a diagram showing a single-phase circuit constituting a power conversion device according to Embodiment 1 of the present invention. [Figure 2] It is a diagram showing a timing chart of the gate command of a multi-gate IGBT, the MOS gate diode current, and the load voltage when current flows from the load into the main circuit direction. [Figure 3] It is a diagram showing a timing chart of the gate command of a multi-gate IGBT, the MOS gate diode current, and the load voltage when current flows out from the main circuit to the load direction. [Figure 4] It is a diagram showing a single-phase circuit constituting a power conversion device according to Embodiment 2 of the present invention. [Figure 5] It is a diagram showing a single-phase circuit constituting a power conversion device according to Embodiment 3 of the present invention.

Mode for Carrying Out the Invention

[0019] Hereinafter, Embodiments 1 to 3 will be described as modes for carrying out the present invention with reference to the drawings. Note that the present invention is not limited by these embodiments. Also, in the description of the drawings, the same parts are denoted by the same reference numerals.

Embodiment

[0020] FIG. 1 is a diagram showing a single-phase circuit constituting a power conversion device according to Embodiment 1 of the present invention. Here, the circuit shown in FIG. 1 is a single-phase of a DC / AC power conversion device that mutually converts DC and AC, that is, a so-called converter / inverter circuit.

[0021] Three power sources, a DC positive power supply (+E [V]), a neutral point (0 [V]), and a negative power supply (-E [V]), are respectively connected to a DC power supply positive terminal 232, a DC power supply neutral point terminal 231, and a DC power supply negative terminal 233, and power is converted by operating multi-gate IGBTs 235 to 238 in a predetermined order.

[0022] The multi-gate IGBTs 235 and 238 are connected in antiparallel to MOS gate freewheeling diodes 201 and 204, respectively. In addition, MOS gate clamp diodes 205 and 206 are connected as clamp diodes between the neutral point and the emitter of the multi-gate IGBT 235, and between the neutral point and the collector of the multi-gate IGBT 238, respectively.

[0023] Gate command lines 002 to 009 are connected from the upper-level controller 001 to the gate drivers 101 to 104, and gate commands from the upper-level controller 001 are input. The signals input to the gate drivers 101 to 104 are transmitted in isolation using an isolation circuit with a photocoupler (not shown) inside the driver, and are amplified by an amplification circuit or the like.

[0024] The amplified gate signals are output to the main gate voltage output terminals 107, 111, 115, and 119, the auxiliary gate voltage output terminals 108, 112, 116, and 120, and the diode voltage output terminals 109, 113, 117, and 121, respectively, with reference to the auxiliary emitter potential terminals 110, 114, 118, and 122, controlling the multi-gate IGBTs 235-238, the MOS gate freewheeling diodes 201 and 204, and the MOS gate clamping diodes 205 and 206.

[0025] As mentioned above, the multi-gate IGBTs 235-238, MOS gate freewheel diodes 201 and 204, and MOS gate clamp diodes 205 and 206 have auxiliary gates to reduce losses, and by appropriately controlling these, conduction and switching losses can be reduced.

[0026] In other words, in this embodiment 1 and embodiments 2 and 3 described later, the present invention provides gates to all freewheeling diodes and clamp diodes corresponding to the current paths in which recovery losses occur. This makes it possible to reduce recovery losses regardless of the current path taken between the positive or negative terminal and the input / output terminals, and between the neutral terminal and the input / output terminals, including commutation (covering all patterns in which recovery losses occur in a 3-level circuit).

[0027] Next, the features of this embodiment 1 will be described. The first feature is that MOS gate diodes are used for freewheel diodes 201 and 204 and clamp diodes 205 and 206, while conventional PN diodes or Schottky barrier diodes without gate electrodes are used for freewheel diodes 202 and 203.

[0028] In the 3-level main circuit, freewheeling diodes 202 and 203 do not experience recovery losses because no voltage is applied between the anode and cathode when current is commutated. Therefore, these diodes can be made from conventional PN diodes or Schottky barrier diodes without MOS gates.

[0029] The second feature is that the gate driver 102 drives the MOS gate clamp diode 206, and the gate driver 103 drives the MOS gate clamp diode 205.

[0030] Since freewheel diodes 202 and 203 do not require gate control, the MOS gate clamp diodes 205 and 206 can be driven with the now-unnecessary gate control signals, allowing all MOS gate diodes to be controlled without increasing the number of gate drivers.

[0031] Furthermore, since the number of gate drivers does not increase, there is no need to increase the command signals supplied from the higher-level controller, and there is the advantage that the conventional higher-level controller for 3-level circuit control can be used as is. The reason why gate driver 102 drives the MOS gate clamp diode 206 and gate driver 103 drives the MOS gate clamp diode 205 will be explained later.

[0032] Furthermore, in this embodiment 1, a photocoupler 303 and an input buffer circuit 304 are provided between the MOS gate clamp diode 205 and the gate driver 103, and a photocoupler 301 and an input buffer circuit 302 are provided between the MOS gate clamp diode 206 and the gate driver 102 to provide isolation. The reason for this is to prevent overcurrent generation due to the potential difference between the auxiliary emitter terminal 214 and the auxiliary anode terminal 230, and the potential difference between the auxiliary emitter terminal 218 and the auxiliary anode terminal 226.

[0033] Here, we will explain overcurrent generation using the potential difference between the auxiliary emitter terminal 214 and the auxiliary anode terminal 230 as an example. If the diode gate voltage output terminal 113 is directly connected to the MOS clamp diode gate terminal 229, and the auxiliary emitter potential terminal 114 is directly connected to the MOS clamp diode anode terminal 230, the multi-gate IGBTs 235 and 236 will turn on, and a positive power supply voltage (+E[V]) will be output to the AC input / output terminal 234. As a result, the potential of the auxiliary emitter terminal 214 will be +E[V], while the potential of the auxiliary anode terminal 230 will be clamped to the potential of the DC power supply neutral point terminal 231, becoming 0[V], creating a potential difference of E[V] between the auxiliary emitter terminal 214 and the auxiliary anode terminal 230. This will cause an overcurrent to flow from the auxiliary emitter terminal 214 to the auxiliary anode terminal 230.

[0034] Thus, directly connecting the auxiliary emitter terminal and auxiliary anode terminal, which are at different potentials, will cause an overcurrent due to the potential difference. Therefore, as mentioned above, insulation is used to prevent this overcurrent. On the other hand, the input buffer circuits 302 and 304 are necessary when the outputs of the photocouplers 301 and 303 cannot supply sufficient voltage to the gate electrodes of the MOS gate diodes.

[0035] Furthermore, the means of isolation is not limited to photocouplers; other methods such as using an isolation transformer may also be used. In addition, the isolation point may be placed between the gate driver 102 (103) and the multi-gate IGBT 236 (237), provided that the operational delay caused by using the photocoupler and input buffer does not affect the operation of the circuit.

[0036] Next, the detailed operation of the circuit according to this embodiment 1 will be described. Hereafter, "on" and "off" refer to the steady state where the gate voltage is "on" and "off," respectively. Also, "turn on" and "turn off" refer to the state where the gate voltage changes from "off to on" and from "on to off," respectively. Here, in multi-gate IGBT, "gate" refers to the "main gate" unless otherwise specified.

[0037] Figures 2 and 3 show timing charts for the gate commands of a multi-gate IGBT, the current of a MOS gate diode, and the load voltage when current flows from the load towards the main circuit and when current flows out of the main circuit towards the load. Figure 2 shows the operation when current flows from the load (AC input / output terminal 234 in Figure 1) towards the main circuit.

[0038] A1, B1, C1, and D1 are gate commands input to multi-gate IGBTs 235, 236, 237, and 238, respectively; E1 is a gate command input to MOS gate freewheel diode 201; and F1 is a gate command input to MOS gate clamp diode 206.

[0039] Furthermore, G1 represents the current of the MOS gate freewheel diode 201 (with the anode-to-cathode direction being positive), H1 represents the current of the MOS gate clamp diode 206 (with the anode-to-cathode direction being positive), and I1 represents the potential of the AC input / output terminal 234 with the DC power supply neutral point terminal 231 as the reference.

[0040] At time t1, the multi-gate IGBTs 235 (A1 in Figure 2) and 236 (B1 in Figure 2) are ON. Considering the direction of current, the current flows from the AC input / output terminal 234 shown in Figure 1 through the freewheeling diode 202 and the MOS-gate freewheeling diode 201 to the DC power supply positive terminal 232. Therefore, the potential of the AC input / output terminal 234 (I1 in Figure 2) is positive (+E [V]).

[0041] At time t2, the gate command A1 of the multi-gate IGBT235 turns off, but the current path remains unchanged because it flows through the freewheeling diode 202 and the MOS-gate freewheeling diode 201.

[0042] At time t4, when the multi-gate IGBT 237 (C1 in Figure 2) is turned on, the current path is commutated from the MOS-gate freewheeling diode 201 to the multi-gate IGBT 237, and flows through the AC input / output terminal 234, the multi-gate IGBT 237, and the MOS-gate clamp diode 206 to the DC power supply neutral point terminal 231. At this time, the potential of the AC input / output terminal 234 (I1 in Figure 2) changes from +E[V] to 0[V].

[0043] In this scenario, if C1 (multigate IGBT237) is accidentally turned on before A1 (multigate IGBT235) is turned off at time t2, A1, B1 (multigate IGBT236), and C1 will all be turned on. As a current path, a power supply short circuit is formed, as shown in Figure 1, from the DC power supply positive terminal 232 through the multigate IGBT235, multigate IGBT236, multigate IGBT237, and MOS gate clamp diode 206 to the DC power supply neutral terminal 231. This generates an overcurrent, leading to the destruction of the elements in the short circuit path.

[0044] To prevent this, A1 is turned off at time t2, and then C1 is turned on at time t4 after the dead time Td has elapsed, thereby preventing the formation of a short circuit and thus preventing overcurrent.

[0045] For the same reason, a dead time Td is also provided during the following periods: from the time B1 turns off t6 to the time D1 (multigate IGBT238) turns on t8, from the time D1 turns off t10 to the time B1 turns on t12, and from the time C1 turns off t14 to the time A1 turns on t16.

[0046] At time t4, when the current in the diode is commutated to another path (another element), a temporary reverse current flows as the carriers accumulated inside the diode are discharged, and this reverse current causes a recovery loss. In this case, if the carrier concentration inside the diode is high immediately before commutation, the reverse current will be large, and the recovery loss will be large. In a MOS gate diode, to reduce this loss, E1 (MOS gate freewheel diode 201) is turned on from time t3, a period T1 before time t4, to reduce the carrier concentration inside the diode in advance. This reduces the recovery loss.

[0047] Here, period T1 is the time required for the MOS diode to sufficiently reduce its carrier concentration after turn-on. The minimum time for T1 varies depending on the device characteristics of the multi-gate IGBT. Furthermore, period T2 is a margin time to prevent E1 from turning off before C1 turns on due to variations in pulse width. The larger the variation time from the turn-on command from the higher-level controller 001 to the application of a positive bias between the gate and emitter of the multi-gate IGBT in the main circuit, the longer the required period T2 will be.

[0048] At time t6, the gate command B1 of the multi-gate IGBT236 turns off, but the current path remains unchanged because it flows through the multi-gate IGBT237 and the MOS gate clamp diode 206.

[0049] At time t8, when the multi-gate IGBT 238 turns on, the current is commutated from the MOS gate clamp diode 206 to the multi-gate IGBT 238, and the current path flows through the AC input / output terminal 234, the multi-gate IGBT 237, and the multi-gate IGBT 238 to the DC power supply negative terminal 233, as shown in Figure 1. At this time, the potential of the AC input / output terminal 234 (I1 in Figure 2) changes from 0[V] to -E[V].

[0050] Furthermore, since recovery losses occur in the MOS gate clamp diode 206, similar to the MOS gate freewheel diode 201, the recovery losses can be reduced by turning on F1 (MOS gate clamp diode 206) from time t7, which is a period T1 before time t8.

[0051] Subsequently, D1 turns off (time t10), B1 turns on (time t12), C1 turns off (time t14), and A1 turns on (time t16), before returning to the state at time t1.

[0052] Between time t10 and time t17, the current path of the main circuit and the potential of the AC input / output terminal 234 fluctuate due to the control of the multi-gate IGBT. However, since neither the freewheeling diode nor the clamping diode generates recovery losses, the gate control of the diodes remains off at all times.

[0053] As described above, the gate command E1 of the MOS gate freewheel diode 201 should be turned on after a period Td-T1 from the turn-off of the multi-gate IGBT235 shown in A1 of Figure 2, and then turned off after a period T1+T2 from this turn-on.

[0054] Therefore, the gate command E1 for the MOS gate freewheel diode 201 can be generated by the gate driver 101, which receives the gate command for the multi-gate IGBT 235. Similarly, the gate command F1 for the MOS gate clamp diode 206 can be generated by the gate driver 102, which receives the gate command for the multi-gate IGBT 236. This is why the gate driver 102 drives the MOS gate clamp diode 206 and the gate driver 103 drives the MOS gate clamp diode 205.

[0055] Figure 3 shows the operation when current flows out from the main circuit towards the load (AC input / output terminal 234 in Figure 1). A1, B1, C1, D1, and I1 are the same as in Figure 2. E2 is the gate command input to the MOS gate freewheel diode 204, F2 is the gate command input to the MOS gate clamp diode 205, G2 is the current of the MOS gate freewheel diode 204 (with the anode-to-cathode direction being positive), and H2 is the current of the MOS gate clamp diode 205 (with the anode-to-cathode direction being positive).

[0056] At time t1, multi-gate IGBTs 235 (A1 in Figure 3) and 236 (B1 in Figure 3) are ON. Considering the direction of current, the current flows from the DC power supply positive terminal 232 shown in Figure 1 through multi-gate IGBTs 235 and 236 to the AC input / output terminal 234. Therefore, the potential of the AC input / output terminal 234 (I1 in Figure 3) is positive (+E [V]).

[0057] Subsequently, A1 turns off (time t2), C1 turns on (time t4), B1 turns off (time t6), and D1 turns on (time t8).

[0058] Between time t1 and time t10, the current path of the main circuit and the potential of the AC input / output terminal 234 fluctuate due to the control of the multi-gate IGBT. However, since no recovery loss occurs in either the freewheeling diode or the clamping diode, the gate control of the diodes remains off at all times.

[0059] At time t12, when the multi-gate IGBT 236 (B1 in Figure 3) is turned on, the current is commutated from the MOS-gate freewheeling diode 204 to the multi-gate IGBT 236, and flows through the DC power supply neutral point terminal 231, the MOS-gate clamp diode 205, and the multi-gate IGBT 236 to the AC input / output terminal 234. At this time, as shown in I1 in Figure 3, the potential of the AC input / output terminal 234 changes from -E[V] to 0[V].

[0060] At time t14, the multi-gate IGBT237 (C1 in Figure 3) turns off, but the current flows through the MOS gate clamp diode 205 and the multi-gate IGBT236, so there is no change in the current path.

[0061] At time t16, when the multi-gate IGBT 235 (A1 in Figure 3) is turned on, the current is commutated from the MOS gate clamp diode 205 to the multi-gate IGBT 235, and flows through the DC power supply positive terminal 232, the multi-gate IGBT 235, and the multi-gate IGBT 236 to the AC input / output terminal 234. At this time, as shown in I1 in Figure 3, the potential of the AC input / output terminal 234 changes from 0[V] to +E[V].

[0062] Furthermore, since recovery loss occurs in the MOS gate clamp diode 205, similar to the MOS gate freewheel diode 201, the recovery loss can be reduced by turning on the MOS gate clamp diode 205 (F2 in Figure 3) from time t15, which is a period T1 before time t16.

[0063] As described above, the gate command E2 of the MOS gate freewheel diode 204 should be turned on after a period Td-T1 from the turn-off of the multi-gate IGBT 238, as shown in D1 of Figure 3, and then turned off after a period T1+T2 from this turn-on.

[0064] Therefore, the gate command E2 of the MOS gate freewheel diode 204 can be generated by the gate driver 104 that receives the gate command of the multi-gate IGBT 238. Similarly, the gate command F2 of the MOS gate clamp diode 205 can be generated by the gate driver 103 that receives the gate command C1 of the multi-gate IGBT 237.

[0065] To summarize the above operating modes, the gate commands for MOS gate clamp diodes 205 and 206 can be generated by gate drivers 103 and 102, respectively, and the gate commands for MOS gate freewheel diodes 201 and 204 can be generated by gate drivers 101 and 104, respectively.

[0066] In addition, the diode gate commands E1 and F1 in Figure 2, and E2 and F2 in Figure 3, are all generated using the same logic. Therefore, these gate drivers can be applied in common whether the controlled object is a clamp diode or a freewheeling diode. [Examples]

[0067] Figure 4 shows a single-phase circuit diagram constituting a power conversion device according to Embodiment 2 of the present invention. Here, components common to Embodiment 1 shown in Figure 1 are denoted by the same reference numerals.

[0068] A feature of Embodiment 2 is that independent gate drivers 105 and 106 are provided for the gates of the MOS gate clamp diodes 205 and 206. The command signals input to these gate drivers 105 and 106 are branched from gate commands 006 and 007 and gate commands 004 and 005, respectively, from the higher-level controller 001.

[0069] Furthermore, the gate command generation logic of the gate driver 105 for the MOS gate clamp diode 205 is the same as that of the gate driver 103, and the gate command generation logic of the gate driver 106 for the MOS gate clamp diode 206 is the same as that of the gate driver 102.

[0070] In the previous embodiment 1, commands are transmitted via photocouplers 301 and 303 and input buffer circuits 302 and 304 to isolate the MOS gate clamp diodes 205 and 206. However, the photocouplers and buffer circuits have an operational delay, causing the MOS gate clamp diodes to operate later than the other elements. Therefore, when applying this to a system that requires high-precision control of the operating timing, it is necessary to eliminate this delay.

[0071] In this embodiment 2, gate drivers 105 and 106, which have internal insulating photocouplers, are added for MOS gate clamp diodes 205 and 206. This eliminates the aforementioned insulating photocouplers and buffer circuits, thereby preventing the operational delays caused by them.

[0072] Therefore, it is desirable to apply Example 1 to systems where minimizing the implementation space of the gate driver is important, and to apply Example 2 to systems where high-precision gate control is required. [Examples]

[0073] Figure 5 shows a single-phase circuit diagram constituting a power conversion device according to Embodiment 3 of the present invention. Here, components common to Embodiment 1 shown in Figure 1 and Embodiment 2 shown in Figure 4 are denoted by the same reference numerals.

[0074] The distinguishing feature of this third embodiment is that all the components in the circuit are unified to the same multi-gate IGBT and MOS-gate diode. Generally, IGBTs and freewheeling diodes are connected in antiparallel and housed in the same package. Therefore, as in the third embodiment shown in Figure 1, if conventional PN diodes are used for freewheeling diodes 202 and 203, and only diodes are used for clamp diodes 205 and 206, it becomes necessary to newly acquire or develop dedicated components, and in addition, managing multiple types of components becomes complicated.

[0075] In this embodiment 3, the aforementioned procurement and management problems can be solved by using identical components for all constituent elements. Furthermore, in order to replace all constituent elements with multi-gate IGBTs, the multi-gate IGBTs 239 and 240 shown in Figure 5 must be kept off at all times. For this reason, for the multi-gate IGBT 239, the main gate terminal 223 and auxiliary gate 224 must be short-circuited to the auxiliary emitter 226, and similarly for the multi-gate IGBT 240, the main gate terminal 227 and auxiliary gate 228 must be short-circuited to the auxiliary emitter 230, or a separate power supply must be prepared and a negative bias applied at all times to each gate terminal of the multi-gate IGBTs 239 and 240.

[0076] Furthermore, in this embodiment 3, the gate voltage is input to the MOS gate freewheel diodes 241 and 242. However, as mentioned above, these MOS gate diodes do not generate recovery losses during operation, so the main circuit losses are the same as in embodiments 1 and 2.

[0077] However, in this embodiment 3, the multi-gate IGBT and MOS gate diode elements are common, and the wiring connections to the gate driver are also made as common as possible. Therefore, both cost reduction due to the use of identical components and a reduction in the rate of manufacturing defects can be expected.

[0078] Although Examples 1 to 3 have been described above as embodiments of the present invention, the present invention is not limited to these embodiments, and various modifications are possible without departing from the spirit of the invention. [Explanation of Symbols]

[0079] 001: Higher-level controller, 002-009: Gate command lines, 101-106: Gate drivers, 107, 111, 115, 119, 123, 127: Main gate voltage output terminals of IGBTs, 108, 112, 116, 120, 124, 128: Auxiliary gate voltage output terminals of IGBTs, 109, 113, 117, 121, 125, 129: Gate voltage output terminals of diodes, 110, 114, 118, 122, 126, 130: Auxiliary emitter potential terminals, 201, 204, 241, 242: MOS gate freewheeling diodes, 202, 203: Freewheeling diodes, 205, 206: MOS gate clamping dies Ode, 207, 211, 215, 219, 223, 227: Main gate terminals of IGBT, 208, 212, 216, 220, 224, 228: Auxiliary gate terminals of IGBT, 209, 213, 217, 221, 225, 229: Gate terminals of diodes, 210, 214, 218, 222: Auxiliary emitter terminals, 226, 230: Auxiliary anode terminals, 231: DC power supply neutral point terminal, 232: DC power supply positive terminal, 233: DC power supply negative terminal, 234: AC input / output terminals, 235, 236, 237, 238, 239, 240: Multi-gate IGBT, 301, 303: Photocoupler, 302, 304: Input buffer circuit

Claims

1. A power conversion circuit for one phase of a power conversion device that converts between direct current and alternating current, A first unit circuit and a fourth unit circuit, each consisting of a semiconductor element having a pair of main terminals and a plurality of control terminals, and a diode with control terminals connected in antiparallel to the semiconductor element, It comprises a second unit circuit and a third unit circuit, each consisting of a semiconductor element having a pair of main terminals and a plurality of control terminals, and a diode connected in antiparallel to the semiconductor element. The first unit circuit, the second unit circuit, the third unit circuit, and the fourth unit circuit are connected in series in that order, from the first unit circuit to the fourth unit circuit. The positive terminal of the first unit circuit is connected to the positive power supply line, and the negative terminal of the fourth unit circuit is connected to the negative power supply line. The neutral point terminal is defined as the midpoint potential between the potentials of the positive power line and the negative power line. The connection point between the second unit circuit and the third unit circuit is used as an input / output terminal for one phase of AC. A first clamp diode with a control terminal, the cathode of which is connected to the connection point between the first unit circuit and the second unit circuit, and the anode of which is connected to the neutral point terminal, A second clamp diode with a control terminal, the cathode of which is connected to the neutral point terminal and the anode of which is connected to the connection point between the third unit circuit and the fourth unit circuit, and A power conversion circuit equipped with the following features.

2. A power conversion circuit according to claim 1, A first driver that drives and controls the semiconductor element and the diode with control terminal that constitute the first unit circuit, A second driver that drives and controls the semiconductor element and the second clamp diode with control terminal that constitute the second unit circuit, A third driver that drives and controls the semiconductor element and the first clamp diode with control terminal that constitute the third unit circuit, A fourth driver that drives and controls the semiconductor element and the diode with control terminal that constitute the fourth unit circuit. A power conversion circuit characterized by comprising the following features.

3. A power conversion circuit according to claim 2, The second driver drives and controls the second clamp diode with control terminals via an insulating element. The third driver drives and controls the first clamp diode with control terminals via an insulating element. A power conversion circuit characterized by the following features.

4. A power conversion circuit according to claim 1, A first driver that drives and controls the semiconductor element and the diode with control terminal that constitute the first unit circuit, A second driver that drives and controls the semiconductor elements constituting the second unit circuit, A third driver that drives and controls the semiconductor elements constituting the third unit circuit, A fourth driver that drives and controls the semiconductor element and the diode with control terminal that constitute the fourth unit circuit, A fifth driver that drives and controls the first clamp diode with the control terminal, A sixth driver that drives and controls the second clamp diode with the control terminal, A power conversion circuit characterized by comprising the following features.

5. A power conversion circuit according to claim 4, The fifth driver uses the drive command input to the third driver as its own drive command. The sixth driver uses the drive command input to the second driver as its own drive command. A power conversion circuit characterized by the following features.

6. A power conversion circuit according to claim 1, Both the second unit circuit and the third unit circuit are configured with diodes equipped with control terminals that allow gate control. A semiconductor element having a pair of main terminals and a plurality of control terminals is additionally connected between the connection point of the first unit circuit and the second unit circuit and the neutral point terminal, such that the first clamp diode with control terminals is connected in antiparallel to the semiconductor element, forming a fifth unit circuit composed of the semiconductor element and the first clamp diode with control terminals. A semiconductor element having a pair of main terminals and a plurality of control terminals is additionally connected between the neutral point terminal and the connection point between the third unit circuit and the fourth unit circuit, such that the second clamp diode with the control terminals is connected in antiparallel to the semiconductor element, thereby forming a sixth unit circuit composed of the semiconductor element and the second clamp diode with the control terminals. A first driver that drives and controls the semiconductor element and the diode with control terminal that constitute the first unit circuit, A second driver that drives and controls the semiconductor element and the diode with control terminal that constitute the second unit circuit, A third driver that drives and controls the semiconductor element and the diode with control terminal that constitute the third unit circuit, A fourth driver that drives and controls the semiconductor element and the diode with control terminal that constitute the fourth unit circuit, A fifth driver that drives and controls the diode with a control terminal that constitutes the fifth unit circuit, A sixth driver that drives and controls the diode with a control terminal that constitutes the sixth unit circuit, Equipped with, The semiconductor elements constituting the fifth unit circuit and the sixth unit circuit are kept off at all times. A power conversion circuit characterized by the following features.

7. A power conversion circuit according to claim 6, The gate terminals of the semiconductor elements constituting the fifth and sixth unit circuits are connected to a negative bias, thereby keeping each of the semiconductor elements permanently off. A power conversion circuit characterized by the following features.

8. A power conversion circuit according to claim 6, The fifth driver uses the drive command input to the third driver as its own drive command. The sixth driver uses the drive command input to the second driver as its own drive command. A power conversion circuit characterized by the following features.

9. A power conversion circuit according to any one of claims 1 to 8, Each of the semiconductor elements constituting the aforementioned unit circuit is a multi-gate IGBT. The diode with the control terminal and the first and second clamp diodes with the control terminal are MOS gate diodes. A power conversion circuit characterized by the following features.

10. A power conversion method using a single-phase power conversion circuit of a power conversion device that mutually converts direct current and alternating current, A first unit circuit is formed by a semiconductor element having a pair of main terminals and a plurality of control terminals, and a diode with a control terminal connected in antiparallel to the semiconductor element. The semiconductor element and the diode with a control terminal are driven and controlled based on a first drive command. The semiconductor element constituting a second unit circuit, which consists of a semiconductor element having a pair of main terminals and a plurality of control terminals and a diode connected in antiparallel to the semiconductor element, is driven and controlled based on a second drive command. A semiconductor element constituting a third unit circuit, which consists of a semiconductor element having a pair of main terminals and a plurality of control terminals and a diode connected in antiparallel to the semiconductor element, is driven and controlled based on a third drive command. A fourth unit circuit is formed by a semiconductor element having a pair of main terminals and a plurality of control terminals, and a diode with a control terminal connected in antiparallel to the semiconductor element. The semiconductor element and the diode with a control terminal are driven and controlled based on a fourth drive command. A first clamp diode with a control terminal is driven and controlled based on the third drive command. Its cathode is connected to the connection point between the first unit circuit and the second unit circuit, and its anode is connected to the neutral point terminal which is at the midpoint potential between the positive power supply line to which the positive terminal of the first unit circuit is connected and the negative power supply line to which the negative terminal of the fourth unit circuit is connected. A second clamp diode with a control terminal, whose cathode is connected to the neutral point terminal and whose anode is connected to the connection point between the third unit circuit and the fourth unit circuit, is driven and controlled based on the second drive command. A power conversion method characterized by the following features.

11. A power conversion method according to claim 10, The diode in the second unit circuit is configured with a diode having a control terminal that allows gate control, and the drive is controlled based on the second drive command. The diode in the third unit circuit is configured with a diode having a gate control terminal, and the drive is controlled based on the third drive command. A semiconductor element having a pair of main terminals and a plurality of control terminals is additionally connected between the connection point of the first unit circuit and the second unit circuit and the neutral point terminal, such that the first clamp diode with control terminals is connected in antiparallel to the semiconductor element, and the first clamp diode with control terminals, which constitutes a fifth unit circuit composed of the semiconductor element and the first clamp diode with control terminals, is driven and controlled based on the third drive command. A semiconductor element having a pair of main terminals and a plurality of control terminals is additionally connected between the neutral point terminal and the connection point between the third unit circuit and the fourth unit circuit, such that the second clamp diode with control terminals is connected in antiparallel to the semiconductor element, and the second clamp diode with control terminals, which constitutes a sixth unit circuit composed of the semiconductor element and the second clamp diode with control terminals, is driven and controlled based on the second drive command. The semiconductor elements constituting the fifth unit circuit and the sixth unit circuit are kept off at all times. A power conversion method characterized by the following features.

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