Wiring board and method for manufacturing the same

Abstract

To provide a wiring board capable of suppressing occurrence of a crack in a wiring layer and an insulation layer.SOLUTION: A wiring board comprises a first wiring structure including a first wiring layer and a first insulation layer and a second wiring structure including a second wiring layer and a second insulation layer and arranged on the first wiring structure. A wiring width and a wiring interval of the second wiring layer are smaller than those of the first wiring layer. The first insulation layer covers a side surface of the first wiring layer and exposes the upper surface thereof. The second insulation layer covers the upper surfaces of the first wiring layer and the first insulation layer. The first and second insulation layers contain a filler. An average grain diameter and a maximum grain diameter of the filler contained in the second insulation layer are smaller than an average grain diameter and a maximum grain diameter of the filler contained in the first insulation layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a wiring board and a method for manufacturing the same.

Background Art

[0002] Conventionally, a multilayer wiring board in which a plurality of wiring layers and a plurality of insulating layers are alternately laminated by a build-up method is known. In such a wiring board, for example, a fine gap is intentionally provided between the side surface of a wiring layer including via wiring and the insulating layer, and plating is embedded in this gap to form the wiring layer, thereby improving the adhesion between the side surface of the wiring layer including via wiring and the insulating layer (see, for example, Patent Document 1).

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, it is difficult to embed plating in a fine gap. In addition, an unintentional gap may be formed between the side surface of the wiring layer and the insulating layer, and cracks may occur in the wiring layer or the insulating layer due to this gap, which may cause disconnection or the like.

[0005] The present invention has been made in view of the above points, and an object thereof is to provide a wiring board capable of suppressing the occurrence of cracks in a wiring layer and an insulating layer.

Means for Solving the Problems

[0006] This wiring board comprises a first wiring structure having a first wiring layer and a first insulating layer, and a second wiring structure having a second wiring layer and a second insulating layer, the second wiring structure being arranged on the first wiring structure, wherein the wiring width and wiring spacing of the second wiring layer are smaller than those of the first wiring layer, and the first insulating layer covers the sides of the first wiring layer while exposing its upper surface. The upper surface of the first insulating layer is flush with the upper surface of the first wiring layer. The second insulating layer covers the upper surface of the first wiring layer and the upper surface of the first insulating layer, and the first insulating layer and the second insulating layer contain fillers, and the average particle size and maximum particle size of the fillers contained in the second insulating layer are smaller than the average particle size and maximum particle size of the fillers contained in the first insulating layer. Furthermore, the average particle size of the filler contained in the second insulating layer is 0.1 μm or less, and the maximum particle size of the filler contained in the second insulating layer is 1 μm or less. . [Effects of the Invention]

[0007] According to the disclosed technology, it is possible to provide a wiring board that can suppress the occurrence of cracks in the wiring layer and insulating layer. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional view illustrating a wiring board according to the first embodiment. [Figure 2] This is a diagram (part 1) illustrating the manufacturing process of a wiring board according to the first embodiment. [Figure 3] This is a diagram (part 2) illustrating the manufacturing process of a wiring board according to the first embodiment. [Figure 4] This is a diagram (part 3) illustrating the manufacturing process of a wiring board according to the first embodiment. [Figure 5] This is a diagram (part 4) illustrating the manufacturing process of a wiring board according to the first embodiment. [Figure 6] This is a diagram (part 5) illustrating the manufacturing process of a wiring board according to the first embodiment. [Figure 7] This is a cross-sectional view illustrating a semiconductor device according to an application example of the first embodiment. [Modes for carrying out the invention]

[0009] The embodiments for carrying out the invention will be described below with reference to the drawings. In each drawing, the same reference numerals are used for identical components, and redundant explanations may be omitted.

[0010] <First Embodiment> [Structure of a wiring board] Figure 1 is a cross-sectional view illustrating a wiring board according to the first embodiment. Figure 1(a) is an overall view, and Figure 1(b) is an enlarged view of part A in Figure 1(a).

[0011] Referring to Figure 1, the wiring board 5 includes a core substrate 10, a first wiring structure 1, a second wiring structure 2, a third wiring structure 3, solder resist layers 40 and 50, and external connection terminals 60. The first wiring structure 1 and the second wiring structure 2 are arranged on one side of the core substrate 10, and the third wiring structure 3 is arranged on the other side of the core substrate 10. The solder resist layers 40 and 50 and the external connection terminals 60 can be provided as needed.

[0012] In this embodiment, for convenience, the solder resist layer 40 side of the wiring board 5 in Figure 1 is referred to as the upper side or one side, and the solder resist layer 50 side as the lower side or the other side. Also, the surface of each part facing the solder resist layer 40 is referred to as one surface or the upper surface, and the surface facing the solder resist layer 50 is referred to as the other surface or the lower surface. However, the wiring board 5 can be used upside down or positioned at any angle. Furthermore, a plan view refers to viewing the object from the direction normal to one surface of the solder resist layer 40, and a planar shape refers to the shape of the object viewed from the direction normal to one surface of the solder resist layer 40.

[0013] As the core substrate 10, for example, a so-called glass epoxy substrate can be used, which is made by impregnating glass cloth with a thermosetting insulating resin such as epoxy resin. As the core substrate 10, a substrate made by impregnating woven or nonwoven fabric of glass fiber, carbon fiber, aramid fiber, etc. with a thermosetting insulating resin such as epoxy resin may also be used. The thickness of the core substrate 10 can be, for example, about 80 to 1200 μm. Note that the illustration of glass cloth, etc., is omitted in each figure.

[0014] The core substrate 10 has a plurality of through holes 10x formed therein. The planar shape of the through holes 10x can be, for example, a circle with a diameter of about 50 to 100 μm. The pitch of the through holes 10x can be, for example, about 100 to 1000 μm. Through electrodes 20 are formed on the inner wall surface of the through holes 10x, and a resin part 30 is filled in the center of the through hole 10x (inside the through electrodes 20). For example, copper (Cu) can be used as the material for the through electrodes 20. The thickness of the through electrodes 20 can be, for example, about 15 to 35 μm. For example, a thermosetting insulating resin such as epoxy resin can be used as the material for the resin part 30.

[0015] The first wiring structure 1 is laminated on one surface 10a of the core substrate 10. The first wiring structure 1 is a wiring structure in which a plurality of first wiring layers and a plurality of first insulating layers are laminated. In this embodiment, the plurality of first wiring layers include first wiring layer 11, first wiring layer 13, and first wiring layer 15. First wiring layer 15 is the uppermost first wiring layer among the plurality of first wiring layers, located on the side closest to the second wiring structure 2. Note that the number of first wiring layers is not limited to the example of this embodiment. There may be only one first wiring layer. In this embodiment, the plurality of first insulating layers include first insulating layer 12, first insulating layer 14, and first insulating layer 16. First insulating layer 16 is the uppermost first insulating layer among the plurality of first insulating layers, located on the side closest to the second wiring structure 2. Note that the number of first insulating layers is not limited to the example of this embodiment. There may be only one first insulating layer.

[0016] The third wiring structure 3 is laminated on the other surface 10b of the core substrate 10. The third wiring structure 3 is a wiring structure in which a plurality of third wiring layers and a plurality of third insulating layers are laminated. In the present embodiment, the plurality of third wiring layers include a third wiring layer 31, a third wiring layer 33, and a third wiring layer 35. Note that the number of third wiring layers is not limited to the example of the present embodiment. In the present embodiment, the plurality of third insulating layers include a third insulating layer 32 and a third insulating layer 34. Note that the number of third insulating layers is not limited to the example of the present embodiment.

[0017] The first wiring layer 11 is a wiring pattern formed on one surface 10a of the core substrate 10. The third wiring layer 31 is a wiring pattern formed on the other surface 10b of the core substrate 10. The first wiring layer 11 is electrically connected to the third wiring layer 31 via a through electrode 20 penetrating the core substrate 10. The first wiring layer 11 and the third wiring layer 31 are made of, for example, a metal foil such as a copper foil or a plating layer such as copper plating. The thickness of the first wiring layer 11 and the third wiring layer 31 can be set to about 15 to 35 μm, for example. The line / space of the first wiring layer 11 and the third wiring layer 31 can be set to about 10 μm / 10 μm to 50 μm / 50 μm, for example.

[0018] Note that the "line" in the line / space represents the wiring width, and the "space" represents the interval (wiring interval) between adjacent wirings. For example, when the line / space is described as 10 μm / 10 μm to 50 μm / 50 μm, it means that the wiring width is 10 μm or more and 50 μm or less, and the wiring interval between adjacent wirings is 10 μm or more and 50 μm or less. It is not always necessary to make the wiring width and the wiring interval equal.

[0019] The first insulating layer 12 is formed on one surface 10a of the core substrate 10 so as to cover the first wiring layer 11. The third insulating layer 32 is formed on the other surface 10b of the core substrate 10 so as to cover the third wiring layer 31. The first insulating layer 12 and the third insulating layer 32 are insulating layers mainly composed of a non-photosensitive resin. The first insulating layer 12 and the third insulating layer 32 can mainly be composed of a thermosetting non-photosensitive resin such as an epoxy resin, an imide resin, a phenolic resin, a cyanate resin, etc. The thickness of the first insulating layer 12 and the third insulating layer 32 can be, for example, about 20 to 40 μm. The first insulating layer 12 and the third insulating layer 32 may contain a filler such as silica (SiO2). The average particle size, the maximum particle size, and the content of the filler contained in the first insulating layer 12 and the third insulating layer 32 can be the same as those of the filler 16f contained in the first insulating layer 16 described later, for example. The average particle size and the maximum particle size of the filler can be measured using a scanning electron microscope.

[0020] The first wiring layer 13 is formed on one side of the first insulating layer 12 and is electrically connected to the first wiring layer 11. The first wiring layer 13 includes a via wiring filled in a via hole 12x that penetrates the first insulating layer 12 and exposes one surface of the first wiring layer 11, and a wiring pattern formed on one surface of the first insulating layer 12. The via hole 12x can be a frustum-shaped concave portion with a diameter of the opening on the first insulating layer 14 side being larger than the diameter of the bottom surface of the opening formed by the upper surface of the first wiring layer 11.

[0021] The third wiring layer 33 is formed on the other side of the third insulating layer 32 and is electrically connected to the third wiring layer 31. The third wiring layer 33 includes a via wiring filled in a via hole 32x that penetrates the third insulating layer 32 and exposes the other surface of the third wiring layer 31, and a wiring pattern formed on the other surface of the third insulating layer 32. The via hole 32x can be a frustum-shaped concave portion with a diameter of the opening on the third insulating layer 34 side being larger than the diameter of the bottom surface of the opening formed by the lower surface of the third wiring layer 31.

[0022] The diameter of the openings of the via holes 12x and 32x can be, for example, about 50 to 60 μm. For the material of the first wiring layer 13 and the third wiring layer 33, copper can be used, for example. The thickness of the wiring pattern of the first wiring layer 13 and the third wiring layer 33 can be, for example, about 15 to 25 μm. The line / space of the wiring pattern of the first wiring layer 13 and the third wiring layer 33 can be, for example, about 10 μm / 10 μm to 50 μm / 50 μm.

[0023] The first insulating layer 14 is formed to cover the first wiring layer 13 on one side of the first insulating layer 12. The third insulating layer 34 is formed to cover the third wiring layer 33 on the other side of the third insulating layer 32. The material and thickness of the first insulating layer 14 and the third insulating layer 34 can be the same as, for example, the first insulating layer 12 and the third insulating layer 32. The first insulating layer 14 and the third insulating layer 34 may contain fillers such as silica (SiO2). The average particle size, maximum particle size, and filler content of the fillers contained in the first insulating layer 14 and the third insulating layer 34 can be the same as, for example, the filler 16f contained in the first insulating layer 16 described later.

[0024] The first wiring layer 15 is formed on one side of the first insulating layer 14 and is electrically connected to the first wiring layer 13. The first wiring layer 15 consists of via wiring filled in via holes 14x that penetrate the first insulating layer 14 and expose one side of the first wiring layer 13, and a wiring pattern formed on one side of the first insulating layer 14. The via holes 14x can be inverted frustoconical recesses in which the diameter of the opening that opens to the first insulating layer 16 side is larger than the diameter of the bottom of the opening formed by the upper surface of the first wiring layer 13.

[0025] The third wiring layer 35 is formed on the other side of the third insulating layer 34 and is electrically connected to the third wiring layer 33. The third wiring layer 35 consists of via wiring filled in via holes 34x that penetrate the third insulating layer 34 and expose the other side of the third wiring layer 33, and a wiring pattern formed on the other side of the third insulating layer 34. The via holes 34x can be frustoconical recesses in which the diameter of the opening that opens to the solder resist layer 50 side is larger than the diameter of the bottom surface of the opening formed by the lower surface of the third wiring layer 33.

[0026] The diameter of the openings of the via holes 14x and 34x can be, for example, about 50-60 μm. The material of the first wiring layer 15 and the third wiring layer 35, the thickness of the wiring patterns of the first wiring layer 15 and the third wiring layer 35, and the line / space of the wiring patterns of the first wiring layer 15 and the third wiring layer 35 can be, for example, the same as that of the first wiring layer 13 and the third wiring layer 33.

[0027] The first insulating layer 16 is formed so as to cover the side surface of the first wiring layer 15 on the upper surface of the first insulating layer 14, leaving the upper surface exposed. The material of the first insulating layer 16 can be, for example, the same as that of the first insulating layer 12. The first insulating layer 16 contains a filler 16f such as silica (SiO2). The average particle size of the filler 16f can be, for example, 0.5 μm or less. The maximum particle size of the filler 16f can be, for example, 5 μm or less. The content of the filler 16f can be, for example, about 72 wt%. The average particle size and maximum particle size of the filler 16f contained in the first insulating layer 16 are larger than the average particle size and maximum particle size of the filler 21f contained in the second insulating layer 21, which will be described later.

[0028] The thickness of the first insulating layer 16 can be, for example, about 5 to 15 μm. The thickness of the first insulating layer 16 is the same as the thickness of the wiring pattern constituting the first wiring layer 15, and the upper surface of the first insulating layer 16 is flush with the upper surface of the first wiring layer 15. The roughness of the upper surface of the first insulating layer 16 can be, for example, about Ra 20 to 60 nm. The roughness of the upper surfaces of the first insulating layers 12 and 14 is, for example, about Ra 150 to 200 nm. In other words, the roughness of the upper surface of the first insulating layer 16 is smaller than the roughness of the upper surfaces of the first insulating layers other than the first insulating layer 16.

[0029] The second wiring structure 2 is arranged on the first wiring structure 1. The second wiring structure 2 is a wiring structure in which a plurality of second wiring layers and a plurality of second insulating layers are stacked. In this embodiment, the plurality of second wiring layers include second wiring layer 22, second wiring layer 24, and second wiring layer 26. The second wiring layer 22 is the bottommost second wiring layer among the plurality of second wiring layers, located on the side closest to the first wiring structure 1. Note that the number of second wiring layers is not limited to the example in this embodiment. There may be only one second wiring layer. In this embodiment, the plurality of second insulating layers include a second insulating layer 21, a second insulating layer 23, and a second insulating layer 25. The second insulating layer 21 is the bottommost second insulating layer among the plurality of second insulating layers, located on the side closest to the first wiring structure 1. Note that the number of second insulating layers is not limited to the example of this embodiment. There may be only one second insulating layer.

[0030] The wiring width and spacing of the second wiring layer are smaller than those of the first wiring layer. Furthermore, the wiring width and spacing of the second wiring layer are smaller than those of the third wiring layer. In other words, the second wiring layer constituting the second wiring structure 2 is a fine wiring layer with a higher wiring density than the first wiring layer constituting the first wiring structure 1 and the third wiring layer constituting the third wiring structure 3.

[0031] The second insulating layer 21 is formed to cover the upper surface of the first wiring layer 15 and the upper surface of the first insulating layer 16 of the first wiring structure 1. The second insulating layer 21 is an insulating layer mainly composed of a non-photosensitive resin. The second insulating layer 21 can be mainly composed of a thermosetting non-photosensitive resin such as epoxy resin, imide resin, phenolic resin, or cyanate resin. The second insulating layer 21 contains a filler 21f such as silica (SiO2). The average particle size and maximum particle size of the filler 21f contained in the second insulating layer 21 are smaller than the average particle size and maximum particle size of the filler 16f contained in the first insulating layer 16. The average particle size of the filler 21f can be, for example, 0.1 μm or less. The maximum particle size of the filler 21f can be, for example, 1 μm or less. The content of the filler 21f can be, for example, about 50 wt%. The second insulating layer 21 is a thinner insulating layer than the first insulating layers 12 and 14. The thickness of the second insulating layer 21 can be, for example, about 10 to 20 μm.

[0032] The second wiring layer 22 is formed on one side of the second insulating layer 21 and is electrically connected to the first wiring layer 15 of the first wiring structure 1. The second wiring layer 22 is composed of via wiring filled in via holes 21x that penetrate the second insulating layer 21 and expose one surface of the first wiring layer 15, and a wiring pattern formed on one surface of the second insulating layer 21. The via holes 21x can be inverted truncated cone-shaped recesses in which the diameter of the opening that opens to the second insulating layer 23 side is larger than the diameter of the bottom surface of the opening formed by the upper surface of the first wiring layer 15. The diameter of the opening of the via hole 21x can be, for example, about 5 to 10 μm. As the material of the second wiring layer 22, for example, copper can be used. The thickness of the wiring pattern constituting the second wiring layer 22 can be, for example, about 5 to 10 μm. The line / space of the wiring pattern constituting the second wiring layer 22 can be, for example, about 3 μm / 3 μm to 8 μm / 8 μm.

[0033] The second insulating layer 23 is formed on one side of the second insulating layer 21 so as to cover the second wiring layer 22. The material and thickness of the second insulating layer 23 can be the same as, for example, the second insulating layer 21. The second insulating layer 23 may contain a filler such as silica (SiO2). The average particle size and maximum particle size of the filler contained in the second insulating layer 23 are smaller than the average particle size and maximum particle size of the filler contained in any of the first insulating layers. The average particle size, maximum particle size, and filler content of the filler contained in the second insulating layer 23 can be the same as, for example, the filler 21f contained in the second insulating layer 21.

[0034] The second wiring layer 24 is formed on one side of the second insulating layer 23 and is electrically connected to the second wiring layer 22. The second wiring layer 24 consists of via wiring filled in via holes 23x that penetrate the second insulating layer 23 and expose one side of the second wiring layer 22, and a wiring pattern formed on one side of the second insulating layer 23. The via holes 23x can be inverted frustoconical recesses in which the diameter of the opening that opens towards the second insulating layer 25 is larger than the diameter of the bottom of the opening formed by the upper surface of the second wiring layer 22. The diameter of the opening of the via hole 23x can be, for example, about 5 to 10 μm. The material of the second wiring layer 24, the thickness of the wiring pattern constituting the second wiring layer 24, and the line / space of the wiring pattern constituting the second wiring layer 24 can be, for example, the same as those of the second wiring layer 22.

[0035] The second insulating layer 25 is formed on one side of the second insulating layer 23 so as to cover the second wiring layer 24. The material and thickness of the second insulating layer 25 can be the same as, for example, the second insulating layer 23. The second insulating layer 25 may contain a filler such as silica (SiO2). The average particle size and maximum particle size of the filler contained in the second insulating layer 25 are smaller than the average particle size and maximum particle size of the filler contained in any of the first insulating layers. The average particle size, maximum particle size, and filler content of the filler contained in the second insulating layer 25 can be the same as, for example, the filler 21f contained in the second insulating layer 21.

[0036] The second wiring layer 26 is formed on one side of the second insulating layer 25 and is electrically connected to the second wiring layer 24. The second wiring layer 26 consists of via wiring filled in via holes 25x that penetrate the second insulating layer 25 and expose one side of the second wiring layer 24, and wiring patterns and pads formed on one side of the second insulating layer 25. The via holes 25x can be inverted frustoconical recesses in which the diameter of the opening that opens to the solder resist layer 40 side is larger than the diameter of the bottom surface of the opening formed by the upper surface of the second wiring layer 24. The diameter of the opening of the via hole 25x can be, for example, about 5 to 10 μm.

[0037] The material of the second wiring layer 26 and the thickness of the wiring pattern constituting the second wiring layer 26 can be the same as, for example, the second wiring layer 22. The thickness of the pads constituting the second wiring layer 26 can be, for example, about 10 to 20 μm. The planar shape of the pads constituting the second wiring layer 26 can be, for example, a circle with a diameter of about 20 to 30 μm. The pitch of the pads constituting the second wiring layer 26 can be, for example, about 40 to 50 μm. The pads constituting the second wiring layer 26 function as pads for mounting electronic components to electrically connect to electronic components such as semiconductor chips.

[0038] Furthermore, a surface treatment layer (not shown) may be formed on the surface (top surface only, or top surface and side surface) of the pads constituting the second wiring layer 26. Examples of surface treatment layers include an Au layer, a Ni / Au layer (a metal layer formed by stacking a Ni layer and an Au layer in that order), a Ni / Pd / Au layer (a metal layer formed by stacking a Ni layer, a Pd layer, and an Au layer in that order), etc. Alternatively, an anti-oxidation treatment such as OSP (Organic Solderability Preservative) treatment may be applied to the surface (top surface only, or top surface and side surface) of the pads constituting the second wiring layer 26 to form a surface treatment layer.

[0039] The solder resist layer 40 is the outermost insulating layer formed on the outer periphery of one side of the second insulating layer 25 of the second wiring structure 2. As the material for the solder resist layer 40, for example, a photosensitive insulating resin mainly composed of phenolic resin or polyimide resin can be used. The solder resist layer 40 may also contain fillers such as silica (SiO2). The solder resist layer 40 has an opening 40x, and a part of the second wiring layer 26 is exposed within the opening 40x.

[0040] The solder resist layer 50 is the outermost insulating layer formed on the other side of the third insulating layer 34 of the third wiring structure 3, so as to cover the third wiring layer 35 of the third wiring structure 3. As the material for the solder resist layer 50, for example, a photosensitive insulating resin mainly composed of phenolic resin or polyimide resin can be used. The solder resist layer 40 may contain fillers such as silica (SiO2).

[0041] The solder resist layer 50 has an opening 50x, and a portion of the third wiring layer 35 of the third wiring structure 3 is exposed at the bottom of the opening 50x. External connection terminals 60, such as solder balls, are formed on the third wiring layer 35 exposed within the opening 40x, as needed.

[0042] As shown in Figure 1(b), during the manufacturing process of the wiring board 5, a gap G with a width of approximately 5 μm may be formed between the outer edge of the wiring pattern constituting the first wiring layer 15 and the first insulating layer 16. If the gap G is left as is, cracks may occur in the first wiring layer 15 and the first insulating layer 16, potentially leading to disconnections or other problems.

[0043] However, as described later, the manufacturing process of the wiring board 5 includes a step of forming a second insulating layer 21 that covers the upper surface of the first wiring layer 15 and the upper surface of the first insulating layer 16. In this step, an uncured second insulating resin layer that covers the upper surface of the first wiring layer 15 and the upper surface of the first insulating layer 16 is placed, and the second insulating resin layer is heated and pressurized toward the first wiring structure 1 to cure it, thereby forming the second insulating layer 21. At this time, the softened second insulating resin layer fills the gap G and then hardens, so that the gap G eventually disappears. As a result, the occurrence of cracks in the first wiring layer 15 and the first insulating layer 16 can be suppressed. In addition, since a part of the second insulating layer 21 penetrates into the gap G, an anchoring effect is created, which can improve the adhesion between the first wiring layer 15 and the first insulating layer 16 and the second insulating layer 21.

[0044] If the second insulating layer 21 contains filler 16f in the same way as the first insulating layer 16, the average particle size of filler 16f is 0.5 μm or less, and the maximum particle size is 5 μm or less. Therefore, if larger filler 16f is present near the gap G, it may hinder the filling of the gap G, which is about 5 μm wide, and the gap G may not be completely filled. However, since the average particle size of filler 21f contained in the second insulating layer 21 is 0.1 μm or less, and the maximum particle size is 1 μm or less, there is no problem in filling the gap G, which is about 5 μm wide. In other words, generally, non-photosensitive resins used in insulating layers contain fillers to adjust the insulating properties and thermal expansion coefficient, but when filling gaps with resin, as in the wiring board 5, it is necessary to adjust the particle size of the filler to ensure proper filling of the gaps.

[0045] [Manufacturing method for wiring boards] Next, a method for manufacturing a wiring board according to the first embodiment will be described. Figures 2 to 6 illustrate the manufacturing process of a wiring board according to the first embodiment. Here, the manufacturing process of the wiring board 5 will be explained while illustrating the area enclosed by the dashed line B of the wiring board 5 shown in Figure 1(a).

[0046] First, in the process shown in Figure 2(a), a core substrate 10 having through electrodes 20 is formed. Specifically, a laminate is prepared in which plain, unpatterned copper foil is formed on one side and the other side of the core substrate 10, which is, for example, a so-called glass epoxy substrate. Then, in the prepared laminate, after thinning the copper foil on each side as necessary, through holes 10x that penetrate the core substrate 10 and the copper foil on each side are formed by laser processing using a CO2 laser or the like.

[0047] Next, if necessary, desmear treatment is performed to remove any resin residue from the core substrate 10 that has adhered to the inner wall surface of the through-hole 10x. Then, a seed layer (copper, etc.) is formed to cover the copper foil on each surface and the inner wall surface of the through-hole 10x by methods such as electroless plating or sputtering, and an electroplated layer (copper, etc.) is formed on the seed layer by an electroplating method that uses the seed layer as a power supply layer. As a result, a through-electrode 20 is formed on the inner wall of the through-hole 10x with the electroplated layer laminated on the seed layer, and a first wiring layer 11 and a third wiring layer 31 are formed on one side and the other side of the core substrate 10, with the copper foil, seed layer, and electroplated layer laminated on top of each other. Next, the first wiring layer 11 and the third wiring layer 31 are patterned into a predetermined planar shape by methods such as subtractive plating. In addition, the resin part 30 is filled inside the through-electrode 20 within the through-hole 10x.

[0048] Next, in the process shown in Figure 2(b), a semi-cured film-like epoxy resin or the like is laminated onto one surface 10a of the core substrate 10 so as to cover the first wiring layer 11, and then cured to form the first insulating layer 12. Similarly, a semi-cured film-like epoxy resin or the like is laminated onto the other surface 10b of the core substrate 10 so as to cover the third wiring layer 31, and then cured to form the third insulating layer 32. Alternatively, instead of laminating with a film-like epoxy resin, a liquid or paste-like epoxy resin or the like may be applied and then cured to form the first insulating layer 12 and the third insulating layer 32. The thickness of each of the first insulating layer 12 and the third insulating layer 32 can be, for example, about 20 to 40 μm. Each of the first insulating layer 12 and the third insulating layer 32 may contain a filler such as silica (SiO2).

[0049] Next, in the process shown in Figure 2(c), a via hole 12x is formed in the first insulating layer 12, penetrating the first insulating layer 12 and exposing the upper surface of the first wiring layer 11. Also, a via hole 32x is formed in the third insulating layer 32, penetrating the third insulating layer 32 and exposing the lower surface of the third wiring layer 31. The via holes 12x and 32x can be formed by a laser processing method, for example, using a CO2 laser. The via hole 12x can be an inverted frustoconical recess in which the diameter of the opening on the side where the first insulating layer 14 is formed is larger than the diameter of the bottom surface of the opening formed by the upper surface of the first wiring layer 11. The via hole 32x can be a frustoconical recess in which the diameter of the opening on the side where the third insulating layer 34 is formed is larger than the diameter of the bottom surface of the opening formed by the lower surface of the third wiring layer 31. After forming via holes 12x and 32x, it is preferable to perform a desmear treatment to remove resin residue adhering to the surfaces of the first wiring layer 11 and the third wiring layer 31 that are exposed at the bottom of the via holes 12x and 32x, respectively.

[0050] Next, in the process shown in Figure 3(a), a seed layer 13a is formed on the surface of the first insulating layer 12, including the inner wall of the via hole 12x, and on the surface of the first wiring layer 11 exposed inside the via hole 12x, by electroless copper plating or copper sputtering. Also, a seed layer 33a is formed on the surface of the third insulating layer 32, including the inner wall of the via hole 32x, and on the surface of the third wiring layer 31 exposed inside the via hole 32x, by electroless copper plating or copper sputtering. The thickness of the seed layers 13a and 33a can be, for example, about 200 to 400 nm. Next, a plating resist pattern 300 having openings 300x that match the shape of the wiring pattern of the first wiring layer 13 is formed on the seed layer 13a. Also, a plating resist pattern 310 having openings 310x that match the shape of the wiring pattern of the third wiring layer 33 is formed on the seed layer 33a.

[0051] Next, electroplating of copper supplied from seed layer 13a deposits an electroplated layer 13b on the seed layer 13a exposed to the opening 300x of the plating resist pattern 300. Furthermore, electroplating of copper supplied from seed layer 33a deposits an electroplated layer 33b on the seed layer 33a exposed to the opening 310x of the plating resist pattern 310.

[0052] Next, in the process shown in Figure 3(b), the plating resist patterns 300 and 310 are removed using a plating resist stripping solution. Then, etching is performed using the electroplating layer 13b as a mask to remove the seed layer 13a exposed from the electroplating layer 13b and form the first wiring layer 13. Furthermore, etching is performed using the electroplating layer 33b as a mask to remove the seed layer 33a exposed from the electroplating layer 33b and form the third wiring layer 33.

[0053] Next, in the process shown in Figure 3(c), a first insulating layer 14 is formed on the upper surface of the first insulating layer 12 so as to cover the first wiring layer 13, using the same formation method as for the first insulating layer 12. The material and thickness of the first insulating layer 14 can be, for example, the same as for the first insulating layer 12. Furthermore, a third insulating layer 34 is formed on the lower surface of the third insulating layer 32 so as to cover the third wiring layer 33, using the same formation method as for the third insulating layer 32. The material and thickness of the third insulating layer 34 can be, for example, the same as for the third insulating layer 32.

[0054] Next, in the process shown in Figure 4(a), via holes 14x and 34x are formed in the same manner as in the process shown in Figure 2(c). Then, a seed layer 15a is formed on the surface of the first insulating layer 14, including the inner wall of the via hole 14x, and on the surface of the first wiring layer 13 exposed inside the via hole 14x, by electroless copper plating or sputtering. In addition, a seed layer 35a is formed on the surface of the third insulating layer 34, including the inner wall of the via hole 34x, and on the surface of the third wiring layer 33 exposed inside the via hole 34x, by electroless copper plating or sputtering. Next, a plating resist pattern 320 having openings 320x that match the shape of the wiring pattern of the first wiring layer 15 is formed on the seed layer 15a. In addition, a plating resist pattern 330 having openings 330x that match the shape of the wiring pattern of the third wiring layer 35 is formed on the seed layer 35a.

[0055] Next, electroplating of copper supplied from seed layer 15a is performed to deposit an electroplated layer 15b on the seed layer 15a exposed to the opening 330x of the plating resist pattern 330. Furthermore, electroplating of copper supplied from seed layer 35a is performed to deposit an electroplated layer 35b on the seed layer 35a exposed to the opening 330x of the plating resist pattern 330. The deposition of the electroplated layer 15b is continued until a curved projection is formed on the upper surface of the electroplated layer 15b.

[0056] With respect to the upper surface of the first insulating layer 14, the thickness of the thinnest part of the electroplated layer 15b (the thickness of the outer edge of the electroplated layer 15b) can be, for example, about 15 to 25 μm. With respect to the upper surface of the first insulating layer 14, the thickness of the thickest part of the electroplated layer 15b (the thickness of the central part of the electroplated layer 15b) can be, for example, the thickness of the thinnest part plus about 3 to 8 μm. That is, the height of the protrusion formed on the upper surface of the electroplated layer 15b can be, for example, about 3 to 8 μm.

[0057] Furthermore, in order to improve the filling properties of the electroplating layer 15b and facilitate the formation of curved protrusions on the upper surface of the electroplating layer 15b, the opening diameter of the via hole 14x may be made smaller than the opening diameters of the via holes 12x and 34x. Also, the lower surface of the electroplating layer 35b may be flat or may have curved protrusions. Moreover, even if curved protrusions are formed on the lower surface of the electroplating layer 35b, it is not necessary to polish the protrusions to flatten them in subsequent processes, because no fine wiring layer is formed in the third wiring structure 3.

[0058] Next, in the process shown in Figure 4(b), the plating resist patterns 320 and 330 are removed. Then, etching is performed using the electroplating layer 15b as a mask to remove the seed layer 15a exposed from the electroplating layer 15b and form the first wiring layer 15. Furthermore, etching is performed using the electroplating layer 35b as a mask to remove the seed layer 35a exposed from the electroplating layer 35b and form the third wiring layer 35. Through this process, the third wiring structure 3 is formed on the lower surface of the core substrate 10.

[0059] Next, in the process shown in Figure 4(c), a first insulating resin layer 16A is formed to cover the side and top surfaces of the first wiring layer 15 using the same formation method as for the first insulating layer 12. The material of the first insulating resin layer 16A can be, for example, the same as that of the first insulating layer 12. The thickness of the first insulating resin layer 16A is set to be sufficient to cover the entire first wiring layer 15, including the protruding parts. The thickness of the first insulating resin layer 16A can be, for example, about 20 to 40 μm.

[0060] Next, in the process shown in Figure 5(a), the first insulating resin layer 16A is polished to form a first insulating layer 16 that covers the side surface of the first wiring layer 15 and exposes its upper surface. Polishing is continued until the upper surface of the first wiring layer 15 is exposed from the upper surface of the first insulating layer 16, and further until the upper surface of the first wiring layer 15 is flattened. In other words, the protrusions formed on the upper surface of the first wiring layer 15 are removed by polishing, and the upper surface of the first wiring layer 15 and the upper surface of the first insulating layer 16 are made flush. For polishing, for example, the CMP method (chemical mechanical polishing method) can be used. The thickness of the wiring pattern constituting the first wiring layer 15 after polishing is the same as the thickness of the first insulating layer 16. The thickness of the first insulating layer 16 can be, for example, about 5 to 15 μm. The roughness of the upper surface of the first insulating layer 16 after polishing is smaller than the roughness of the upper surface of the first insulating resin layer 16A before polishing. The surface roughness of the upper surface of the first insulating resin layer 16A before polishing is, for example, about Ra150-200nm. By performing polishing, the surface roughness of the upper surface of the first insulating layer 16 can be reduced to about Ra20-60nm.

[0061] This process forms the first wiring structure 1 on the upper surface of the core substrate 10. The roughness of the upper surfaces of the first insulating layers 12 and 14 is, for example, about Ra 150 to 200 nm. In other words, polishing in this process makes the roughness of the upper surface of the first insulating layer 16 smaller than the roughness of the upper surfaces of the other insulating layers (first insulating layers 12 and 14) that constitute the first wiring structure 1. That is, the upper surface of the first insulating layer 16 is flatter than the upper surfaces of the other insulating layers (first insulating layers 12 and 14) that constitute the first wiring structure 1. By reducing the roughness of the upper surface of the first insulating layer 16 and flattening it in this way, it becomes possible to form a fine wiring layer (high-density wiring pattern) on the upper surface of the first insulating layer 16 in a subsequent process.

[0062] Next, in the step shown in Figure 5(b), an uncured film-like second insulating resin layer is placed to cover the upper surface of the first wiring layer 15 and the upper surface of the first insulating layer 16 of the first wiring structure 1. This second insulating resin layer is heated and pressurized towards the first wiring structure 1 to cure it and form the second insulating layer 21. Alternatively, instead of laminating the film-like second insulating resin layer, a liquid or paste-like insulating resin may be applied and then cured to form the second insulating layer 21. This step is preferably performed in a vacuum in order to fill the gap G (see Figure 1(b)) with the second insulating layer 21.

[0063] As the insulating resin for the second insulating layer 21, for example, thermosetting resins such as epoxy resins, imide resins, phenolic resins, and cyanate resins can be used.

[0064] The second insulating layer 21 is preferably mainly composed of a thermosetting, non-photosensitive resin such as an epoxy resin, imide resin, phenolic resin, or cyanate resin. The second insulating layer 21 contains a filler 21f such as silica (SiO2) (see Figure 1(b)). The average and maximum particle sizes of the filler 21f contained in the second insulating layer 21 are smaller than the average and maximum particle sizes of the filler 16f contained in the first insulating layer 16. The average particle size of the filler 21f can be, for example, 0.1 μm or less. The maximum particle size of the filler 21f can be, for example, 1 μm or less. The content of the filler 21f can be, for example, about 50 wt%. The second insulating layer 21 is a thinner insulating layer than the first insulating layers 12 and 14. The thickness of the second insulating layer 21 can be, for example, about 10 to 20 μm.

[0065] The reason why it is preferable for the second insulating layer 21 to be mainly composed of a non-photosensitive resin is as follows: Non-photosensitive resins have a lower coefficient of thermal expansion compared to photosensitive resins. Also, non-photosensitive resins have lower relative permittivity and dielectric loss tangent compared to photosensitive resins. This is because, while these physical properties can be adjusted in non-photosensitive resins by incorporating fillers, it is difficult to incorporate fillers in photosensitive resins due to the exposure process and other factors, making it difficult to obtain good physical properties.

[0066] Generally, the thermal expansion coefficient of the resin used in the insulating layer is greater than that of the metal, such as copper, used in the wiring layer. If the difference in thermal expansion coefficients between the wiring layer and the insulating layer is large, stress caused by the difference in thermal expansion coefficients will occur between the wiring layer and the insulating layer, which may lead to delamination or fracture of the wiring layer. This tendency becomes greater as the wiring layer becomes finer. For this reason, it is preferable to make the thermal expansion coefficient of the insulating layer as low as possible, in order to bring it closer to that of the wiring layer. Therefore, it is preferable to use a non-photosensitive resin with a lower thermal expansion coefficient than a photosensitive resin for the second insulating layer 21 that forms the fine wiring layer. The same applies to the other second insulating layers.

[0067] Furthermore, the lower the relative permittivity and dielectric loss tangent of the insulating layer, the easier it is for high-frequency signals to flow through the wiring layer. If the relative permittivity and dielectric loss tangent of the insulating layer are high, a delay occurs in the signals flowing through the wiring layer. This tendency becomes greater as the wiring layer becomes finer. Therefore, in order to obtain good high-frequency characteristics, it is preferable to use a non-photosensitive resin with a lower relative permittivity and dielectric loss tangent than a photosensitive resin for the second insulating layer 21 that forms the fine wiring layer. The same applies to the other second insulating layers.

[0068] Furthermore, after polishing in the process shown in Figure 5(a), a gap G approximately 5 μm wide may be formed between the outer edge of the wiring pattern constituting the first wiring layer 15 and the first insulating layer 16, as shown in Figure 1(b). However, when the second insulating layer 21 is formed in the process shown in Figure 5(b), the softened second insulating resin layer fills the gap G and then hardens, so the gap G ultimately disappears. As a result, the occurrence of cracks in the first wiring layer 15 and the first insulating layer 16 can be suppressed. In addition, since a part of the second insulating layer 21 penetrates into the gap G, an anchoring effect is generated, improving the adhesion between the first wiring layer 15 and the first insulating layer 16 and the second insulating layer 21. Furthermore, there may be cases where no gap G is formed after polishing in the process shown in Figure 5(a).

[0069] Next, in the process shown in Figure 5(c), via holes 21x are formed in the same manner as in the process shown in Figure 2(c). The via holes 21x are frustoconical in shape, similar to the other via holes. The aperture diameter of the via holes 21x can be, for example, about 5 to 10 μm. Next, the second wiring layer 22 is formed in the same manner as in Figures 4(a) and 4(b). The line / space ratio of the second wiring layer 22 can be, for example, about 3 μm / 3 μm to 8 μm / 8 μm. Since each via hole in the second wiring structure 2, including the via holes 21x, has a smaller aperture diameter than each via hole in the first wiring structure 1, it is preferable to form them using an excimer laser suitable for microfabrication.

[0070] Next, in the process shown in Figure 6(a), the same process as in Figures 4(a) and 4(b) is repeated to sequentially laminate the second insulating layer 23, the second wiring layer 24, the second insulating layer 25, and the second wiring layer 26. Through this process, the second wiring structure 2 is formed on the first wiring structure 1.

[0071] Next, in the process shown in Figure 6(b), a solder resist layer 40 (see Figure 1) with openings 40x is formed on the second insulating layer 25. A solder resist layer 50 with openings 50x is also formed on the third wiring layer 35. Then, external connection terminals 60, such as solder balls, are formed on the third wiring layer 35 exposed through the openings 50x in the solder resist layer 50. With these steps, the wiring board 5 is completed.

[0072] <Application examples of the first embodiment> The application example of the first embodiment shows an example of a semiconductor device in which a semiconductor chip is mounted on a wiring board. In the application example of the first embodiment, descriptions of components that are the same as those described in the previously described embodiments may be omitted.

[0073] Figure 7 is a cross-sectional view illustrating a semiconductor device according to an application example of the first embodiment. Referring to Figure 7, the semiconductor device 7 includes the wiring board 5 shown in Figure 1, a semiconductor chip 110, and electrode posts 120.

[0074] The semiconductor chip 110 is formed by creating a semiconductor integrated circuit (not shown) on a thin semiconductor substrate (not shown) made of, for example, silicon. Electrode posts 120 electrically connected to the semiconductor integrated circuit (not shown) are formed on the semiconductor substrate (not shown). The electrode posts 120 are, for example, copper posts.

[0075] The electrode post 120 is connected to the second wiring layer 26 of the wiring board 5. The electrode post 120 and the second wiring layer 26 may be directly connected, for example, by diffusion bonding, or indirectly connected via solder bumps. In the latter case, the solder bump material can be, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, or an alloy of Sn, Ag, and Cu. An underfill resin may be filled between the semiconductor chip 110 and the upper surface of the wiring board 5.

[0076] Thus, a semiconductor device 7 can be realized by mounting a semiconductor chip on the wiring substrate 5 according to the first embodiment. Since the semiconductor device 7 includes a wiring substrate 5 that can suppress the occurrence of cracks in the wiring layer and insulating layer, a highly reliable semiconductor device can be realized.

[0077] Although preferred embodiments have been described in detail above, the invention is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims.

[0078] For example, the present invention can also be applied to coreless wiring boards that do not have a core substrate or a third wiring structure, but in which a second wiring structure is laminated on a first wiring structure. [Explanation of Symbols]

[0079] 1 1st wiring structure 2 Second wiring structure 3 Third wiring structure 5 Wiring board 7 Semiconductor devices 10 Core boards 10a One side 10b The other side 10x through holes 11,13,15 1st wiring layer 12, 14, 16 First insulating layer 12x, 14x, 21x, 23x, 25x, 32x, 34x Beer Hall 16A First insulating resin layer 16f, 21f filler 21, 23, 25 Second insulating layer 22,24,26 2nd wiring layer 31,33,35 3rd wiring layer 32,34 Third insulating layer 20 Through electrode 30 Resin part 40,50 Solder Resist Layers 40x,50x opening 60 External connection terminals 110 semiconductor chips 120 electrode posts 300, 310, 320, 330 Plating Resist Pattern 300x,310x,320x,330x opening

Claims

1. A first wiring structure having a first wiring layer and a first insulating layer, A second wiring structure having a second wiring layer and a second insulating layer, wherein the second wiring structure is arranged on the first wiring structure, The wiring width and wiring spacing of the second wiring layer are smaller than the wiring width and wiring spacing of the first wiring layer. The first insulating layer covers the side surface of the first wiring layer and exposes its upper surface. The upper surface of the first insulating layer is flush with the upper surface of the first wiring layer. The second insulating layer covers the upper surface of the first wiring layer and the upper surface of the first insulating layer. The first insulating layer and the second insulating layer contain a filler, The average particle size and maximum particle size of the filler contained in the second insulating layer are smaller than the average particle size and maximum particle size of the filler contained in the first insulating layer. A wiring board in which the average particle size of the filler contained in the second insulating layer is 0.1 μm or less, and the maximum particle size of the filler contained in the second insulating layer is 1 μm or less.

2. The wiring board according to claim 1, wherein the first insulating layer and the second insulating layer are insulating layers mainly composed of a non-photosensitive resin.

3. The first wiring structure has a plurality of first wiring layers and a plurality of first insulating layers, The second wiring structure described above has a plurality of second wiring layers and a plurality of second insulating layers, The plurality of first wiring layers include the uppermost first wiring layer located on the side closest to the second wiring structure among the plurality of first wiring layers, The plurality of first insulating layers include an uppermost first insulating layer that is positioned on the side closest to the second wiring structure among the plurality of first insulating layers, covers the side surface of the uppermost first wiring layer, and exposes its upper surface. The plurality of second insulating layers include the upper surface of the uppermost first wiring layer and the lowermost second insulating layer that covers the upper surface of the uppermost first insulating layer. The uppermost first insulating layer and the lowermost second insulating layer contain a filler. The wiring substrate according to claim 1 or 2, wherein the average particle size and maximum particle size of the filler contained in the lowest second insulating layer are smaller than the average particle size and maximum particle size of the filler contained in the uppermost first insulating layer.

4. All of the aforementioned first insulating layers and all of the aforementioned second insulating layers contain a filler. The wiring substrate according to claim 3, wherein the average particle size and maximum particle size of the filler contained in each of the second insulating layers are smaller than the average particle size and maximum particle size of the filler contained in any of the first insulating layers.

5. The wiring board according to claim 3, wherein the roughness of the upper surface of the uppermost first insulating layer is smaller than the roughness of the upper surface of the first insulating layers other than the uppermost first insulating layer.

6. The invention further comprises a core substrate and a third wiring structure in which a plurality of third wiring layers and a plurality of third insulating layers are laminated, The first wiring structure and the second wiring structure are arranged on one side of the core substrate. The third wiring structure is arranged on the other side of the core substrate. The wiring board according to claim 3, wherein the wiring width and wiring spacing of the second wiring layer are smaller than the wiring width and wiring spacing of the third wiring layer.

7. A first wiring structure having a first wiring layer and a first insulating layer, A method for manufacturing a wiring substrate, comprising a second wiring structure having a second wiring layer and a second insulating layer, wherein the second wiring structure is disposed on the first wiring structure, The process of forming the first wiring layer, A step of forming a first insulating resin layer that covers the side and top surfaces of the first wiring layer, The process involves polishing the first insulating resin layer to form a first insulating layer that covers the side surface of the first wiring layer and exposes its upper surface, The process involves placing an uncured second insulating resin layer that covers the upper surface of the first wiring layer and the upper surface of the first insulating layer, heating the second insulating resin layer and applying pressure to the first wiring structure side to cure it, thereby forming the second insulating layer. The process includes the step of forming a second wiring layer on the second insulating layer, The wiring width and wiring spacing of the second wiring layer are smaller than the wiring width and wiring spacing of the first wiring layer. The first insulating layer and the second insulating layer contain a filler, The average particle size and maximum particle size of the filler contained in the second insulating layer are smaller than the average particle size and maximum particle size of the filler contained in the first insulating layer. A method for manufacturing a wiring board, wherein the average particle size of the filler contained in the second insulating layer is 0.1 μm or less, and the maximum particle size of the filler contained in the second insulating layer is 1 μm or less.

8. In the step of forming the first wiring layer, a curved projection is formed on the upper surface of the first wiring layer. The method for manufacturing a wiring board according to claim 7, wherein in the step of forming the first insulating layer, the protruding portion is removed by polishing, and the upper surface of the first wiring layer and the upper surface of the first insulating layer are made flush.

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