Method and apparatus for manufacturing semiconductor substrates

Abstract

The present invention comprises: a step in which a first nitride semiconductor part is grown from a first seed region to the above of a growth suppression region, and a second nitride semiconductor part is grown from a second seed region to the above of the growth suppression region; a step in which a semiconductor substrate, which comprises a template substrate and the first and second nitride semiconductor parts that are being grown, is irradiated with first light; a step in which second light from the semiconductor substrate is received; and a step in which the growth of the first and second nitride semiconductor parts is stopped before the first and second nitride semiconductor parts meet each other.

Description

Technical Field

[0001] The present disclosure relates to a method and apparatus for manufacturing a semiconductor substrate.

Background Art

[0002] Patent Document 1 discloses a method of forming a GaN-based semiconductor layer on a GaN-based substrate or a heterogeneous substrate (e.g., a sapphire substrate) using the ELO (Epitaxial Lateral Overgrowth) method.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] The method for manufacturing a semiconductor substrate according to the present disclosure includes: preparing a template substrate including a base substrate and having a growth suppression region and first and second seed regions; growing a first nitride semiconductor part upward from the first seed region above the growth suppression region and growing a second nitride semiconductor part upward from the second seed region above the growth suppression region; irradiating a semiconductor substrate including the template substrate and the growing first and second nitride semiconductor parts with first light; receiving second light from the semiconductor substrate; and stopping the growth of the first and second nitride semiconductor parts before the first and second nitride semiconductor parts meet.

Brief Description of the Drawings

[0005] <000003!>[[ID=4Q]]It is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment. [Figure 2] It is a flowchart showing the method for manufacturing a semiconductor substrate according to the present embodiment. [Figure 3] It is a cross-sectional view showing the method for manufacturing a semiconductor substrate according to the present embodiment. [Figure 4] This is a cross-sectional view showing the configuration of the semiconductor substrate of this embodiment. [Figure 5] This graph shows the time evolution of the reflectivity of a semiconductor substrate (when the wavelength of the first light is 405 nm and 633 nm). [Figure 6] This graph shows the relationship between the slope angle of a sloped area and its reflectivity. [Figure 7] This graph shows the temporal change in the gap width of the first and second nitride semiconductor regions. [Figure 8] This is a cross-sectional view showing an example of the shape of a nitride semiconductor portion having a gradient region. [Figure 9] This graph shows the time-dependent change in reflectivity of a semiconductor substrate. [Figure 10] This graph shows the time-dependent change in reflectivity of a semiconductor substrate. [Figure 11] This graph shows the area around the inflection point in Figure 10. [Figure 12] This is a cross-sectional view showing the shape changes of the side facets of the first and second nitride semiconductor portions. [Figure 13] This is a plan view showing an example of a mask. [Figure 14] This is a cross-sectional view showing an example of the base substrate configuration. [Figure 15] This is a cross-sectional view showing an example of the structure of the base layer. [Figure 16] This is a cross-sectional view showing another example of the method for manufacturing a semiconductor substrate according to this embodiment. [Figure 17] This is a schematic diagram showing the configuration of a semiconductor substrate manufacturing apparatus according to this embodiment. [Figure 18] This is a cross-sectional view showing the method for manufacturing a semiconductor substrate according to Example 1. [Figure 19] This is a cross-sectional view showing the method for manufacturing a semiconductor device according to Example 2. [Figure 20] This is a schematic diagram showing the configuration of the semiconductor substrate manufacturing apparatus according to Example 3. [Figure 21] This is a cross-sectional view showing the method for manufacturing a semiconductor substrate according to this embodiment. [Modes for carrying out the invention]

[0006] (Semiconductor substrate) Figure 1 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. As shown in Figure 1, the semiconductor substrate 10 (semiconductor wafer) according to this embodiment includes a base substrate BS and a template substrate TS having a growth suppression region SP and first and second seed regions 4F and 4S, a first nitride semiconductor portion 8F positioned above the growth suppression region SP from the first seed region 4F, and a second nitride semiconductor portion 8S positioned above the growth suppression region SP from the second seed region 4S. The template substrate TS has a mask portion 5 and a mask pattern 6 having a first opening K1 and a second opening K2 on the base substrate BS. The upper surface of the mask portion 5 is the growth suppression region SP, and a first seed region 4F overlapping the first opening K1 and a second seed region 4F overlapping the second opening K2 may be located on the upper surface of the base substrate BS. The first and second nitride semiconductor portions 8F and 8S are adjacent to each other with a gap GP. In the following, the first and second seed regions 4F and 4S may be collectively referred to as seed region 4, the first and second openings K1 and K2 as opening K, and the first and second nitride semiconductor sections 8F and 8S as nitride semiconductor section 8. The nitride semiconductor section 8 may also be a nitride semiconductor layer.

[0007] The nitride semiconductor section 8 includes a nitride semiconductor as its main material. Nitride semiconductors can be represented, for example, as AlxGayInzN (0≦x≦1;0≦y≦1;0≦z≦1;x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.

[0008] The nitride semiconductor portion 8 may be a doped type (e.g., an n-type containing donors) or an undoped type. The semiconductor substrate means a substrate containing a nitride semiconductor, and the base substrate BS may contain a semiconductor other than the nitride semiconductor (e.g., a silicon-based semiconductor) or a non-semiconductor. The template substrate TS may be referred to as including the base substrate BS and the mask pattern 6.

[0009] The nitride semiconductor portion 8 can be formed by the ELO (Epitaxial Lateral Overgrowth) method starting from the seed region 4 (the region exposed from the opening K on the upper surface of the base substrate BS). The seed region 4 may be a region that serves as a starting point for the growth of the nitride semiconductor portion �. The thickness direction of the nitride semiconductor portion 8 may be the c-axis direction (<0001> direction). The opening K has a longitudinal shape, and its width direction may be the a-axis direction (<11-20> direction) of the nitride semiconductor portion 8. In the semiconductor substrate 10, the direction from the base substrate BS to the nitride semiconductor portion 8 is referred to as "upward". Viewing an object with a line of sight parallel to the normal direction of the semiconductor substrate 10 (including the case of perspective) may be referred to as "planar view".

[0010] (Method for manufacturing a semiconductor substrate) FIG. 2 is a flowchart showing a method of manufacturing a semiconductor substrate according to the present embodiment. FIG. 3 is a cross-sectional view showing a method of manufacturing a semiconductor substrate according to the present embodiment. As shown in FIGS. 2 to 3, the method of manufacturing a semiconductor substrate according to the present embodiment includes a step of preparing a template substrate TS including a base substrate BS and having a growth suppression region SP and first and second seed regions 4F and 4S, a step of growing a first nitride semiconductor portion 8F from the first seed region 4F above the growth suppression region SP and growing a second nitride semiconductor portion 8S from the second seed region 4S above the growth suppression region SP of the growth suppression region SP, a step of irradiating a semiconductor substrate 10 including the template substrate TS and the growing first and second nitride semiconductor portions 8F and 8S with a first light L1, a step of receiving a second light L2 from the semiconductor substrate 10, and a step of stopping the growth of the first and second nitride semiconductor portions 8F and 8S before they meet. The template substrate TS has a mask pattern 6 having a mask portion 5 and first and second openings K1 and K2 on the base substrate BS, the upper surface of the mask portion 5 is the growth suppression region SP, and the upper surface of the base substrate BS may include a first seed region 4F overlapping the first opening K1 and a second seed region 4F overlapping the second opening K2.

[0011] The step of receiving the second light L2 can be performed by a detector including, for example, a photosensor. For the first and second nitride semiconductor portions 8F and 8S, the growth can be stopped by stopping the supply of at least a part of the raw materials (described later).

[0012] The first light L1 may be irradiated onto the upper surfaces of the first and second nitride semiconductor portions 8F and 8S and the mask portion 5 (growth suppression region SP). The second light L2 may include reflected light of the first light L1 on the upper surfaces of the first and second nitride semiconductor portions 8F and 8S and reflected light of the first light L1 on the upper surface of the mask portion 5.

[0013] The ratio of the incident light intensity to the reflected light intensity at the upper surface of the nitride semiconductor portion 8 (reflectance of the nitride semiconductor portion) may differ from the ratio of the incident light intensity to the reflected light intensity at the upper surface of the mask portion 5 (reflectance of the mask portion). The timing for stopping the growth of the first and second nitride semiconductor portions 8F and 8S may be determined using the second light L2. The reflectance, which is the ratio of the intensity of the second light L2 to the intensity of the first light L1 (reflectance of the semiconductor substrate), or the intensity of the second light L2 (second light intensity) may be detected over time.

[0014] Figure 4 is a cross-sectional view showing the configuration of the semiconductor substrate of this embodiment. Figure 5 is a graph showing the change in reflectivity of the semiconductor substrate over time (when the wavelengths of the first light are 405 nm and 633 nm). When a sloped region is included on the upper surface of the nitride semiconductor portion 8 as shown in Figure 4, the growth of the first and second nitride semiconductor portions 8F and 8S may be stopped when the reflectivity of the semiconductor substrate 10 or the second light intensity falls below a threshold. When a sloped region SA is formed on the upper surface of the nitride semiconductor portion 8 as both ends of the nitride semiconductor portion 8 grow thinner than the central part, the reflected light in the sloped region SA is tilted with respect to the first light L1, and the luminous flux of the second light L2 detected by the detector decreases. As a result, the reflectivity of the semiconductor substrate 10 decreases with the growth of the nitride semiconductor portion 8, as shown in Figure 5. Therefore, by stopping the growth of the first and second nitride semiconductor portions 8F and 8S when the reflectivity of the semiconductor substrate 10 (the ratio of the intensity of the second light L2 to the intensity of the first light L1) falls below a threshold, the width of the gap GP can be controlled to a desired value.

[0015] Figure 6 is a graph showing the relationship between the tilt angle of the tilted region and the reflectance. As shown in Figure 6, it can be seen that the (detectable) reflectance decreases as the tilt angle of the tilted region SA increases. Although reflectance is used in Figure 5, it is not limited to this. For example, the intensity of the first light may be kept constant, and the growth of the first and second nitride semiconductor parts 8F and 8S may be stopped when the intensity of the second light L2 falls below a threshold.

[0016] Figure 7 is a graph showing the temporal change in the gap width of the first and second nitride semiconductor portions. As shown in Figures 5 to 7, the gap width of the first and second nitride semiconductor portions 8F and 8S may be calculated over time using the reflectance of the semiconductor substrate 10, and the growth of the first and second nitride semiconductor portions 8F and 8S may be stopped when the gap width reaches a specified value. Alternatively, the gap width may be calculated over time using the intensity of the second light L2. The gap widths when the growth of the first and second nitride semiconductor portions 8F and 8S is stopped may be less than three times the width of each aperture K.

[0017] Figure 8 is a cross-sectional view showing an example of the shape of a nitride semiconductor portion having a gradient region. For the nitride semiconductor portion 8, the thickness of the portion above the opening K (central part) is s1, the thickness of the edge is s2, the width of the opening K is s3, the distance from the opening K to the edge is s4, the gradient angle of the gradient region SA is θ, and tanθ = (s1-s2) / s4 can be set to, for example, s1 = 1 to 7 μm, s2 = 0.5 to 5 μm, s3 = 5 to 20 μm, s4 = 10 to 50 μm, and θ = 0.5 to 2.0 degrees. The thickness of the mask portion 5 can be, for example, 50 nm to 5 μm or 70 nm to 700 nm.

[0018] Figure 9 is a graph showing the time evolution of the reflectance of the semiconductor substrate. When the upper surface of the nitride semiconductor portion 8 is not sloped (flat), as shown in Figure 3, the reflectance of the nitride semiconductor portion 8 becomes dominant as the first and second nitride semiconductor portions 8F and 8S grow on the mask portion 5. Therefore, for example, if the reflectance of the nitride semiconductor portion 8 is greater than the reflectance of the mask portion 5, the reflectance of the semiconductor substrate 10 will increase. Thus, when the upper surface of the nitride semiconductor portion 8 is not sloped, the growth of the first and second nitride semiconductor portions 8F and 8S may be stopped at the timing when the reflectance of the semiconductor substrate 10 or the second light intensity exceeds a threshold, as shown in Figure 9.

[0019] Figure 10 is a graph showing the change in reflectance of the semiconductor substrate over time. Figure 11 is a graph showing the area around the inflection point in Figure 10. As shown in Figure 8, when a gradient region SA is formed on the upper surface of the nitride semiconductor portion 8 and the (detected) reflectance decreases as growth progresses, the trend of the reflectance profile may change (for example, the reflectance shifts from a decreasing trend to an increasing trend) just before the first and second nitride semiconductor portions 8F and 8S meet, as shown in Figures 10 and 11. This phenomenon can be used to control the width of the gap GP to a desired value. That is, the growth of the first and second nitride semiconductor portions 8F and 8S may be stopped at the timing when a change in the trend of the reflectance of the semiconductor substrate 10 appears (is observed). For example, a change in trend may be determined when the minimum value within a unit period shifts from decreasing to increasing. The unit period may be set to a value according to the characteristics of the semiconductor substrate 10 and the first light L1.

[0020] As the first and second nitride semiconductor portions 8F and 8S approach each other, the shape of their respective side facets changes, which is thought to cause an inflection point in the reflectivity. Figure 12 is a cross-sectional view showing the shape change of the side facets of the first and second nitride semiconductor portions. As shown in Figure 12, a side surface 8Z that forms an acute angle with respect to the mask portion 5 is formed, and this side surface 8Z may change from a state where it is perpendicular to the mask portion 5 to a state where it overhangs. Before stopping the growth of the first and second nitride semiconductor portions 8F and 8S, the side surface 8Z that overhangs the upper surface of the mask portion 5, which has formed on each nitride semiconductor portion 8, may be expanded. As a result, when the growth of the first and second nitride semiconductor portions 8F and 8S is stopped, each nitride semiconductor portion 8 may have a side surface 8Z that overhangs the upper surface of the mask portion 5. The width of the gap GP after growth cessation can be, for example, 2 μm or less.

[0021] When forming multiple nitride semiconductor regions using the ELO method, it is crucial to control the gap width between two adjacent nitride semiconductor regions. When controlling the gap width by deposition time, variations in the deposition rate due to aperture width, manufacturing equipment characteristics, etc., can lead to the nitride semiconductor region growth stopping too early or too late, resulting in a decrease in manufacturing yield. Manufacturing yield refers to the rate at which nitride semiconductor regions that meet conformance conditions, such as dislocation density (defect density) and aspect ratio, are produced.

[0022] In this embodiment, by detecting the reflected light from the surface of the nitride semiconductor portion 8 during growth and the reflected light from the mask portion 5 using light of a wavelength absorbed by the nitride semiconductor portion 8 at the growth temperature (e.g., 405 nm), the growth state in the lateral direction (a-axis direction) can be monitored regardless of the internal structure of the base substrate BS. The wavelength of the first light L1 may be included in the wavelength range of 395 to 415 nm. Alternatively, the first light L1 may be light of a wavelength that penetrates the nitride semiconductor at the growth temperature (e.g., 633 nm, 950 nm). The first light L1 may also be laser light.

[0023] The nitride semiconductor portion 8 may have an absorption coefficient of first light L1 at the growth temperature (e.g., 1000°C) that is 10 times or more than the absorption coefficient of first light L1 at room temperature. The band gap of the nitride semiconductor portion 8 at the growth temperature may be smaller than the band gap of the nitride semiconductor portion 8 at room temperature (e.g., 20°C) (3.4 eV in the case of GaN). The wavelength of first light L1 may be set according to the band gap of the nitride semiconductor portion 8 at the growth temperature.

[0024] The a-axis direction of the nitride semiconductor portion 8 is defined as the width direction of the mask portion 5 and the opening K, and the width of the mask portion 5 may be 20 [μm] or more. The ratio of the thickness of the mask portion 5 to the width of the opening K may be 3.0 or less.

[0025] Figure 13 is a plan view showing an example of a mask pattern. The first and second openings K1 and K2 of the mask pattern 6 function as growth initiation openings that expose the first and second seed regions 4F and 4S and initiate the growth of the first and second nitride semiconductor regions 8F and 8S, while the mask region 5 may function as a selective growth mask (deposition suppression mask) that causes the nitride semiconductor region 8 to grow laterally. The openings K are areas in the mask pattern 6 where the mask region 5 is not present (non-formed areas) and do not necessarily have to be surrounded by the mask region 5.

[0026] As the mask portion 5, a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, a silicon oxynitride (SiON) film, a titanium nitride (TiNx) film, etc., can be used. The openings K are longitudinal in shape, and multiple openings K may be periodically arranged in the <11-20> direction (a-axis direction) of the nitride semiconductor portion 8. The width of the openings K may be about 0.2 μm to 20 μm. The smaller the width of the openings K, the fewer the number of through-dislocations propagating from the openings K to the nitride semiconductor portion 8. In addition, peeling of the nitride semiconductor portion 8 in a subsequent process (described later) becomes easier. A multilayer film containing the above materials (for example, at least two of silicon oxide, silicon nitride, and silicon oxynitride) can also be used for the mask portion 5.

[0027] In mask pattern 6, the first and second openings K1 and K2 may be aligned in the <11-20> direction (a-axis direction) of the nitride semiconductor portion 8, and the first and third openings K1 and K3 may be aligned in the <1-100> direction (m-axis direction) of the nitride semiconductor portion 8.

[0028] Figure 14 is a cross-sectional view showing an example of the base substrate configuration. The base substrate BS may have a main substrate 1 which is a different type of substrate with a different lattice constant from the nitride semiconductor portion 8. The nitride semiconductor portion 8 may contain a GaN-based semiconductor, and the main substrate 1, which is a different type of substrate, may be a silicon substrate. Examples of different types of substrates include a silicon substrate, a sapphire (Al2O3) substrate, a silicon carbide (SiC) substrate, etc. The plane orientation of the main substrate 1 is, for example, the (111) plane of a silicon substrate, the (0001) plane of a sapphire substrate, and the 6H-SiC(0001) plane of a SiC substrate. These are examples, and any substrate and plane orientation that can grow the nitride semiconductor portion 8 by the ELO method is acceptable.

[0029] The base substrate BS includes a main substrate 1 and an underlayment UB on the main substrate 1, and the nitride semiconductor portion 8 may grow from the upper surface (seed region 4) of the underlayment UB exposed to the opening K. The underlayment UB may contain a nitride semiconductor. The base substrate BS is composed of a self-supporting single-crystal substrate such as GaN or SiC (for example, a wafer cut from a bulk crystal), and a mask pattern 6 may be arranged on the single-crystal substrate.

[0030] Figure 15 is a cross-sectional view showing an example of the configuration of the base portion. The base portion UB may include at least one of the buffer portion 2 and the seed portion 3. The base portion UB may consist of the seed portion 3, or the base portion UB may consist of the buffer portion 2 and the seed portion 3. GaN-based semiconductors, AlN, SiC, etc., can be used for the buffer portion 2. Nitride semiconductors (e.g., GaN-based semiconductors) can be used for the seed portion 3.

[0031] Figure 16 is a cross-sectional view showing another semiconductor substrate manufacturing method according to this embodiment. As shown in Figure 16, a buffer portion 2 may be provided in the template substrate TS so as to cover the mask pattern 6. A highly reactive AlGaN film can be used for the buffer portion 2. In this case, the upper surface of the buffer portion 2 (AlGaN film) includes a growth suppression region SP that overlaps with the mask portion 5 in a plan view, a first seed region 4F that overlaps with the first opening K1 in a plan view, and a second seed region 4S that overlaps with the second opening K2 in a plan view. On the upper surface of the buffer portion 2 (AlGaN film surface), the region located above the mask portion 5 has low crystallinity and therefore functions as the growth suppression region SP. On the other hand, the region located above the first and second openings K1 and K2 (above the exposed portion of the base substrate BS) has high crystallinity and therefore functions as the first and second seed regions 4F and 4S.

[0032] (Manufacturing equipment for semiconductor substrates) Figure 17 is a schematic diagram showing the configuration of a semiconductor substrate manufacturing apparatus according to this embodiment. As shown in Figure 17, the semiconductor substrate manufacturing apparatus 20 includes a stage 21 on which a template substrate TS including a base substrate BS and including a growth suppression region and a seed region is placed, a raw material supply device 22 that supplies raw materials for growing nitride semiconductor portions 8 on the template substrate TS, an optical device 23 that irradiates the template substrate TS and the semiconductor substrate 10 including the growing nitride semiconductor portions with a first light L1 and receives a second light L2 from the semiconductor substrate 10, and a control device 24 that controls the raw material supply device 22 so that the growth of the first and second nitride semiconductor portions 8F and 8S stops before the first and second nitride semiconductor portions 8F and 8S meet. The control device 24 may be capable of at least one of wired communication and wireless communication with the optical device 23. The control device 24 may use the second light L2 to determine the timing for stopping the supply of at least some of the raw materials to the raw material supply device 22.

[0033] The semiconductor substrate manufacturing apparatus 20 may include a chamber 25 containing a stage SG, a flow channel 27 passing through the chamber 25, and a heating device 26 for heating the chamber 25, with the semiconductor substrate 10 placed inside the flow channel 27. The control device 24 may use the second light L2 to determine the timing for stopping high-temperature heating (1000 degrees or more) with respect to the heating device 26. The optical device 23 may be located outside the chamber 25. The chamber 25 may be provided with a window 28 through which the first light L1 and the second light L2 pass.

[0034] Stage 21 may rotate (using the axis of rotation as the axis normal to the template substrate TS). In Figure 17, the raw material supply device 22 flows the raw material gas horizontally (parallel to the top surface of the template substrate) into the flow channel 27 and exhausts it horizontally, but is not limited to this. The raw material gas can also be flowed vertically (normal to the template substrate TS).

[0035] The control device 24 uses reflectance, which is the ratio of the intensity of the second light L2 to the intensity of the first light L1, to detect the gap width of the first and second nitride semiconductor parts 8F and 8S over time. When the gap width reaches a specified value, the control device 24 may instruct the raw material supply device 22 to stop supplying at least some of the raw material (for example, trimethylgallium if the nitride semiconductor part 8 is a GaN crystal). The control device 24 may also instruct the heating device 26 to stop high-temperature heating.

[0036] The control device 24 may be configured to control at least one of the raw material supply device 22 and the heating device 26 by executing a program stored in, for example, an internal memory, a communication device, or an accessible network. This program and the recording medium on which it is stored are also included in this embodiment.

[0037] (Example 1) Figure 18 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to Example 1. In Figure 18, a base portion UB containing a nitride semiconductor is formed on a main substrate 1, and a mask pattern 6 including a plurality of stripe-shaped mask portions 5 is provided on the base portion UB. The mask portion 5 consists of a silicon nitride film with a thickness of 100 nm and a width of 52 μm, with the m-axis direction of the nitride semiconductor portion 8 being the longitudinal direction. The pitch of the stripes in the mask portion 5 is 55 μm.

[0038] A resist stripe pattern is formed on a base substrate BS, which has a nitride semiconductor film deposited as the underlayment UB, using photolithography technology. Next, a silicon nitride film with a thickness of 100 nm is deposited over the entire surface by sputtering. Then, the silicon nitride film is patterned using the lift-off method to form a mask pattern 6 (stripe pattern). Subsequently, the nitride semiconductor portion 8 is grown on the mask pattern 6 by metal-organic vapor deposition (MOCVD) using, for example, trimethylgallium (TMG) and ammonia (NH3) (ELO method).

[0039] In Figure 18, an initial growth area 8p is formed above the base area UB (seed area) exposed at the openings K1 and K2. The growth conditions at this time are designated as the first condition. The transition of the growth conditions (from the first condition to the second condition) begins just before the edge of the initial growth area 8p rises onto the upper surface of the mask area 5 (when it is in contact with the upper side of the mask area 5), ​​or immediately after it rises onto the upper surface of the mask area 5.

[0040] In Example 1, the first condition (prioritizing longitudinal growth) was set as follows: growth temperature (set temperature): 1100°C, growth pressure: 10kPa, ammonia flow rate: 7.5slm, trimethylgallium flow rate: 3sccm. The second condition (prioritizing lateral growth) was set as follows: growth temperature (set temperature): 1175°C, growth pressure: 10kPa, ammonia flow rate: 7.5slm, trimethylgallium flow rate: 11sccm.

[0041] The initial growth layer 8p serves as the starting point for lateral growth of the nitride semiconductor layer 8. The initial growth layer 8p can be formed to a thickness of, for example, 30 nm to 1000 nm, 50 nm to 400 nm, or 70 nm to 350 nm. By allowing lateral growth from a state where the initial growth layer 8p slightly protrudes from the mask layer 5, growth of the nitride semiconductor layer 8 in the c-axis direction (thickness direction) is suppressed, enabling high-speed and highly crystallinity lateral growth of the nitride semiconductor layer 8, while also reducing raw material consumption. This makes it possible to form a thin, wide, low-defect nitride semiconductor layer 8 (crystalline nitride semiconductor such as GaN) at low cost.

[0042] The nitride semiconductor portions 8, which grow laterally in opposite directions from two adjacent openings K, do not come into contact (meet) on the mask portion 5, and have a gap GP, thereby reducing the internal stress of the nitride semiconductor portions 8. This reduces cracks and defects (dislocations) that occur in the nitride semiconductor portions 8. This effect is particularly effective when the main substrate 1 is a different type of substrate. The width of the gap GP can be, for example, 10 μm or less, 5 μm or less, 3 μm or less, or 2 μm or less.

[0043] Of the nitride semiconductor portion 8, the portion located on the initial growth portion 8p becomes a dislocation inheritance portion with many threading dislocations, while the portion on the mask portion 5 (wing portion) becomes a low-defect portion YS with a threading dislocation density of 1 / 10 or less compared to the dislocation inheritance portion. A threading dislocation is a dislocation that travels through the nitride semiconductor portion 8 in its c-axis direction. <0001> These are dislocations (defects) that extend in the direction. The penetration dislocation density of the low-defect area YS is, for example, 5 × 10⁻⁶. 6 [pcs / cm 2 The following is possible. As described later, when an active portion (active layer) including a light-emitting portion is formed above the nitride semiconductor portion 8, the light-emitting portion can be positioned above the low-defect portion YS (so as to overlap with the low-defect portion YS in a plan view).

[0044] For the low-defect portion YS, the ratio of the size W1 in the a-axis direction to the thickness d1 (W1 / d1) can be set to, for example, 2.0 or more. Using the method of Example 1, W1 / d1 can be set to 1.5 or more, 2.0 or more, 4.0 or more, 5.0 or more, 7.0 or more, or 10.0 or more. It has been found that setting W1 / d1 to 1.5 or more facilitates the subsequent process of dividing the nitride semiconductor portion 8 (for example, a dividing process in which the cross-section becomes the m-plane). In addition, the internal stress of the nitride semiconductor portion 8 is reduced, and the warping of the semiconductor substrate 10 is reduced.

[0045] The aspect ratio (ratio of size in the X direction to thickness = WL / d1) of the nitride semiconductor portion 8 can be 3.5 or greater, 5.0 or greater, 6.0 or greater, 8.0 or greater, 10 or greater, 15 or greater, 20 or greater, 30 or greater, or 50 or greater. Furthermore, by using the method of Example 1, the ratio of the size WL of the nitride semiconductor portion 8 in the X direction to the width WK of the aperture KS (WL / WK) can be 3.5 or greater, 5.0 or greater, 6.0 or greater, 8.0 or greater, 10 or greater, 15 or greater, 20 or greater, 30 or greater, or 50 or greater, thereby increasing the ratio of low-defect portions. The nitride semiconductor portion 8 (including the initial growth portion 8p) shown in Figure 18 can be a nitride semiconductor crystal (for example, a GaN crystal, an AlGaN crystal, an InGaN crystal, or an InAlGaN crystal).

[0046] In the initial stages of lateral growth, the reflectivity of the mask portion 5 (growth suppression region) is dominant in the substrate reflectivity, but as lateral growth progresses, the reflectivity of the nitride semiconductor portion 8 becomes dominant. Therefore, when the width of the mask portion 5 is large, the change in substrate reflectivity also becomes larger, improving the accuracy of lateral growth control. For this reason, the width of the mask portion 5 may be 20 μm or more, and may be 30 μm or more, 50 μm or more, or 70 μm or more.

[0047] (Example 2) Figure 19 is a cross-sectional view showing a method for manufacturing a semiconductor device according to Example 2. Figure 19 includes the steps of: preparing the semiconductor substrate 10 as described above; forming a compound semiconductor portion 9 and electrodes D1 and D2 on the semiconductor substrate 10; bonding a laminate EB including a nitride semiconductor portion 8, a compound semiconductor portion 9, and electrodes D1 and D2 to a support substrate SK via bonding layers H1 and H2; peeling off the base substrate BS; and separating the support substrate SK into a plurality of supports ST to form a semiconductor device SD in which the laminate EB is held on the supports ST. Before peeling off the base substrate BS, the mask portion 5 may be removed by wet etching or the like.

[0048] The nitride semiconductor portion 8 may be an n-type semiconductor crystal. The compound semiconductor portion 9 may contain a GaN-based semiconductor. The compound semiconductor portion 9 may include an active portion (e.g., an active layer such as a quantum well structure) and a p-type semiconductor portion, and may include an n-type semiconductor portion (e.g., a regrowth layer, an n-type contact layer) below the active portion. If the active portion of the compound semiconductor portion 9 includes a light-emitting portion, the light-emitting portion can be positioned above the low-defect portion YS (overlapping with the low-defect portion YS in a plan view). This can increase the luminescence efficiency.

[0049] Electrode D1 located above the low-defect portion YS may be the anode and electrode D2 may be the cathode. The support substrate SK may have conductive pads in contact with bonding layer H1 and bonding layer H2. Bonding layers H1 and H2 may be formed of solder material. Before, during, or after bonding to the support substrate SK, the longitudinally shaped laminate EB may be divided into multiple parts (by cutting in the short direction), in which case the division process may be performed by cleavage of the nitride semiconductor portion 8 and the compound semiconductor portion 9 (for example, m-plane cleavage where the cleavage plane is the m-plane). If it is a semiconductor laser element, an end-face coating (formation of a reflective mirror film) may be performed on the m-plane, which is the cleavage plane. In Figure 19, the laminate EB is transferred from the base substrate BS to the support substrate SK, but it is not limited to this. It may be transferred from the base substrate BS to a tape or the like one or more times.

[0050] The semiconductor element SD may function as an LED (light-emitting diode) element or a semiconductor laser element. The support ST may be a submount substrate. Example 2 includes electronic equipment having the semiconductor element SD (e.g., lighting device, laser device, display device, measuring device, information processing device, etc.).

[0051] (Example 3) Figure 20 is a schematic diagram showing the configuration of a semiconductor substrate manufacturing apparatus according to Example 3. The semiconductor substrate manufacturing apparatus of Example 3 includes an imaging device 29 for imaging the surface (top surface) of a semiconductor substrate 10 including a template substrate TS and a growing nitride semiconductor portion. The imaging device 29 may irradiate the semiconductor substrate 10 with a first light L1 (illumination light for imaging) and receive a second light L2 (light from the mask portion 5 and light from the nitride semiconductor portion 8) from the semiconductor substrate 10.

[0052] The control device 24 uses images sent from the imaging device 29 to recognize the gap widths of the first and second nitride semiconductor sections 8F and 8S in a time series, and when the gap width reaches a specified value, it may instruct the raw material supply device 22 to stop supplying at least some of the raw materials (for example, trimethylgallium if the nitride semiconductor section 8 is a GaN crystal). It may also instruct the heating device 26 to stop high-temperature heating.

[0053] The gap is recognized by light from the mask portion 5. Therefore, a larger difference between the reflectivity of the mask portion 5 and the reflectivity of the nitride semiconductor portion 8 with respect to the first light L1 allows for a clearer image of the gap.

[0054] Figure 21 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to this embodiment. As shown in Figure 21, the low-defect portion YS (wing portion YS) of the nitride semiconductor portion 8, which is above the growth suppression region SP, may be grown to be separated from the growth suppression region SP. Even when the wing portion YS grows facing the growth suppression region SP through a gap J, the width of the gap GP can be controlled to a desired value by stopping the growth of the first and second nitride semiconductor portions 8F and 8S using the first light L1 and the second light L2. In Figure 21, the seed region 4 (4F and 4S) is located below the growth suppression region SP, but is not limited to this. The seed region 4 may be located flush with the growth suppression region SP, or it may be located above it.

[0055] (Additional items) The foregoing disclosures are for illustrative and explanatory purposes only, and not for limitation. Many variations will be obvious to those skilled in the art based on these examples and descriptions, and therefore, these variations are also included in the embodiments. [Explanation of Symbols]

[0056] 1 Main board 3. Seed section 4F 1st Seed Area 4S 2nd Seed Area 5 Mask section 6. Mask (Mask Pattern) 8F First Nitride Semiconductor Section 8S Second Nitride Semiconductor Section 10 Semiconductor substrates 20 Semiconductor substrate manufacturing equipment 22 Raw material supply device 23 Optical equipment 24 Control device SP growth suppression area BS base board UB Base part TS template substrate K1 1st opening K2 2nd opening SA slope area YS Low-Defect Part

Claims

1. A step of preparing a template substrate which includes a base substrate and has a growth-inhibiting region and first and second seed regions, A step of growing a first nitride semiconductor portion from the first seed region above the growth suppression region, and growing a second nitride semiconductor portion from the second seed region above the growth suppression region, A step of irradiating the template substrate and the semiconductor substrate including the growing first and second nitride semiconductor portions with first light, A step of receiving a second light from the semiconductor substrate, The process includes a step of stopping the growth of the first and second nitride semiconductor parts before the first and second nitride semiconductor parts associate, In the process of growing the first and second nitride semiconductor portions, an inclined region is formed on the upper surface of each of the first and second nitride semiconductor portions, having an inclination angle not exceeding 2° with respect to a plane perpendicular to the c-axis of each nitride semiconductor portion. A method for manufacturing a semiconductor substrate, comprising determining the timing for stopping the growth of the first and second nitride semiconductor portions using the second light, which includes reflected light from the aforementioned inclined region.

2. The method for manufacturing a semiconductor substrate according to claim 1, wherein the first light is irradiated onto the first and second nitride semiconductor portions and the growth-inhibiting region.

3. The method for manufacturing a semiconductor substrate according to claim 1, wherein the second light includes the reflected light from the upper surface of the first and second nitride semiconductor portions of the first light and the reflected light from the growth suppression region of the first light.

4. The method for manufacturing a semiconductor substrate according to claim 2, wherein the ratio of the reflected light intensity to the incident light intensity of the first light on the upper surface of the first and second nitride semiconductor portions is different from the ratio of the reflected light intensity to the incident light intensity of the first light in the growth suppression region.

5. The method for manufacturing a semiconductor substrate according to any one of claims 1 to 4, wherein the inclination angle of the inclined region is 0.5 degrees or more and 2.0 degrees or less.

6. A method for manufacturing a semiconductor substrate according to claim 1, comprising detecting the reflectance, which is the ratio of the intensity of the second light to the intensity of the first light, or the intensity of the second light over time.

7. A method for manufacturing a semiconductor substrate according to claim 6, wherein the growth of the first and second nitride semiconductor portions is stopped at a timing when the reflectance or the intensity of the second light falls below a threshold.

8. The method for manufacturing a semiconductor substrate according to claim 1, wherein the thickness of the edges of the first and second nitride semiconductor portions is 0.5 μm or more and 5 μm or less.

9. A method for manufacturing a semiconductor substrate according to claim 6, wherein the growth of the first and second nitride semiconductor portions is stopped at the timing when a change in trend is observed in the reflectance or the intensity of the second light.

10. A method for manufacturing a semiconductor substrate according to claim 1, wherein the thickness of each nitride semiconductor portion is smaller at the edges than at the center.

11. A method for manufacturing a semiconductor substrate according to claim 6, comprising detecting the gap width of the first and second nitride semiconductor portions over time using the reflectance, and stopping the growth of the first and second nitride semiconductor portions when the gap width reaches a specified value.

12. The method for manufacturing a semiconductor substrate according to claim 2, wherein when the growth of the first and second nitride semiconductor portions is stopped, each nitride semiconductor portion has a side surface that overhangs with respect to the growth suppression region.

13. The method for manufacturing a semiconductor substrate according to claim 12, wherein, before stopping the growth of the first and second nitride semiconductor portions, the side surfaces that overhang the growth suppression region in each nitride semiconductor portion are expanded.

14. A method for manufacturing a semiconductor substrate according to any one of claims 1 to 4, wherein the first light is absorbed by each nitride semiconductor portion at the growth temperature of each nitride semiconductor portion.

15. The method for manufacturing a semiconductor substrate according to claim 14, wherein the wavelength of the first light is included in the wavelength range of 395 to 415 nm.

16. The template substrate has a mask portion and a mask pattern including first and second openings. The method for manufacturing a semiconductor substrate according to claim 1, wherein the upper surface of the base substrate includes a first seed region overlapping the first opening and a second seed region overlapping the second opening.

17. The base substrate has a silicon substrate, A method for manufacturing a semiconductor substrate according to any one of claims 1 to 4, wherein the first and second nitride semiconductor portions include a GaN-based semiconductor.

18. The method for manufacturing a semiconductor substrate according to claim 16, wherein the gap widths of the first and second nitride semiconductor portions when their growth is stopped are less than three times the width of either the first or second opening.

19. The method for manufacturing a semiconductor substrate according to claim 16, wherein the width of the mask portion is 20 [μm] or more.

20. The base substrate includes a main substrate and a base portion located on the main substrate. The method for manufacturing a semiconductor substrate according to claim 16, wherein the upper surface of the base portion includes a first seed region that overlaps with the first opening and a second seed region that overlaps with the second opening.

21. The method for manufacturing a semiconductor substrate according to claim 20, wherein the base portion includes a nitride semiconductor.

22. The method for manufacturing a semiconductor substrate according to claim 20, wherein the base portion includes at least one of a buffer portion and a seed portion.

23. A method for manufacturing a semiconductor substrate according to any one of claims 20 to 22, wherein the lattice constants of the main substrate and the first and second nitride semiconductor portions are different.

24. A method for manufacturing a semiconductor substrate according to any one of claims 16, 18 to 22, wherein the thickness of the mask portion is 50 nm or more and 5 μm or less.

25. A stage on which a template substrate is placed, which includes a base substrate and has growth-inhibiting regions and first and second seed regions, A raw material supply device for supplying raw materials to grow a first nitride semiconductor portion from the first seed region above the growth suppression region, and a second nitride semiconductor portion from the second seed region above the growth suppression region, and for forming inclined regions on the upper surfaces of the first and second nitride semiconductor portions, each having an inclination angle not exceeding 2° with respect to a plane perpendicular to the c-axis of each nitride semiconductor portion, An optical device that irradiates the template substrate and the semiconductor substrate including the growing first and second nitride semiconductor portions with first light and receives second light from the semiconductor substrate, The system includes a control device that controls the raw material supply device so that the growth of the first and second nitride semiconductor parts stops before the first and second nitride semiconductor parts combine, A semiconductor substrate manufacturing apparatus, wherein the control device determines the timing for stopping the supply of at least a portion of the raw materials to the raw material supply device using the second light, which includes the reflected light from the inclined region.

26. The semiconductor substrate manufacturing apparatus according to claim 25, wherein the control device detects the gap width of the first and second nitride semiconductor portions over time using the reflectance, which is the ratio of the intensity of the second light to the intensity of the first light, and instructs the raw material supply device to stop supplying at least a portion of the raw materials when the gap width reaches a predetermined value.

27. A raw material supply device is provided to supply raw materials to a template substrate including a base substrate and having a growth suppression region and first and second seed regions, to grow a first nitride semiconductor portion from the first seed region to above the growth suppression region, and to grow a second nitride semiconductor portion from the second seed region to above the growth suppression region, and to form inclined regions on the upper surfaces of each of the first and second nitride semiconductor portions having an inclination angle not exceeding 2° with respect to a plane perpendicular to the c-axis of each nitride semiconductor portion; and an optical device is capable of communicating with the template substrate and the semiconductor substrate including the growing first and second nitride semiconductor portions, to irradiate the semiconductor substrate with first light, and to receive second light from the semiconductor substrate, including reflected light from the inclined regions. A control device that controls the raw material supply device so that the growth of the first and second nitride semiconductor portions stops before they associate.

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