Error correction management for data storage systems

Abstract

To provide a system, method and device for managing error corrections for a data storage system.SOLUTION: A data storage system 400 includes a data storage device 410 comprising at least one memory 412 and a memory controller including at least one first error correction code (ECC) decoder 414. The memory controller reads data from the at least one memory, executes an ECC test on the read-out data using the at least one first ECC decoder, and transmits the read-out data to an external device having at least one second ECC decoder for decoding the read-out data in response to a determination that the read-out data has not passed the ECC test. The external device 420 is located external of the data storage device. A second ECC decoder 422 has an ECC function stronger than the first ECC decoder.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] This disclosure relates to error correction for data storage systems, such as data storage systems for data storage systems.

Background Art

[0002] Once a storage cell in a data storage device, such as a memory device, is programmed, data can be read from the storage cell by sensing the programming state of each memory cell by comparing the cell threshold voltage with one or more read voltages. However, the cell threshold voltage may change due to one or more factors such as read disturbance or data retention, which may cause the sensed programming state to differ from the written programming state, and a fail bit may occur in the read output of the data.

Summary of the Invention

[0003] This disclosure describes systems, devices, methods and techniques for managing error correction for data storage systems, such as data storage systems including a plurality of data storage devices such as solid state drives (SSDs), high density drives (HDDs), NAND flash modules, combinations thereof, etc.

[0004] One aspect of the present disclosure comprises a data storage system including one or more data storage devices; and a system controller coupled to one or more data storage devices. The one or more data storage devices include a data storage device having at least one memory and a memory controller coupled to at least one memory, the memory controller including at least one first error correction code (ECC) decoder. The memory controller is configured to read data from at least one memory, perform a first ECC test on the read data using at least one first ECC decoder, and, in response to a determination that the read data has failed the first ECC test, transmit the read data to an external device having at least one second ECC decoder for decoding the read data. The external device is outside the data storage device, and the at least one second ECC decoder has stronger ECC capabilities than the at least one first ECC decoder.

[0005] In some implementations, at least one memory includes one or more memory chips.

[0006] In some implementations, the memory controller is configured to, in response to a determination that the read data has failed the first ECC test, and before transmitting the read data to an external device, determine whether the number of times the read data has failed the first ECC test is less than a predetermined threshold; if the number is less than the predetermined threshold, modify one or more read parameters to read the data again from at least one memory, or perform soft decoding on the data; and if the number has reached the predetermined threshold, transmit the read data to an external device that includes at least one second ECC decoder for decoding the read data.

[0007] In some implementations, the memory controller is configured to, in response to a determination that the read data has failed a first ECC test, and before transmitting the read data to at least one second ECC decoder, perform one of the following based on the result of the first ECC test: i) modify one or more parameters to read data from at least one memory, or perform soft decoding on the data and run the first ECC test again using at least one first ECC decoder; or ii) transmit the read data to an external device containing at least one second ECC decoder for decoding the read data.

[0008] In some implementations, the external device is configured to perform a second ECC test on the read data using at least one second ECC decoder, and to transmit the corrected read data to the system controller in response to a determination that the read data has passed the second ECC test.

[0009] In some implementations, the external device is configured to respond to a determination that the read data has failed the second ECC test by determining whether the number of times the read data has failed the second ECC test is less than a predetermined threshold; if the number is less than the predetermined threshold, it transmits a notification to the memory controller to i) change one or more parameters to read data from at least one memory, or ii) perform soft decoding on the data; and if the number has reached the predetermined threshold, it triggers the RAID (Independent Disk Redundancy Array) circuit to perform error correction on the read data.

[0010] In some implementations, the external device is configured to respond to a determination that the read data has failed the second ECC test, and before triggering the RAID circuit, to perform one of the following based on the result of the second ECC test: i) modify one or more parameters to read data from at least one memory, or perform soft decoding on the data and re-run at least one of the first ECC test using at least one first ECC decoder or the second ECC test using at least one second ECC decoder; or ii) trigger the RAID circuit to perform error correction on the read data.

[0011] In some implementations, the RAID circuitry is integrated into the memory controller and configured to perform error correction on data read from the data storage device.

[0012] In some implementations, the RAID circuitry is integrated into the system controller and configured to perform error correction on data read from one or more data storage devices.

[0013] In some implementations, the memory controller is configured to perform an ECC decoding operation on the read data using at least one first ECC decoder; determine whether the number of error bits in the read data after the ECC decoding operation is less than a predetermined threshold; determine that the read data has passed the first ECC test if the number of error bits is less than the predetermined threshold; and determine that the read data has not passed the first ECC test if the number of error bits is equal to or greater than the predetermined threshold.

[0014] In some implementations, the system controller is configured to receive commands from a host device outside the data storage system instructing it to read data from one or more data storage devices, to send commands to the data storage devices to read the data, and to transmit the corrected read data to the host device in response to receiving the corrected read data from the data storage device or an external device.

[0015] In some implementations, the external device is separate from one or more data storage devices and is coupled to one or more data storage devices and a system controller.

[0016] In some implementations, the data storage device includes only one first ECC decoder, without a second ECC decoder.

[0017] In some implementations, the external device includes only one second ECC decoder, without a first ECC decoder.

[0018] In some implementations, a second data storage device of one or more data storage devices includes an external device, and the second data storage device includes one or more first ECC decoders and at least one second ECC decoder.

[0019] In some implementations, one or more data storage devices include one or more first data storage devices, each containing only one or more first ECC decoders, and one or more second data storage devices each contain one or more first ECC decoders and one or more second ECC decoders.

[0020] In some implementations, the system controller is configured to store a first type of data in one or more first data storage devices and a second type of data in one or more second data storage devices. The first type of data is configured to be read more frequently than the second type of data.

[0021] In some implementations, one or more first data storage devices and one or more second data storage devices are configured to operate on a protocol. Each of the one or more first data storage devices is configured to transmit the read first data to one of the one or more second data storage devices in response to a determination that one or more first ECC decoders within the first data storage device have failed to correct the first data read from the corresponding first memory. Each of the one or more second data storage devices is configured to decode the corresponding read data using one or more second ECC decoders within the second data storage device in response to receiving the corresponding read data from one of the one or more first data storage devices.

[0022] In some implementations, external devices are included within the system controller.

[0023] In some implementations, the data storage system further includes one or more external devices, each of which includes one or more external devices, and each of these external devices includes one or more second ECC decoders.

[0024] In some implementations, the system controller is configured to generate an alert message to discard a data storage device based on at least one of the results of a first ECC test using at least one first ECC decoder or a second ECC test using at least one second ECC decoder.

[0025] In some implementations, the memory controller includes a first ECC encoder configured to encode data to generate first ECC data, and the memory controller is configured to store the data together with the first ECC data in at least one memory. At least one first ECC decoder is configured to decode the read data based on the first ECC data, and at least one second ECC decoder is configured to decode the read data based on the first ECC data.

[0026] In some implementations, the memory controller includes a first ECC encoder configured to encode data to produce first ECC data, and the external device includes a second ECC encoder configured to encode data to produce second ECC data. The memory controller is configured to store data together with the first and second ECC data in at least one memory, to read data together with the first and second ECC data from at least one memory, and, in response to a determination that the read data has failed the first ECC test, to transmit the read data and the second ECC data to an external device having at least one second ECC decoder. At least one first ECC decoder is configured to decode the read data based on the first ECC data, and at least one second ECC decoder is configured to decode the read data based on second ECC data received from the memory controller.

[0027] In some implementations, the memory controller is configured to store the first ECC data and the second ECC data as a concatenated code of the data in at least one memory.

[0028] In some implementations, the system controller is configured to transmit each of a plurality of portions of specific data to a plurality of data storage devices of one or more data storage devices, respectively. Each of the plurality of data storage devices includes a first ECC encoder and one or more first ECC decoders, and the first ECC encoder is configured to encode a corresponding portion of the specific data to generate a corresponding first ECC data. The external device includes a second ECC encoder configured to encode a plurality of portions of the specific data to generate second ECC data. Each of the plurality of data storage devices includes a memory controller configured to store a corresponding portion of the specific data together with the corresponding first ECC data and the second ECC data in a corresponding memory. For each of the plurality of data storage devices, the one or more first ECC decoders are configured to decode a corresponding portion of the specific data from the corresponding memory based on the corresponding first ECC data. At least the second ECC decoder in the external device is configured to decode a portion of the specific data based on the second ECC data in response to receiving a portion of the specific data from one of the plurality of data storage devices and the second ECC data.

[0029] In some implementations, at least one first ECC decoder and at least one second ECC decoder include decoders of the same type having different ECC functions.

[0030] In some implementations, at least one first ECC decoder and at least one second ECC decoder include decoders of different types having different ECC functions.

[0031] In some implementations, at least one first ECC decoder includes a low-power (LP) low-density parity-check (LDPC) decoder, and at least one second ECC decoder includes a min-sum (MS) LDPC decoder.

[0032] In some implementations, at least one of at least one first ECC decoder or at least one second ECC decoder is configured to perform Bose-Chaudhuri-Hocquenghem (BCH) decoding or LDPC decoding.

[0033] In some implementations, the first ECC decoder consumes less power than the second ECC decoder.

[0034] Another aspect of the present disclosure comprises a data storage device including at least one memory and a memory controller coupled to the at least one memory. The memory controller includes at least one first error correction code (ECC) decoder. The memory controller is configured to read data from the at least one memory, perform a first error correction code (ECC) test on the read data using at least one first ECC decoder, and, in response to a determination that the read data has failed the first ECC test, transmit the read data to an external device having at least one second ECC decoder for decoding the read data. The external device is outside the data storage device, and the at least one second ECC decoder has stronger ECC capabilities than the at least one first ECC decoder.

[0035] In some implementations, the memory controller includes only one first ECC decoder, without a second ECC decoder.

[0036] In some implementations, the memory controller is configured to, in response to a determination that the read data has failed the first ECC test, and before transmitting the read data to an external device, determine whether the number of times the read data has failed the first ECC test is less than a predetermined threshold; if the number is less than the predetermined threshold, modify one or more read parameters to read the data again from at least one memory, or perform soft decoding on the data; and if the number has reached the predetermined threshold, transmit the read data to an external device that includes at least one second ECC decoder for decoding the read data.

[0037] Another aspect of the present disclosure comprises a device comprising at least one first error correction code (ECC) decoder externally coupled to at least one data storage device comprising at least one memory configured to store data. The at least one data storage device comprises at least one second ECC decoder, the at least one first ECC decoder having stronger ECC capabilities than the at least one second ECC decoder. The at least one first ECC decoder is configured to perform an ECC test on the data read out using the at least one first ECC decoder in response to receiving read data from the at least one data storage device, and to generate corrected read data for the at least one data storage device in response to a determination that the read data has passed the ECC test.

[0038] In some implementations, the device is configured to respond to a determination that the read data has failed the ECC test by determining whether the number of times the read data has failed the ECC test is less than a predetermined threshold; if the number is less than the predetermined threshold, it transmits a notification to at least one data storage device to i) modify one or more parameters to read the data from at least one memory, or ii) perform soft decoding on the data; and if the number has reached the predetermined threshold, it triggers a RAID (Independent Disk Redundancy Array) circuit to perform error correction on the read data.

[0039] In some implementations, at least one second ECC decoder is configured to decode data read based on ECC data associated with data stored in at least one memory, and at least one first ECC decoder is configured to decode data read based on ECC data.

[0040] In some implementations, the device further includes a first ECC encoder configured to encode data to generate first ECC data and transmit the first ECC data to at least one data storage device. The at least one data storage device includes a second ECC encoder configured to encode data to generate second ECC data. The at least one data storage device is configured to store data together with the first and second ECC data in at least one memory, to read data together with the first and second ECC data from at least one memory, and to transmit the read data and the first ECC data to at least one first ECC decoder in response to a determination that the read data has not been decoded based on the second ECC data. The at least one first ECC decoder is configured to decode the read data based on the first ECC data in response to receiving the read data and the first ECC data from at least one data storage device.

[0041] In some implementations, the data comprises multiple parts, and at least one data storage device comprises multiple data storage devices, each configured to store multiple parts. The device further includes a first ECC encoder configured to encode multiple parts of the data to produce first ECC data and to transmit the first ECC data to each of the multiple data storage devices. Each of the multiple data storage devices includes a second ECC encoder configured to encode corresponding parts of the data to produce corresponding second ECC data. Each of the multiple data storage devices is configured to store corresponding parts of the data in corresponding memory along with the corresponding second ECC data and the first ECC data. At least a first ECC decoder is configured to decode parts of the data based on the first ECC data in response to receiving parts of the data from one of the multiple data storage devices and the first ECC data.

[0042] Implementations of the above technology include methods, systems, computer program products, and computer-readable media. In one example, the method may be performed by a data storage system including a plurality of data storage devices and a system controller coupled to the plurality of data storage devices, and the method may include the above operations performed by the system controller and data storage devices, for example, operations for managing error correction for the data storage devices. Another example is a computer program product which is appropriately embodied in a non-temporary machine-readable medium that stores instructions executable by one or more processors. The instructions are configured to cause one or more processors to perform the above operations. A computer-readable medium stores instructions configured to cause one or more processors to perform the above operations when executed by one or more processors.

[0043] Details of one or more disclosed implementations are described in the accompanying drawings and the following description. Other features, embodiments, and advantages will become apparent from the description, drawings, and claims. [Brief explanation of the drawing]

[0044] [Figure 1A] This is a schematic diagram of an example system, including a data storage system.

[0045] [Figure 1B] This is a schematic diagram of an example of a first data storage device that includes both a weaker ECC decoder and a stronger ECC decoder.

[0046] [Figure 1C] This is a schematic diagram of an example of a second data storage device that includes only a weaker ECC decoder.

[0047] [Figure 1D] This is a schematic diagram of an example of an external device that includes only a stronger ECC decoder.

[0048] [Figure 2] This is a schematic diagram of an example of a data storage system that includes one or more external devices having stronger ECC decoders for data storage devices having only weaker ECC decoders.

[0049] [Figure 3] This is a schematic diagram of another example of a data storage system, including a data storage device with a stronger ECC decoder for a data storage device with only a weaker ECC decoder.

[0050] [Figure 4] This is a schematic diagram of another example of a data storage system that includes a system controller, which includes one or more external devices having stronger ECC decoders for data storage devices.

[0051] [Figure 5] This is a flowchart illustrating an exemplary process for managing error correction within a data storage system.

[0052] [Figure 6A] This is a schematic diagram illustrating the exemplary processes of data encoding and data decoding within a data storage system.

[0053] [Figure 6B] This is a schematic diagram illustrating another exemplary process of data encoding and data decoding within a data storage system.

[0054] [Figure 6C] This is a schematic diagram illustrating another exemplary process of data encoding and data decoding within a data storage system.

[0055] Similar reference numbers and symbols in various drawings refer to the same elements. It should be understood that the various exemplary implementations shown in the drawings are illustrative representations only and are not necessarily drawn to scale. [Modes for carrying out the invention]

[0056] Due to frequent read operations or long retention times, data stored in memory may suffer read disturbance or data retention, where the state of the memory cells within the memory, such as an erase state and one or more programmed states, may have altered the threshold voltage. Read disturbance or data retention can result in fail bits (or error bits) in the data read output. These problems are more severe in data storage systems that include multiple data storage devices, such as SSDs, HDDs, flash modules, or combinations thereof.

[0057] Multiple approaches can be employed to ensure data accuracy. In some cases, read optimization (or calibration) approaches, such as read retries, valley tracking readouts, and machine learning-based readouts, may be employed to reduce error bits. In some cases, an error correction code (ECC) decoder may be configured to decode data read from memory and detect and correct any bit errors that may exist in the data up to the error correction function of the ECC scheme.

[0058] In some cases, erase coding is implemented in storage systems to enhance fault tolerance and recover data from memory chip and / or storage device failures. In storage systems using erase coding, data can be reconstructed even if a certain number of storage nodes become unavailable or data loss occurs. This makes erase coding valuable in distributed storage environments where hardware failures or network problems are common. While erase coding offers attractive advantages, it increases computational requirements. The encoding and decoding processes involve complex mathematical calculations and can potentially impact system performance. In some cases, RAID (Independent Disk Redundancy Array) is a data storage virtualization technique that combines multiple physical disk drive components into one or more logical units for data redundancy, performance improvement, or both. Unlike ECC data stored as user data on the same page, RAID-redundant data is stored across different physical disk drive components. Therefore, RAID can provide page-to-page or disk-to-disk RAID protection to recover ECC-uncorrectable data as additional protection. However, implementing page-to-page or disk-to-disk RAID protection requires reading all pages for failed data, which takes significantly longer to recover than ECC. The probability of triggering RAID can be configured to be extremely low due to the performance requirements of the data storage system.

[0059] To avoid long recovery times for RAID procedures and / or high computational requirements for erase coding, the error handling process of a data storage system may iteratively repeat read-optimized and ECC-decode procedures with different parameter settings. Error correction for read-optimized and ECC-decode may also be improved to efficiently reduce the trigger rate of RAID and / or erase coding. Generally, read-optimized and ECC-decode approaches are implemented in the device controller (e.g., SSD controller) of a data storage device (e.g., SSD). However, achieving high ECC capabilities requires enormous hardware resources (e.g., gate count of ASICs in the SSD controller). In some cases, data storage devices may include dual-mode ECC decoders, e.g., both a weaker ECC decoder and a stronger ECC decoder, to reduce the overall hardware cost and power consumption of the ECC decoder. However, the hardware overhead of the stronger ECC decoder is still a major part of the device controller. Also, the power consumption of the stronger ECC decoder is advantageous compared to the power consumption of the data storage device.

[0060] Implementations of this disclosure provide techniques for managing error correction for data storage systems by, for example, providing i) cost-effective data storage devices having weaker built-in ECC decoders for most read requests, and ii) one or more external devices having stronger ECC decoders to ensure the reliability of the entire data storage system. These techniques may be implemented using a novel error correction architecture for data storage systems, which enables efficient cost reduction of data storage devices (e.g., SSDs) with the same (or similar) reliability for the entire data storage system.

[0061] In some examples, a data storage system includes a rack cabinet or rack mount of a storage system that may contain multiple data storage devices (e.g., SSDs or HDDs). In some examples, a data storage system is an all-flash array. A processing unit (e.g., FPGA or DPU) can function as a controller for multiple memory chips (e.g., NAND flash memory chips), and a combination of the processing unit and multiple memory chips may be considered a storage module (or flash module). An all-flash array may contain multiple storage modules. A data storage system may include a system controller configured to manage data allocation between multiple data storage devices or multiple storage modules, which may improve read / write performance and storage lifespan.

[0062] A data storage device (or a single storage module) may include an internal (or local) ECC decoder for detecting and correcting error bits in one or more memories (e.g., NAND flash memory chips). The internal (or local) ECC decoder may be implemented with only a weaker ECC decoder, which may be less expensive, lower power consumption, and take up less space. If the weaker ECC decoder is unable to decode the data read from one or more memories, the data storage device may transmit the read data to an external device within the data storage system. The external device may be a reliable device or accelerator. The external device may be outside the data storage device and may include a stronger ECC decoder for decoding the read data. The stronger ECC decoder has stronger ECC capabilities than the internal (or local) ECC decoder. The internal (or local) ECC decoder can handle most read requests with low power consumption, while the stronger ECC decoder ensures the reliability of the entire data storage system. The number of stronger ECC decoders may be scalable to improve the end-of-life (EOL) performance of the entire data storage system. The data storage system may include one or more external devices, each containing one or more stronger ECC decoders.

[0063] External devices can be implemented as field-programmable gate array (FPGA) devices, or any processing unit such as a central processing unit (CPU), graphics processing unit (GPU), data processing unit (DPU), or full SSD. In a data storage system, data storage devices or flash modules (e.g., SSDs or NAND flash modules) are consumables due to their limited lifespan (e.g., durability, maximum total bytes written (TBW)). Therefore, by implementing data storage devices or flash modules with lower-cost, weaker ECC decoders, the cost of the data storage devices or flash modules can be reduced, thereby efficiently lowering the total cost of ownership (TCO) of the data storage system. These techniques allow the primary burden of SSD / flash modules (e.g., stronger ECC decoders) to be shifted externally, making it possible to rely on external devices to maintain the reliability of the entire data storage system. In this way, the cost of consumables for the entire data storage system is significantly reduced. Furthermore, improvements in read performance for end-of-life devices can be achieved by adding stronger ECC decoders to external devices. Furthermore, read optimization approaches can be performed locally or globally with the support of external devices that have stronger ECC decoders, such as machine learning-based read optimization, which is online inference by external devices.

[0064] In some implementations, for example as shown in further detail in Figure 2, the external device is outside the data storage device and system controller but is coupled to them. In some implementations, for example as shown in further detail in Figure 4, the external device is included within the system controller.

[0065] In some implementations, for example, as shown in further detail in Figure 3, the external device is integrated into a data storage device that has its own memory chip and provides the functionality of a normal data storage device (e.g., a normal SSD, HDD, or NAND flash module). The data storage device may include only a stronger ECC decoder, or it may include a dual-mode ECC decoder (e.g., both a weaker ECC decoder and a stronger ECC decoder). The data storage device may be useful for decoding faulty data in other data storage devices that have only a weaker ECC decoder. In some cases, the data storage system includes one or more first data storage devices having only a weaker ECC decoder, and one or more second data storage devices having a stronger ECC decoder and optionally a weaker ECC decoder. A data storage system can store hot data (e.g., more data reads) in one or more first data storage devices with more frequent exchanges, and cold data (e.g., less frequent data reads) in one or more second data storage devices with less frequent exchanges, thereby potentially reducing the total cost of ownership (TCO) of the data storage system. The data storage system may include a protocol between one or more first data storage devices and one or more second data storage devices to enable stronger ECC decoders in one or more second data storage devices to help decode fault data in one or more first data storage devices.

[0066] In this disclosure, a weaker ECC decoder represents an ECC decoder having a weaker ECC function that has lower power consumption and lower cost compared to a stronger ECC decoder having a stronger ECC function that has higher power consumption and higher cost. In some examples, a weaker ECC decoder is an ECC decoder having an ECC function lower than a specified threshold for a data storage device, and a stronger ECC decoder is an ECC decoder having an ECC function that is the same as or higher than the specified threshold. In some examples, a weaker ECC decoder and a stronger ECC decoder are the same type of decoder having different ECC functions. For example, a weaker ECC decoder may be a low-power (LP) low-density parity-check (LDPC) decoder, and a stronger ECC decoder may be a min-sum (MS) LDPC decoder. In some examples, a weaker ECC decoder and a stronger ECC decoder are different types of decoders having different ECC functions. For example, a weaker ECC decoder may be a Bose-Chaudhuri-Hocquenghem (BCH) decoder, and a stronger ECC decoder may be an LDPC decoder. The ECC code is not limited to the LDPC code; any linear block ECC, such as an algebraic code, a concatenation code, or a product code, may be used in this disclosure.

[0067] In some cases, the same ECC decoder (e.g., an LDPC decoder) may be configured to be either a weaker or stronger ECC decoder. For example, an ECC encoder is configured to encode data of a predetermined length or size (e.g., 4KB) to produce ECC data of a predetermined size (e.g., 512B). The ECC data may include an ECC parity bit. The ECC decoder is configured to decode data of a predetermined length or size (e.g., 4KB) using ECC data of a predetermined size (e.g., 512B). For data of the same size, larger ECC data can provide higher error correction (or ECC functionality) than smaller ECC data. For ECC data of the same size, ECC data can provide higher error correction for smaller data than for larger data. For example, a 4KB ECC encoder produces 512B ECC data. When using an ECC encoder to encode 2KB of data and 2KB of a predetermined (or fixed) value (e.g., 1 or 0) to generate 512B ECC data, if an ECC decoder decodes the data using the ECC data, the 512B ECC data generated based on 2KB of data can provide a higher error correction capability than the 512B ECC data generated based on 4KB of data.

[0068] These technologies can be applied to various types of semiconductor devices, volatile memory devices, or non-volatile memory (NVM) devices, particularly NAND flash memory, NOR flash memory, resistive random-access memory (RRAM®), phase-change memory (PCM) such as phase-change random-access memory (PCRAM), and spin-transfer torque (STT) magnetoresistive random-access memory (MRAM). These technologies can also be applied to charge-trapped memory devices, such as silicon oxide nitride (SONOS) memory devices and floating-gate memory devices. These technologies can be applied to two-dimensional (2D) or three-dimensional (3D) memory devices. These technologies can be applied to various memory types, such as single-level cell (SLC) devices, two-level cell devices, triple-level cell (TLC) devices, quad-level cell (QLC) devices, or multi-level cell (MLC) devices such as penta-level cell (PLC) devices. Additionally, or alternatively, these technologies can be applied to various types of devices and systems, including, among others, Secure Digital (SD) cards, Embedded Multimedia Cards (eMMC) or Solid State Drives (SSDs), and embedded systems. These technologies can be applied to SSD or HDD-based storage systems or all-flash arrays.

[0069] Figure 1A is a schematic diagram of an example of a system 100 including a data storage system 110 and a host device 120. The data storage system 110 may include a system controller 112 and a plurality of data storage devices 130-1, 130-2, ..., 130-n (collectively referred to as data storage device 130, and individually referred to as data storage device 130), where n is an integer of 1 or more. The system controller 112 and the data storage devices 130 may be coupled to a communication bus 115, through which the system controller 112 can communicate with each of the data storage devices 130, and the data storage devices 130 themselves can also communicate with each other. In some examples, the communication bus 115 includes a Peripheral Component Interconnect Express (PCIe) based bus or interface. In some implementations, the system controller 112 and the data storage devices 130 communicate wirelessly or via a wired connection.

[0070] The system controller 112 is configured to manage data allocation between the data storage devices 130. For example, the system controller 112 can receive data and write commands from the host device 120 and store this data in one or more data storage devices 130. The system controller can also receive read commands from the host device 120 and read data from one or more data storage devices 130.

[0071] The host device 120 includes a host controller which may include at least one processor and at least one memory, the at least one memory being coupled to at least one processor and storing program instructions for execution by at least one processor to perform one or more corresponding operations. The system controller 112 may include at least one memory and at least one processor configured to execute instructions in at least one memory and process data. The instructions may include firmware instructions and / or other program instructions stored as firmware code and / or other program code, respectively. The data includes, among other suitable data, program data corresponding to firmware and / or other programs executed by at least one processor. In some implementations, the at least one processor is a general-purpose microprocessor or an application-specific microcontroller, e.g., a CPU, GPU, or DPU.

[0072] The data storage device 130 may be a solid-state drive (SSD), an embedded multimedia card (eMMC), a secure digital (SD) card, a flash module (e.g., a NAND flash memory module), or any other suitable storage device. As will be described in further detail below, the data storage devices 130 may be the same as or different from each other, as shown, for example, in Figure 3.

[0073] In some implementations, the data storage device 130 includes a memory controller and one or more memories. Each memory may include one or more memory chips (e.g., NAND flash memory chips). The memory controller is configured to receive data and instructions from the system controller 112 and to send data to the system controller 112. The memory controller may also be configured to send data and commands to one or more memories and to receive data from one or more memories. For example, the memory controller may be configured to send data and write commands to instruct one or more memories to store data at a specified address. In another example, the memory controller may be configured to receive a read request (or read command) from the system controller 112 and send a corresponding read command to one or more memories to read data from a specified address in one or more memories.

[0074] In some implementations, the memory controller includes one or more ECC encoders and one or more ECC decoders. In some implementations, one or more ECC encoders and one or more ECC decoders may also be arranged to be externally coupled to the memory controller. The ECC encoder may be configured to receive data to be stored in memory and generate check bits by encoding the data using, for example, an ECC encoding scheme. The check bits may be referred to as ECC data. The ECC encoder may include a Reed-Solomon encoder, a Bose-Chaudhuri-Hocquenghem (BCH) encoder, a low-density parity-check (LDPC) encoder, or any combination thereof. The ECC decoder may be configured to decode data read from memory and detect and correct any bit errors that may be present in the data, up to the error correction function of the ECC scheme. The ECC decoder can perform BCH decoding or LDPC decoding. The ECC decoder may be a BCH decoder, a low-power (LP) LDPC decoder, or a min-sum (MS) LDPC decoder. The ECC decoder may use any linear block ECC, such as algebraic codes, concatenated codes, product codes, etc.

[0075] In some implementations, the data storage system 110 includes a RAID circuit (or RAID configuration) configured to protect data using RAID technology. The RAID circuit can distribute data across different disk drives within the data storage device 130 or between multiple data storage devices 130. The RAID circuit may be configured to provide additional phase error protection in case read optimization and ECC protection are not available within the data storage system 110.

[0076] Figure 1B is a schematic diagram of an example of a first data storage device 150 that includes both a weaker ECC decoder and a stronger ECC decoder. The first data storage device 150 may be an SSD, HDD, or NAND flash module.

[0077] The first data storage device 150 may be implemented as the data storage device 130 in Figure 1A. The first data storage device 150 may include one or more memories 152 and a memory controller 151. Each of the one or more memories 152 may include one or more memory chips 153, for example, NAND flash memory chips. The memory controller 151 may include one or more first ECC decoders 154 (e.g., weaker ECC decoders) and one or more second ECC decoders 156 (e.g., stronger ECC decoders). The second ECC decoders may have stronger ECC capabilities than the first ECC decoders. If one or more first ECC decoders 154 are unable to decode the data read from one or more memories 152, the memory controller 151 can control one or more second ECC decoders 156 within the first data storage device 150 to decode the read data.

[0078] Figure 1C is a schematic diagram of an example of a second data storage device 160 that includes only a weaker ECC decoder. The second data storage device 160 may be an SSD, HDD, or NAND flash module. The second data storage device 160 may be implemented as the data storage device 130 in Figure 1A.

[0079] Similar to the first data storage device 150 in Figure 1B, the second data storage device 160 may include a memory controller 161 and one or more memories 152. Unlike the memory controller 151 in Figure 1B, the memory controller 161 may include only one or more first ECC decoders 154 (e.g., weaker ECC decoders) without any other ECC decoders such as a second ECC decoder 156. As described in further detail in Figures 2 to 5, if one or more first ECC decoders 154 are unable to decode the data read from one or more memories 152, the memory controller 161 can transmit the read data to an external device that includes a stronger ECC decoder (e.g., a second ECC decoder 156). The external device is outside the second data storage device 160.

[0080] Figure 1D is a schematic diagram of an example of an external device 170 that includes only a stronger ECC decoder. The external device 170 may be considered a reliable device or accelerator. The external device 170 may include only a stronger ECC decoder for decoding read data. The external device 170 may include a controller configured to control the stronger ECC decoder. The stronger ECC decoder may be a second ECC decoder 156, which may be the same as the second ECC decoder 156 in Figure 1B. The stronger ECC decoder has stronger ECC capabilities than an internal (or local) ECC decoder, e.g., the first ECC decoder 154 in the data storage device 150 in Figure 1B, or in the data storage device 160 in Figure 1C. The external device 170 may be implemented by a field-programmable gate array (FPGA) device, or by any processing unit, e.g., a central processing unit (CPU), graphics processing unit (GPU), data processing unit (DPU), or full SSD.

[0081] In some implementations, for example, as illustrated in further detail in Figure 2, the external device 170 may be outside the data storage device 130 (e.g., the second data storage device 160 in Figure 1C) and the system controller 112. In some implementations, for example, as illustrated in further detail in Figure 3, the external device 170 may be one of the data storage devices 130, or may be included in one of the data storage devices 130 (e.g., the first data storage device 150 in Figure 1B). In some implementations, for example, as illustrated in further detail in Figure 4, the external device 170 may be included within the system controller 112.

[0082] As shown in Figure 1A, the data storage system 110 may include one or more accessory devices 140 that can be coupled to the data storage device 130 and the system controller 112 via the bus 115. In some implementations, one or more accessory devices 140 may include one or more external devices 170 as shown in Figure 1D, each of which may include one or more stronger ECC decoders (e.g., the second ECC decoder 156 in Figure 1B or Figure 1D). If the data storage device 130 (e.g., the data storage device 160 in Figure 1C) is unable to decode the read data using the built-in ECC decoder in the data storage system 110 (e.g., the first ECC decoder 154 in Figure 1C), the data storage device 130 may transmit the read data to one or more accessory devices 140 that can decode the read data using one or more stronger ECC decoders.

[0083] Figure 2 is a schematic diagram of an example of a data storage system 200 that includes one or more external devices 220 having a stronger ECC decoder 222 for a data storage device 210 having only a weaker ECC decoder 214. The data storage system 200 may be implemented as the data storage system 110 in Figure 1A. The data storage system 200 includes a system controller 202 (e.g., system controller 112 in Figure 1A) that communicates with the data storage device 210 via a bus 204 (e.g., communication bus 115 in Figure 1A). The data storage device 210 and one or more external devices 220 can also communicate with each other via the bus 204.

[0084] Each of the data storage devices 210 may be the data storage device 160 in Figure 1C, which includes only one or more weaker ECC decoders 214 (e.g., the first ECC decoder 154 in Figure 1B or Figure 1C). Each of the one or more external devices 220 may be the external device 170 in Figure 1D, which includes only one or more stronger ECC decoders 222 (e.g., the second ECC decoder 156 in Figure 1B or Figure 1D). If one or more weaker ECC decoders 214 are unable to decode the data read from one or more memories 212, the data storage device 210 may transmit the read data to one or more external devices 220 for decoding the data up to the ECC function using one or more stronger ECC decoders 222.

[0085] Compared to the data storage system in Figure 1B that includes all of the first data storage devices 150, the data storage system 200 includes a data storage device 210 that has lower cost and lower power consumption due to having only one or more external devices 220 having a weaker ECC decoder 214 and a stronger ECC decoder 222. The weaker ECC decoder 214 is configured to handle most read requests in the data storage device 210 with low power consumption, and the one or more external devices 220 are configured to ensure the overall reliability of the data storage system 200 with the stronger ECC decoder 222. The number of stronger ECC decoders 222 and / or the number of external devices 220 may be scalable to improve the end-of-life (EOL) performance of the data storage system 200.

[0086] Figure 3 is a schematic diagram of another example of a data storage system 300 that includes a data storage device having a stronger ECC decoder for a data storage device having only a weaker ECC decoder. The data storage system 300 may be implemented as the data storage system 110 in Figure 1A. The data storage system 300 includes a system controller 302 (e.g., system controller 112 in Figure 1A) that communicates with a first data storage device 310 and a second data storage device 320 via a bus 304 (e.g., communication bus 115 in Figure 1A). The first data storage device 310 and the second data storage device 320 can also communicate with each other via the bus 304.

[0087] Each of the second data storage devices 320 may be the first data storage device 150 in Figure 1B and may include both a weaker ECC decoder 324 (e.g., the first ECC decoder 154 in Figure 1B or Figure 1C) and a stronger ECC decoder 326 (e.g., the second ECC decoder 156 in Figure 1B or Figure 1D). If the weaker ECC decoder 324 is unable to decode the data read from one or more memories 322 (e.g., one or more memories 152 in Figure 1B or Figure 1C), the stronger ECC decoder 326 in the second data storage device 320 can decode the read data within the second data storage device 320.

[0088] Each of the first data storage devices 310 may be the data storage device 160 in Figure 1C, which includes only one or more weaker ECC decoders 314 (e.g., the first ECC decoder 154 in Figure 1B or Figure 1C). If the weaker ECC decoder 314 is unable to decode the data read from one or more memories 312 in the first data storage device 310 (e.g., one or more memories 152 in Figure 1B or Figure 1C), the first data storage device 310 may be configured to transmit the read data to one or more second data storage devices 320 for decoding using a stronger ECC decoder 326 in one or more second data storage devices 320.

[0089] The data storage system 300 may include a protocol between one or more first data storage devices 310 and one or more second data storage devices 320 to enable a stronger ECC decoder 326 in one or more second data storage devices 320 to decode faulty data in one or more first data storage devices 310. For example, each of the one or more first data storage devices 310 is configured to transmit the read first data to one of the one or more second data storage devices 320 for decoding in response to a determination that a weaker ECC decoder 314 in the first data storage device 310 has not been able to correct the first data read from the corresponding first memory 312. Each of the one or more second data storage devices 320 is configured to decode the corresponding read data using one or more stronger ECC decoders 326 in the second data storage device 320 in response to receiving the corresponding read data from one of the one or more first data storage devices 310.

[0090] In some implementations, the system controller 302 may be configured to store a first type of data (e.g., hot data) in one or more first data storage devices 310 and a second type of data (e.g., cold data) in one or more second data storage devices 320. The first type of data may be data that is read more frequently than the second type of data. In this way, the data storage system 300 can reduce the total cost of ownership (TCO) because the first data storage devices 310 are much less expensive than the second data storage devices 320 and can be replaced more frequently than the second data storage devices 320.

[0091] Figure 4 is a schematic diagram of another example of a data storage system 400 that includes a system controller 402, which includes one or more external devices 420 having a stronger ECC decoder 422 for the data storage device 410. The data storage system 400 may be implemented as the data storage system 110 in Figure 1A.

[0092] Similar to the data storage system 200 in Figure 2, each of the data storage devices 410 may be the data storage device 160 in Figure 1C, the data storage device 210 in Figure 2, or the first data storage device 310 in Figure 3. The data storage device 410 may include only one or more weaker ECC decoders 414 (e.g., the first ECC decoder 154 in Figure 1B or Figure 1C, 214 in Figure 2, or 314 in Figure 3). Each of the one or more external devices 420 may be the external device 170 in Figure 1D or 220 in Figure 2, and may include only one or more stronger ECC decoders 422 (e.g., the second ECC decoder 156 in Figure 1B or Figure 1D, 222 in Figure 2, or 326 in Figure 3). If a weaker ECC decoder 414 within the data storage device 410 is unable to decode the data read from one or more memories 412 (for example, memory 152 in Figure 1B or Figure 1C, 212 in Figure 2, or 312 or 322 in Figure 3), the data storage device 410 can transmit the read data to one or more external devices 420 for decoding the data up to the ECC function level using one or more stronger ECC decoders 422.

[0093] Unlike the data storage system 200 in Figure 2, where one or more external devices 220 are located outside the system controller 202, in the data storage system 400, one or more external devices 420 may be included within the system controller 402. The number of one or more external devices 420 may be increased to improve the overall read performance of the data storage system 400.

[0094] Figure 5 is a flowchart of an exemplary process 500 for managing error correction within a data storage system. The data storage system may be data storage system 110 in Figure 1A, data storage system 200 in Figure 2, data storage system 300 in Figure 3, or data storage system 400 in Figure 4. The data storage system may include a system controller and one or more data storage devices. The system controller may be, for example, system controller 112 in Figure 1A, system controller 202 in Figure 2, system controller 302 in Figure 3, or system controller 402 in Figure 4. The data storage devices may be, for example, data storage device 130 in Figure 1A, data storage device 150 in Figure 1B, data storage device 160 in Figure 1C, data storage device 210 in Figure 2, first data storage device 310 in Figure 3, second data storage device 320 in Figure 3, or data storage device 410 in Figure 4.

[0095] In step 502, the system controller receives a read request from the host device (for example, host device 120 in Figure 1A). The read request may be a read command to read data from one or more data storage devices in the data storage system. The system controller can transmit the read command to one or more data storage devices.

[0096] In step 504, in response to the data storage device receiving a read command from the system controller, the memory controller within the data storage device (e.g., memory controller 161 in Figure 1C) reads data from at least one memory within the data storage device (e.g., memory 152 in Figure 1C, memory 212 in Figure 2, memory 312 in Figure 3, or memory 412 in Figure 4). The memory controller may include at least one first ECC decoder, which may be a weaker ECC decoder (e.g., ECC decoder 154 in Figure 1B or Figure 1C, ECC decoder 214 in Figure 2, ECC decoder 314 in Figure 3, or ECC decoder 414 in Figure 1C).

[0097] In step 506, the memory controller performs a weaker ECC decoding within the data storage device using at least one first ECC decoder, and in step 508, determines whether the read data has passed the first ECC test. In some implementations, the memory controller performs an ECC decoding operation on the read data using at least one first ECC decoder. In some implementations, the memory controller includes a first ECC encoder configured to encode the data to produce first ECC data (e.g., ECC parity bits), and the memory controller can store the data with the first ECC data in at least one memory and read the data with the first ECC data from at least one memory. At least one first ECC decoder can decode the data read from at least one memory using the first ECC data.

[0098] The memory controller can determine whether the read data has passed the first ECC test by determining whether the number of error bits in the read data after the ECC decoding operation is less than a predetermined threshold. If the number of error bits is less than the predetermined threshold, the memory controller may determine that the read data has passed the first ECC test. If the number of error bits is the same as or greater than the predetermined threshold, the memory controller determines that the read data has not passed the first ECC test.

[0099] If the memory controller determines that the read data has passed the first ECC test, in step 510, the memory controller returns the corrected read data to the system controller, and the system controller transmits the corrected read data to the host device.

[0100] If the memory controller determines that the read data has not passed the first ECC test, in step 512, the memory controller determines, for example, by comparing the count counter with a predetermined number, whether the number of times the read data has failed the first ECC test is less than a predetermined threshold. If the count is less than the predetermined threshold, in step 514, the memory controller modifies one or more read parameters to read the data again from at least one memory, or performs soft decoding on the data (in step 504). Accordingly, the counter may be incremented by 1.

[0101] When the number of read operations reaches a predetermined threshold, the memory controller transmits the read data to an external device containing at least one second ECC decoder for stronger ECC decoding. The external device may be, for example, external device 170 in Figure 1D, external device 220 in Figure 2, second data storage device 320 in Figure 3, or external device 420 in Figure 4 within the system controller. The at least one second ECC decoder may be, for example, second ECC decoder 156 in Figure 1B, second ECC decoder 156 in Figure 1D, stronger ECC decoder 222 in Figure 2, stronger ECC decoder 326 in Figure 3, or stronger ECC decoder 422 in Figure 4. The at least one second ECC decoder in the external device may have stronger ECC capabilities than the at least one first ECC decoder in the data storage device.

[0102] In some implementations, in addition to or alternative to step 512, in response to a determination that the read data has failed the first ECC test, and before transmitting the read data to at least one second ECC decoder, the memory controller may, based on the result of the first ECC test, either i) modify one or more parameters to read data from at least one memory, or perform soft decoding on the data and re-run the first ECC test using at least one first ECC decoder, or ii) transmit the read data to an external device containing at least one second ECC decoder for decoding the read data. For example, if the result of the first ECC test indicates that the error bits in the read data are slightly above the capabilities of the first ECC decoder, the memory controller may decide to proceed with option i). If the result of the first ECC test indicates that the error bits are much greater than the capabilities of the first ECC decoder, the memory controller may decide to proceed with option ii).

[0103] In step 518, the external device performs stronger ECC decoding on the read data using at least one second ECC decoder, and in step 520, it determines whether the read data has passed the second ECC test. In some implementations, the external device performs the ECC decoding operation on the read data using at least one second ECC decoder. As described in further detail in Figures 6A, 6B, or 6C, at least one second ECC decoder can perform the ECC decoding operation on first ECC data generated by at least one first ECC decoder (e.g., shown in Figure 6A), or second ECC data generated based on data read using a second ECC encoder (e.g., shown in Figure 6B) in the external device or a data storage device, or second ECC data generated based on multiple data portions of data read from multiple data storage devices using a second ECC decoder in the external device (e.g., shown in Figure 6C).

[0104] An external device can determine whether the read data has passed the second ECC test by determining whether the number of error bits in the read data after the ECC decoding operation is less than a predetermined threshold. If the number of error bits is less than the predetermined threshold, the external device may determine that the read data has passed the second ECC test. If the number of error bits is the same as or greater than the predetermined threshold, the external device determines that the read data has not passed the second ECC test.

[0105] If the external device determines that the retrieved data has passed the second ECC test, in step 510, the external device returns the corrected retrieved data to the system controller, which then transmits the corrected retrieved data to the host device. In some implementations, the external device transmits the corrected retrieved data back to the data storage device.

[0106] If the external device determines that the retrieved data has not passed the second ECC test, in step 522, the external device determines, for example, whether the number of times the retrieved data has failed the second ECC test is less than a predetermined threshold by comparing the count counter with a predetermined number. If the count is less than the predetermined threshold, the external device may send a notification to the memory controller to either i) change one or more parameters to retrieve the data again from at least one memory, or ii) perform soft decoding on the data, as shown in step 514. The counter may be incremented by 1.

[0107] When the number of reads reaches a predetermined threshold, the external device can, in step 524, trigger a RAID (Independent Disk Redundancy Array) circuit to perform error correction on the read data for data recovery. For example, the external device can send a message to the system controller instructing it to trigger the RAID circuit, and the system controller can trigger the RAID circuit accordingly. In some implementations, the RAID circuit may be contained within the memory controller and configured to perform error correction on the data read from the data storage device. In some implementations, the RAID circuit may be contained within the system controller and configured to perform error correction on the data read from one or more data storage devices. The RAID circuit may be located in an accessory device (e.g., accessory device 140 in Figure 1A) outside the data storage device and the system controller.

[0108] In some implementations, in addition to or alternative to step 522, in response to a determination that the read data has failed the second ECC test, and before triggering the RAID circuit, the external device may, based on the results of the second ECC test, either i) modify one or more parameters to read data from at least one memory, or perform soft decoding on the data and re-run at least one of the first ECC test using at least one first ECC decoder or the second ECC test using at least one second ECC decoder, or ii) trigger the RAID circuit to perform error correction on the read data. For example, if the results of the second ECC test indicate that the error bits in the read data are slightly above the capacity of the second ECC decoder, the external device may decide to proceed with option i). If the results of the second ECC test indicate that the error bits in the read data are much greater than the capacity of the second ECC decoder, the external device may decide to proceed with option ii).

[0109] In some implementations, the system controller is configured to generate an alert message to discard a data storage device based on at least one of the results of a first ECC test using at least one first ECC decoder or a second ECC test using at least one second ECC decoder. For example, a data storage device may be designed to be inexpensive and to be discardable when it is difficult to correct the error bits by the first and / or second ECC decoders.

[0110] Figures 6A to 6C illustrate different examples of data encoding and data decoding within a data storage system implemented in this disclosure. The data storage system may be data storage system 110 in Figure 1A, data storage system 200 in Figure 2, data storage system 300 in Figure 3, or data storage system 400 in Figure 4. The data storage system may include a system controller and one or more data storage devices. The system controller may be, for example, system controller 112 in Figure 1A, system controller 202 in Figure 2, system controller 302 in Figure 3, or system controller 402 in Figure 4. The data storage devices may be, for example, data storage device 130 in Figure 1A, data storage device 150 in Figure 1B, data storage device 160 in Figure 1C, data storage device 210 in Figure 2, first data storage device 310 in Figure 3, second data storage device 320 in Figure 3, or data storage device 410 in Figure 4.

[0111] Figure 6A is a schematic diagram of an exemplary process 600 for encoding and decoding data 601 in a data storage system using the same ECC data for a weaker ECC decoder and a stronger ECC decoder, for example. The data storage device may include a memory controller and memory 604. The memory controller may be, for example, the memory controller 161 in Figure 1C. The memory controller may include an ECC encoder 602 and a weaker ECC decoder 606. The weaker ECC decoder 606 may be, for example, the ECC decoder 154 in Figure 1B or Figure 1C, the ECC decoder 214 in Figure 2, the ECC decoder 314 in Figure 3, or the ECC decoder 414 in Figure 1C.

[0112] The ECC encoder 602 can encode the data 601 to generate ECC data 603 (e.g., ECC parity bits). The memory controller can write the data 601 together with the ECC data 603 to memory 604. The data 601 together with the ECC data 603 can be read from memory 604, for example, in response to a read command from the system controller. The read data 605 may contain error bits.

[0113] As described above, the weaker ECC decoder 606 in the data storage device can first decode the read data 605 based on the ECC data 603. If the weaker ECC decoder 606 is unable to decode the read data 605, the memory controller can transmit the read data 605 and the ECC data 603 to an external device, which may include a stronger ECC decoder 608 having stronger ECC capabilities than the weaker ECC decoder 606. The external device may be, for example, the external device 170 in Figure 1D, the external device 220 in Figure 2, the second data storage device 320 in Figure 3, or the external device 420 in Figure 4 within the system controller. The stronger ECC decoder 608 may be, for example, the second ECC decoder 156 in Figure 1B, the second ECC decoder 156 in Figure 1D, the stronger ECC decoder 222 in Figure 2, the stronger ECC decoder 326 in Figure 3, or the stronger ECC decoder 422 in Figure 4. A stronger ECC decoder 608 can decode the read data 605 based on the ECC data 603 to generate corrected read data 609.

[0114] In some implementations, a bit-inverting-based LDPC decoder (as a low-power decoding mode) and a min-sum LDPC decoder (as a stronger decoding mode) are implemented as a pair of weaker ECC decoders 606 and stronger ECC decoders 608. As shown in Figure 6A, only one ECC encoder 602 is used for both modes, and ECC data 603 (e.g., ECC parity bits) is shared for both the weaker ECC decoder 606 and the stronger ECC decoder 608.

[0115] Figure 6B is a schematic diagram of another exemplary process 630 for encoding and decoding data within a data storage system. Unlike process 610 in Figure 6A, process 630 involves two different ECC data. In some implementations, the memory controller within the data storage device may include an internal ECC encoder 634 and an internal ECC decoder 638. An external device may include an external ECC encoder 632 and an external ECC decoder 640. In some implementations, the memory controller includes an internal ECC encoder 634, an external ECC encoder 632, and an internal ECC decoder 638, while the external device includes only an external ECC decoder 640. The internal ECC encoder 634 may correspond to the internal ECC decoder 638, while the external ECC encoder 632 may correspond to the external ECC decoder 640. The internal ECC decoder 638 is configured to decode data using ECC data generated by the internal ECC encoder 634, and the external ECC decoder 640 is configured to decode data using ECC data generated by the external ECC encoder 632.

[0116] The external device could be, for example, the external device 170 in Figure 1D, the external device 220 in Figure 2, the second data storage device 320 in Figure 3, or the external device 420 in Figure 4 within the system controller. The external ECC decoder 640 may have higher ECC capabilities than the internal ECC decoder 638. The internal ECC decoder 638 could be a weaker decoder, for example, the ECC decoder 154 in Figure 1B or Figure 1C, the ECC decoder 214 in Figure 2, the ECC decoder 314 in Figure 3, or the ECC decoder 414 in Figure 1C. The external ECC decoder 640 could be a stronger decoder, for example, the second ECC decoder 156 in Figure 1B, the second ECC decoder 156 in Figure 1D, the stronger ECC decoder 222 in Figure 2, the stronger ECC decoder 326 in Figure 3, or the stronger ECC decoder 422 in Figure 4.

[0117] The data 631 to be stored in the memory 636 of the data storage device can first be encoded by an external ECC encoder 632 to generate external ECC data 633 (e.g., external ECC parity bits). The external device can then transmit the data 631 together with the ECC data 633 to the data storage device. An internal ECC encoder 634 can encode the data 631 to generate internal ECC data 635 (e.g., internal ECC parity bits). The memory controller can store the data 631 together with the external ECC data 633 and the internal ECC data 635 in the memory 636 of the data storage device. The memory controller can store the internal ECC data 635 and the external ECC data in memory 636 as a concatenated code of the data 631. The internal ECC decoder 638 can cover most read requests, and a more robust external ECC decoder 640, at the cost of longer latency and higher power consumption, may rarely need to be used.

[0118] The memory controller can read data 631 from memory 636 along with external ECC data 633 and internal ECC data 635 to obtain read data 637, which may contain error bits. The memory controller can decode the read data 637 using an internal ECC decoder 638, as illustrated in Figure 5, for example. If the internal ECC decoder 638 successfully decodes the read data 637 using internal ECC data 635, the memory controller generates corrected read data 639. If the internal ECC decoder 638 fails to decode the read data 637 using internal ECC data 635, the memory controller can transmit the read data 637 and external ECC data 633 to an external device. Next, an external ECC decoder 640 in the external device can decode the read data 637 based on the external ECC data 633 to generate corrected read data 639.

[0119] Figure 6C is a schematic diagram of another exemplary process 650 for encoding and decoding data within a data storage system. Unlike process 630 in Figure 6B, process 650 involves storing multiple data portions of the data in multiple data storage devices within the data storage system.

[0120] In some implementations, each of the multiple data storage devices includes a memory controller (e.g., memory controller 161 in Figure 1C) and a corresponding memory 656. The memory controller within the data storage device may include an internal ECC encoder 654 and an internal ECC decoder 658. The external device may include an external ECC encoder 652 and an external ECC decoder 660. The internal ECC encoder 654 may correspond to the internal ECC decoder 658, while the external ECC encoder 652 may correspond to the external ECC decoder 660. The internal ECC decoder 658 is configured to decode data using ECC data generated by the internal ECC encoder 654, and the external ECC decoder 660 is configured to decode data using ECC data generated by the external ECC encoder 652.

[0121] The external device could be, for example, the external device 170 in Figure 1D, the external device 220 in Figure 2, the second data storage device 320 in Figure 3, or the external device 420 in Figure 4 within the system controller. The external ECC decoder 660 may have stronger ECC capabilities than the internal ECC decoder 658. The internal ECC decoder 658 could be a weaker decoder, for example, the ECC decoder 154 in Figure 1B or Figure 1C, the ECC decoder 214 in Figure 2, the ECC decoder 314 in Figure 3, or the ECC decoder 414 in Figure 1C. The external ECC decoder 660 could be a stronger ECC decoder, for example, the second ECC decoder 156 in Figure 1B, the second ECC decoder 156 in Figure 1D, the stronger ECC decoder 222 in Figure 2, the stronger ECC decoder 326 in Figure 3, or the stronger ECC decoder 422 in Figure 4.

[0122] Multiple data portions 651 of data stored in multiple data storage devices can first be encoded by an external ECC encoder 652 in the external device to generate external ECC data 653 (e.g., external ECC parity bits) for the multiple data portions 651 of the data. Next, each data portion 651 and the external ECC data 653 can be transmitted to the corresponding data storage device among the multiple data storage devices, for example, by the external device or by the system controller. An internal ECC encoder 654 in the corresponding data storage device can encode the data portion 651 to generate internal ECC data 655 (e.g., internal ECC parity bits) for the data portion 651. A memory controller in the corresponding data storage device can store the data portion 651 of the data, along with the internal ECC data 655 and the external ECC data 653, in the memory 656 of the corresponding data storage device.

[0123] The system controller, in response to receiving a read request from a host device (for example, host device 120 in Figure 1A), can transmit a read command to each of the multiple data storage devices. For each of the multiple data storage devices, the memory controller can read the corresponding data portion 651 of the data from memory 656 along with the corresponding internal ECC data 655 and external ECC data 653. The internal ECC decoder 658 first decodes the read corresponding data portion 657 based on the corresponding internal ECC data 655. If the internal ECC decoder 655 has successfully decoded the read corresponding data portion 657 using the internal ECC data 655, the memory controller generates a corrected read data portion 659. If the internal ECC decoder 658 has not been able to decode the read corresponding data portion 657 using the internal ECC data 655, the memory controller can transmit the read corresponding data portion 657 and external ECC data 653 to an external device. Next, the external ECC decoder 660 in the external device can decode the read-out corresponding data portion 657 based on the external ECC data 653 to generate a corrected read-out corresponding data portion 659.

[0124] In process 650, product code may be implemented using pairs of weaker and stronger ECC encoders and decoders. The two types of ECC encoders 652 and 654 generate two types of part bits: internal ECC data for corresponding data portions, and external ECC data for multiple data portions or the entire data. Both encoding and decoding of the external (stronger) ECC are performed by an external device. Both encoding and decoding of the internal (weaker or lower power) ECC are performed within a single data storage device. The internal ECC decoder can cover most read requests, and the stronger external ECC decoder, at the cost of longer latency and higher power consumption, may rarely need to be performed.

[0125] The disclosed examples and other examples may be implemented as one or more modules of computer program instructions encoded on a computer-readable medium for execution by one or more computer program products, for example, a data processing device, or for controlling the operation of a data processing device. The computer-readable medium may be a machine-readable storage device, a machine-readable storage board, a memory device, or one or more combinations thereof. The term “data processing device” encompasses all devices and machines for processing data, including, for example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, a device may include code that makes up an execution environment for the computer program, for example, processor firmware, a protocol stack, a database management system, an operating system, or code that constitutes one or more combinations thereof.

[0126] A system may encompass all devices, machines, and equipment that process data, including, for example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, a system may include code that creates the execution environment for the computer program, such as processor firmware, a protocol stack, a database management system, an operating system, or code that constitutes one or more of these.

[0127] A computer program (also known as a program, software, software application, script, or code) may be written in any form of programming language, including compiled or interpreted languages, and may be deployed as a standalone program or in any form, including modules, components, subroutines, or other units suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program may be stored in a single file dedicated to it, in part of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), or in multiple coordinated files (e.g., a file that stores one or more modules, subprograms, or code sections). A computer program may be deployed for execution on one computer, or on multiple computers located in one location or distributed across multiple locations and interconnected by a communication network.

[0128] The processes and logic flows described herein can be executed by one or more programmable processors that run one or more computer programs to perform the functions described herein. The processes and logic flows can also be executed by dedicated logic circuits, such as FPGAs (Field-Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits), and devices can be implemented as such.

[0129] Processors suitable for executing computer programs include, for example, both general-purpose and dedicated microprocessors, and any one or more processors of any type of digital computer. Generally, processors receive instructions and data from read-only memory or random-access memory or both. Essential elements of a computer may include a processor that executes instructions, and one or more memory devices that store instructions and data. Generally, a computer may also include one or more mass storage devices that store data, e.g., magnetic, magneto-optical, or optical disks, or may be operablely coupled to receive data from or transfer data to them, or both. However, a computer is not required to have such devices. Computer-readable media suitable for storing computer program instructions and data may include any form of non-volatile memory, medium, and memory device, for example, semiconductor memory devices, e.g., EPROM, EEPROM, flash memory devices, and magnetic disks. Processors and memory may be complemented by or incorporated into dedicated logic circuits.

[0130] While this specification may describe many specific examples, these should not be interpreted as limitations on the scope of the claimed invention or what can be claimed, but rather as descriptions of features specific to particular embodiments. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable partial combination. Furthermore, features described above as operating in a particular combination, and may even be initially claimed as such, but in some cases, one or more features from a claimed combination may be removed from that combination, and the claimed combination may cover a partial combination or a variation of a partial combination. Similarly, while the drawings show each operation in a particular order, this should not be interpreted as requiring that such operations be performed in the specific order or sequence shown, or that all shown operations be performed, in order to achieve the desired result.

[0131] Only a few examples and implementations are disclosed. Variations, modifications, and enhancements to the described examples and implementations, as well as other implementations, may be made based on what is disclosed.

Claims

1. One or more data storage devices; and System controller coupled to the one or more data storage devices Equipped with, The one or more data storage devices include a data storage device comprising at least one memory and a memory controller coupled to the at least one memory, the memory controller comprising at least one first error correction code (ECC) decoder, Here, the memory controller is Reading data from at least one of the aforementioned memories, Using the at least one first ECC decoder, perform a first ECC test on the data read out, and In response to a determination that the read data has failed the first ECC test, the read data is transmitted to an external device that includes at least one second ECC decoder for decoding the read data. It is configured to do the following: Here, the external device is located outside the data storage device, the at least one second ECC decoder has ECC performance equal to or higher than a specified threshold, and the at least one first ECC decoder has ECC performance lower than the specified threshold. Data storage block.

2. The aforementioned memory controller In response to the determination that the read data has failed the first ECC test, and before transmitting the read data to the external device, it is determined whether the number of times the read data has failed the first ECC test is less than a predetermined threshold. If the number of times is less than the predetermined threshold, change one or more read parameters to read the data again from at least one memory, or perform soft decoding on the data, and If the number of times reaches the predetermined threshold, the read data is transmitted to the external device which includes at least one second ECC decoder for decoding the read data. It is configured to do, The data storage system according to claim 1.

3. The aforementioned memory controller In response to the determination that the read data has not passed the first ECC test, and before transmitting the read data to the at least one second ECC decoder, Based on the results of the first ECC test, i) Modifying one or more parameters to read the data from the at least one memory, or performing soft decoding on the data and performing the first ECC test again using the at least one first ECC decoder, or ii) Transmitting the read data to the external device which includes the at least one second ECC decoder for decoding the read data. one of the two It is configured to perform The data storage system according to claim 1.

4. The aforementioned external device is Using the at least one second ECC decoder, perform a second ECC test on the read data, and In response to the determination that the read data has passed the second ECC test, the corrected read data is transmitted to the system controller. It is configured to do, The data storage system according to claim 1.

5. The aforementioned external device is In response to the determination that the read data has not passed the second ECC test, it is determined whether the number of times the read data has not passed the second ECC test is less than a predetermined threshold. If the number of times is less than the predetermined threshold, a notification is transmitted to the memory controller to i) change one or more parameters to read the data from at least one memory, or ii) perform soft decoding on the data, and If the number of times reaches the predetermined threshold, the RAID (Independent Disk Redundancy Array) circuit is triggered to perform error correction on the read data. It is configured to do, The data storage system according to claim 4.

6. The aforementioned external device is In response to the determination that the read data has failed the second ECC test, and before triggering the RAID circuit, Based on the results of the second ECC test, i) Modifying one or more parameters to read the data from the at least one memory, or performing soft decoding on the data, and again performing at least one of the first ECC test using the at least one first ECC decoder or the second ECC test using the at least one second ECC decoder, or ii) Triggering the RAID circuit to perform error correction on the read data. one of the two It is configured to perform The data storage system according to claim 4.

7. The aforementioned memory controller Using the at least one first ECC decoder, perform an ECC decoding operation on the read data; Determining whether the number of error bits in the data read after the ECC decoding operation is less than a predetermined threshold; If the number of error bits is less than the predetermined threshold, it is determined that the read data has passed the first ECC test; and If the number of error bits is the same as or greater than the predetermined threshold, it is determined that the read data has not passed the first ECC test. It is configured to do, The data storage system according to claim 1.

8. The one or more data storage devices are One or more first data storage devices, each containing only one or more first ECC decoders, and One or more second data storage devices, each including one or more first ECC decoders and one or more second ECC decoders. Having, The data storage system according to claim 1.

9. The aforementioned system controller The first data is stored in one or more of the first data storage devices, and The second data is stored in one or more of the second data storage devices. It is configured to do, The data storage system according to claim 8.

10. The one or more first data storage devices and the one or more second data storage devices are configured to operate based on a protocol. Each of the one or more first data storage devices is configured to transmit the read first data to one of the one or more second data storage devices in response to a determination that the one or more first ECC decoders in the first data storage device have failed to correct the first data read from the corresponding first memory. Each of the one or more second data storage devices is configured to decode the corresponding read data using the one or more second ECC decoders in the second data storage device in response to receiving the corresponding read data from one of the one or more first data storage devices. The data storage system according to claim 8.

11. The data storage system according to claim 1, wherein the external device is included in the system controller.

12. The memory controller includes a first ECC encoder configured to encode the data and generate first ECC data, and the memory controller is configured to store the data together with the first ECC data in at least one memory. The at least one first ECC decoder is configured to decode the read data based on the first ECC data, and the at least one second ECC decoder is configured to decode the read data based on the first ECC data. The data storage system according to claim 1.

13. The memory controller includes a first ECC encoder configured to encode the data and generate first ECC data, and the external device includes a second ECC encoder configured to encode the data and generate second ECC data. The aforementioned memory controller The data is stored in the at least one memory together with the first ECC data and the second ECC data. Reading the aforementioned data together with the first ECC data and the second ECC data from at least one memory, In response to a determination that the read data has failed the first ECC test, the read data and the second ECC data are transmitted to the external device which includes at least one second ECC decoder. It is configured to do the following: The at least one first ECC decoder is configured to decode the read data based on the first ECC data, and the at least one second ECC decoder is configured to decode the read data based on the second ECC data received from the memory controller. The data storage system according to claim 1.

14. The system controller is configured to transmit multiple portions of specific data to multiple data storage devices of one or more data storage devices, respectively. Each of the plurality of data storage devices includes a first ECC encoder and one or more first ECC decoders, wherein the first ECC encoder is configured to encode a corresponding portion of the specific data to generate corresponding first ECC data. The external device includes a second ECC encoder configured to encode the plurality of portions of the specific data to generate second ECC data, Each of the plurality of data storage devices includes a memory controller configured to store the corresponding portion of the specific data together with the corresponding first ECC data and the second ECC data in the corresponding memory. For each of the plurality of data storage devices, the one or more first ECC decoders are configured to decode the corresponding portion of the specific data from the corresponding memory based on the corresponding first ECC data. The at least one second ECC decoder in the external device is configured to decode the portion of the specific data based on the second ECC data in response to receiving the portion of the specific data from one of the plurality of data storage devices and the second ECC data. The data storage system according to claim 1.

15. At least one memory; and A memory controller coupled to at least one of the aforementioned memories, A data storage device comprising, The memory controller has at least one first error correction code (ECC) decoder, Here, the memory controller is Reading data from at least one of the aforementioned memories, Using the at least one first ECC decoder, perform a first error correction code (ECC) test on the data read out, and In response to a determination that the read data has failed the first ECC test, the read data is transmitted to an external device that includes at least one second ECC decoder for decoding the read data. It is configured to do the following: Here, the external device is located outside the data storage device, the at least one second ECC decoder has ECC performance equal to or higher than a specified threshold, and the at least one first ECC decoder has ECC performance lower than the specified threshold. Data storage device.

16. The aforementioned memory controller In response to the determination that the read data has failed the first ECC test, and before transmitting the read data to the external device, it is determined whether the number of times the read data has failed the first ECC test is less than a predetermined threshold. If the number of times is less than the predetermined threshold, change one or more read parameters to read the data again from at least one memory, or perform soft decoding on the data, and If the number of times reaches the predetermined threshold, the read data is transmitted to the external device which includes at least one second ECC decoder for decoding the read data. It is configured to do, The data storage device according to claim 15.

17. At least one first error correction code (ECC) decoder externally coupled to at least one data storage device including at least one memory configured to store data. A device equipped with, The at least one data storage device includes at least one second ECC decoder, wherein the at least one first ECC decoder has ECC performance equal to or higher than a specified threshold, and the at least one second ECC decoder has ECC performance lower than the specified threshold. Here, the at least one first ECC decoder is In response to receiving the read data from the at least one data storage device, perform an ECC test on the read data using the at least one first ECC decoder, and In response to the determination that the read data has passed the ECC test, the corrected read data is generated for the at least one data storage device. It is configured to do, device.

18. The at least one second ECC decoder is configured to decode the read data based on the ECC data associated with the data stored in the at least one memory, The at least one first ECC decoder is configured to decode the read data based on the ECC data. The device according to claim 17.

19. The system further comprises a first ECC encoder configured to encode the aforementioned data to generate first ECC data and to transmit the first ECC data to the at least one data storage device. The at least one data storage device includes a second ECC encoder configured to encode the data and generate second ECC data, Here, the at least one data storage device is The data is stored in the at least one memory together with the first ECC data and the second ECC data. Reading the aforementioned data together with the first ECC data and the second ECC data from at least one memory, In response to a determination that the at least one second ECC decoder is unable to decode the read data based on the second ECC data, the read data and the first ECC data are transmitted to the at least one first ECC decoder. It is configured to do the following: The at least one first ECC decoder is In response to receiving the read data and the first ECC data from the at least one data storage device, the read data is decoded based on the first ECC data. It is configured to do, The device according to claim 17.

20. The data includes a plurality of parts, and the at least one data storage device includes a plurality of data storage devices configured to each store the plurality of parts. The device further comprises a first ECC encoder configured to encode the plurality of parts of the data to generate first ECC data and to transmit the first ECC data to each of the plurality of data storage devices. Each of the plurality of data storage devices includes a second ECC encoder configured to encode a corresponding portion of the data to generate a corresponding second ECC data, Each of the plurality of data storage devices is configured to store the corresponding portion of the data together with the corresponding second ECC data and the first ECC data in the corresponding memory. The at least one first ECC decoder is configured to decode the portion of the data based on the first ECC data in response to receiving a portion of the data from one of the plurality of data storage devices and the first ECC data. The device according to claim 17.

Images