Display device and method for manufacturing the same

Abstract

To provide a display device and a method of manufacturing the same capable of suppressing reduction in reliability.SOLUTION: A display device according to one embodiment comprises: a lower electrode; a rib that covers a part of the lower electrode, having an opening overlapped with the lower electrode; a barrier arranged on the rib; an upper electrode opposed to the lower electrode while being in contact with the barrier; an organic layer located between the lower and upper electrodes, emitting light depending on a potential difference between the lower and upper electrodes; and an encapsulation layer located on the upper electrode. The barrier has: a lower part arranged on the rib; and an upper part arranged on the lower part, having an end part protruding from a lateral face of the lower part. The upper part is formed of a material having light transmissivity and different from a material of the encapsulation layer.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device and a method for manufacturing the same.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. This display element includes a lower electrode, an organic layer covering the lower electrode, and an upper electrode covering the organic layer.

[0003] In the process of manufacturing the above display device, a technique for suppressing a decrease in reliability is required.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0005] An object of the present invention is to provide a display device capable of suppressing a decrease in reliability and a method for manufacturing the same.

Means for Solving the Problems

[0006] A display device according to one embodiment includes a lower electrode, a rib that covers a portion of the lower electrode and has an opening that overlaps with the lower electrode, a partition wall disposed on the rib, an upper electrode that faces the lower electrode and contacts the partition wall, an organic layer located between the lower electrode and the upper electrode that emits light in accordance with the potential difference between the lower electrode and the upper electrode, and a sealing layer located on the upper electrode. The partition wall has a lower part disposed on the rib and an upper part disposed on the lower part and having an end that protrudes from the side surface of the lower part. The upper part is translucent and is made of a different material from the sealing layer. The lower part includes a barrier layer disposed on the rib and a metal layer disposed on the barrier layer.

[0007] In a method for manufacturing a display device according to one embodiment, a lower electrode is formed, a rib is formed that covers at least a part of the lower electrode, and a lower part is placed on the rib, For light with a wavelength of 436 nm, or light with a wavelength of 405 nm A partition wall is formed, which has light-transmitting properties and includes an upper part that protrudes from the lower side surface; an organic layer is formed on the lower electrode; an upper electrode is formed on the organic layer in contact with the partition wall; a sealing layer is formed on the upper electrode using a material different from the upper part; and a resist is formed on the sealing layer. Using light with a wavelength of 436 nm or light with a wavelength of 405 nm The resist is exposed to light, the exposed portion of the resist is removed, and the portion of the organic layer, the upper electrode, and the sealing layer exposed from the resist is removed by etching using the resist from which the exposed portion has been removed as a mask. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows an example of the configuration of a display device according to one embodiment. [Figure 2] Figure 2 shows an example of a sub-pixel layout. [Figure 3] Figure 3 is a schematic cross-sectional view of the display device along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic cross-sectional view of the partition wall. [Figure 5] Figure 5 is an example of a schematic cross-sectional view showing an enlarged portion of the partition wall. [Figure 6]FIG. 6 is a schematic cross-sectional view showing a manufacturing process for forming a partition wall. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a manufacturing process following FIG. 6. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a manufacturing process following FIG. 7. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a manufacturing process following FIG. 8. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a manufacturing process following FIG. 9. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a manufacturing process for forming a display element. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing process following FIG. 11. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a manufacturing process following FIG. 12. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a manufacturing process following FIG. 13. [Figure 15] FIG. 15 is a schematic cross-sectional view showing another example of a structure applicable to a partition wall. [Figure 16] FIG. 16 is a schematic cross-sectional view showing still another example of a structure applicable to a partition wall. [Figure 17] FIG. 17 is a schematic cross-sectional view showing another example of a manufacturing process of a partition wall. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a manufacturing method of a display device according to a comparative example. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a manufacturing process following FIG. 18. [Figure 20] FIG. 20 is a table showing Examples 1 to 4. [Figure 21] FIG. 21 is a table showing Examples 5 to 8.

DETAILED DESCRIPTION OF THE INVENTION

[0009] One embodiment will be described with reference to the drawings. The disclosure is merely an example, and any modifications that a person skilled in the art could easily conceive of while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part in order to clarify the explanation, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, the same reference numerals are used for components that perform the same or similar functions as those described above with respect to previously shown drawings, and redundant detailed explanations may be omitted as appropriate.

[0010] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X axis will be referred to as the first direction, the direction along the Y axis as the second direction, and the direction along the Z axis as the third direction. Viewing the various elements parallel to the third direction Z is called a plan view.

[0011] The display device according to this embodiment is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted in televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and the like.

[0012] Figure 1 shows an example configuration of a display device DSP according to this embodiment. The display device DSP has a display area DA for displaying an image and a peripheral area SA around the display area DA on an insulating substrate 10. The substrate 10 may be glass or a flexible resin film.

[0013] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to a rectangle; it may be a square, a circle, an ellipse, or other shape.

[0014] The display area DA comprises multiple pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes multiple sub-pixels SP. In one example, pixel PX includes a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. Pixel PX may also include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of SP1, SP2, or SP3.

[0015] The sub-pixel SP comprises a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0016] The gate electrode of pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to the power line PL and capacitor 4, and the other is connected to display element 20.

[0017] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0018] The display element 20 is an organic light-emitting diode (OLED) as a light-emitting element. For example, sub-pixel SP1 is equipped with a display element 20 that emits light in the red wavelength range, sub-pixel SP2 is equipped with a display element 20 that emits light in the green wavelength range, and sub-pixel SP3 is equipped with a display element 20 that emits light in the blue wavelength range.

[0019] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 2, sub-pixels SP1 and SP2 are aligned in the second direction Y. Furthermore, sub-pixels SP1 and SP2 are aligned with sub-pixel SP3 in the first direction X.

[0020] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP1 and SP2 are alternately arranged in the second direction Y, and columns in which multiple sub-pixels SP3 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0021] Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2. Another example is that the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged sequentially in the first direction X.

[0022] The display area DA has ribs 5 and partition walls 6. Ribs 5 have apertures AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. In the example in Figure 2, aperture AP2 is larger than aperture AP1, and aperture AP3 is larger than aperture AP2.

[0023] The partition wall 6 is positioned at the boundary between adjacent subpixels SP and overlaps with the rib 5 in a plan view. The partition wall 6 has a plurality of first partition walls 6x extending in the first direction X and a plurality of second partition walls 6y extending in the second direction Y. The plurality of first partition walls 6x are positioned between adjacent apertures AP1 and AP2 in the second direction Y, and between two adjacent apertures AP3 in the second direction Y. The second partition walls 6y are positioned between adjacent apertures AP1 and AP3 in the first direction X, and between adjacent apertures AP2 and AP3 in the first direction X.

[0024] In the example shown in Figure 2, the first partition wall 6x and the second partition wall 6y are connected to each other. As a result, the partition wall 6 as a whole forms a grid that surrounds the openings AP1, AP2, and AP3. It can also be said that the partition wall 6, like the rib 5, has openings in the sub-pixels SP1, SP2, and SP3.

[0025] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with aperture AP3. In the example in Figure 2, the outer shapes of upper electrode UE1 and organic layer OR1 match, upper electrode UE2 and organic layer OR2 match, and upper electrode UE3 and organic layer OR3 match.

[0026] The lower electrode LE1, upper electrode UE1, and organic layer OR1 constitute the display element 20 of the sub-pixel SP1. The lower electrode LE2, upper electrode UE2, and organic layer OR2 constitute the display element 20 of the sub-pixel SP2. The lower electrode LE3, upper electrode UE3, and organic layer OR3 constitute the display element 20 of the sub-pixel SP3.

[0027] The lower electrode LE1 is connected to the pixel circuit 1 of the sub-pixel SP1 (see Figure 1) through the contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the sub-pixel SP2 through the contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the sub-pixel SP3 through the contact hole CH3.

[0028] In the example in Figure 2, contact holes CH1 and CH2 completely overlap with the first partition wall 6x between adjacent openings AP1 and AP2 in the second direction Y. Contact hole CH3 completely overlaps with the first partition wall 6x between two adjacent openings AP3 in the second direction Y. In another example, at least a portion of contact holes CH1, CH2, and CH3 may not overlap with the first partition wall 6x.

[0029] In the example shown in Figure 2, the lower electrodes LE1 and LE2 each have protrusions PR1 and PR2. Protrusion PR1 extends from the main body of the lower electrode LE1 (the part overlapping with the opening AP1) toward the contact hole CH1. Protrusion PR2 extends from the main body of the lower electrode LE2 (the part overlapping with the opening AP2) toward the contact hole CH2. The contact holes CH1 and CH2 overlap with the protrusions PR1 and PR2, respectively.

[0030] Figure 3 is a schematic cross-sectional view of the display device DSP along the line III-III in Figure 2. A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring, such as the pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1. The circuit layer 11 is covered by an insulating layer 12. The insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11. Although not shown in the cross-section of Figure 3, the contact holes CH1, CH2, and CH3 described above are provided in the insulating layer 12.

[0031] The lower electrodes LE1, LE2, and LE3 are positioned on the insulating layer 12. The rib 5 is positioned on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5.

[0032] The bulkhead 6 includes a lower section 61 positioned on the rib 5 and an upper section 62 covering the upper surface of the lower section 61. The upper section 62 has a greater width than the lower section 61. As a result, in Figure 3, both ends of the upper section 62 protrude beyond the sides of the lower section 61. This shape of the bulkhead 6 can also be described as overhanging.

[0033] The organic layer OR1 shown in Figure 2 includes a first organic layer OR1a and a second organic layer OR1b, which are spaced apart from each other. Similarly, the upper electrode UE1 shown in Figure 2 also includes a first upper electrode UE1a and a second upper electrode UE1b, which are spaced apart from each other. As shown in Figure 3, the first organic layer OR1a contacts the lower electrode LE1 through the opening AP1 and covers a portion of the rib 5. The second organic layer OR1b is located above the upper part 62. The first upper electrode UE1a faces the lower electrode LE1 and covers the first organic layer OR1a. Furthermore, the first upper electrode UE1a contacts the side surface of the lower part 61. The second upper electrode UE1b is located above the partition wall 6 and covers the second organic layer OR1b.

[0034] The organic layer OR2 shown in Figure 2 includes a first organic layer OR2a and a second organic layer OR2b, which are spaced apart from each other. Similarly, the upper electrode UE2 shown in Figure 2 also includes a first upper electrode UE2a and a second upper electrode UE2b, which are spaced apart from each other. As shown in Figure 3, the first organic layer OR2a contacts the lower electrode LE2 through the opening AP2 and covers a portion of the rib 5. The second organic layer OR2b is located above the upper part 62. The first upper electrode UE2a faces the lower electrode LE2 and covers the first organic layer OR2a. Furthermore, the first upper electrode UE2a contacts the side surface of the lower part 61. The second upper electrode UE2b is located above the partition wall 6 and covers the second organic layer OR2b.

[0035] The organic layer OR3 shown in Figure 2 includes a first organic layer OR3a and a second organic layer OR3b, which are spaced apart from each other. Similarly, the upper electrode UE3 shown in Figure 2 also includes a first upper electrode UE3a and a second upper electrode UE3b, which are spaced apart from each other. As shown in Figure 3, the first organic layer OR3a contacts the lower electrode LE3 through the opening AP3 and covers a portion of the rib 5. The second organic layer OR3b is located above the upper part 62. The first upper electrode UE3a faces the lower electrode LE3 and covers the first organic layer OR3a. Furthermore, the first upper electrode UE3a contacts the side surface of the lower part 61. The second upper electrode UE3b is located above the partition wall 6 and covers the second organic layer OR3b.

[0036] In the example shown in Figure 3, the sub-pixels SP1, SP2, and SP3 include cap layers CP1, CP2, and CP3 for adjusting the optical properties of the light emitted by the light-emitting layers of the organic layers OR1, OR2, and OR3.

[0037] The cap layer CP1 includes a first cap layer CP1a and a second cap layer CP1b that are spaced apart from each other. The first cap layer CP1a is located at the opening AP1 and is positioned above the first upper electrode UE1a. The second cap layer CP1b is located above the partition wall 6 and is positioned above the second upper electrode UE1b.

[0038] The cap layer CP2 includes a first cap layer CP2a and a second cap layer CP2b that are spaced apart from each other. The first cap layer CP2a is located at the opening AP2 and is positioned above the first upper electrode UE2a. The second cap layer CP2b is located above the partition wall 6 and is positioned above the second upper electrode UE2b.

[0039] The cap layer CP3 includes a first cap layer CP3a and a second cap layer CP3b that are spaced apart from each other. The first cap layer CP3a is located at the opening AP3 and is positioned above the first upper electrode UE3a. The second cap layer CP3b is located above the partition wall 6 and is positioned above the second upper electrode UE3b.

[0040] Sub-pixels SP1, SP2, and SP3 are each provided with sealing layers SE1, SE2, and SE3. Sealing layer SE1 continuously covers each component of sub-pixel SP1, including the first cap layer CP1a, partition wall 6, and second cap layer CP1b. Sealing layer SE2 continuously covers each component of sub-pixel SP2, including the first cap layer CP2a, partition wall 6, and second cap layer CP2b. Sealing layer SE3 continuously covers each component of sub-pixel SP3, including the first cap layer CP3a, partition wall 6, and second cap layer CP3b.

[0041] In the example shown in Figure 3, the second organic layer OR1b, second upper electrode UE1b, second cap layer CP1b, and sealing layer SE1 on the partition wall 6 between sub-pixels SP1 and SP3 are separated from the second organic layer OR3b, second upper electrode UE3b, second cap layer CP3b, and sealing layer SE3 on the same partition wall 6. Similarly, the second organic layer OR2b, second upper electrode UE2b, second cap layer CP2b, and sealing layer SE2 on the partition wall 6 between sub-pixels SP2 and SP3 are separated from the second organic layer OR3b, second upper electrode UE3b, second cap layer CP3b, and sealing layer SE3 on the same partition wall 6.

[0042] The sealing layers SE1, SE2, and SE3 are covered by a resin layer 13. The resin layer 13 is covered by a sealing layer 14. Furthermore, the sealing layer 14 is covered by a resin layer 15.

[0043] The insulating layer 12 and the resin layers 13 and 15 are made of organic materials. The ribs 5 and the sealing layers 14, SE1, SE2, and SE3 are made of inorganic materials such as silicon nitride (SiN).

[0044] The lower part 61 of the partition wall 6 is conductive. The upper part 62 of the partition wall 6 may also be conductive. The lower electrodes LE1, LE2, and LE3 may be formed of a transparent conductive oxide such as ITO (IndiumTin Oxide), or they may have a layered structure of a metallic material such as silver (Ag) and a conductive oxide. The upper electrodes UE1, UE2, and UE3 are formed of a metallic material such as a magnesium-silver alloy (MgAg). The upper electrodes UE1, UE2, and UE3 may also be formed of a conductive oxide such as ITO.

[0045] When the potentials of the lower electrodes LE1, LE2, and LE3 are relatively higher than the potentials of the upper electrodes UE1, UE2, and UE3, the lower electrodes LE1, LE2, and LE3 correspond to the anodes, and the upper electrodes UE1, UE2, and UE3 correspond to the cathodes. Also, when the potentials of the upper electrodes UE1, UE2, and UE3 are relatively higher than the potentials of the lower electrodes LE1, LE2, and LE3, the upper electrodes UE1, UE2, and UE3 correspond to the anodes, and the lower electrodes LE1, LE2, and LE3 correspond to the cathodes.

[0046] The organic layers OR1, OR2, and OR3 include a pair of functional layers and an emissive layer disposed between these functional layers. As an example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in that order.

[0047] The cap layers CP1, CP2, and CP3 are formed, for example, by a multilayer structure of multiple transparent thin films. The multilayer structure may include thin films formed from inorganic materials and thin films formed from organic materials. Furthermore, these multiple thin films have different refractive indices. The materials of the thin films constituting the multilayer structure are different from the materials of the upper electrodes UE1, UE2, and UE3, and also different from the materials of the sealing layers SE1, SE2, and SE3. Note that the cap layers CP1, CP2, and CP3 may be omitted.

[0048] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the first upper electrodes UE1a, UE2a, and UE3a, which are in contact with the sides of the lower part 61. Pixel voltages are supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0049] When a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the first organic layer OR1a emits light in the red wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the first organic layer OR2a emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the first organic layer OR3a emits light in the blue wavelength range.

[0050] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0051] Figure 4 is a schematic enlarged cross-sectional view of the partition wall 6. In this figure, elements other than the rib 5, partition wall 6, insulating layer 12, and the pair of lower electrodes LE are omitted. The pair of lower electrodes LE correspond to any of the lower electrodes LE1, LE2, and LE3 described above. The first partition wall 6x and the second partition wall 6y described above have the same structure as partition wall 6 shown in Figure 4.

[0052] In the example shown in Figure 4, the lower part 61 of the partition wall 6 includes a barrier layer 600 placed on the rib 5 and a metal layer 610 placed on the barrier layer 600. The metal layer 610 is formed to be thicker than the barrier layer 600. The metal layer 610 may be a single layer or a laminated structure of different metal materials.

[0053] The upper part 62 is thinner than the lower part 61. In the example in Figure 4, the upper part 62 includes a first layer 621 placed on the metal layer 610 and a second layer 622 covering the first layer 621.

[0054] In the example shown in Figure 4, the width of the lower section 61 decreases as it approaches the upper section 62. That is, the sides 61a and 61b of the lower section 61 are inclined with respect to the third direction Z. The upper section 62 has an end 62a protruding from the side 61a and an end 62b protruding from the side 61b.

[0055] The amount of protrusion D from the sides 61a and 61b to the ends 62a and 62b is, for example, 2.0 μm or less. Here, the amount of protrusion D corresponds to the distance in the width direction (first direction X or second direction Y) of the partition wall 6 from the lower end (barrier layer 600) of the sides 61a and 61b to the ends 62a and 62b.

[0056] Figure 5 is an example of a schematic cross-sectional view showing an enlarged portion of the partition wall 6. In this figure, in addition to the partition wall 6, the rib 5, the lower electrode LE1, the first organic layer OR1a, the first upper electrode UE1a, the first cap layer CP1a, the second organic layer OR1b, the second upper electrode UE1b, and the second cap layer CP1b are shown.

[0057] As shown in Figure 5, the side surface 61a of the lower part 61 has fine irregularities. Alternatively, the side surface 61a is rough. These irregularities are formed, for example, on the surface of the metal layer 610 on the side surface 61a. From another point of view, at least a portion of the side surface 61a has a greater roughness than the upper surface of the metal layer 610 that is in contact with the first layer 621, the lower surface of the metal layer 610 that is in contact with the barrier layer 600, the upper surface of the barrier layer 600 that is in contact with this lower surface, or the upper surface of the rib 5.

[0058] The first upper electrode UE1a is in contact with a region of the side surface 61a that includes irregularities. This increases the contact area between the first upper electrode UE1a and the lower part 61, ensuring good electrical conductivity between the lower part 61 and the first upper electrode UE1a.

[0059] In Figure 5, we focused on the side surface 61a, but the side surface 61b also has similar irregularities. Furthermore, these irregularities ensure good conductivity between the first upper electrodes UE2a, UE3a and the lower part 61. Although Figure 5 shows an example where the side surface 61a has fine irregularities, the lower part 61 is not limited to this, and the side surfaces 61a and 61b of the lower part 61 may be smooth or flat. In this case as well, good conductivity can be ensured as long as the first upper electrode UE1a is formed by the manufacturing method described later.

[0060] Next, we will explain the manufacturing method of the DSP display device. Figures 6 to 10 are schematic cross-sectional views showing the process for forming the partition wall 6, which is the main step in the manufacturing method of the display device DSP. First, as shown in Figure 6, a circuit layer 11, an insulating layer 12, a lower electrode LE, and a rib 5 are formed in order on top of the substrate 10.

[0061] Next, as shown in Figure 7, a barrier layer 600a is formed to cover the rib 5 and the lower electrode LE, a metal layer 610a is formed on top of the barrier layer 600a, a first layer 621a is formed on top of the metal layer 610a, and a second layer 622a is formed on top of the first layer 621a. Sputtering can be used to form the barrier layer 600a, the metal layer 610a, the first layer 621a, and the second layer 622a.

[0062] Furthermore, as shown in Figure 7, a resist R1 is formed on the second layer 622a. The resist R1 is patterned to have the same shape as the partition wall 6 in a plan view.

[0063] Next, as shown in Figure 8, etching is performed using resist R1 as a mask, and the portion of the second layer 622a exposed from resist R1 is removed. This forms the second layer 622 with the shape shown in Figure 4. In the following explanation, the portion of the metal layer 610a exposed from resist R1 and the second layer 622 (the portion that does not overlap in the third direction Z) will be called the first portion P1. The portion of the metal layer 610a located below resist R1 and the second layer 622 will be called the second portion P2.

[0064] In this embodiment, two types of etching are performed on the metal layer 610a to form a metal layer 610 with the shape shown in Figure 4. Specifically, anisotropic dry etching as shown in Figure 9 and isotropic wet etching as shown in Figure 10 are performed.

[0065] As shown in Figure 9, in anisotropic dry etching, the portion of the first layer 621a exposed from the resist R1 and the second layer 622 is removed. This forms the upper part 62 including the first layer 621 and the second layer 622, which have the shape shown in Figure 4.

[0066] Furthermore, in anisotropic dry etching, the thickness of the first portion P1 is reduced. The first portion P1 may be completely removed, but in this case, contamination caused by the barrier layer 600a may occur in the chamber of the etching apparatus. Therefore, it is preferable to stop the anisotropic dry etching while a portion of the first portion P1 remains. In anisotropic dry etching, the second portion P2 located below the resist R1 is hardly removed.

[0067] In isotropic wet etching, as shown in Figure 10, a portion of the first part P1 remaining from anisotropic dry etching, and the barrier layer 600a beneath it, are removed. Furthermore, the width of the second part P2 is reduced by removing the portion of the second part P2 located below the ends 62a and 62b of the upper part 62. This forms the lower part 61, which includes the barrier layer 600 and the metal layer 610, as shown in Figure 4. The irregularities on the side surface 61a shown in Figure 5 are formed, for example, during isotropic wet etching.

[0068] The amount by which the width of the second portion P2 is reduced by isotropic wet etching can be changed according to the shape required for the partition wall 6. In one example, the width of the second portion P2 is reduced in isotropic wet etching so that the above-mentioned protrusion amount D is 2.0 μm or less.

[0069] After the partition wall 6 is completed through the processes shown in Figures 6 to 10, the resist R1 is removed. Furthermore, a process is carried out to form the display elements 20 on the sub-pixels SP1, SP2, and SP3.

[0070] Figures 11 to 14 are schematic cross-sectional views showing the process for manufacturing a display device DSP, mainly for forming the display element 20. The sub-pixels SPα, SPβ, and SPγ shown in these figures correspond to one of the sub-pixels SP1, SP2, and SP3.

[0071] As described above, after the partition wall 6 is formed, the organic layer OR, upper electrode UE, cap layer CP, and sealing layer SE are sequentially formed on the entire substrate by vapor deposition, as shown in Figure 11. The organic layer OR includes a light-emitting layer that emits light of a color corresponding to the sub-pixel SPα. The overhanging partition wall 6 divides the organic layer OR into a first organic layer ORa covering the lower electrode LE and a second organic layer ORb on the partition wall 6, the upper electrode UE into a first upper electrode UEa covering the first organic layer ORa and a second upper electrode UEb covering the second organic layer ORb, and the cap layer CP into a first cap layer CPa covering the first upper electrode UEa and a second cap layer CPb covering the second upper electrode UEb. The first upper electrode UEa is in contact with the lower part 61 of the partition wall 6. The sealing layer SE continuously covers the first cap layer CPa, the second cap layer CPb, and the partition wall 6.

[0072] Next, as shown in Figure 12, a resist R2 is formed on the sealing layer SE. The resist R2 is, for example, a positive-type photoresist.

[0073] Furthermore, the resist R2 is exposed using the photomask MSK. The photomask MSK overlaps with the sub-pixel SPα and a portion of the surrounding partition wall 6. Sub-pixels SPβ and SPγ are exposed from the photomask MSK and are subjected to exposure. For exposure, a light source with a wavelength of 436 nm (g-line) or 405 nm (h-line) is used, for example.

[0074] After exposure, as shown in Figure 13, the exposed portion of the resist R2 is removed by the developer. The resist R2 shown in Figure 13 covers the subpixel SPα. That is, the resist R2 is located directly above the first organic layer ORa, the first upper electrode UEa, and the first cap layer CPa located on the subpixel SPα. The resist R2 is also located directly above the portion of the second organic layer ORb, the second upper electrode UEb, and the second cap layer CPb on the partition wall 6 between the subpixels SPα and SPβ that is closer to the subpixel SPα. That is, at least a part of the partition wall 6 is exposed from the resist R2.

[0075] Furthermore, etching using the resist R2 as a mask removes the portions of the organic layer OR, upper electrode UE, cap layer CP, and sealing layer SE that are exposed from the resist R2, as shown in Figure 14. As a result, a display element 20 including the lower electrode LE, first organic layer ORa, first upper electrode UEa, and first cap layer CPa is formed in the sub-pixel SPα. On the other hand, the lower electrode LE is exposed in the sub-pixels SPβ and SPγ. This etching is a dry etching using an etching gas such as CF4 or CF6.

[0076] Subsequently, the resist R2 is removed, and the steps for forming the sub-pixels SPβ and SPγ display elements 20 are carried out in sequence. These steps are the same as those described above for the sub-pixel SPα.

[0077] By forming the sub-pixels SP1, SP2, and SP3 display elements 20 through the exemplified steps for the sub-pixels SPα, SPβ, and SPγ described above, and then forming the resin layer 13, sealing layer 14, and resin layer 15, the display device DSP shown in Figure 3 is completed.

[0078] The structure and manufacturing process of partition wall 6 are not limited to the examples shown in Figures 4 to 10. Figure 15 is a schematic cross-sectional view showing another example of a structure that can be applied to the partition wall 6. The partition wall 6 shown in this figure has a single-layer structure for the upper part 62. Also, the upper part 62 is thicker than the example shown in Figure 4. Furthermore, the width of the upper part 62 decreases as it goes upwards. That is, the sides of the upper part 62 at the ends 62a and 62b are tapered with respect to the third direction Z.

[0079] Figure 16 is a schematic cross-sectional view showing yet another example of a structure that can be applied to the partition wall 6. The partition wall 6 shown in this figure does not have a barrier layer 600; that is, the metal layer 610 is in contact with the rib 5.

[0080] Figure 17 is a schematic cross-sectional view showing another example of the manufacturing process for the partition wall 6. This process corresponds to the anisotropic dry etching shown in Figure 9. Depending on the etching conditions, the width of the resist R1 may be reduced during etching, as shown in Figure 17. Even in this case, damage to the upper layer 62 can be prevented, for example, by forming the second layer 622 with a material that is highly resistant to anisotropic dry etching.

[0081] Here, we will explain some of the requirements for partition wall 6. Figures 18 and 19 are schematic cross-sectional views showing a method for manufacturing a display device according to a comparative example. In Figure 18, as in the example in Figure 13, the exposed and developed resist R2 is placed on the sub-pixel SPα.

[0082] If the light used to expose the resist R2 is blocked by the upper part 62 of the partition wall 6, the resist R2 located below the upper part 62 will not be illuminated by that light. If development is performed in this case, an unexposed portion R2a of the resist R2 will remain below the upper part 62.

[0083] If etching is performed in the same manner as in Figure 14 with the unexposed portion R2a present, the sealing layer SE covered by the unexposed portion R2a will not be removed, resulting in residual SEa as shown in Figure 19. Since this residual SEa remains even after the resist R2 and the unexposed portion R2a are removed, it may hinder the normal formation of the sub-pixels SPβ and SPγ of the display elements 20. For example, if the side surface of the lower part 61 is covered with residual SEa, the upper electrode UE of the sub-pixels SPβ and SPγ may not make contact with the lower part 61.

[0084] Silicon nitride absorbs the i-line (365 nm) as described above. Therefore, even when the sealing layer SE is formed of silicon nitride and only the i-line is used for the exposure described above, a residue SEa similar to that shown in Figure 19 may be generated.

[0085] In order to suppress the generation of such residue SEa, in this embodiment, the upper part 62 is transparent to light (at least g-line or h-line) used for exposure of the resist R2.

[0086] Furthermore, in order to improve the reliability of the display device DSP, it is necessary to form the display element 20 after forming a well-formed overhang-shaped partition wall 6. In other words, if there is a distortion in the shape of at least a part of the partition wall 6, for example, if the amount of protrusion D of the upper part 62 is small, there will be places where the organic layers OR1, OR2, OR3 and the upper electrodes UE1, UE2, UE3 are not separated by the partition wall 6, and the structure shown in Figure 3 cannot be obtained.

[0087] Even if the partition wall 6 is formed well through the processes shown in Figures 6 to 10, it may disappear or deform in subsequent processes. For example, in the etching process shown in Figure 14, at least a part of the partition wall 6 is exposed, so if the partition wall 6 is formed from a material with low resistance to etching, the partition wall 6 may be damaged. Therefore, it is preferable that at least the upper part 62 be formed from a material different from the sealing layer SE, specifically from a material with higher etching selectivity compared to the sealing layer SE during the etching process.

[0088] Furthermore, in order to obtain a shape in which the lower part 61 is well constricted, it is preferable to form the metal layer 610 with a material that is easily removed by isotropic wet etching as shown in Figure 10.

[0089] The structure of the partition wall 6 and the materials of each part of the partition wall 6 are selected considering these various reasons. Examples of the structure of the partition wall 6 and the materials of each part are disclosed below.

[0090] Figure 20 is a table showing Examples 1 to 4. The partition wall 6 in Examples 1 to 3 all have a barrier layer 600, a metal layer 610, a first layer 621, and a second layer 622. On the other hand, the partition wall 6 in Example 4 has a metal layer 610, a first layer 621, and a second layer 622, but does not have a barrier layer 600.

[0091] In all of Examples 1 to 4, the metal layer 610 is formed of aluminum (Al), the first layer 621 is formed of silicon oxide (SiO), and the second layer 622 is formed of ITO. In Example 1, the barrier layer 600 is formed of molybdenum (Mo), in Example 2, the barrier layer 600 is formed of molybdenum-tungsten alloy (MoW), and in Example 3, the barrier layer 600 is formed of copper (Cu). The metal layer 610 may also be formed of an aluminum alloy.

[0092] When the upper part 62 has a layered structure of silicon oxide and ITO, the overall thickness of the upper part 62 is preferably, for example, 50 to 300 nm. The overall thickness of the lower part 61 is preferably, for example, 400 to 1500 nm.

[0093] In all of Examples 1 to 4, the thickness of the first layer 621 is 100 nm, and the thickness of the second layer 622 is 50 nm. That is, the second layer 622 is thinner than the first layer 621. The thickness of the metal layer 610 is 950 nm in Examples 1 and 3, 800 nm in Example 2, and 1000 nm in Example 4. The thickness of the barrier layer 600 is 50 nm in Examples 1 and 3, and 200 nm in Example 2.

[0094] In each of Examples 1 to 4, the second layer 622 may be formed from a conductive oxide other than ITO. Examples of such conductive oxides include IZO (Indium Zinc Oxide) and IGZO (Indium Gallium Zinc Oxide).

[0095] Figure 21 is a table showing Examples 5 to 8. The partition wall 6 in Examples 5 to 8 all have an aluminum metal layer 610 and an upper part 62 which is a single-layer structure of silicon oxide. The metal layer 610 may be formed of an aluminum alloy. The partition wall 6 in Examples 5 to 7 has a barrier layer 600, while the partition wall 6 in Example 8 does not have a barrier layer 600. The barrier layer 600 in Example 5 is made of molybdenum, the barrier layer 600 in Example 6 is made of a molybdenum-tungsten alloy, and the barrier layer 600 in Example 7 is made of copper.

[0096] Even when the upper part 62 has a single-layer structure of silicon oxide, the thickness of the upper part 62 is preferably, for example, 50 to 300 nm. Furthermore, the overall thickness of the lower part 61 is preferably, for example, 400 to 1500 nm.

[0097] In all of Examples 5 to 8, the thickness of the upper layer 62 is 250 nm. The thickness of the metal layer 610 is 950 nm in Examples 5 and 7, 800 nm in Example 6, and 1000 nm in Example 8. The thickness of the barrier layer 600 is 50 nm in Examples 5 and 7, and 200 nm in Example 6.

[0098] In Examples 1 to 8 described above, the conductive oxide and silicon oxide forming the upper part 62 have good light transmission with respect to the g-line at a wavelength of 436 nm or the h-line at a wavelength of 405 nm. Therefore, when patterning the resist R2 as described above, it is possible to expose the portion of the resist R2 located below the upper part 62, and the generation of unexposed portions R2a and residue SEa, as explained using Figures 18 and 19, can be suppressed.

[0099] Furthermore, conductive oxides and silicon oxides exhibit a lower etching rate in the etching process shown in Figure 14 compared to the sealing layer SE formed from silicon nitride. In other words, by forming the upper section 62 using these materials, damage to the partition wall 6 during etching can be suppressed.

[0100] In particular, conductive oxides such as ITO, IZO, and IGZO have high resistance to dry etching using etching gases such as CF4 and SF6. Therefore, by using these conductive oxides as the second layer 622, which is the surface layer of the upper layer 62, damage to the upper layer 62 can be effectively suppressed.

[0101] If the upper layer 62 is thick, the area cast by the upper layer 62 will increase when forming the organic layer OR (OR1, OR2, OR3), upper electrode UE (UE1, UE2, UE3), and cap layer CP (CP1, CP2, CP3) by vapor deposition. In this case, it will not be possible to form the organic layer OR, upper electrode UE, and cap layer CP of sufficient thickness near the partition wall 6. In contrast, when a conductive oxide is used for the second layer 622, as described above, etching damage is suppressed, making it possible to form the upper layer 62 thinner. This makes it possible to narrow the area cast by the vapor deposition source.

[0102] Furthermore, if the upper part 62 is relatively thick, as in Examples 5-8, the area cast by the vapor deposition source can be narrowed by making the ends 62a and 62b of the upper part 62 tapered, as shown in Figure 15.

[0103] Furthermore, conductive oxides such as ITO have high resistance to anisotropic dry etching, as shown in Figure 9. Therefore, when a conductive oxide is used for the upper part 62, the upper part 62 is less likely to be damaged even if the width of the resist R1 is reduced during anisotropic dry etching, as explained using Figure 17.

[0104] The aluminum and aluminum alloys exemplified as materials for the metal layer 610 in Examples 1 to 8 are easily reduced in width during isotropic wet etching as shown in Figure 10. Therefore, the formation of overhanging partition walls 6 is facilitated. Furthermore, because aluminum and aluminum alloys have low internal stress during formation, it is possible to create thick films of, for example, 500 nm or more.

[0105] When the lower part 61 has a barrier layer 600 made of molybdenum, molybdenum-tungsten alloy, or copper, as in Examples 1-3 and 5-7, damage to the rib 5 can be suppressed in the isotropic wet etching shown in Figure 10.

[0106] For example, in the peripheral region SA, the lower part 61 is connected to the power supply section. This power supply section may be formed from the same material as the lower electrodes LE (LE1, LE2, LE3), in which case the surface layer of the power supply section may be made of ITO. If the lower part 61 does not have a barrier layer 600, the aluminum metal layer 610 and the ITO will be in contact. However, in a structure where aluminum and ITO are in contact, problems such as high resistance at the interface and galvanic corrosion may occur. In contrast, if the lower part 61 has a barrier layer 600 made of molybdenum, molybdenum-tungsten alloy, or copper, even if the lower part 61 and ITO are in contact, the above-mentioned high resistance and galvanic corrosion will be suppressed.

[0107] Molybdenum alloys, such as molybdenum-tungsten alloys, exhibit low internal stress during formation. Therefore, it is possible to increase the thickness of the barrier layer 600 compared to, for example, forming the barrier layer 600 with molybdenum.

[0108] Due to the various effects illustrated here, the configurations disclosed in this embodiment and each example provide a highly reliable display device DSP and a method for manufacturing the same.

[0109] All display devices and manufacturing methods that a person skilled in the art can implement by appropriately modifying the design based on the display device and manufacturing method described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0110] Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, any modifications made by a person skilled in the art to add, delete, or change the design of any of the above-described embodiments, or to add, omit, or change the conditions of any process, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0111] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0112] DSP...Display device, DA...Display area, SA...Peripheral area, PX...Pixel, SP(SP1,SP2,SP3)...Sub-pixel, LE(LE1,LE2,LE3)...Lower electrode, UE(UE1,UE2,UE3)...Upper electrode, OR(OR1,OR2,OR3)...Organic layer, SE(SE1,SE2,SE3)...Sealing layer, 1...Pixel circuit, 5...Rib, 6...Partition, 10...Substrate, 12...Insulating layer, 61...Lower part of partition, 62...Upper part of partition, 600...Barrier layer, 610...Metal layer, 621...First layer, 622...Second layer.

Claims

1. The lower electrode and A rib that covers a portion of the lower electrode and has an opening that overlaps with the lower electrode, A partition wall positioned above the rib, An upper electrode facing the lower electrode and in contact with the partition wall, An organic layer located between the lower electrode and the upper electrode, which emits light in accordance with the potential difference between the lower electrode and the upper electrode, The upper electrode comprises a sealing layer located on the upper electrode, The partition wall has a lower part positioned on the rib and an upper part positioned on the lower part and having an end that protrudes from the side surface of the lower part. The upper part is translucent and is formed of a different material from the sealing layer. The lower part includes a barrier layer disposed on the rib and a metal layer disposed on the barrier layer. Display device.

2. The lower electrode and A rib that covers a portion of the lower electrode and has an opening that overlaps with the lower electrode, A partition wall positioned above the rib, An upper electrode facing the lower electrode and in contact with the partition wall, An organic layer located between the lower electrode and the upper electrode, which emits light in accordance with the potential difference between the lower electrode and the upper electrode, The upper electrode comprises a sealing layer located on the upper electrode, The partition wall has a lower part positioned on the rib and an upper part positioned on the lower part and having an end that protrudes from the side surface of the lower part. The upper part is translucent and is formed of a different material from the sealing layer. The lower side surface has an uneven surface. Display device.

3. The upper part has light transmittance to light with a wavelength of 436 nm or light with a wavelength of 405 nm. The display device according to claim 1 or 2.

4. The upper part includes a first layer made of silicon oxide and a second layer made of conductive oxide. The display device according to any one of claims 1 to 3.

5. The second layer covers the first layer. The display device according to claim 4.

6. The second layer is thinner than the first layer. The display device according to claim 4 or 5.

7. The conductive oxide forming the second layer is ITO, IZO, or IGZO. The display device according to any one of claims 4 to 6.

8. The upper part has a single-layer structure of silicon oxide. The display device according to any one of claims 1 to 3.

9. The lower part includes aluminum, The display device according to any one of claims 1 to 8.

10. The barrier layer is formed of molybdenum, a molybdenum-tungsten alloy, or copper. The display device according to claim 1.

11. The sealing layer is formed of silicon nitride. The display device according to any one of claims 1 to 10.

12. Form the lower electrode, A rib is formed to cover at least a portion of the lower electrode, A partition wall is formed, comprising a lower portion positioned on the rib and an upper portion that is transparent to light with a wavelength of 436 nm or light with a wavelength of 405 nm and protrudes from the side surface of the lower portion. An organelle is formed on the lower electrode, An upper electrode in contact with the partition wall is formed on the organic layer. A sealing layer is formed on the upper electrode using a material different from the upper part. A resist is formed on the aforementioned sealing layer. The resist is exposed using light with a wavelength of 436 nm or light with a wavelength of 405 nm. The exposed portion of the resist is removed, By etching using the resist from which the exposed portion has been removed as a mask, the portions of the organic layer, the upper electrode, and the sealing layer that are exposed from the resist are removed. A method for manufacturing a display device.

13. The upper part includes a first layer made of silicon oxide and a second layer made of conductive oxide. A method for manufacturing a display device according to claim 12.

14. The upper part has a single-layer structure of silicon oxide. A method for manufacturing a display device according to claim 12 or 13.

15. The sealing layer is formed of silicon nitride. A method for manufacturing a display device according to any one of claims 12 to 14.

16. A metal layer is formed on the aforementioned rib, The upper part is formed on the metal layer, The thickness of the first portion of the metal layer exposed from the upper part is reduced by anisotropic etching. The lower part is formed by reducing the width of the second portion of the metal layer located below the upper part by isotropic etching. A method for manufacturing a display device according to any one of claims 12 to 15.

Images