Display device and method for manufacturing the same

Abstract

To provide a display device capable of improving the reliability against moisture and the display quality, and a method of manufacturing the same.SOLUTION: A display device includes: a lower electrode; a rib that covers an end part of the lower electrode, having a pixel opening for exposing a part of the lower electrode; a barrier arranged on the rib; an upper electrode opposed to the lower electrode, being in contact with the barrier; an organic layer arranged between the lower electrode and the upper electrode, emitting light depending on a potential difference between the lower electrode and the upper electrode; and an encapsulation layer that continuously covers a display element including the lower and upper electrodes and the organic layer, and the barrier. The encapsulation layer includes: a first portion located above the rib, having a first thickness; and a second portion located above the lower electrode exposed from the rib via the pixel opening, having a second thickness smaller than the first thickness.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device and a method for manufacturing the same.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. This display element includes a lower electrode, an organic layer covering the lower electrode, and an upper electrode covering the organic layer, and the organic layer emits light according to the potential difference between the lower electrode and the upper electrode.

[0003] In the display device as described above, improvement in reliability against moisture and improvement in display quality are required.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0005] An object of the present invention is to provide a display device capable of improving reliability against moisture and display quality, and a method for manufacturing the same. [Means for solving the problem]

[0006] A display device according to one embodiment includes a lower electrode, a rib having a pixel aperture that covers the end of the lower electrode and exposes a part of the lower electrode, a partition wall disposed on the rib, an upper electrode facing the lower electrode and in contact with the partition wall, an organic layer disposed between the lower electrode and the upper electrode that emits light in accordance with the potential difference between the lower electrode and the upper electrode, a display element including the lower electrode, the upper electrode and the organic layer, and a sealing layer that continuously covers the partition wall. The sealing layer includes a first portion located above the rib and having a first thickness, and a second portion located above the lower electrode exposed from the rib through the pixel aperture and having a second thickness smaller than the first thickness. Furthermore, the display device includes an area above the region where the rib and the partition wall overlap, in which the sealing layer is not provided.

[0007] In a method for manufacturing a display device according to one embodiment, a lower electrode is formed above a substrate, a rib is formed that covers the end of the lower electrode and has a pixel opening that exposes a part of the lower electrode, a partition wall is formed on the rib, an organic layer is formed that covers the lower electrode through the pixel opening, an upper electrode is formed that covers the organic layer and contacts the partition wall, a sealing layer is formed that continuously covers the display element including the lower electrode, the upper electrode and the organic layer and the partition wall, and the portion of the sealing layer located above the lower electrode exposed from the rib through the pixel opening is thinned. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows an example of the configuration of a display device according to one embodiment. [Figure 2] Figure 2 shows an example of a sub-pixel layout. [Figure 3] Figure 3 is a schematic cross-sectional view of the display device along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic cross-sectional view of the partition wall and its vicinity, magnified. [Figure 5] Figure 5 is a schematic cross-sectional view showing other examples that may be applicable to a partition wall and its vicinity. [Figure 6] FIG. 6 is a schematic plan view of the partition wall, the rib, and the sealing layer. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a part of the manufacturing process of the display device. [Figure 8] FIG. 8 is a schematic cross-sectional view showing the process following FIG. 7. [Figure 9] FIG. 9 is a schematic cross-sectional view showing the process following FIG. 8. [Figure 10] FIG. 10 is a schematic cross-sectional view showing the process following FIG. 9. [Figure 11] FIG. 11 is a schematic cross-sectional view showing the process following FIG. 10. [Figure 12] FIG. 12 is a schematic cross-sectional view showing the process following FIG. 11. [Figure 13] FIG. 13 is a schematic cross-sectional view showing the process following FIG. 12. [Figure 14] FIG. 14 is a schematic cross-sectional view showing the process following FIG. 13.

BEST MODE FOR CARRYING OUT THE INVENTION

[0009] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and for those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the invention, they are naturally included in the scope of the present invention. Also, the drawings may be schematically represented in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the purpose of making the description clearer, but it is merely an example and does not limit the interpretation of the present invention. Also, in this specification and each figure, components that exhibit the same or similar functions as those previously described with respect to the existing figures may be assigned the same reference numerals, and detailed descriptions that overlap may be omitted as appropriate.

[0010] In the drawings, for ease of understanding as necessary, the X-axis, Y-axis, and Z-axis that are orthogonal to each other are described. The direction along the X-axis is referred to as the first direction, the direction along the Y-axis is referred to as the second direction, and the direction along the Z-axis is referred to as the third direction. Looking at various elements parallel to the third direction Z is called a plan view.

[0011] The display device according to each embodiment is an organic electroluminescence display device including an organic light-emitting diode (OLED) as a display element, and can be mounted on a television, a personal computer, in-vehicle equipment, a tablet terminal, a smartphone, a mobile phone terminal, or the like.

[0012] FIG. 1 is a diagram showing a configuration example of a display device DSP according to this embodiment. The display device DSP has a display area DA for displaying an image and a peripheral area SA around the display area DA on an insulating substrate 10. The substrate 10 may be glass or a resin film having flexibility.

[0013] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0014] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the pixel PX includes a first sub-pixel SP1 of red, a second sub-pixel SP2 of green, and a third sub-pixel SP3 of blue. Note that the pixel PX may include sub-pixels SP of other colors such as white, together with or instead of the sub-pixels SP1, SP2, and SP3.

[0015] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements constituted by, for example, thin film transistors.

[0016] The gate electrode of pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to the power line PL and capacitor 4, and the other is connected to display element DE. Display element DE is an organic light-emitting diode (OLED) as a light-emitting element.

[0017] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0018] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 2, the first sub-pixel SP1 and the third sub-pixel SP3 are aligned in the first direction X. The second sub-pixel SP2 and the third sub-pixel SP3 are also aligned in the first direction X. Furthermore, the first sub-pixel SP1 and the second sub-pixel SP2 are aligned in the second direction Y.

[0019] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP1 and SP2 are alternately arranged in the second direction Y, and columns in which multiple third sub-pixels SP3 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0020] Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2. Another example is that the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged sequentially in the first direction X.

[0021] The display area DA has ribs 5 and partition walls 6. Ribs 5 have a first pixel aperture AP1 in the first sub-pixel SP1, a second pixel aperture AP2 in the second sub-pixel SP2, and a third pixel aperture AP3 in the third sub-pixel SP3. In the example in Figure 2, the second pixel aperture AP2 is larger than the first pixel aperture AP1, and the third pixel aperture AP3 is larger than the second pixel aperture AP2.

[0022] The partition wall 6 is positioned at the boundary between adjacent subpixels SP and overlaps with the rib 5 in a plan view. The partition wall 6 has a plurality of first partition walls 6x extending in the first direction X and a plurality of second partition walls 6y extending in the second direction Y. The plurality of first partition walls 6x are positioned between adjacent pixel apertures AP1 and AP2 in the second direction Y, and between two adjacent third pixel apertures AP3 in the second direction Y. The second partition walls 6y are positioned between adjacent pixel apertures AP1 and AP3 in the first direction X, and between adjacent pixel apertures AP2 and AP3 in the first direction X.

[0023] In the example shown in Figure 2, the first partition wall 6x and the second partition wall 6y are connected to each other. As a result, the partition wall 6 as a whole forms a grid surrounding the pixel apertures AP1, AP2, and AP3. It can also be said that the partition wall 6, like the rib 5, has apertures in the sub-pixels SP1, SP2, and SP3.

[0024] The first sub-pixel SP1 comprises a first lower electrode LE1, a first upper electrode UE1, and a first organic layer OR1, which overlap with the first pixel aperture AP1. The second sub-pixel SP2 comprises a second lower electrode LE2, a second upper electrode UE2, and a second organic layer OR2, which overlap with the second pixel aperture AP2. The third sub-pixel SP3 comprises a third lower electrode LE3, a third upper electrode UE3, and a third organic layer OR3, which overlap with the third pixel aperture AP3.

[0025] The first lower electrode LE1, the first upper electrode UE1, and the first organic layer OR1 constitute the first display element DE1 of the first sub-pixel SP1. The second lower electrode LE2, the second upper electrode UE2, and the second organic layer OR2 constitute the second display element DE2 of the second sub-pixel SP2. The third lower electrode LE3, the third upper electrode UE3, and the third organic layer OR3 constitute the third display element DE3 of the third sub-pixel SP3. Display elements DE1, DE2, and DE3 may include a cap layer, as described later.

[0026] For example, the first display element DE1 emits light in the red wavelength range, the second display element DE2 emits light in the green wavelength range, and the third display element DE3 emits light in the blue wavelength range.

[0027] The first lower electrode LE1 is connected to the pixel circuit 1 of the first sub-pixel SP1 (see Figure 1) through the first contact hole CH1. The second lower electrode LE2 is connected to the pixel circuit 1 of the second sub-pixel SP2 through the second contact hole CH2. The third lower electrode LE3 is connected to the pixel circuit 1 of the third sub-pixel SP3 through the third contact hole CH3.

[0028] In the example in Figure 2, the contact holes CH1 and CH2 completely overlap with the first partition wall 6x between adjacent pixel apertures AP1 and AP2 in the second direction Y. Similarly, the third contact hole CH3 completely overlaps with the first partition wall 6x between two adjacent third pixel apertures AP3 in the second direction Y. In another example, at least a portion of the contact holes CH1, CH2, and CH3 may not overlap with the first partition wall 6x.

[0029] Figure 3 is a schematic cross-sectional view of the display device DSP along the line III-III in Figure 2. A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring such as the pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1.

[0030] The circuit layer 11 is covered by an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11. Although not shown in the cross-section of Figure 3, the aforementioned contact holes CH1, CH2, and CH3 are all provided in the organic insulating layer 12.

[0031] The lower electrodes LE1, LE2, and LE3 are positioned on top of the organic insulating layer 12. The ribs 5 are positioned on top of the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the ribs 5.

[0032] The partition wall 6 includes a conductive lower section 61 positioned on the rib 5 and an upper section 62 positioned on top of the lower section 61. The upper section 62 has a greater width than the lower section 61. As a result, in Figure 3, both ends of the upper section 62 protrude beyond the sides of the lower section 61. This shape of the partition wall 6 can also be described as overhanging.

[0033] The first organic layer OR1 covers the first lower electrode LE1 through the first pixel aperture AP1. The first upper electrode UE1 covers the first organic layer OR1 and faces the first lower electrode LE1. The second organic layer OR2 covers the second lower electrode LE2 through the second pixel aperture AP2. The second upper electrode UE2 covers the second organic layer OR2 and faces the second lower electrode LE2. The third organic layer OR3 covers the third lower electrode LE3 through the third pixel aperture AP3. The third upper electrode UE3 covers the third organic layer OR3 and faces the third lower electrode LE3.

[0034] In the example shown in Figure 3, the first cap layer CP1 is placed on the first upper electrode UE1, the second cap layer CP2 is placed on the second upper electrode UE2, and the third cap layer CP3 is placed on the third upper electrode UE3. The cap layers CP1, CP2, and CP3 adjust the optical properties of the light emitted by the organic layers OR1, OR2, and OR3, respectively.

[0035] A portion of the first organic layer OR1, the first upper electrode UE1, and the first cap layer CP1 is located above the upper section 62. This portion is separated from the other portions of the first organic layer OR1, the first upper electrode UE1, and the first cap layer CP1. Similarly, a portion of the second organic layer OR2, the second upper electrode UE2, and the second cap layer CP2 is located above the upper section 62, and this portion is separated from the other portions of the second organic layer OR2, the second upper electrode UE2, and the second cap layer CP2. Furthermore, a portion of the third organic layer OR3, the third upper electrode UE3, and the third cap layer CP3 is located above the upper section 62, and this portion is separated from the other portions of the third organic layer OR3, the third upper electrode UE3, and the third cap layer CP3.

[0036] The first sub-pixel SP1 is covered with the first sealing layer SE1, the second sub-pixel SP2 is covered with the second sealing layer SE2, and the third sub-pixel SP3 is covered with the third sealing layer SE3. The first sealing layer SE1 continuously covers the first cap layer CP1 and the partition wall 6 surrounding the first sub-pixel SP1. The second sealing layer SE2 continuously covers the second cap layer CP2 and the partition wall 6 surrounding the second sub-pixel SP2. The third sealing layer SE3 continuously covers the third cap layer CP3 and the partition wall 6 surrounding the third sub-pixel SP3.

[0037] The edges (periphery) of the sealing layers SE1, SE2, and SE3 are located above the upper part 62. In the example in Figure 3, the edges of the sealing layers SE1 and SE3 located above the upper part 62 of the partition wall 6 between sub-pixels SP1 and SP3 are spaced apart, and the edges of the sealing layers SE2 and SE3 located above the upper part 62 of the partition wall 6 between sub-pixels SP2 and SP3 are also spaced apart.

[0038] The sealing layers SE1, SE2, and SE3 are covered by a resin layer 13. The resin layer 13 is covered by a sealing layer 14. Furthermore, the sealing layer 14 is covered by a resin layer 15.

[0039] The organic insulating layer 12 and the resin layers 13 and 15 are formed from organic materials. The ribs 5 and the sealing layers 14, SE1, SE2, and SE3 are formed from inorganic materials such as silicon nitride (SiN), silicon oxide (SiO), or silicon oxynitride (SiON).

[0040] The lower electrodes LE1, LE2, and LE3 each have an intermediate layer formed of, for example, silver (Ag), and a pair of conductive oxide layers covering the upper and lower surfaces of this intermediate layer, respectively. Each conductive oxide layer can be formed of a transparent conductive oxide such as ITO (IndiumTin Oxide), IZO (IndiumZinc Oxide), or IGZO (IndiumGalliumZinc Oxide).

[0041] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0042] The organic layers OR1, OR2, and OR3 have, for example, a laminated structure consisting of a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0043] The cap layers CP1, CP2, and CP3 are formed, for example, by a multilayer structure of multiple transparent thin films. The multilayer structure may include thin films formed from inorganic materials and thin films formed from organic materials. These multiple thin films have different refractive indices. The materials of the thin films constituting the multilayer structure are different from the materials of the upper electrodes UE1, UE2, and UE3, and also different from the materials of the sealing layers SE1, SE2, and SE3. Note that the cap layers CP1, CP2, and CP3 may be omitted.

[0044] The lower part 61 of the partition wall 6 is formed of, for example, aluminum (Al). The lower part 61 may be formed of an aluminum alloy such as aluminum-neodymium (AlNd), or it may have a laminated structure of an aluminum layer and an aluminum alloy layer. Furthermore, the lower part 61 may have a thin film formed of a metallic material different from aluminum or an aluminum alloy beneath the aluminum layer or aluminum alloy layer. Such a thin film can be formed of, for example, molybdenum (Mo).

[0045] The upper part 62 of the partition wall 6 has a laminated structure consisting of a first thin film made of a metallic material such as titanium (Ti) and a second thin film made of a conductive oxide such as ITO. The upper part 62 may also have a single-layer structure of a metallic material such as titanium. Alternatively, the upper part 62 may have a single-layer structure of an inorganic material such as silicon oxide.

[0046] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the side surface of the lower part 61. Pixel voltages are supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0047] When a potential difference is formed between the first lower electrode LE1 and the first upper electrode UE1, the light-emitting layer of the first organic layer OR1 emits light in the red wavelength range. When a potential difference is formed between the second lower electrode LE2 and the second upper electrode UE2, the light-emitting layer of the second organic layer OR2 emits light in the green wavelength range. When a potential difference is formed between the third lower electrode LE3 and the third upper electrode UE3, the light-emitting layer of the third organic layer OR3 emits light in the blue wavelength range.

[0048] Figure 4 is a schematic cross-sectional view of the partition wall 6 located between sub-pixels SP1 and SP3, and its vicinity, magnified. In this figure, the substrate 10, circuit layer 11, resin layer 13, sealing layer 14, and resin layer 15 are omitted.

[0049] The lower section 61 has a pair of sides 61a and 61b. Both ends of the upper section 62 protrude beyond the sides 61a and 61b, respectively. In the example in Figure 4, the lower section 61 has a shape that tapers as it approaches the upper section 62. That is, the sides 61a and 61b are inclined with respect to the third direction Z such that the distance between them decreases as they approach the upper section 62. In another example, the sides 61a and 61b may be substantially parallel to the third direction Z.

[0050] Depending on the conditions for forming the first sealing layer SE1, voids V, which are cavities not filled by the first sealing layer SE1, may occur near the side surface 61a. Similarly, depending on the conditions for forming the third sealing layer SE3, voids V, which are cavities not filled by the third sealing layer SE3, may occur near the side surface 61b.

[0051] The first sealing layer SE1 includes a first portion P1 having a first thickness T1 and a second portion P2 having a second thickness T2. The first portion P1 is mostly located above the rib 5 and continuously covers the first cap layer CP1, a portion of the side surface 61a of the lower portion 61, the bottom surface and sides of the upper portion 62, etc. The second portion P2 is located above the first pixel aperture AP1 (above the first lower electrode LE1 exposed from the rib 5 through the first pixel aperture AP1). In the example in Figure 4, the boundary between the first portion P1 and the second portion P2 is located above the first pixel aperture AP1. In another example, the boundary may be located above the rib 5.

[0052] The thickness of the first portion P1 is not constant and can vary depending on the shape of the substrate. For example, in the example in Figure 4, the thickness of the first portion P1 is reduced around the void V. In one example, the first thickness T1 is the average value of the thickness at various points in the first portion P1. In another example, the first thickness T1 may be the thickness of the portion of the first portion P1 excluding the area around the void V, or its average value.

[0053] Regarding the second part P2, the base is relatively flat and the thickness is generally constant. In one example, the second thickness T2 is the average value of the thicknesses at various locations of the second part P2. For example, if there are irregularities on the base of the second part P2, such as near the ends of the ribs 5, the second thickness T2 may be the thickness or the average value of the part excluding the periphery of such irregularities.

[0054] In this embodiment, the second thickness T2 is smaller than the first thickness T1 (T2 < T1). For example, the second thickness T2 is at most 1 / 2 of the first thickness T1. In one example, the first thickness T1 is 1.0 μm or more, and the second thickness T2 is less than 1.0 μm. The second thickness T2 is preferably 0.1 μm or more.

[0055] The distance D between the partition wall 6 and the second part P2 is preferably not less than the height H of the partition wall 6 (D ≧ H). Here, the distance D corresponds to the distance in the width direction of the partition wall 6 between the lower end of the side surface 61a and the second part P2 of the first sealing layer SE1. The width direction of the partition wall 6 is the first direction X with respect to the second partition wall 6y shown in FIG. 4, and the second direction Y with respect to the first partition wall 6x shown in FIG. 2. The height H corresponds to the distance in the third direction Z from the upper surface of the rib 5 to the upper surface of the upper portion 62, and in one example is 1.0 μm or more.

[0056] Preferably, the relationship D ≧ H holds over the entire circumference of the second part P2. However, there may be a portion where this relationship does not hold at least in part around the second part P2.

[0057] Similar to the first sealing layer SE1, the second sealing layer SE2 and the third sealing layer SE3 also each include the first part P1 and the second part P2. The relationship between the first thickness T1 and the second thickness T2 in the sealing layers SE2 and SE3, and the relationship between the height H and the distance D are the same as those described above for the first sealing layer SE1. However, the first thicknesses T1 in the sealing layers SE1, SE2, and SE3 may be different from each other, and the second thicknesses T2 in the sealing layers SE1, SE2, and SE3 may be different from each other. Also, the distances D in the sealing layers SE1, SE2, and SE3 may be different from each other.

[0058] FIG. 5 is a schematic cross-sectional view showing another example applicable to the partition wall 6 and its vicinity. In the example of FIG. 4 described above, both the first thickness T1 and the second thickness T2 are smaller than the height H (T1, T2 < H). On the other hand, in the example of FIG. 5, the first thickness T1 is larger than the height H (T1 > H), and the second thickness T2 is smaller than the height H (T2 < H).

[0059] The first thickness T1 in the example of FIG. 5 is, for example, 1.0 μm or more, and in one example, it is about 3.0 μm. When the sealing layers SE1, SE2, SE3 are formed thick in this way, the second thickness T2 may be, for example, 1 / 3 or less of the first thickness T1.

[0060] FIG. 6 is a schematic plan view of the partition wall 6, the rib 5, and the sealing layers SE1, SE2, SE3. In the sealing layers SE1, SE2, SE3 shown in FIG. 6, the region with upward right diagonal lines corresponds to the first portion P1, and the region with upward left diagonal lines corresponds to the second portion P2.

[0061] The rectangular dashed lines drawn in each of the sealing layers SE1, SE2, SE3 indicate the boundaries between the first portion P1 and the second portion P2. In the example of FIG. 6, these boundaries overlap the pixel openings AP1, AP2, AP3, respectively. That is, in the example of FIG. 6, the area of the second portion P2 of the first sealing layer SE1 is slightly smaller than the area of the first pixel opening AP1, the area of the second portion P2 of the second sealing layer SE2 is slightly smaller than the area of the second pixel opening AP2, and the area of the second portion P2 of the third sealing layer SE3 is slightly smaller than the area of the third pixel opening AP3. As another example, these boundaries may overlap the rib 5 around the pixel openings AP1, AP2, AP3, respectively.

[0062] The first portion P1 of the first sealing layer SE1 surrounds the second portion P2 of the first sealing layer SE1 and overlaps with the ribs 5 and partition walls 6 around the first pixel aperture AP1. The first portion P1 of the second sealing layer SE2 surrounds the second portion P2 of the second sealing layer SE2 and overlaps with the ribs 5 and partition walls 6 around the second pixel aperture AP2. The first portion P1 of the third sealing layer SE3 surrounds the second portion P2 of the third sealing layer SE3 and overlaps with the ribs 5 and partition walls 6 around the third pixel aperture AP3.

[0063] Next, the manufacturing method of the display device DSP will be described. In this embodiment, as an example, we assume that the third display element DE3 is formed first, the second display element DE2 is formed next, and the first display element DE1 is formed last. However, the formation order of the display elements DE1, DE2, and DE3 is not limited to this example.

[0064] Figures 7 to 14 are schematic cross-sectional views showing part of the manufacturing process of the DSP display device in this embodiment. In these figures, the substrate 10 and circuit layer 11 are omitted.

[0065] In manufacturing a display device DSP, first, a circuit layer 11 and an organic insulating layer 12 are formed on the substrate 10 shown in Figure 3. Then, as shown in Figure 7, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12, ribs 5 are formed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3, and partition walls 6 are formed on the ribs 5. The pixel apertures AP1, AP2, and AP3 of the ribs 5 may be formed before or after the partition walls 6.

[0066] Next, as shown in Figure 8, the third organic layer OR3, the third upper electrode UE3, the third cap layer CP3, and the third sealing layer SE3 are sequentially formed on the entire substrate by vapor deposition. At this time, the third organic layer OR3, the third upper electrode UE3, and the third cap layer CP3 formed on each sub-pixel SP1, SP2, and SP3 are separated by the overhanging partition wall 6. The third sealing layer SE3 continuously covers the third display element DE3, which includes the third lower electrode LE3, the third organic layer OR3, the third upper electrode UE3, and the third cap layer CP3, as well as the partition wall 6.

[0067] Next, as shown in Figure 9, the resist R1 is placed on the third sealing layer SE3. The resist R1 is patterned to overlap with the third subpixel SP3. The resist R1 is also located directly above the portion of the partition wall 6 surrounding the third subpixel SP3 that is closer to the third subpixel SP3.

[0068] Furthermore, etching using the resist R1 as a mask removes the portions of the third organic layer OR3, third upper electrode UE3, third cap layer CP3, and third sealing layer SE3 that are exposed from the resist R1, as shown in Figure 10. As a result, the third sub-pixel SP3 is formed with a third display element DE3 including the third lower electrode LE3, third organic layer OR3, third upper electrode UE3, and third cap layer CP3, and a third sealing layer SE3 covering it, while the sub-pixels SP1 and SP2 are left without display elements or sealing layers.

[0069] Subsequently, the resist R1 is removed, and a process is carried out to form the second display element DE2 on the second sub-pixel SP2 using the same procedure as for the third display element DE3. As a result, as shown in Figure 11, a substrate is obtained in which the second display element DE2, which includes the second lower electrode LE2, the second organic layer OR2, the second upper electrode UE2, and the second cap layer CP2, and a second sealing layer SE2 covering it are further formed on the second sub-pixel SP2.

[0070] After the formation of the second display element DE2, a process is carried out to form the first display element DE1 on the first sub-pixel SP1 using the same procedure as for the third display element DE3. As a result, as shown in Figure 12, a substrate is obtained in which the first display element DE1, which includes the first lower electrode LE1, the first organic layer OR1, the first upper electrode UE1, and the first cap layer CP1, and the first sealing layer SE1 covering it are further formed on the first sub-pixel SP1. In the state shown in Figure 12, the thickness of the sealing layers SE1, SE2, and SE3 is generally the first thickness T1 described above.

[0071] Next, as shown in Figure 13, the resist R2 is placed on the portion of the sealing layers SE1, SE2, and SE3 that covers the partition wall 6 (corresponding to the first portion P1 mentioned above). The resist R2 is also located above the ribs 5 that protrude from both sides of the partition wall 6.

[0072] Furthermore, etching using resist R2 as a mask thins the portions of the encapsulating layers SE1, SE2, and SE3 that are exposed from resist R2, as shown in Figure 14. This etching is, for example, dry etching and continues until the thickness of the portions of the encapsulating layers SE1, SE2, and SE3 that are exposed from resist R2 is reduced to the second thickness T2 mentioned above. This dry etching is stopped, for example, after a predetermined amount of time has elapsed. Alternatively, the encapsulating layers SE1, SE2, and SE3 may be thinned by wet etching instead of dry etching.

[0073] Through the processes shown in Figures 13 and 14, the first portion P1 and the second portion P2 are formed on the encapsulation layers SE1, SE2, and SE3. Subsequently, the resist R2 is removed, and the resin layer 13, encapsulation layer 14, and resin layer 15 are formed in sequence. This completes the DSP display device with the structure shown in Figure 3.

[0074] In this description, the process of forming the display elements DE1, DE2, and DE3, and then simultaneously providing the first portion P1 and the second portion P2 to each of the sealing layers SE1, SE2, and SE3, was explained. However, the first portion P1 and the second portion P2 may be provided to the sealing layers SE1, SE2, and SE3 in separate processes.

[0075] In this embodiment, the sealing layers SE1, SE2, and SE3 each have a first portion P1 and a second portion P2 that is thinner than the first portion P1. A partition wall 6 is positioned above the rib 5, where there is a significant change in the substrate of the sealing layers SE1, SE2, and SE3. By covering this area with the thicker first portion P1, the intrusion of moisture into the display elements DE1, DE2, DE3, etc., is effectively suppressed, thereby improving the reliability of the display device DSP against moisture.

[0076] On the other hand, above the pixel apertures AP1, AP2, and AP3, the substrates of the sealing layers SE1, SE2, and SE3 are relatively flat. In such regions, a large thickness is not required for the sealing layers SE1, SE2, and SE3 from the viewpoint of suppressing moisture intrusion. Therefore, even when these regions are covered with a thin second portion P2, moisture intrusion into the display elements DE1, DE2, and DE3 can be suppressed.

[0077] If thick sealing layers SE1, SE2, SE3 are placed above the pixel apertures AP1, AP2, AP3, the optical properties of the display elements DE1, DE2, DE3 may deteriorate. On the other hand, if the sealing layers SE1, SE2, SE3 above the pixel apertures AP1, AP2, AP3 are thinned out as in the second portion P2, it is possible to improve the optical properties of the display elements DE1, DE2, DE3.

[0078] Thus, in this embodiment, by providing a first portion P1 and a second portion P2 with different thicknesses in the sealing layers SE1, SE2, and SE3, a display device DSP that achieves both reliability against moisture and improved display quality can be obtained.

[0079] As described above, for example, if the first thickness T1 is 1.0 μm or more, moisture intrusion near the partition wall 6 can be suitably suppressed. Furthermore, if the second thickness T2 is less than 1.0 μm and 0.1 μm or more, the optical characteristics of the display elements DE1, DE2, and DE3 can be improved, and moisture intrusion near the pixel apertures AP1, AP2, and AP3 can be suitably suppressed.

[0080] If the second section P2 is too close to the partition wall 6, moisture intrusion in the vicinity of the partition wall 6 may not be sufficiently suppressed. Therefore, as described above, it is preferable that the distance D between the partition wall 6 and the second section P2 be greater than or equal to the height H of the partition wall 6. By setting the distance D in this way, the effectiveness of suppressing moisture intrusion by the first section P1 can be increased. In addition to those exemplified here, various other desirable effects can be obtained from this embodiment.

[0081] All display devices and manufacturing methods thereof that can be implemented by those skilled in the art by appropriately modifying the design based on the display devices and manufacturing methods thereof described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0082] Within the scope of the spirit of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, modifications made by a person skilled in the art to the above-described embodiments, such as adding, deleting, or changing the design of components, or adding, omitting, or changing the conditions of processes, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0083] Furthermore, any other effects and benefits brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0084] DSP... Display device, DA... Display area, SA... Peripheral area, PX... Pixel, SP1, SP2, SP3... First to third sub-pixels, LE1, LE2, LE3... First to third lower electrodes, OR1, OR2, OR3... First to third organic layers, UE1, UE2, UE3... First to third upper electrodes, SE1, SE2, SE3... First to third sealing layers, DE1, DE2, DE3... First to third display elements, 5... Rib, 6... Partition, 61... Lower part of partition, 62... Upper part of partition, P1... First part of sealing layer, P2... Second part of sealing layer.

Claims

1. The lower electrode and A rib that covers the end of the lower electrode and has a pixel opening that exposes a part of the lower electrode, A partition wall positioned above the rib, An upper electrode facing the lower electrode and in contact with the partition wall, An organic layer is placed between the lower electrode and the upper electrode and emits light in accordance with the potential difference between the lower electrode and the upper electrode, A display element comprising the lower electrode, the upper electrode, and the organic layer, and a sealing layer that continuously covers the partition wall, Equipped with, The sealing layer is A first portion located above the rib and having a first thickness, A second portion is located above the lower electrode exposed from the rib through the pixel aperture and has a second thickness smaller than the first thickness, Includes, A display device comprising a region above the region where the rib and the partition wall overlap, in which the sealing layer is not disposed.

2. The first part surrounds the second part in a plan view. The display device according to claim 1.

3. The second thickness is less than or equal to half of the first thickness. The display device according to claim 1.

4. The first thickness is greater than the height of the partition wall. The second thickness is smaller than the height of the partition wall. The display device according to claim 1.

5. The first thickness is 1.0 μm or more. The second thickness is less than 1.0 μm. The display device according to claim 1.

6. The second thickness is 0.1 μm or more. The display device according to claim 5.

7. The distance between the partition wall and the second portion is greater than or equal to the height of the partition wall. The display device according to claim 1.

8. The aforementioned partition wall is The lower part positioned on the rib, An upper part positioned above the lower part and protruding from the side of the lower part, It has, The upper electrode is in contact with the side surface, The first part covers a portion of the side surface. The display device according to any one of claims 1 to 7.

9. A lower electrode is formed above the substrate. A rib is formed that covers the end of the lower electrode and has a pixel opening that exposes a part of the lower electrode. A partition wall is formed on the rib, An organic layer is formed to cover the lower electrode through the pixel aperture, The above organic layer is covered, and an upper electrode in contact with the partition wall is formed, A sealing layer is formed to continuously cover the display element, which includes the lower electrode, the upper electrode, and the organic layer, and the partition wall. Of the sealing layer, the portion located above the lower electrode that is exposed from the rib through the pixel aperture is thinned. A method for manufacturing a display device.

10. The aforementioned thinning process is, A resist is placed on the portion of the sealing layer that covers the partition wall. Etching reduces the thickness of the portion of the sealing layer that is exposed from the resist. Including, A method for manufacturing a display device according to claim 9.

11. The sealing layer includes a region that is not located above the region where the rib and the partition wall overlap. A method for manufacturing a display device according to claim 9.

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