Error checking of data used in offloaded operations

Abstract

Error checking of data used in an offloaded operation is disclosed. A remote execution device receives a request from a host to store a data block in a memory region. The data block includes data and host-generated error checking information for the data. The remote execution device updates the data block by overwriting the host-generated error checking information with locally generated error checking information for the data. The data block is then stored in the memory region.

Description

Background Art

[0001] Computing systems often include several processing resources (e.g., one or more processors) that can fetch and execute instructions and store the results of the executed instructions in an appropriate location. A processing resource (e.g., a central processing unit (CPU)) can be used to execute instructions by performing logical operations on data (e.g., one or more operands), and can include several functional units such as, for example, an arithmetic logic unit (ALU) circuit, a floating point unit (FPU) circuit, and / or a combinatorial logic block. For example, the functional unit circuit may be used to perform arithmetic operations such as addition, subtraction, multiplication, and / or division on operands. Typically, the processing resources (e.g., the processor and / or associated functional unit circuits) are external to the memory array, and data is accessed via a bus between the processing resources and the memory array to execute the instruction set. To reduce the amount of accesses to fetch or store data in the memory array, a computing system may use a cache hierarchy that temporarily stores recently accessed or modified data for use by the processing resources or group of processing resources. However, processing performance can be further improved by offloading certain operations to a processor-in-memory (PIM) device, where the processing resources are implemented inside and / or near the memory, so that data processing is performed near the memory location that stores the data, rather than bringing the data close to the processing resources for computation. The PIM device can save time by reducing and / or eliminating external communication, and can also save power.

Brief Description of the Drawings

[0002] [Figure 1]This is a block diagram of an exemplary system for error checking data used in offloaded operations according to embodiments of the present disclosure. [Figure 2] This is a block diagram of an exemplary system for error checking data used in offloaded operations according to embodiments of the present disclosure. [Figure 3] This flowchart shows another exemplary method for error checking data used in offloaded operations according to embodiments of the present disclosure. [Figure 4] This flowchart shows another exemplary method for error checking data used in offloaded operations according to embodiments of the present disclosure. [Figure 5] This flowchart shows another exemplary method for error checking data used in offloaded operations according to embodiments of the present disclosure. [Figure 6] This flowchart shows another exemplary method for error checking data used in offloaded operations according to embodiments of the present disclosure. [Figure 7] This flowchart shows another exemplary method for error checking data used in offloaded operations according to embodiments of the present disclosure. [Figure 8] This flowchart shows another exemplary method for error checking data used in offloaded operations according to embodiments of the present disclosure. [Figure 9] This flowchart shows another exemplary method for error checking data used in offloaded operations according to embodiments of the present disclosure. [Modes for carrying out the invention]

[0003] Processing-in-Memory (PIM) architectures support offloading instructions to execute in or near memory, which can save bandwidth on the data link between the processor and memory and reduce processor power consumption. For example, execution of offloaded instructions by a PIM device does not require loading data into local central processing unit (CPU) registers and writing data back from local CPU storage to memory. A PIM architecture typically includes a PIM-enabled host (e.g., a CPU or graphics processing unit GPU) configured to execute PIM instructions to offload operations to a PIM device. Typically, a PIM device is a memory device that implements computing power (e.g., PIM computation logic) within a memory device, although a PIM device may be tightly coupled to a memory device. For ease of explanation, this disclosure assumes that a PIM device is a PIM-enabled memory device having PIM computation logic embedded within a memory device that implements computing power.

[0004] To support error detection of data written to memory, a host can generate reliability, availability, and serviceability (RAS) metadata for the data written to memory. This metadata is typically stored with the memory device along with the data and is used to perform error detection checks when the data is later retrieved from the memory device. For example, a host can apply an error detection function to data read from memory and determine whether the result of that function matches the metadata. Failure to satisfy this error detection check may indicate that the data cannot be accurately retrieved from memory or that the data itself is corrupted. Problems arise when data is modified by PIM operation because data modification may invalidate the RAS metadata. That is, when PIM-modified data is retrieved by the host, the result of the error detection function applied to the PIM-modified data is likely to not match the RAS metadata stored with the data. Another problem is that a PIM device cannot use the RAS metadata generated by the host without knowledge of the host's error detection scheme. Therefore, the data remains unprotected because the PIM-enabled memory device simply ignores the host error checking information.

[0005] One solution to this problem is to mirror the host-based error protection technology in the memory device. However, this may require all PIM-enabled memory vendors and all PIM-enabled host vendors to agree to use the same error protection technology, or it may require the host to specifically configure the PIM-enabled memory device using its own proprietary error detection technology. Very often, host vendors are unwilling to disclose these proprietary technologies. Therefore, mirroring or exactly replicating the host-based error detection technology in the PIM-enabled memory device may not be a viable solution. Furthermore, in order for the PIM-enabled memory device to track the RAS metadata for operations performed within the PIM-enabled memory device using its own error checking scheme, a separate buffer must be used to store the RAS metadata generated by the PIM-enabled memory device, or additional space must be allocated for data received from the host to store locally generated RAS metadata.

[0006] To address this and other issues, embodiments of the present disclosure utilize the space occupied by host-generated RAS metadata by overwriting the host-generated RAS metadata with locally generated RAS metadata, thereby enabling a remote execution device, such as a PIM-enabled memory device, to identify and correct on-device data errors. Before sending data to the remote execution device, the host performs error checking using the host-generated RAS metadata and marks any uncorrectable errors encountered. Before sending data to the host, the remote execution device performs error checking using locally generated RAS metadata and marks any uncorrectable errors encountered.

[0007] One embodiment of the present disclosure relates to a method for error checking data used in offloaded operations. The method includes identifying a request issued by a host to store a data block in a memory area, wherein the data block includes data and host-generated error checking information for the data. The method also includes updating the data block by overwriting the host-generated error checking information with locally generated error checking information for the data. The method also includes storing the updated data block in a memory area. In some embodiments, the method may include identifying error indicators provided by the host in the data block.

[0008] In some embodiments, the memory region is coupled to a processing unit configured to perform operations offloaded from the host. In these embodiments, the method may include validating the data using locally generated error checking information when reading updated data blocks from the memory region to the processing unit. In these embodiments, the method may include the processing unit generating new data and generating error checking information for the new data. In such embodiments, the method includes storing the new data in a new data block and storing locally generated error checking information for the new data in a new memory block in the memory region, wherein the new data block is marked to indicate that the new data was generated from an offloaded operation. The memory region and the processing unit may be embodied in a processing-in-memory device.

[0009] In some embodiments, the method includes validating new data using locally generated error checking information for the new data before providing the new data to the host. In these embodiments, the method may include marking an error indicator on the new data if an unrecoverable error is detected.

[0010] Another embodiment of the present disclosure relates to a device for error checking data used in offloaded operations, the device comprising: a processing unit configured to perform offloaded operations from a host; a memory area coupled to the processing unit; and a logic circuit configured to identify a request issued by the host to store a data block in the memory area, the data block comprising data and host-generated error checking information for the data. The logic circuit is also configured to update the data block by overwriting the host-generated error checking information with locally generated error checking information for the data. The logic circuit is also configured to store the updated data block in the memory area.

[0011] In some embodiments, the logic circuit is further configured to identify error indicators provided by the host in the data block. In some embodiments, the logic circuit is further configured to validate the data using locally generated error checking information when reading the updated data block from the memory area to the processor. In some embodiments, the logic circuit is further configured to generate error checking information for the new data generated by the processor, store the new data in a new data block, and store the locally generated error checking information for the new data in a new memory block in the memory area, the new data block being marked to indicate that the new data was generated from an offloaded operation.

[0012] In some embodiments, the logic circuit is further configured to validate new data using locally generated error checking information for the new data before providing the new data to the host. In these embodiments, the logic circuit may be further configured to mark an error indicator on the new data if an unrecoverable error is detected. In some embodiments, the device is a processing-in-memory (PIM) device.

[0013] Another embodiment of this disclosure relates to a system for error checking data used in offloaded operations. The system includes a host, which includes a processor configured to configure a remote execution device to perform offloaded operations from the host's processor. The host is also configured to perform error checking on data blocks read from host memory using host-generated error checking information stored in the data blocks before copying the data blocks to the remote execution device. The host is further configured to send a request to store the data blocks in a memory area of ​​the remote execution device. The remote execution device is configured to identify the request issued by the host to store the data blocks in a memory area, the data blocks including data and host-generated error checking information for the data. The remote execution device is also configured to update the data blocks by overwriting the host-generated error checking information with locally generated error checking information for the data. The remote execution device is also configured to store the updated data blocks in a memory area.

[0014] In some embodiments, the remote execution device may be further configured to generate new data, generate error checking information for the new data, store the new data in a new data block, and store locally generated error checking information for the new data in a new memory block in the memory area, the new data block being marked to indicate that the new data was generated from an offloaded operation. In some embodiments, the remote execution device may be further configured to validate the new data using locally generated error checking information for the new data before providing the new data to the host. In these embodiments, the remote execution device may be further configured to mark an error indicator on the new data if an unrecoverable error is detected. In some embodiments, the remote execution device may be a processing-in-memory (PIM) device.

[0015] Embodiments of the present disclosure will be described in further detail, beginning with Figure 1. Figure 1 shows a block diagram of an exemplary system 100 for error checking data used in offloaded operations according to the present disclosure. The exemplary system 100 in Figure 1 includes a host device 102 coupled to a remote execution device 104, such as an accelerator, coprocessor, processing-in-memory (PIM) device, or other type of remote execution device that operates on behalf of the host processor 102 as a target for offloaded execution of a compute kernel. The host device 102 includes at least one processor 105 (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)) that executes instructions including instructions for reading and writing data to a host memory area 106, instructions for generating commands for offloaded execution by the remote execution device 104, and instructions for reading and writing data to a remote execution device memory area 108. The remote execution device memory area 108 and the host memory area 106 may be embodied in the same memory device (e.g., a chip or module) or in separate memory devices. The remote execution device 112 is coupled to the remote execution device memory area 108. The remote execution device 112 includes logic, ALUs, registers, and other components for executing the computation kernel offloaded by the host device 102. In some examples, when the computation kernel is offloaded for execution by the remote execution device 112, the data used by the kernel is copied from the host memory area 106 to the remote execution device memory area 108. In these examples, the copied data may be rearranged to provide more efficient execution of the offloaded code.

[0016] In some examples, the remote execution device 104 is a PIM-enabled memory device, such as a memory bank configured using a PIM device as the remote execution device. Therefore, this PIM-enabled memory bank may be implemented in the same memory device as other memory banks designated as host memory. In other examples, the remote execution device 104 is an accelerator or coprocessor having dedicated memory including the remote execution device memory region 108, such that the remote execution device memory region 108 and the host memory region are implemented in separate memory devices. In various examples, the remote execution device 104 is a “remote” device in that the execution logic for executing offloaded instructions (e.g., PIM commands) is not part of the processor 105. For example, the remote execution device 104 may be implemented on the same chip or in the same package as the host device 102, while remaining “remote” from the processor 105 with respect to execution locality. In some examples, the host device 102 and the remote execution device 104 of system 100 are integrated on the same chip (e.g., a system-on-chip (SoC)). In another example, system 100 implements a system-in-package (SiP) architecture in which a host device 102 and its components (e.g., as a SoC) are placed on an interposer wafer together with a remote execution device 104 in the same semiconductor package.

[0017] The memory controller 113 of the host processor 102 receives a memory request generated from an executed instruction and interprets the request as a memory command to be sent via the memory channel to the host memory area 106 and the remote execution device memory area 108. The memory interface logics 116 and 118 corresponding to the host memory area 106 and the remote execution device memory area 108, respectively, receive the command (and associated data) and satisfy the request by reading or writing the data to their respective memory areas.

[0018] To achieve the objectives of RAS, the host device 102 can use error detection and correction techniques when reading and writing data to the host memory area 106. One such technique is to generate error detection and correction information for the data being written to memory. Error detection and correction information may include error correction code (ECC), cyclic redundancy check (CRC), checksum, parity information, etc. In the example in Figure 1, it is assumed that the error correction and detection code is ECC. The ECC check bit can be stored as metadata along with the data written to the host memory area 106. Subsequently, when data is read from the host memory area 106, a check bit is generated for the retrieved data, and it is determined whether that check bit matches the check bit stored in the metadata along with the data. If there is a mismatch, there is a possibility that an error occurred when reading the data from the memory device.

[0019] Consider the example shown in Figure 1, in which the host device 102 performs an operation to write data 120 to the host memory area 106 in the memory device 140 (via the memory controller 113 and memory interface logic 116). Before issuing a write request for data 120, the host error checking module 115 applies a function to generate an ECC check bit 122 for data 120. Data 120 and the ECC check bit 122 are stored in the host memory area 106 as part of the write operation. Subsequently, when data 120 and the ECC check bit 122 are read from the host memory area 106, the error checking module 115 applies the same function to generate a new ECC check bit for data 120 and verifies the integrity of the received data 120 by comparing the new ECC check bit with the stored ECC check bit 122. If there is a mismatch, it is likely that a read error or corruption of data 120 has occurred. In some cases, the ECC check bit 122 and ECC function may be used to correct the error. Otherwise, the data may be marked as corrupted.

[0020] Continuing the above example, data 120 may be required to execute a computation kernel offloaded to the remote execution device 104. Therefore, data 120 is copied to the remote execution device memory area 108. As part of offloading the kernel, data 120 (and other data used by the kernel) is read from the host memory area 106, and an ECC check is performed by the host error checking module 115 using the ECC check bit 122 to verify the integrity of data 120 before writing data 120 and the ECC check bit 122 to the remote execution device memory area 108. However, without knowledge of the ECC scheme used by the host device 102, the remote execution device 104 cannot perform an integrity check using the ECC check bit 122 generated by the host device 102. Furthermore, without knowledge of the ECC scheme used by the host device 102, the remote execution device 104 cannot correctly update the ECC check bit 122 when the data 120 is modified by the remote execution device, and subsequent reading of the modified data with the original ECC check bit by the host device 102 is likely to cause the host error check module 115 to incorrectly identify a data reading / corruption error. Since the remote execution device 104 cannot replicate the host device 102's ECC scheme to verify the data 120 or update the host-generated ECC check bit 122, this information unnecessarily occupies metadata bits of the data 120.

[0021] According to embodiments of the present disclosure, the remote execution device 104 overwrites the host-generated ECC check bit 122 with a locally generated ECC check bit 132 generated by the remote execution device error checking module 130, and uses the locally generated ECC check bit 132 to achieve the objective of RAS when reading and writing data between the remote execution device 114 and the remote execution device memory area 108. In this way, the remote execution device 104 utilizes the space occupied by the host-generated ECC check bit 122, and as a result, no additional space allocation is required to store local error detection and correction information used to detect and correct read and write errors between the remote execution device 114 and the remote execution device memory area 108. In some embodiments, the remote execution device 104 overwrites the host-generated ECC check bit 122 with a locally generated ECC check bit 132 when data 120 is copied from the host memory area 106 to the remote execution device memory area 108. When data 120 is read from the remote execution device memory area 108 by the remote execution device 114, the ECC check bit 132 and the local ECC scheme are used to verify the integrity of data 120. If data 120 is corrected, the corrected data 120 and the updated ECC check bit 132 are written to the remote execution device memory area 108. In some examples, the ECC check bit 132 is used to verify the integrity of data 120 when data 120 is read from the remote execution device memory area 108 or copied to the host memory area 106 by the host device 102. In these examples, if an uncorrectable error is detected, the error may be marked to the host device 102 for error handling by the host device 102. In some embodiments, data 120 may be marked as containing (or potentially containing) remotely corrected data such that the bits containing ECC information are not valid ECC bits for the host-based ECC scheme.That is, the remote execution device 104 may indicate to the host device 102 that the ECC check bits included with the data 120 are not the ECC generated by the host, or that the data 120 is remotely modified data.

[0022] For further illustration, FIG. 2 shows a block diagram of another exemplary system 200 for error checking data used in offloaded operations according to the present disclosure. In the example of FIG. 2, the remote execution device described above is embodied as a PIM - compliant memory device (device) 204 that includes a PIM device (device) 210 (similar to the remote execution device 114 in FIG. 1) coupled to a PIM memory region 208 (similar to the remote execution device memory region 108 in FIG. 1). In some embodiments, the PIM memory region 208 and the host memory region 106 are separate regions (e.g., separate banks or groups of banks) of the same memory device 230, and as a result, the host memory region 106, the PIM memory region 208, and the PIM device 210 are embodied in the same chip, module, or package. In other embodiments, the PIM memory region 208 and the host memory region 106 are embodied in separate memory devices.

[0023] In the example in Figure 2, the PIM device 210 includes a command buffer 212 that stores the kernel of a computation instruction offloaded from the host device 102 for remote execution on the PIM-enabled memory device 204. The PIM device also includes a PIM ALU 216 for executing instructions in the computation kernel and a PIM register file 218 for temporarily holding operands and the results of their operations. When the host device 102 configures the PIM-enabled memory device 204 to execute the kernel, the host device 102 writes the kernel to the command buffer 212 and copies the data used by the kernel from the host memory area 106 to the PIM memory area 208. The data copied to the PIM memory area may be rearranged by the host device 102 so that the data in the PIM memory area is organized into the address space used by the computation kernel. The PIM device 210 also includes PIM control logic 214, such as a program counter and a scheduler, to facilitate the execution of the computation kernel. As an example, and not an limitation, the PIM-enabled memory device 204 may be configured with a kernel for loading data from a location in the PIM memory area 208 into register r0 of the PIM register file 218, and for loading data received from the host device 102, calculated by the host processor 105, into register r1 of the PIM register file 218. In this example, the PIM ALU 216 adds the value of register r1 to the value of register r0 and stores the result in register r0. Next, the result from register r0 is written back to that location in the PIM memory area 208.

[0024] As described above, when the host device 102 reads the data block 260 from the host memory area 106 for copying to the PIM memory area 208, the host device 102 uses the ECC check bits 268 generated by the host and the host's ECC method in the ECC part 266 of the data block 260 to verify the integrity of the data 262 in the data part 264 of the data block 260. If the host device 102 identifies an uncorrectable error when verifying the integrity of the data 262, a poison bit for the data can be set in the data block 260 for processing by the PIM - compliant memory device 204. In some examples, when writing the data block 260 to the PIM memory area 208, the data block 260 is marked as containing PIM data (e.g., in control information). As used herein, "PIM data" is data used by the PIM - compliant memory device 204 to perform PIM operations.

[0025] When the data block 260 is copied to the PIM memory area 208, the PIM error - checking module 220 generates PIM ECC check bits 274 for the data 262 using the PIM ECC method and writes the PIM ECC check bits 274 to the ECC part 266 of the data block 260. When the data 262 is read from the PIM memory area 208 into a register of the PIM register file 218 of the PIM device 210, the PIM error - checking module 220 verifies the integrity of the data 262 using the PIM ECC check bits 274. When new or modified data is written from a register of the PIM register file 218 of the PIM device 210 to the data block 260 in the PIM memory area 208, the PIM error - checking module 220 generates updated PIM ECC check bits 274 to be written to the data block 260.

[0026] When data block 260 is read from the PIM memory area 208 by the host device, the PIM error checking module 220 verifies the integrity of data 262 using the PIM ECC check bit 274. If the PIM-enabled memory device 204 identifies an uncorrectable error when verifying the integrity of data 262, a poison bit for the data may be set in data block 260 for processing by the host device 102. Data block 260 is marked to contain PIM data and / or PIM ECC check bits so that the host device 102 recognizes that it should not rely on the ECC check bits of the ECC portion 266.

[0027] For further explanation, Figure 3 shows a flowchart illustrating an exemplary method for error checking data used in offloaded operations according to this disclosure. The example in Figure 3 includes a host 302 which may be similar to the host device 102 described above with reference to Figures 1 and 2. The host 302 shown in Figure 3 may include the same, fewer, or additional components as the storage system described above. The example in Figure 3 also includes a remote execution device 304 which may be similar to the remote execution device 104 or PIM-enabled memory device 204 described above with reference to Figures 1 and 2. The remote execution device 304 shown in Figure 3 may include the same, fewer, or additional components as the storage system described above. In some examples, the remote execution device 304 includes a memory area coupled to a processing unit configured to perform operations offloaded from the host. In some embodiments, the remote execution device 304 is a PIM-enabled memory device such as a PIM-enabled memory device 204, which is embodied in a memory device such as a memory device 230, as described above with reference to Figure 2. Many of the following examples are explained in the context of PIM-enabled memory devices, but readers should understand that these examples can also be implemented in the context of accelerators or coprocessors that are not embodied within a memory device.

[0028] As described above, when host 302 initiates remote execution of an operation offloaded from the processor, the compute kernel and the data targeted by the compute kernel are copied to the remote execution device 304. Specifically, one or more data blocks used by the offloaded operation are copied to the memory area of ​​the remote execution device 304. For example, host 302 issues a request to write one or more data blocks to a memory area coupled to the remote processing unit. In a particular example, host 302 initiates offloading a PIM compute kernel, which includes a request to write one or more data blocks from the host memory area to the PIM memory area. In this example, the request is received by the memory control logic in the PIM-enabled memory device containing the PIM memory area. One or more data blocks include data and metadata, and may also include control bits containing error checking information. For example, the error checking information may include several ECC check bits for the data.

[0029] The method in Figure 3 includes identifying a request issued by a host to store a data block in a memory area, wherein the data block includes data and host-generated error checking information for the data. In some examples, identifying a request issued by a host to store a data block in a memory area, wherein the data block includes data and host-generated error checking information for the data, is performed when a remote execution device 304 receives a request to write the data block to a remote processing device memory area coupled to the processing unit. In some embodiments, the host initiates a copy operation in which the data block is copied from a host memory area to a memory area, using host-based error checking technology. In host-based error checking technology, the host generates error checking information for the data and stores the error checking information together with the data in the data block. For example, the error checking information may be ECC information such as check bits. In some examples, the process includes identifying a request issued by a host to store a data block in a memory area, wherein the data block includes data and host-generated error detection information for the data, and identifying that the host-generated error checking information may be overwritten by locally generated error checking information. Identifying that the host-generated error checking information may be overwritten by locally generated error checking information may be done based on the memory area to which the request is directed, or through inference based on control information in the data block.

[0030] In certain examples where the remote execution device is a PIM-enabled memory device, the host initiates a copy operation to copy data blocks from the host memory area to the PIM memory area. The PIM-enabled memory device receives a request to write the data blocks to the PIM memory area and receives the data blocks in the write buffer. The data blocks copied from the host memory area include error checking information generated by the host. In some examples, the data blocks may include control information indicating that the data blocks contain PIM data.

[0031] Furthermore, the method in Figure 3 includes updating the data block 308 by overwriting the host-generated error detection information with locally generated error checking information for the data. In some examples, updating the data block 308 by overwriting the host-generated error detection information with locally generated error checking information for the data is performed by an error checking module in the remote execution device 304 generating error checking information for the data in the data block. For example, the locally generated error detection information may be ECC check bits encoded using a local ECC scheme different from the host-based ECC scheme. In these examples, updating the data block 308 by overwriting the host-generated error detection information with locally generated error checking information for the data is further performed by storing the locally generated error detection information at a location in the data block occupied by the host-generated error checking information. For example, host-based ECC check bits in the data block are replaced with locally generated ECC check bits. Thus, the error checking information used by the remote execution device is generated for the data in the data block without allocating additional space in the memory area for the data block and without requiring separate storage for the error checking information.

[0032] In a specific example where the remote execution device 304 is a PIM-enabled memory device (e.g., PIM-enabled memory device 204 in Figure 2), the PIM-enabled memory device updates the data block by overwriting the host-generated error detection information with error checking information generated by an error checking module in the PIM-enabled memory device that generates ECC check bits using a PIM-based ECC scheme different from the host-based ECC scheme. For example, the PIM-enabled memory device overwrites the host-generated ECC check bits with PIM ECC check bits while the data block is in the write buffer. In some examples, the PIM-enabled memory device automatically overwrites the host-generated ECC check bits with PIM ECC check bits in response to a request to write data to the PIM memory area. In other examples, the PIM-enabled memory device overwrites the host-generated ECC check bits with PIM ECC check bits based on control information in the data block indicating that the data block contains PIM data or that the host-generated ECC check bits may be overwritten.

[0033] Furthermore, the method in Figure 3 includes storing the updated data block in a memory area 310. In some examples, storing the updated data block in a memory area 310 is performed by the remote execution device 304, which stores the data block, in which locally generated error checking information replaces the error checking information generated by the host, in a memory area coupled to the processing unit in the remote execution device 304. In a specific example, a PIM-enabled memory device stores the updated data block, which includes PIM ECC check bits instead of host-generated ECC check bits, in a PIM memory area coupled to the PIM device.

[0034] For further explanation, Figure 4 shows a flowchart illustrating an exemplary method for error checking data used in offloaded operations as described herein. Similar to the exemplary method in Figure 3, the method in Figure 4 includes identifying a request issued by a host to store a data block in a memory area, wherein the data block includes data and host-generated error checking information for the data, 306 updating the data block by overwriting the host-generated error detection information with locally generated error checking information for the data, 308 and storing the updated data block in a memory area, 310.

[0035] Furthermore, the method in Figure 4 includes identifying an error indicator provided by the host in the data block 402. As described above, with respect to the host devices in Figures 1 and 2, the host 302 can read one or more data blocks from the host memory area and perform error checking on the data blocks before writing the data blocks to the remote execution device memory area. If the host 302 encounters an uncorrectable error in the data block, the data block is marked with an error. For example, the host 302 marks the data block with a poison bit. In some examples, identifying an error indicator provided by the host in the data block 402 is performed by the remote execution device 304 detecting a marker in the data block included by the host 302. For example, the marker may be a poison bit.

[0036] For further explanation, Figure 5 shows a flowchart illustrating an exemplary method for error checking data used in offloaded operations as described herein. Similar to the exemplary method in Figure 3, the method in Figure 5 includes identifying a request issued by a host to store a data block in a memory area, wherein the data block includes data and host-generated error checking information for the data, 306 updating the data block by overwriting the host-generated error detection information with locally generated error checking information for the data, 308 and storing the updated data block in a memory area, 310.

[0037] Furthermore, the method in Figure 5 includes verifying the data using locally generated error checking information when reading the updated data block from the memory area to the processing unit 502. In some examples, verifying the data using locally generated error checking information when reading the updated data block from the memory area to the processing unit 502 is performed in response to the processing unit performing an operation to read the data from the remote execution device memory area into the processing unit's registers. In some examples, verifying the data using locally generated error checking information when reading the updated data block from the memory area to the processing unit 502 is performed by an error checking module in the remote execution device 304 decoding the error checking information, generating error checking information for the data in the data block using a local error checking scheme, and comparing the generated error checking information with the error checking information stored in the data block. For example, the remote execution device 304 may use a local ECC scheme to generate ECC check bits for the data in the data block and compare the generated ECC check bits with the stored ECC check bits in the data block. If an error is encountered, the remote execution device 304 may attempt to correct the error using error checking information.

[0038] In a specific example where the remote execution device is a PIM-enabled memory device (e.g., the PIM-enabled memory device 210 in Figure 2), the validation of the data using locally generated error checking information when reading an updated data block from the memory area to the processing unit is performed when the PIM device encounters a PIM operation to load PIM data from the PIM memory area. When the PIM device reads data from the data block into registers in the PIM register file, the PIM error checking module generates an ECC check bit for the data and compares the generated ECC check bit with the ECC check bit in the data block. If an error is encountered, the PIM device attempts to correct the error in the data before reading the data into the register. If the error cannot be corrected, the load operation is aborted and the data is marked as corrupted.

[0039] For further explanation, Figure 6 shows a flowchart illustrating an exemplary method for error checking data used in offloaded operations as described herein. Similar to the exemplary method in Figure 5, the method in Figure 6 includes identifying a request issued by a host to store a data block in a memory area, wherein the data block includes data and host-generated error checking information for the data; updating the data block by overwriting the host-generated error detection information with locally generated error checking information for the data; storing the updated data block in a memory area; and verifying the data using locally generated error checking information when reading the updated data block from the memory area to a processing unit.

[0040] Furthermore, the method in Figure 6 includes generating new data by the processing unit 602. In some examples, generating new data by the processing unit 602 is performed by the processing unit in the remote execution device 304 generating data by performing an operation offloaded by the host 302. In these examples, generating new data may include modifying data in an updated data block or generating data. The new data resulting from the operation is temporarily stored in a register in the processing unit. In a specific example where the remote execution device 304 is a PIM-enabled memory device (e.g., the PIM-enabled memory device 210 in Figure 2), generating new data by the processing unit 602 is performed by the PIM processing unit performing a PIM operation offloaded from the host 302 to generate PIM data. The PIM operation modifies data in a PIM register loaded from the PIM memory area, and the result is stored in the PIM register or a different PIM register.

[0041] Furthermore, the method in Figure 6 includes generating error checking information for the new data 604. In some examples, generating error checking information 604 is performed by an error checking module in the remote execution device 304 generating error checking information for the new data. For example, the error checking module may use an ECC scheme to generate ECC check bits for the new data. In a specific example where the remote execution device 304 is a PIM-enabled memory device (e.g., the PIM-enabled memory device 210 in Figure 2), generating error checking information 604 is performed by a PIM error checking module calculating new ECC check bits for the PIM data resulting from the PIM operation.

[0042] Furthermore, the method in Figure 6 involves storing the new data and locally generated error checking information for the new data in a new memory block in the memory area 606, and the new data block is marked to indicate that the new data was generated from an offloaded operation. In some examples, storing the new data and locally generated error checking information for the new data in a new memory block in the memory area 606, and the new data block is marked to indicate that the new data was generated from an offloaded operation 606 is performed by the remote execution device 304 writing the new data, along with the generated error checking information for the new data, from the registers of the processor to the data block in the memory area coupled to the processor. For example, the new data block includes the new data generated from the offloaded operation and the ECC check bits calculated for the new data. The new data block may be written from the registers in the processor to the address of the same memory area as the updated data block, and thus may overwrite the updated data block, or the new data block may be written to a different address. The new data block is marked to indicate that the data in the data block was generated from an offloaded operation. Therefore, when the host subsequently reads the data, it can recognize that the new data block does not contain the error checking information generated by the host. In some examples, marking a new data block to indicate that the data in the data block was generated from an offloaded operation is done by setting control bits in the new data block.

[0043] In a particular example where the remote execution device 304 is a PIM-enabled memory device (e.g., the PIM-enabled memory device 210 in Figure 2), storing new data and locally generated error checking information for the new data in a new memory block of the memory area 606, wherein the new data block is marked to indicate that the new data was generated from an offloaded operation, is performed by the PIM-enabled memory device writing the PIM data, along with the PIM ECC check bits, from the PIM register to the new data block of the PIM memory area. The new data block is marked to contain PIM data, for example, by setting control bits in the new data block.

[0044] For further explanation, Figure 7 shows a flowchart illustrating an exemplary method for error checking data used in offloaded operations as described herein. Similar to the exemplary method in Figure 6, the method in Figure 7 includes identifying a request issued by a host to store a data block in a memory area, wherein the data block includes data and host-generated error checking information for the data, 306; updating the data block by overwriting the host-generated error detection information with locally generated error checking information for the data, 308; storing the updated data block in a memory area, 310; verifying the data using locally generated error checking information when reading the updated data block from the memory area to the processor, 502; generating new data by the processor, 602; generating error checking information for the new data, 604; and storing the new data and locally generated error checking information for the new data in a new memory block in the memory area, 606, wherein the new data block is marked to indicate that the new data was generated from offloaded operations, 606.

[0045] Furthermore, the method in Figure 7 includes verifying the new data using locally generated error checking information for the new data before providing the new data to the host 702. In some examples, verifying the new data using locally generated error checking information for the new data before providing the new data to the host 702 is performed by an error checking module in the remote execution device 304 using a local error checking scheme to generate error checking information for the data in the new data block and comparing the generated error checking information with the error checking information stored in the new data block. For example, the remote execution device 304 generates ECC check bits for the data in the data block and compares the generated ECC check bits with the stored ECC check bits in the data block. If an error is encountered, the remote execution device 304 may attempt to correct the error using the error checking information. In some examples, verifying the new data using locally generated error checking information for the new data before providing the new data to the host 702 is performed upon completion of an offloaded operation or upon a read request. In some examples, providing the new data to the host is performed by directly copying the data from the remote execution device memory area to the host memory area. In other examples, providing new data to the host is performed by sending data to the host in response to a read request. In some embodiments, providing new data to the host includes providing an entire data block containing data, control information, and locally generated error checking information. In other embodiments, providing new data to the host includes providing only data and control information.

[0046] In certain examples where the remote execution device is a PIM-enabled memory device (e.g., PIM-enabled memory device 210 in Figure 2), verifying the new data using locally generated error checking information for the new data before providing the new data to the host 702 is performed by the PIM error checking module generating ECC check bits for the data and comparing the generated ECC check bits with the ECC check bits in the data block. If an error is encountered, the PIM device attempts to correct the error in the data before providing the new data to the host. In some examples, providing the new data to the host is performed by directly copying the data from the PIM memory area to the host memory area. In other examples, providing the new data to the host is performed by sending the data to the host in response to a read request.

[0047] For further explanation, Figure 8 shows a flowchart illustrating an exemplary method for error checking data used in offloaded operations as described in this disclosure. Similar to the exemplary method in Figure 7, the method in Figure 8 includes identifying a request issued by a host to store a data block in a memory area, wherein the data block includes data and host-generated error checking information for the data, 306; updating the data block by overwriting the host-generated error detection information with locally generated error checking information for the data, 308; storing the updated data block in a memory area, 310; verifying the data using locally generated error checking information when reading the updated data block from the memory area to the processor, 502; the processor generating new data, 602; generating error checking information for the new data, 604; and storing the new data and locally generated error checking information for the new data in a new memory block in the memory area, wherein the new data block is marked to indicate that the new data was generated from an offloaded operation, 606; and verifying the new data using locally generated error checking information for the new data before providing the new data to the host, 702.

[0048] Furthermore, the method in Figure 8 includes marking an error indicator 802 in the new data if an unrecoverable error is detected. If the remote execution device 304 cannot correct an error found when verifying the new data using locally generated error checking information, the error is unrecoverable and therefore the data block or part of the data block is corrupted. In some examples, marking an error indicator 802 in the new data if an unrecoverable error is detected is performed by the remote execution device 304 indicating within the data block that the data or part of it is corrupted. For example, the new data block may be marked with a poison bit to indicate that the data in the data block is corrupted. The host can then read this data block from the host memory area and recognize the indicator that the data is corrupted, and can handle the error. In a specific example where the remote execution device is a PIM-enabled memory device (e.g., the PIM-enabled memory device 210 in Figure 2), marking an error indicator 802 in the new data if an unrecoverable error is detected is performed by the PIM-enabled memory device marking the data block containing the PIM data as corrupted.

[0049] For further explanation, Figure 9 shows a flowchart illustrating an exemplary method for error checking data used in offloaded operations as described herein. Similar to the exemplary method in Figure 3, the method in Figure 9 includes identifying a request issued by a host to store a data block in a memory area, wherein the data block includes data and host-generated error checking information for the data, 306 updating the data block by overwriting the host-generated error detection information with locally generated error checking information for the data, 308 and storing the updated data block in a memory area, 310.

[0050] Furthermore, the method in Figure 9 includes configuring the remote execution device 902 to perform operations offloaded from the host processor. In some examples, configuring the remote execution device 902 to perform operations offloaded from the host processor is performed by the host 302 offloading the compute kernel to the remote execution device 304, as described above. In a specific example where the remote execution device is a PIM-enabled memory device (e.g., the PIM-enabled memory device 210 in Figure 2), configuring the remote execution device 902 to perform operations offloaded from the host processor is performed by configuring the PIM device of the PIM-enabled memory device with PIM commands.

[0051] Furthermore, the method in Figure 9 includes performing an error check on the data block read from host memory using host-generated error checking information stored in the data block before copying the data block to the remote execution device 904. In some examples, performing an error check on the data block read from host memory using host-generated error checking information stored in the data block before copying the data block to the remote execution device 904 is performed by an error checking module generating error checking information for the data in the data block and comparing the generated error checking information for the data with the error checking information stored in the data block. For example, the error checking module may generate ECC check bits for the data using a host-based ECC scheme and compare the generated ECC check bits with the ECC check bits stored in the data block. If an error is encountered, the PIM device attempts to correct the error in the data before writing the data block to the remote execution device memory area.

[0052] In some embodiments, before copying the data block to the remote execution device, error checking 904 is performed on the data block read from host memory using host-generated error checking information stored in the data block, and if an unrecoverable error is detected, error indicators 802 are marked on the data block. In some examples, marking error indicators 802 on the data block if an unrecoverable error is detected is performed by the host 302 indicating within the data block that the data or part thereof is corrupted. For example, the data block may be marked with a poison bit to indicate that the data in the data block is corrupted. When the remote execution device 304 receives this data block, the remote execution device can recognize the indicator that the data is corrupted and process the error.

[0053] Furthermore, the method in Figure 9 includes sending a request 906 to store the data block in the memory area of ​​the remote execution device. In some examples, sending a request 906 to store the data block in the memory area of ​​the remote execution device is performed by the host 302 issuing a write request for the data block directed to the memory area of ​​the remote execution device 304. In a specific example where the remote execution device is a PIM-enabled memory device (e.g., the PIM-enabled memory device 210 in Figure 2), the host 302 issues a write request to the PIM-enabled memory device to store the data block in the PIM memory area.

[0054] Some embodiments may be systems, devices, methods, and / or logic circuits. The computer-readable program instructions of this disclosure may be any of the following: assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, source code or object code written in any combination of one or more programming languages, such as object-oriented programming languages ​​like Smalltalk and C++, and conventional procedural programming languages ​​such as the C programming language or similar programming languages. In some embodiments, for example, electronic circuits including programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may execute computer-readable program instructions by individualizing the electronic circuits using state information of the computer-readable program instructions.

[0055] Aspects of this disclosure are described herein with reference to flow diagrams and / or block diagrams of methods, apparatus (systems) and logic circuits according to some embodiments of this disclosure. It will be understood that each block in the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by logic circuits.

[0056] Furthermore, logic circuits can be implemented in a processor, other programmable data processing device, or other device to perform a series of operational steps executed on the processor, other programmable device, or other device in order to generate a computer implementation process, and so the instructions executed on the computer, other programmable device, or other device perform the functions / actions specified in the blocks of the flow diagram and / or block diagram.

[0057] The flow diagrams and block diagrams in the figures illustrate the architecture, function, and operation of possible embodiments of the systems, methods, and logic circuits according to various embodiments of the present disclosure. In this regard, each block in a flow diagram or block diagram may represent a module, segment, or portion of instructions containing one or more executable instructions for implementing a specified logic function. In some alternative embodiments, the functions described in a block may occur in a different order than shown in the figure. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or blocks may be executed in reverse order depending on the functions involved. It should also be noted that each block in a block diagram and / or flow diagram, and combinations of blocks in a block diagram and / or flow diagram, may be implemented by a dedicated hardware-based system that performs a specified function or action, or combines dedicated hardware with computer instructions.

[0058] While this disclosure has been specifically illustrated and described with reference to its embodiments, it should be understood that various modifications may be made in form and detail without departing from the spirit and scope of the following claims. Therefore, the embodiments described herein are for illustrative purposes only and do not limit the invention. This disclosure is defined by the appended claims rather than the detailed description, and all differences within that scope should be construed as being included within the invention.

Claims

1. A device for error checking data used in offloaded operations, wherein the device is A processing unit configured to perform operations offloaded from the host, A memory area coupled to the aforementioned processing device, Equipped with logic circuits, The aforementioned logic circuit is Identifying a request issued by the host to store a data block in the memory area, wherein the data block includes data and error checking information generated by the host for the data. The data block is updated by overwriting the error checking information generated by the host included in the data block with error checking information locally generated by the error checking module in the memory area for the data. The updated data block is stored in the memory area, It is configured to do, Device.

2. The logic circuit is configured to identify an error indicator provided by the host in the data block. The apparatus according to claim 1.

3. The logic circuit is configured to verify the data using the locally generated error checking information when reading the updated data block from the memory area to the processing unit. The apparatus according to claim 1.

4. The aforementioned logic circuit is To generate error checking information for the new data generated by the aforementioned processing device, The new data is stored in a new data block, and locally generated error checking information for the new data is stored in a new memory block in the memory area, wherein the new data block is marked to indicate that the new data was generated from an offloaded operation. It is configured to do, The apparatus according to claim 1.

5. The logic circuit is configured to verify the new data using locally generated error checking information before providing the new data to the host. The apparatus according to claim 4.

6. The logic circuit is configured to mark an error indicator on the new data when an unrecoverable error is detected. The apparatus according to claim 5.

7. The aforementioned device is a processing-in-memory (PIM) device. The apparatus according to claim 1.

8. A system for error checking data used in offloaded operations, Equipped with a host including a processor, The aforementioned host, Configuring a remote execution device to perform operations offloaded from the aforementioned processor, Error checking of data blocks read from host memory is performed using error checking information generated by the host and stored in the data blocks, before copying the data blocks to the remote execution device. Sending a request to store the data block in the memory area of ​​the remote execution device, It is configured to do the following: The aforementioned remote execution device, Identifying the request issued by the host to store a data block in the memory area, wherein the data block includes data and error checking information generated by the host for the data. The data block is updated by overwriting the error checking information generated by the host with locally generated error checking information for the data. The updated data block is stored in the memory area, It is configured to do, system.

9. The aforementioned remote execution device, Generating new data, To generate error checking information for the aforementioned new data, The new data is stored in a new data block, and locally generated error checking information for the new data is stored in a new memory block in the memory area, wherein the new data block is marked to indicate that the new data was generated from an offloaded operation. It is configured to do, The system according to claim 8.

10. The remote execution device is configured to validate the new data using locally generated error checking information before providing the new data to the host. The system according to claim 9.

11. The remote execution device is configured to mark an error indicator on the new data if an unrecoverable error is detected. The system according to claim 10.

12. The remote execution device is a processing-in-memory (PIM) device. The system according to claim 8.

Images