Data transmission method and data transmission device

Abstract

An embodiment of this application provides a data transmission method and a data transmission device. The data transmission method includes the steps of generating a bit stream, the bit stream including data and a control word, the control word including a first field indicating start position information of the control word, a second field indicating end position information of the control word, and a third field used to carry link information indicating a wired serial link, and transmitting the bit stream on a wired serial link. The data transmission method can reduce the complexity of a control signal transmitted at a physical layer.

Description

Technical Field

[0001] Embodiments of this application relate to the field of communication networks, and more particularly, to data transmission methods and data transmission devices.

Background Art

[0002] In communication network technology, communication devices typically communicate with each other over a data link. The physical layer at the signal transmission end transmits a bit stream over the link to the physical layer at the signal receiving end for signal exchange between communication devices. The bit stream includes both an encoded data signal and a plurality of control signals indicating information such as link configuration or link state, thereby enabling the signal receiving end to accurately decode the data from the bit stream. For example, the plurality of control signals includes a control signal indicating the frame delimiter of a data packet and a control signal indicating the link bandwidth. The plurality of control signals are independent encoded segments. Further, the plurality of control signals are typically added to specific positions of the data signal for transmission.

[0003] However, due to the continuous development of the operating rate at the physical layer and more accurate control over the link, more control signals need to be set to meet the requirements. As a result, the amount of control signals increases, thereby complicating the design of the physical layer in the communication device and increasing the cost of the physical layer. Therefore, how to reduce the complexity of the control signals transmitted at the physical layer becomes a problem to be solved.

Summary of the Invention

[0004] According to the data transmission method and data transmission device provided in this application, the complexity of the control signals transmitted at the physical layer can be reduced. To achieve the above object, the following technical solutions are used in this application.

[0005] According to a first aspect, an embodiment of the present application provides a data transmission method. The data transmission method is applied at a transmitting end and includes the steps of generating a bitstream, the bitstream comprising data and a control word, the control word comprising a first field indicating the start position information of the control word, a second field indicating the end position information of the control word, and a third field used to carry link information indicating a wired serial link, and transmitting the bitstream over a wired serial link.

[0006] In this implementation, the transmitting end may be, for example, the interface controller shown in Figures 1, 4A, 4B, and 5. The first field indicating the start position information of the control word may be, for example, the start field shown in Figure 2. The second field indicating the end position information of the control word may be, for example, the end field shown in Figure 2. The third field used to carry link information indicating a wired serial link may be, for example, the payload field shown in Figure 2.

[0007] In conventional wired serial links, encoded segments are typically used to transmit data between two communication devices, achieve link alignment, and transfer various information about the link, with one type of information constituting one encoded segment. For example, information indicating link power consumption is encoded in one segment, and information indicating the state of each circuit in the link is encoded in another. In other words, multiple encoded segments exist to achieve link alignment. However, with the continuous evolution of operating rates at the physical layer and the need for more precise control on the link, more link information needs to be configured to meet the requirements. As a result, the amount of link information increases, i.e., the number of encoded segments increases, which complicates the design of the physical layer in the communication device and increases the design cost of the physical layer. The control word provided in this embodiment of this application is configured to include a first field, a second field, and a third field, with the third field carrying the link information. This enables one control word to represent multiple pieces of link information, reducing the complexity of the control signals transmitted at the physical layer and simplifying the design at the physical layer. Furthermore, since the second field within the control word indicates the end position information of the control word, that is, the second field within the control word may limit the length of the control word. Moreover, by flexibly adjusting the end position information of the control word, the amount of link information carried by the control word can be flexibly adjusted, thereby providing flexibility to the control word.

[0008] Optionally, the end position information may be the length of the control word or the end position. The end position may be, for example, a position after a predetermined number of bits starting from the second field.

[0009] The data can be either service data or training data, at the user's discretion.

[0010] In possible implementations, the link information is as follows: ,This includes at least one of the following: the number of lanes for transmitting the stream, the power consumption state of the hardware in the link, the operating state of the circuitry in the link, or the gain of the codec used in the link.

[0011] To reduce the power consumption of hardware in a link at the physical layer, the power consumption of each piece of hardware in a link typically includes multiple types, such as low power consumption, medium power consumption, and high power consumption. For example, when hardware such as scramblers and data distributors included in a link are in one of the following modes, namely standby, sleep, or powered off, the hardware in the link is in a low power consumption state. When some of the hardware included in a link is in one of the following modes, namely standby, sleep, or powered off, and the other parts of the hardware are in an operational state, the hardware in the link is in a medium power consumption state. When all components in a link are in an operational state, the hardware in the link is in a high power consumption state. For example, when the data being transmitted is training data, this may indicate that the power consumption of each piece of hardware in the link is low power consumption. When the data being transmitted is service data, this may indicate that the power consumption of each piece of hardware in the link is medium power consumption or high power consumption. The operating state of the circuitry in a link may include, for example, a powered-on state or a powered-off state. For example, when the transmitted data is training data, the codec circuit may be in a power-off state. When the transmitted data is service data, the codec circuit may be in a power-on state. Therefore, the transmitting end may add information such as one of several power consumption states, information indicating the operating state of one of the circuits in the link, and information indicating the gain of the codec to a third field and transmit the information to the receiving end.

[0012] In possible implementations, the first and second fields instruct the receiving end to perform frame delimiter on the data.

[0013] In this possible implementation, the control word may be followed by the data content of the data. In other words, the first and second fields within the control word may be used as the frame header of the data frame. After identifying the first and second fields within the control word, the receiving end may determine the starting position of the data (i.e., the frame delimiter) and read the data from the bitstream. In this embodiment of the application, the first and second fields within the control word are used as the frame header of the data frame, thereby eliminating the need to further set the frame header of the data frame. This simplifies the bitstream design.

[0014] In possible implementations, multiple bitstreams exist, multiple lanes exist on a wired serial link, the multiple bitstreams correspond one-to-one with the multiple lanes, and the step of transmitting a bitstream on a wired serial link specifically includes the step of transmitting the corresponding multiple streams through the multiple lanes.

[0015] When multiple lanes exist on a wired serial link, one control word is assigned to each lane, allowing the receiving end to accurately read data from the bitstream transmitted on each lane based on the control word within that lane. This improves the data reading accuracy at the receiving end.

[0016] In possible implementations, the control word further includes a fourth field indicating the lane number.

[0017] The fourth field may be, for example, the lane identifier field shown in Figure 2.

[0018] In this implementation, a fourth field is set within the control word that indicates the lane number, allowing the receiving end to adjust the sequence of data received from each lane based on each lane number. This improves the accuracy of the data received by the receiving end.

[0019] In a possible implementation, the first field contains multiple groups of the same field, each group of the field containing multiple bits. These multiple groups of the same field are used to compensate for the difference between the clock cycle at the transmitting end and the clock cycle at the receiving end.

[0020] In this implementation, the transmitting end may encode the first field into a sequence of "0" and "1" signals and then transmit the bitstream to the receiving end based on the local clock cycle over a wired serial link. After receiving the bitstream, the receiving end first reconstructs the transmitting end's clock cycle from the first field, and then, based on the offset between the reconstructed clock cycle and the local cycle, adds at least one group of fields to a group of multiple identical fields, or removes at least one group of fields from a group of multiple identical fields.

[0021] For example, a buffer queue may be located at the receiving end, and the receiving end writes the data carried in the first field to the buffer queue based on the clock cycle recovered from the first field. Furthermore, the receiving end may read more data from the buffer queue based on the local clock cycle. The two operations are performed simultaneously. When the receiving end detects that the rate at which data is written to the buffer queue is greater than the rate at which data is read from the buffer queue, this indicates that the clock cycle at the transmitting end is greater than the clock cycle at the receiving end. In this case, at least one group of fields is removed from the group of multiple identical fields contained in the first field to ensure clock cycle synchronization between the transmitting and receiving ends. When the receiving end detects that the rate at which data is written to the buffer queue is less than the rate at which data is read from the buffer queue, this indicates that the clock cycle at the transmitting end is less than the clock cycle at the receiving end. In this case, at least one group of fields is added to the first field from the group of multiple identical fields to achieve clock cycle synchronization between the transmitting and receiving ends.

[0022] In the prior art, since no structured control word is set, a dedicated sequence to compensate for the difference between the transmitting end's clock cycle and the receiving end's clock cycle is typically set within the transmitted bitstream, and this sequence carries no useful data. In this embodiment of the application, a group of multiple identical fields is set in the first field of the control word, thereby enabling the control word to perform more functions. In other words, a dedicated sequence to compensate for the difference between the transmitting end's clock cycle and the receiving end's clock cycle does not need to be further set within the bitstream. Compared to the prior art, the design at the physical layer can be simplified.

[0023] In a possible implementation, when the data is training data, the step of generating the bitstream includes the step of generating the bitstream by adding a control word after the data.

[0024] According to a second aspect, an embodiment of the present application provides a data transmission method. The data transmission method is applied at a receiving end and includes the steps of receiving a bitstream, the bitstream comprising data and a control word, the control word comprising a first field indicating the start position information of the control word, a second field indicating the end position information of the control word, and a third field used to carry link information indicating a wired serial link; reading the control word from the bitstream based on the first and second fields; and reading data from the bitstream based on the control word.

[0025] In this implementation, the receiving end may be, for example, the network interface card shown in Figures 1, 4A, 4B, and 5. The first field indicating the start position information of the control word may be, for example, the start field shown in Figure 2, the second field indicating the end position information of the control word may be, for example, the end field shown in Figure 2, and the third field used to carry link information indicating a wired serial link may be, for example, the payload field shown in Figure 2.

[0026] The control word provided in this embodiment of this application is configured to include a first field, a second field, and a third field, with the third field carrying link information. This enables a single control word to represent multiple link pieces of information, simplifying the design at the physical layer. Furthermore, since the second field in the control word indicates the end position information of the control word, i.e., the second field in the control word may limit the length of the control word. Moreover, by flexibly adjusting the end position information of the control word, the amount of link information carried by the control word can be flexibly adjusted, providing flexibility to the control word.

[0027] In a possible implementation manner, the method further includes the step of adjusting at least one of the wired serial links based on link information, that is, the power consumption state of the hardware in the link, the operating state of the circuit in the link, or the gain of the codec used in the link.

[0028] To reduce the power consumption of the hardware in the link at the physical layer, the power consumption of each hardware in the link usually includes multiple types, for example, low power consumption, medium power consumption, and high power consumption. For example, when the data to be transmitted is training data, this may indicate that the power consumption of each hardware in the link is low power consumption. When the data to be transmitted is service data, this may indicate that the power consumption of each hardware in the link is medium power consumption or high power consumption. The operating state of the circuit in the link may include, for example, the power-on state or the power-off state. For example, when the data to be transmitted is training data, the state of the codec circuit may be the power-off state. When the data to be transmitted is service data, the state of the codec circuit may be the power-on state. The receiving end adjusts the power consumption state of the hardware in the link to the power consumption state indicated by the third field, adjusts the operating state of the circuit in the link to the operating state indicated by the third field, and adjusts the gain of the codec to the gain indicated by the third field based on one of the multiple power consumption states indicated by the third field, one operating state of the circuit in the link, and the gain of the codec.

[0029] In a possible implementation manner, the step of reading data from a bitstream based on a control word includes: determining the coding length of the control word based on a first field and a second field; identifying the frame start position of the data from the bitstream based on the coding length of the control word, where the frame start position of the data is located after the control word; and reading the data based on the frame start position of the data.

[0030] In this possible implementation manner, the control word may be followed by the data content of the data. In other words, the first field and the second field in the control word may be used as the frame header of the data frame. After identifying the first field and the second field in the control word, the receiving end may determine the start position of the data and read the data from the bitstream. In this embodiment of this application, the first field and the second field in the control word are used as the frame header of the data frame, so that there is no need to further set the frame header of the data frame. This can simplify the design of the bitstream.

[0031] In a possible implementation manner, there are multiple bitstreams, there are multiple lanes on a wired serial link, the multiple bitstreams are received from a transmitting end through multiple corresponding lanes, the link information further includes the number of lanes for transmitting the multiple bitstreams, and the control word further includes a fourth field indicating a lane number. The step of reading data from the bitstream based on the control word includes reading the data from the bitstream received through the corresponding lane based on the number of lanes for transmitting the bitstream and the fourth field.

[0032] The fourth field may be, for example, the lane identifier field shown in FIG. 2.

[0033] In a possible implementation, the method further includes the step of removing data skew between multiple lanes based on a sequence of multiple received bitstreams and a fourth field in each of the multiple control words within the multiple bitstreams.

[0034] In a possible implementation, the first field includes a group of multiple identical fields, each group of fields including multiple bits. The method further includes the step of performing one of the following operations based on a clock frequency offset between the receiving and transmitting ends: removing at least one group of fields from a group of multiple identical fields, or adding at least one group of fields to a group of multiple identical fields.

[0035] In this implementation, the transmitting end may encode the first field into a sequence of "0" and "1" signals and then transmit the bitstream to the receiving end based on the local clock cycle over a wired serial link. After receiving the bitstream, the receiving end first reconstructs the transmitting end's clock cycle from the first field, and then, based on the offset between the reconstructed clock cycle and the local cycle, adds at least one group of fields to a group of multiple identical fields, or removes at least one group of fields from a group of multiple identical fields.

[0036] For example, a buffer queue may be located at the receiving end, and the receiving end writes the data carried in the first field to the buffer queue based on the clock cycle recovered from the first field. Furthermore, the receiving end may read more data from the buffer queue based on the local clock cycle. The two operations are performed simultaneously. When the receiving end detects that the rate at which data is written to the buffer queue is greater than the rate at which data is read from the buffer queue, this indicates that the clock cycle at the transmitting end is greater than the clock cycle at the receiving end. In this case, at least one group of fields is removed from the group of multiple identical fields contained in the first field to ensure clock cycle synchronization between the transmitting and receiving ends. When the receiving end detects that the rate at which data is written to the buffer queue is less than the rate at which data is read from the buffer queue, this indicates that the clock cycle at the transmitting end is less than the clock cycle at the receiving end. In this case, at least one group of fields is added to the first field from the group of multiple identical fields to achieve clock cycle synchronization between the transmitting and receiving ends.

[0037] In the prior art, since no structured control word is set, a dedicated sequence to compensate for the difference between the transmitting end's clock cycle and the receiving end's clock cycle is typically set within the transmitted bitstream, and this sequence carries no useful data. In this embodiment of the application, a group of multiple identical fields is set in the first field of the control word, thereby enabling the control word to perform more functions. In other words, a dedicated sequence to compensate for the difference between the transmitting end's clock cycle and the receiving end's clock cycle does not need to be further set within the bitstream. Compared to the prior art, the design at the physical layer can be simplified.

[0038] According to a third aspect, an embodiment of the present application provides a data transmission device. The data transmission device includes a processor and an interface. The processor is configured to generate a bitstream. The bitstream includes data and a control word, the control word including a first field indicating the start position information of the control word, a second field indicating the end position information of the control word, and a third field used to carry link information indicating a wired serial link. The interface transmits the bitstream over the wired serial link.

[0039] In possible implementations, link information includes at least one of the following: the number of lanes for transmitting the bitstream, the power consumption state of the hardware in the link, the operating state of the circuitry in the link, or the gain of the codec used in the link.

[0040] In possible implementations, the first and second fields instruct the receiving end to perform frame delimiter on the data.

[0041] In possible implementations, multiple bitstreams exist, multiple lanes exist on the wired serial link, and the multiple bitstreams correspond one-to-one with the multiple lanes. The interface is specifically configured to transmit the multiple corresponding streams through the multiple lanes.

[0042] In possible implementations, the control word further includes a fourth field indicating the lane number.

[0043] In a possible implementation, the first field contains multiple groups of the same field, each group of the field containing multiple bits. These multiple groups of the same field are used to compensate for the difference between the clock cycle at the transmitting end and the clock cycle at the receiving end.

[0044] According to a fourth aspect, an embodiment of the present application provides a data transmission device. The data transmission device includes a processor and an interface. The interface is configured to receive a bitstream. The bitstream includes data and a control word, the control word including a first field indicating the start position information of the control word, a second field indicating the end position information of the control word, and a third field used to carry link information indicating a wired serial link. The processor is configured to read the control word from the bitstream based on the first and second fields and to read the data from the bitstream based on the control word.

[0045] In a possible implementation, the processor is further configured to adjust at least one of the wired serial links based on link information, i.e., the power consumption state of the hardware in the link, the operating state of the circuitry in the link, or the gain of the codec used in the link.

[0046] In a possible implementation, the processor is specifically configured to determine the coding length of a control word based on a first field and a second field, to identify the frame start position of the data from the bitstream based on the coding length of the control word, the frame start position of the data is located after the control word, and to read the data based on the frame start position of the data.

[0047] In possible implementations, multiple bitstreams exist, multiple lanes exist on a wired serial link, the multiple bitstreams are received from the transmitting end through multiple corresponding lanes, the link information further includes the number of lanes for transmitting the multiple bitstreams, and the control word further includes a fourth field indicating the lane number. The processor is specifically configured to read data from the bitstreams received through the corresponding lanes based on the number of lanes for transmitting the bitstreams and the fourth field.

[0048] In a possible implementation, the processor is further configured to remove data skew between multiple lanes based on a sequence of multiple received bitstreams and a fourth field in each of the multiple control words within the multiple bitstreams.

[0049] In a possible implementation, the first field includes multiple groups of the same field, each group of fields includes multiple bits. The processor is further configured to perform one of the following operations based on the clock frequency offset between the data transmission device and the transmitting end: namely, removing at least one group of fields from multiple groups of the same field, or adding at least one group of fields to multiple groups of the same field.

[0050] According to a fifth aspect, an embodiment of the present application provides a computer-readable storage medium configured to store a computer program. When the computer program is executed by a processor, the data transmission method of the first aspect or the data transmission method of the second aspect is realized.

[0051] According to the sixth aspect, an embodiment of this application provides a computer program product. When the computer program product is executed on a processor, the data transmission method in the first aspect or the data transmission method in the second aspect is realized.

[0052] It should be understood that the technical solutions in the second to sixth aspects of this application are consistent with the technical solutions in the first aspect of this application, and the beneficial effects achieved by the aspects and corresponding feasible implementations are similar, and therefore the details will not be explained again. [Brief explanation of the drawing]

[0053] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings illustrating the embodiments of this application are briefly introduced below. The accompanying drawings in the following description merely illustrate some embodiments of this application, and it will be apparent that those skilled in the art can still derive other drawings from these accompanying drawings without any creative effort. [Figure 1] This is a diagram of the hardware architecture of an electronic device according to an embodiment of this application. [Figure 2] This is a diagram of the frame structure of a control word according to an embodiment of this application. [Figure 3A] This is a diagram of the eBCH codeword set according to an embodiment of this application. [Figure 3B] This is a diagram of the coding structure of a lane identifier according to an embodiment of this application. [Figure 4A] This is a diagram of the hardware architecture at the physical layer according to an embodiment of this application. [Figure 4B] This is a diagram of the hardware architecture at the physical layer according to an embodiment of this application. [Figure 5] This is a flowchart of the data transmission method according to an embodiment of this application. [Figure 6A] This is another flowchart of the data transmission method according to an embodiment of this application. [Figure 6B] This is another flowchart of the data transmission method according to an embodiment of this application. [Figure 7] This is a diagram showing the structure of a data transmission device according to an embodiment of this application. [Figure 8] This is a diagram showing another structure of the data transmission device according to an embodiment of this application. [Modes for carrying out the invention]

[0054] The technical solutions in the embodiments of this application are described below with reference to the accompanying drawings. CertainlyIt is clear that the embodiments described herein are only a part of, and not all, of, the embodiments of this application. All other embodiments that can be obtained by those skilled in the art in accordance with the embodiments of this application without any creative effort shall fall within the scope of protection of this application.

[0055] The terms “first” or “second” and similar terms used herein do not indicate any order, number, or importance, but are used simply to distinguish between different components. Similarly, similar terms such as “one” or “a” also do not indicate a limit on the number, but indicate at least one. Similar terms such as “joined” are not limited to direct physical or mechanical connections, but may include electrical connections, whether direct or indirect, that are equivalent to connections in a broad sense.

[0056] In embodiments of this application, terms such as “example” or “for example” are used to provide examples, illustrations, or explanations. No embodiment or design described as “example” or “for example” in embodiments of this application should be described as being preferable to or having more advantages than other embodiments or design designs. Strictly speaking, the use of terms such as “example” or “for example” is intended to present the relevant concepts in a particular manner. In the description of embodiments of this application, unless otherwise specified, “multiple” means two or more. For example, “multiple lanes” means two or more lanes.

[0057] The data transmission system provided in the embodiments of this application may include a transmitting end and a receiving end. Both the transmitting end and the receiving end may be electronic devices. For example, the electronic device may be a terminal device, such as a mobile phone, PC computer, tablet computer, notebook computer, or various types of portable devices such as a wearable device (e.g., a smartwatch, AR device, or VR device). The electronic device may also be a switch device, a router device, etc. In the application scenario, the transmitting end may be a terminal device and the receiving end may be a router device. The terminal device communicates with the router device over a wired serial link and transmits signals to the router device. In this application scenario, when the router device transmits signals to the terminal device, the router device may be referred to as the transmitting end and the terminal device may be referred to as the receiving end.

[0058] Furthermore, the transmitting and receiving ends may be modules, chips, circuit boards, components with chips or chipsets, or chipsets located in an electronic device. An electronic device is, for example, one of the electronic devices described above. A network interface card may be located in the electronic device, thereby allowing the electronic device to access a network through the network interface card for communication. The network may be, for example, Ethernet. In the application scenario, the transmitting end may be an interface controller integrated into the electronic device, and the receiving end may be a network interface card located in the electronic device. The interface controller may communicate with the network interface card over a wired serial link. The interface controller transmits a bitstream to the network interface card over the wired serial link, and the network interface card encapsulates the received bitstream in an Ethernet frame and transmits the Ethernet frame to Ethernet. In this application scenario, after receiving the bitstream from Ethernet, the network interface card needs to transmit the received bitstream to the interface controller. In this case, the interface controller is the transmitting end, and the network interface card is the receiving end. In the embodiments of this application, an example is used for illustrative purposes in which the transmitting end is an interface controller and the receiving end is a network interface card, but this is not intended to limit the solutions.

[0059] Figure 1 is a diagram of the structure of an electronic device 100 according to an embodiment of this application. In Figure 1, the electronic device 100 includes one or more processors. The one or more processors include, for example, an interface controller 10 and a central processing unit (CPU) 12. Optionally, the one or more processors may be integrated into one or more chips, and the one or more chips may be considered as a chipset. In the optional implementation, the interface controller 10 and CPU 12 may be integrated into a system on a chip (SOC) as shown in Figure 1, and devices or components such as memory 13 and a direct memory access controller (DMAC) 14 may be further integrated into the SOC. Signals are transmitted between the interface controller 10, the CPU 12, the memory 13, and the DMAC 14 via a bus. The CPU 12 may execute software programs or software plug-ins, such as operating system software and application software. The memory 13 may store software programs or software plug-ins necessary for the execution of the CPU 12. Furthermore, memory 13 may store additional instructions and data necessary for the execution of CPU 12, and CPU 12 retrieves instructions and data from memory 13 via DMAC 14.

[0060] As shown in Figure 1, the electronic device 100 further includes a network interface card 11. The network interface card 11 may be located outside the SOC shown in Figure 1. The interface controller 10 includes interface 101 and processor 102. The network interface card 11 includes interface 111 and processor 112. The network interface card 11 is connected to interface 101 in the interface controller 10 through interface 111. In an optional implementation, interfaces 101 and 111 may be serializer / deserializer (SerDes) interfaces. Interface 101 may be coupled to interface 111 via various physical media (e.g., twisted pair or cable). Thus, the electronic device 100 accesses the network through the network interface card 11 and communicates with other devices in the network (e.g., server devices or terminal devices) for data exchange. In possible implementations, processors 102 and 112 may separately include encoders, decoders, control word generators, link training state machines, and other components. Furthermore, processors 102 and 112 may optionally include scramblers, descramblers, and other components. For a more detailed structure of the interface controller 10 and network interface card 11, refer to the relevant descriptions in Figures 4A and 4B.

[0061] In embodiments of this application, the communication network model of the electronic device 100 may conform to the Open Systems Interconnection Reference Model (OSI reference model) standard. The OSI reference model may specifically include an application layer, a transport layer, a data link layer, and a physical layer, and may further include more layers. This is not particularly limited in embodiments of this application. The application layer may include application software running on the CPU 12, for example, a video playback application and an instant messaging application. The transport layer is used to describe the transport layer protocol specifications of the system, including the definition and arrangement of data types and structures, route control, bandwidth management, etc. The data link layer is used to encapsulate data packets provided by the transport layer into data frames and provide transparent transmission. The physical layer is used to define the link state, clock reference, data encoding, and circuitry of the wired serial link necessary for data transmission and reception, and to provide a standard interface for the data link layer. The physical layer encodes the data frames to generate a bitstream and transmits the bitstream over the wired serial link. It should be noted that the interface controller 10 and network interface card 11 provided in the embodiments of this application typically operate at the physical layer in the OSI standard.

[0062] In the execution process of the electronic device 100, the processor 102 in the interface controller 10 may acquire the original data packet (for example, the CPU 12 may trigger the processor 102 to read the data packet from memory 13). The processor 102 processes the acquired data packet (for example, encapsulating the data packet in a data frame and performing Hamming coding), generates a bitstream, and outputs the bitstream to the network interface card 11 through interface 101. Interface 111 in the network interface card 11 receives the bitstream, and the processor 112 in the network interface card 11 further processes the received bitstream (for example, acquiring a data frame through decoding, encapsulating the data frame in an Ethernet frame and performing Manchester coding), and then transmits the data frame to the network. Similarly, after receiving a data frame from the network, the network interface card 11 may perform processing (for example, performing Manchester decoding, removing the Ethernet frame and performing Hamming coding), and then transmit the data frame to the interface controller 10 through interface 111. After further processing the acquired data frame (for example, by performing decryption and decapsulation), the interface controller 10 generates data packets and either stores the data packets in memory 13 or provides the data packets directly to the CPU 12.

[0063] In embodiments of this application, in order to achieve signal transmission with a low bit error rate, the bitstream transmitted by the interface controller 10 (i.e., the transmitting end) to the network interface card 11 (i.e., the receiving end), as shown in Figure 2, further includes a control word in addition to the data obtained by encoding data frames. Figure 2 schematically shows the bitstream transmitted by the interface controller 10 to the network interface card 11. The control word indicates the link state, clock reference, data frame delimiter of the wired serial link, and other information. Therefore, the physical layer at the receiving end determines the data frame delimiter, adjusts the clock reference, adjusts the link state, etc., based on the control word. The control word includes a start field indicating the start position information of the control word, an end field indicating the end position information of the control word, and a payload field used to carry instruction information. The instruction information carried by the payload field indicates the link information of the wired serial link.

[0064] In conventional wired serial links, encoded segments are typically used to transmit data between two communication devices, achieve link alignment, and transfer various information about the link, with one type of information constituting one encoded segment. For example, information indicating link power consumption is encoded in one segment, and information indicating the state of each circuit in the link is encoded in another. In other words, multiple encoded segments exist to achieve link alignment. However, with the continuous evolution of operating rates at the physical layer and the need for more precise control on the link, more link information needs to be configured to meet the requirements. As a result, the amount of link information increases, i.e., the number of encoded segments increases, which complicates the design of the physical layer in the communication device and increases the design cost of the physical layer. The control word provided in embodiments of this application is configured to include a start field, an end field, and a payload field, with the payload field carrying the link information. This enables one control word to represent multiple pieces of link information, simplifying the design at the physical layer. Furthermore, since the end field in the control word indicates the end position information of the control word, i.e., the end field in the control word may limit the length of the control word. Furthermore, by flexibly adjusting the end position information of the control word, the amount of link information carried by the control word can be flexibly adjusted, thereby providing flexibility to the control word.

[0065] In the bitstream shown in Figure 2, it should be noted that the data is located to the left of the control word. In the process of transmitting the bitstream, the control word signal is transmitted first, followed by the data signal. In the implementation shown in Figure 2, the data may be, for example, service data. Optionally, the data may be located to the right of the control word. In the process of transmitting the bitstream, the data signal is transmitted first, followed by the control word signal. In this implementation, the data may be, for example, training data. Furthermore, since the data and control word are encoded as "0" and "1" signals at the physical layer, the control word may be set to either position in the data as an alternative.

[0066] Figure 2 provides a more schematic overview of the control word frame structure. In Figure 2, the control word includes a start field U_I indicating the start position information of the control word, an end field U_END indicating the end position information of the control word, and a payload field payload indicating the link information of the wired serial link. The control word will be described in more detail below with reference to the control word frame structure shown in Figure 2.

[0067] The start field U_I includes at least one group of U_ID0~U_IDN, i.e., multiple bits. In other words, in the frame structure shown in Figure 2, the first N+1 bits are the header of the control word, and the (N+1) bit header may allow the network interface card 11 to identify the start field of the control word. In an optional implementation of this embodiment of the application, the length of the start field U_I may vary within a preset range to ensure that the control word has a certain fault tolerance capability and to compensate for the difference between the clock cycles at the transmitting end and the clock cycles at the receiving end. For example, the start field U_I may include multiple groups of repeating U_ID0~U_IDN, and the variable length of the start field U_I may be, for example, 8 bytes. Assume that N is 4 and U_ID0~U_IDN are 00101. The start field U_I may also be 001010010100101, i.e., three groups of repeating code streams.

[0068] The interface controller 10 may encode the start field into a sequence of "0" and "1" signals and send the bitstream to the network interface card 11 based on the local clock cycle over the wired serial link. After receiving the bitstream, the network interface card 11 first reconstructs the clock cycle of the interface controller 10 from the start field, and then, based on the offset between the reconstructed clock cycle and the local cycle, adds at least one group of fields to a group of multiple identical fields, or removes at least one group of fields from a group of multiple identical fields. Specifically, a buffer queue may be placed on the network interface card 11, and the network interface card 11 writes the data carried in the start field to the buffer queue based on the clock cycle reconstructed from the start field. Furthermore, the network interface card 11 may read more data from the buffer queue based on the local clock cycle. The two operations are performed simultaneously. When the network interface card 11 detects that the rate at which data is written to the buffer queue is greater than the rate at which data is read from the buffer queue, this indicates that the clock cycle of the interface controller 10 is greater than the clock cycle of the network interface card 11. In this case, one or more groups of U_ID0 to U_IDN in the start field U_I are deleted to ensure clock cycle synchronization between the interface controller 10 and the network interface card 11. When the network interface card 11 detects that the rate at which data is written to the buffer queue is less than the rate at which data is read from the buffer queue, this indicates that the clock cycle of the interface controller 10 is less than the clock cycle of the network interface card 11.In this case, one or more groups of U_ID0 to U_IDN are added to the start field U_I to achieve clock cycle synchronization between the interface controller 10 and the network interface card 11.

[0069] The end field U_END indicates the end position information of the control word. The end position information may be, for example, the length of the control word or the end position. The end position may be, for example, a position after a predetermined number of bits starting from the end field U_END. Therefore, after identifying the end field U_END from the control word, the network interface card 11 may count a predetermined number of bits after the end field to determine that the code stream of the control word has ended.

[0070] In this possible implementation, the control word may be followed by data content. In other words, the start and end fields within the control word may be used as the frame header of the data frame. After identifying the start and end fields within the control word, the receiving end may determine the start position of the data (i.e., the frame delimiter) and read the data from the bitstream. In embodiments of this application, the start and end fields within the control word are used as the frame header of the data frame, thereby eliminating the need for further setting of the data frame's frame header. This simplifies the bitstream design.

[0071] The payload field is used to carry link information. Link information may include, but is not limited to, one or more of the following: clock cycles for adding control words to the data, the power consumption state of the hardware in the link, the operating state of the circuits in the link, and the output gain of the codec circuits used in the link. For example, the power consumption state of the hardware in the link may include, for example, three states: low power consumption, medium power consumption, and high power consumption. For example, when hardware such as scramblers and data distributors included in the link are in one of the following modes: standby, sleep, or powered off, the hardware in the link is in a low power consumption state. When some of the hardware included in the link is in one of the following modes: standby, sleep, or powered off, and the other parts of the hardware are in an operating state, the hardware in the link is in a medium power consumption state. When all components in the link are in an operating state, the hardware in the link is in a high power consumption state. For example, when the data being transmitted is training data, this may indicate that the power consumption of each piece of hardware in the link is low power consumption. When the transmitted data is service data, this may indicate that the power consumption of each piece of hardware in the link is medium power consumption or high power consumption. The operating state of the circuits in the link may include, for example, a power-on state or a power-off state. For example, when the transmitted data is training data, the state of the codec circuit may be a power-off state. When the transmitted data is service data, the state of the codec circuit may be a power-on state. The codec gains in the link may include, for example, gain 1, gain 2, and gain 3.

[0072] In an optional implementation, the payload field may include two parts: a type field and a detail field. The type field indicates various types of link information, and the detail field indicates specific parameters corresponding to each type of link information. For example, the link information may include the hardware power consumption state in the link, the circuit operating state in the link, or the codec gain in the link. The type field indicates that the link information includes the hardware power consumption state in the link and the codec gain in the link. The detail field further indicates that the hardware power consumption state in the link is a medium power consumption state and the codec gain in the link is gain 2. Therefore, the network interface card 11 may adjust the link by determining the link information and the parameters corresponding to the link information based on the type field and the detail field.

[0073] In this embodiment of the application, the wired serial link used to transmit a bitstream between the interface controller 10 and the network interface card 11 may include one lane, or it may include multiple lanes depending on the bandwidth of the wired serial link. In other words, the bitstream may be transmitted between the interface controller 10 and the network interface card 11 through one lane, or the bitstream may be transmitted through multiple lanes. When the interface controller 10 transmits the bitstream to the network interface card 11 through multiple lanes, in an optional implementation, in addition to the data, the bitstream transmitted through each lane further includes a control word. In addition to the above fields, each control word may further include a lane identifier field Lane indicating the link number, as shown in Figure 2. The network interface card 11 may implement lane reversal based on the lane identifier field Lane to eliminate data skew between the data transmitted through the lanes. Furthermore, the interface controller 10 may transmit the bitstream to the network interface card 11 through a fixed number of lanes, or it may transmit the bitstream to the network interface card 11 through a variable number of lanes. When the interface controller 10 transmits the bitstream to the network interface card 11 through a variable number of lanes, in the optional implementation, the link information carried in the payload field may further include the link bandwidth (i.e., the number of lanes for transmitting the bitstream). The network interface card 11 may receive the bitstream from the corresponding lane based on the link information.

[0074] In conclusion, it can be seen that a control word can contain more information by having a start field, an end field, and a payload field, and optionally a lane identifier field. This reduces the complexity of the control word transmitted at the physical layer.

[0075] Based on the above frame structure of the control word, in possible implementations, in embodiments of this application, the control word may be encoded using an error-correcting coding scheme. The interface controller 10 transmits a correctable code. The network interface card 11 can automatically detect errors and automatically correct errors in the code word transmission. Error-correcting coding may include, but is not limited to, forward error-correcting coding, Hamming coding, and eBCH (extended Bose-Chaudhuri-Hocquenghem) coding. Hamming coding is a linear code. For a code block of length m bits, there are n redundant bits, and the remaining bits are payload bits. Each redundant bit is obtained by performing an exclusive OR operation on several payload bits in a particular manner. Hamming coding can correct any single-bit error. eBCH coding is also a linear code, and eBCH coding can correct multiple bit errors in a code block. Below, eBCH coding is used as an example to illustrate the control word coding method in detail using a specific example. In embodiments of this application, the eBCH code set may be constructed first. For example, an eBCH code set may contain 32 codes, and the structure of each code may be BCH(16,5,1), where 16 bits is the coding length, 5 bits is the payload length, and 1 bit is the check coding length. The Hamming distance between any two codes in the eBCH code set is 8. In other words, the number of different bits between any two codes is 8. The eBCH codeword set is shown in Figure 3A.

[0076] From Figure 3A, it can be seen that the eBCH codeword set contains 32 codes, namely CW0 to CW31, with each code having a length of 16 bits. The number of different bits between any two codes is 8. Based on the eBCH code constructed in Figure 3A, specific instances of control words in this embodiment of the application are shown in Table 1. [Table 1]

[0077] From the control word instances shown in Table 1, it can be seen that one control word contains (4*N+27) bytes, i.e., bytes 0 to (4*N+27). The number of bytes in the control word start field may be in the range of 4 to 20. The codes of the control word start field are CW21 and CW28. In other words, the lower 16 bits of the control word start field are code CW28 as shown in Table 1, and the upper 16 bits are code CW21 as shown in Table 1. The codes of the control word end field are CW22 and CW8. In other words, the lower 16 bits of the control word end field are code CW22 as shown in Table 1, and the upper 16 bits are code CW8 as shown in Table 1.

[0078] The lane identifier field is shown in Figure 3B. The maximum link bandwidth between the interface controller 10 and the network interface card 11 is 32 lanes. hmm,That is, assume that the lanes are 0 to 31 as shown in Figure 3B. In this case, the identifier for each lane may be represented by four codes, i.e., 64 bits. Lane 2, shown in Figure 3B, is used as an example. From Figure 3B, it can be seen that lane 2 is represented by four codes, i.e., CW3, CW9, CW3, and CW9. Refer to Table 1 for the specific bits of CW3 and CW9. From Figure 3B, it can be seen that of the 64 bits, bits [0 to 15] are CW3, bits [16 to 31] are CW9, bits [32 to 47] are CW3, and bits [48 to 63] are CW9. Refer to Figures 3A and 3B for detailed codes for the other lanes. Details will not be explained.

[0079] It should be noted that the tables shown in Tables 1, 2, and 3, and Figures 3A and 3B, may be pre-stored separately in the interface controller 10 and the network interface card 11. [Table 2] [Table 3]

[0080] Table 2 shows that the link information includes four types of information: forward error correction (FEC) encoder gain, link bandwidth, hardware power consumption, and control word addition cycle. Each type of information is represented by two codes (i.e., 32 bits). Table 2 shows that the codes for FEC gain are CW8 and CW10, meaning that of the 32 bits representing the FEC gain, the lower 16 bits are CW10 and the upper 16 bits are CW8. The FEC gain further includes four modes: bypass FEC, FEC gain 1, FEC gain 2, and FEC gain 3, as shown in Table 3. Assume that the type field in the control word transmitted by the interface controller 10 to the network interface card 11 includes CW8 and CW10, and the detail field includes CW9 and CW10. After receiving the bitstream, the network interface card 11 obtains the type field and detail field of the control word through analysis. The network interface card 11 finds from Table 2 that CW8 and CW10 exhibit FEC gain. Next, the network interface card 11 further compares CW3 and CW9 with the codes corresponding to the FEC gain in Table 3 and finds that the FEC gain is FEC gain 1. In this case, the network interface card 11 may adjust the FEC gain to gain 1.

[0081] Table 2 shows that the link bandwidth codes are CW10 and CW22, i.e., of the 32 bits indicating the link bandwidth, the lower 16 bits are CW10 and the upper 16 bits are CW22. The link bandwidth further includes the seven modes shown in Table 3, namely X0, X1, X2, X4, X8, X16, and X32. Assume that in the type field of the control word transmitted by the interface controller 10 to the network interface card 11, the first 32 bits are CW8 and CW10 and the last 32 bits are CW10 and CW22, and in the detail field, the first 32 bits are CW9 and CW10 and the last 32 bits are CW9 and CW21. After receiving the bitstream, the network interface card 11, through analysis, finds that the first 32 bits of the type field in the control word indicate the FEC gain and the last 32 bits indicate the link bandwidth. Next, the network interface card 11 compares the first 32 bits of the detail field with the information corresponding to the FEC gain in Table 3, and the last 32 bits of the detail field with the information corresponding to the link bandwidth in Table 3, finding that the FEC gain is FEC gain 1 and the link bandwidth is X1. In this case, the network interface card 11 may adjust the FEC gain to gain 1 and acquire data through one lane. It should be noted that the lanes used for each link bandwidth may be further pre-agreed upon between the physical layer of the interface controller 10 and the physical layer of the network interface card 11. For example, when one lane is used to transmit service data, it may be pre-agreed that the service data is transmitted through the lane whose lane identifier is lane 0. Alternatively, when four lanes are used to transmit service data, it may be pre-agreed that the service data is transmitted through the lanes whose lane identifiers are lane 0 to lane 3.It should be further noted that when the type field of the control word indicates link bandwidth information and the detail fields are codes CW3 and CW9, this indicates that the transmission of service data by the interface controller 10 to the network interface card 11 has ended and the data transmitted in the next cycle is training data. In other words, when the information indicating link bandwidth in the control word is X0, this indicates that the transmission of service data has ended and the data transmitted in the next cycle is training data. When the information indicating link bandwidth in the control word is any one of the pieces of information other than X0, this indicates that the data transmitted by the interface controller 10 to the network interface card 11 is service data. Therefore, the code indicating link bandwidth may further indicate the switching between service data and training data.

[0082] When the control word transmitted by the interface controller 10 to the network interface card 11 includes information indicating hardware power consumption and the control word addition cycle, the network interface card 11 analyzes the control word and determines the link information that needs to be adjusted in the same way as for the FEC encoder gain and link bandwidth. Further details will not be explained again.

[0083] Based on the structure of the electronic device 100 shown in Figure 1 and the control word frame structure shown in Figure 2, Figures 4A and 4B illustrate the hardware structure in the physical layer of the interface controller 10 according to an embodiment of this application. It should be noted that the hardware structure in the physical layer of the network interface card 11 may be the same as the hardware structure in the physical layer of the interface controller 10. In this embodiment of this application, the hardware in the physical layer of the interface controller 10 is used as an example for illustrative purposes. As shown in Figures 4A and 4B, the physical layer of the interface controller 10 includes an encoder 101, a data distributor 102, a control word generator 103, a multiplexer 104, a link training state machine 105, a scrambler 106, a serializer / deserializer 107, a descrambler 108, a control word decoder 109, a data skew remover 1010, and a decoder 1011. It can be understood that the physical layer of the interface controller 10 may further include more circuits, modules, or components. This is not particularly limited in this embodiment of this application. The components included in the physical layer of the interface controller 10 may be integrated onto one or more chips. The components may be implemented using hardware circuits, or some components may be implemented using software-driven hardware. In possible implementations, some components may be integrated into the same processor, which performs the functions corresponding to the components or modules. For example, the encoder 101 and the data distributor 102 may be integrated into the same processor, which implements data encoding and allocation functions. Furthermore, the physical layer of the network interface card 11 may have the same or similar components as the interface controller 10.As shown in Figures 4A and 4B, the physical layer of the network interface card 11 includes an encoder 111, a data distributor 112, a control word generator 113, a multiplexer 114, a link training state machine 115, a scrambler 116, a serializer / deserializer 117, a descrambler 118, a control word decoder 119, a data skew remover 1110, and a decoder 1111. The components or functions of the physical layers of the interface controller 10 and the network interface card 11 will be described below using an example in which the physical layer of the interface controller 10 transmits a bitstream to the physical layer of the network interface card 11.

[0084] In the physical layer of the interface controller 10, the encoder 101 is configured to encode data frames transmitted in the data link layer to generate encoded data. The encoding may be, for example, forward error encoding, error detection and retransmission encoding, or hybrid error correction encoding. The data distributor 102 is configured to divide the encoded data into multiple data streams (hereinafter referred to as service data) and assign the multiple data streams to multiple lanes, with each lane corresponding to one data. The link training state machine 105 is configured to generate link information and provide the generated link information to the control word generator 103. The control word generator 103 generates a control word based on the link information and frame structure of the control word shown in Figure 2. The link information may include, for example, the link power consumption state, the link output gain, and the link encoding mode. Furthermore, the link training state machine 105 is further configured to control the multiplexer 104 based on the current state (e.g., service data transmission state, link training state, or link reset state) and the clock cycle to selectively form a path between one of the multiple input terminals and the output terminal. Figures 4A and 4B show that the multiplexer 104 includes three input terminals. One input terminal is coupled to the data distributor 102, one input terminal is configured to input training data, and the other input terminal is coupled to the control word generator 103. In other words, the multiplexer 104 outputs one of the following to the scrambler 106 under the control of the link training state machine 105: service data, training data, or a control word. It should be noted that the service data in this embodiment of the application may be data generated after data such as audio and video data input by the user using an application program has been encapsulated and encoded in the application layer, transport layer, data link layer, and physical layer. The training data is used to test and tune multiple lanes during the link training phase.The scrambler 106 scrambles the received data stream or control word and provides the scrambled data stream to the serializer / deserializer 107. The serializer / deserializer 107 converts the received multiple parallel low-speed bitstreams into a high-speed serial bitstream and transmits the high-speed serial bitstream to the network interface card 11 through multiple lanes. It should be further noted that the number of lanes is the same as the number of bitstreams being transmitted, and each bitstream contains data and a control word. Under the control of the link training state machine 105, the control word may be added at any position in the corresponding data. Preferably, the control word may be added before the data.

[0085] In the physical layer of the network interface card 11, the serializer / deserializer 117 receives a serial bitstream signal on a lane, converts the serial bitstream into multiple parallel bitstreams, and provides the multiple parallel bitstreams to the descrambler 118. The descrambler 118 descrambles the multiple parallel bitstreams and outputs the descrambled bitstreams to the control word decoder 119. Based on the control word frame structure shown in Figures 4A and 4B, the control word decoder 119 identifies the control word from each bitstream, analyzes the control word, and obtains instruction information in the payload field. The instruction information indicates link information. For example, the instruction information indicates that the link is entering an intermediate power consumption state and that the link coding mode is forward error coding mode. The control word decoder 119 provides the obtained instruction information to the link training state machine 115 and provides the data and the lane identifier corresponding to each data to the data skew remover 1110. The link training state machine 115 performs the corresponding action based on the instruction information. For example, the link is set to a medium power consumption state, and an encoding mode (e.g., forward error encoding mode) is provided to the decoder 1111. The data skew removal unit 1110 performs skew removal on the data stream and provides the skew-removed data stream to the decoder 1111. The decoder 1111 decodes the data stream based on the encoding mode in the corresponding decoding mode and provides the decoded data to the data link layer of the network interface card 11.

[0086] Based on the architecture of the electronic device 100 shown in Figure 1, the frame structure of the control word shown in Figure 2, and the hardware architecture of the physical layer of the interface controller 10 (or network interface card 11) shown in Figures 4A and 4B, embodiments of this application further provide a data transmission method. The data transmission method may be used in the electronic device 100 shown in Figure 1. The data transmission method provided in embodiments of this application will be described below using an example in which the interface controller 10 is the transmitting end and the network interface card 11 is the receiving end. In the data transmission method provided in embodiments of this application, the transmitting and receiving ends of the data transmission method may be realized by one or more components shown in Figure 2. It should be noted that in this embodiment of this application, the interface controller 10 may transmit a control word to the network interface card 11 at any of the data transmission stages. For example, the control word may be added to training data transmitted in the link training stage, the control word may be added to service data transmitted in the service data transmission stage, or the control word may be added to training data transmitted in the link reset stage. It should be further noted that the control word may be set before the service data, at any position in the service data based on the clock cycle, before the training data, or after the training data. This is not particularly limited in this embodiment of the application. Figure 5 shows procedure 500 of a data transmission method according to an embodiment of the application. The data transmission method includes the following steps:

[0087] Step 501: The interface controller 10 generates a bitstream, which includes data and a control word, the control word including a start field indicating the start position information of the control word, an end field indicating the end position information of the control word, and a payload field used to carry link information indicating a wired serial link. Step 502: The interface controller 10 transmits the bitstream over the wired serial link.

[0088] Step 503: The network interface card 11 reads a control word from the bitstream based on the start and end fields. Step 504: The data is read from the bitstream based on the control word.

[0089] In this embodiment, the data may be, for example, service data or training data. The control word has a structure, for example, as shown in Figure 2. The link information may include, but is not limited to, one or more of the following: the clock cycle for adding the control word to the data, the power consumption state of the hardware in the link, the operating state of the circuit in the link, and the output gain of the codec circuit used in the link.

[0090] In this implementation, the start and end fields of a control word may indicate the length of the control word. For example, after reading the start field, the network interface card 11 identifies that the bitstream contains a control word. After reading the end field, the network interface card 11 identifies that the position after a predetermined number of bits starting from the field is the end position of the control word. Furthermore, the control word may be followed by the data content of the data. In other words, the start and end fields of a control word may be used as the frame header of the data frame. After identifying the start and end fields within the control word, the receiving end may determine the start position of the data and read the data from the bitstream.

[0091] The control word provided in the embodiments of this application is configured to include a start field, an end field, and a payload field, with the payload field carrying link information. This enables a single control word to represent multiple link pieces of information, simplifying the design at the physical layer. Furthermore, since the end field within the control word indicates the end position information of the control word, i.e., the end field within the control word may limit the length of the control word. Moreover, by flexibly adjusting the end position information of the control word, the amount of link information carried by the control word can be flexibly adjusted, providing flexibility to the control word.

[0092] Referring to Figures 6A and 6B, the data transmission method provided in embodiments of this application will be described below by using more specific scenarios and examples in which the bitstream includes training data and control words, and in which the bitstream includes service data and control words, and in which the interface controller 10 transmits data to the network interface card 11 on four lanes. Figures 6A and 6B show step 600 of the data transmission method according to embodiments of this application. The data transmission method includes the following steps:

[0093] Step 601: The interface controller 10 adds control words C0 to C3 to training data D0 to D3, respectively, to generate bitstreams B0 to B3. This step is the link training phase. The link training phase is used to match the link state of the interface controller 10 with the link state of the network interface card 11. In this step, the interface controller 10 may assign the pre-configured training data D0 to D3 to lanes 0 to 3. The interface controller 10 may further generate control words C0 to C3 based on the current link information (for example, the link is in a medium power consumption state, each hardware circuit in the physical layer is powered on, the gain of the link encoder in the physical layer is "1", and the link coding mode is forward error coding), the clock cycle for adding the control words to the training data, and the frame structure of the control words shown in Figure 2. The lane identifier field of control word C0 indicates lane 0, the lane identifier field of control word C1 indicates lane 1, the lane identifier field of control word C2 indicates lane 2, and the lane identifier field of control word C3 indicates lane 3. Furthermore, the data carried in the start field, end field, and payload field within control words C0 to C3 may be the same. Next, the interface controller 10 adds control words C0 to C3 to training data D0 to training data D3, respectively, to generate bitstreams B0 to B3. Step 602: The interface controller 10 simultaneously transmits bitstreams B0 to B3 through lanes 0 to 3 to the network interface card 11.

[0094] Step 603: The network interface card 11 identifies control words C0 to C3 from bitstreams B0 to B3 based on a start field indicating the start position of control words C0 to C3 and an end field indicating the end position of control words C0 to C3. Step 604: The network interface card 11 adjusts the link alignment sequence based on the lane identifiers carried in the lane identifier fields within control words C0 to C3. This step is used to align the link number with the data stream sequence. For example, interface controller 10 transmits bitstreams B0-B1-B2-B3 through lanes 0-1-2-3, respectively, and the data streams received by the network interface card 11 from lanes 0-1-2-3 are actually B3-B2-B1-B0. In other words, the lane numbers in interface controller 10 are the exact opposite of the lane numbers in network interface card 11. The network interface card 11 may remark the lane numbers on the network interface card 11 based on the lane identifier field in the control word to achieve alignment with the lane numbers in the interface controller 10. Step 605: The network interface card 11 adjusts the link state based on the link information indicated by the payload fields in control words C0 to C3. For example, the link information indicates that the link has entered a medium power consumption state, that each hardware circuit at the physical layer is powered on, and that the gain of the link encoder at the physical layer is "1". Based on the link information, the network interface card 11 adjusts the power consumption state of hardware circuits such as amplifiers and encoders in the link to a medium power consumption state, and adjusts the gain of the link encoder to "1", etc. Step 606: The network interface card 11 aligns the data transmitted through the lanes based on the sequence in which it receives bitstreams B0 to B3.

[0095] Step 607: The interface controller 10 adds control words C4 to C7 to training data D4 to D7, respectively, to generate bitstreams B4 to B7. The payload fields of control words C4 to C7 carry instruction information indicating the transmission of service data in the next cycle. This step is in the link training phase. After the interface controller 10 adds link information to the payload field and provides the payload field to the network interface card 11 in step 601, the interface controller 10 may further add instruction information indicating the transmission of service data in the next cycle to the payload fields of control words C4 to C7. The payload fields of control words C4 to C7 may further include the link information described in step 601. Furthermore, control words C4 to C7 further include a start field, an end field, and a lane identifier field. The interface controller 10 adds control words C4 to C7 to training data D4 to D7, respectively, to generate bitstreams B4 to B7. Step 608: The interface controller 10 simultaneously transmits bitstreams B4 to B7 to the network interface card 11 through lanes 0 to 3, respectively.

[0096] Step 609: The interface controller 10 adds control words C8 to C111 to service data D8 to D111, respectively, to generate bitstreams B8 to B111. In this step, the interface controller 10 may acquire data frames at the data link layer. Based on a pre-configured encoding format (e.g., forward error encoding format), the interface controller 10 encodes the data frames to generate service data D8 to D11. The interface controller 10 may then assign service data D8 to D11 to lanes 0 to 3. The interface controller 10 then generates control words C8 to C11 based on the current link information, the number of lanes used, the clock period for adding control words to the training data, and the frame configuration of the control words shown in Figure 2. The number of lanes used is carried in the payload field of control words C8 to C11. Finally, the interface controller 10 service Data D8~ service These are added to data D111 to generate bitstreams B8 to B111. In the optional implementation method, control words C8 to C111 may be added to pre-set positions in service data D8 to service data D111, respectively. The pre-set positions may be, for example, before the service data. Step 610: The interface controller 10 simultaneously transmits bitstreams B8 to B111 to the network interface card 11 through lanes 0 to 3, respectively.

[0097] Step 611: The network interface card 11 identifies control words C8 to C111 from bitstreams B8 to B111, and reads service data D8 to D111 from bitstreams B8 to B111 based on the start field indicating the start position of control words C8 to C111 and the end field indicating the end position of control words C8 to C111. In this step, the network interface card 11 may perform frame delimiter on the service data based on the position of the control words in the bitstream, i.e., it may determine the start position of the service data. In the optional implementation, the position of the service data in the bitstream is a preset position after the control word. For example, the second bit after the end bit of the control word is the start bit of the service data. After reading the end field of the control word, the network interface card 11 may determine the end bit of the control word, thereby allowing the network interface card 11 to read the service data from the second bit after the end bit of the control word. Step 612: The network interface card 11 decodes the read service data D8~D111 based on the encoding format used by the interface controller 10 to obtain the decoded data frame.

[0098] It should be noted that step 600 of the data transmission method is an example. It can be understood that the data transmission method provided in embodiments of this application may include more or fewer steps than step 600. For example, before step 604 and after step 603, the network interface card 11 may further transmit information to the interface controller 10 indicating that the link setup is complete. In another example, before step 604 and after step 603, the network interface card 11 may further transmit a bitstream to the interface controller 10. The bitstream includes training data and control words added to the training data, the control words indicating the link state of the physical layer of the network interface card 11.

[0099] To implement the functions described above, it may be understood that the interface controller includes corresponding hardware and / or software modules for performing the functions. Referring to the steps of each example described in the embodiments disclosed in this specification, this application may be implemented in hardware form or in a combination of hardware and computer software. Whether the functions are performed by hardware or by hardware driven by computer software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the functions described for each specific application, referring to the embodiments. However, the implementation methods should not be considered to exceed the scope of this application.

[0100] In embodiments, the components included in the interface controller 10 shown in Figure 1 may be divided into functional modules based on the example of the method described above. For example, components corresponding to functions may be divided, or two or more components having functions may be integrated into a single processing module. The integrated processing module may be implemented in hardware form. It should be noted that in embodiments, the division into modules is an example and is merely a logical functional division. Other division methods may be used in actual implementations. When an integrated module is used, Figure 7 is a possible diagram of the data transmission device 700. As shown in Figure 7, the data transmission device 700 may include a processing unit 701 and a transmission unit 702. The above device may be further extended. The processing unit 701 is configured to generate a bitstream. The bitstream includes data and control words, the control words including a first field indicating the start position information of the control word, a second field indicating the end position information of the control word, and a third field used to carry link information indicating a wired serial link. The transmission unit 702 is configured to transmit the bitstream over a wired serial link.

[0101] In possible implementations, link information includes at least one of the following: the number of lanes for transmitting the bitstream, the power consumption state of the hardware in the link, the operating state of the circuitry in the link, or the gain of the codec used in the link.

[0102] In possible implementations, the first and second fields instruct the receiving end to perform frame delimiter on the data.

[0103] In possible implementations, multiple bitstreams exist, multiple lanes exist on the wired serial link, and the multiple bitstreams correspond one-to-one with the multiple lanes. The transmitting unit 702 is specifically configured to transmit the corresponding multiple streams through the multiple lanes.

[0104] In possible implementations, the control word further includes a fourth field indicating the lane number.

[0105] In a possible implementation, the first field contains multiple groups of the same field, each group of the field containing multiple bits. These multiple groups of the same field are used to compensate for the difference between the clock cycle at the transmitting end and the clock cycle at the receiving end.

[0106] The data transmission device 700 provided in this embodiment is used in a data transmission method performed by the interface controller 10 and can achieve the same effects as the method or device of the implementation described above. Specifically, the module corresponding to Figure 7 may be implemented by software, hardware, or a combination thereof. For example, each module may be implemented in software form and correspond to the processor 102 and interface 101 corresponding to the module in Figure 1, and is configured to drive and operate the corresponding component. Alternatively, each module may include two parts, namely the corresponding component and the corresponding driver software, i.e., it may be implemented by using a combination of software and hardware. Thus, the data transmission device 700 may be considered to logically include the interface controller 10 shown in Figure 1 and Figures 4A and 4B, and each module may include a driver software program for at least the corresponding function. Details are not described in this embodiment.

[0107] In embodiments, the components included in the interface card 11 shown in Figure 1 may be divided into functional modules based on the example of the method described above. For example, components corresponding to functions may be divided, or two or more components having functions may be integrated into a single processing module. The integrated processing module may be implemented in hardware form. It should be noted that in embodiments, the division into modules is an example and is merely a logical functional division. Other division methods may be used in actual implementations. When an integrated module is used, Figure 8 is a possible diagram of the data transmission device 800. As shown in Figure 8, the data transmission device 800 may include a receiving unit 801 and a processing unit 802. The above device may be further extended. The receiving unit 801 is configured to receive a bitstream, which includes data and a control word, the control word including a first field indicating the start position information of the control word, a second field indicating the end position information of the control word, and a payload field used to carry link information indicating a wired serial link. The processing unit 802 is configured to read control words from the bitstream based on the first field and the second field, and to read data from the bitstream based on the control words.

[0108] In a possible implementation, the processing unit 802 is further configured to adjust at least one of the wired serial links based on link information, i.e., the power consumption state of the hardware in the link, the operating state of the circuitry in the link, or the gain of the codec used in the link.

[0109] In a possible implementation, the processing unit 802 is specifically configured to determine the coding length of a control word based on a first field and a second field, to identify the start position of a data frame from the bitstream based on the coding length of the control word, the start position of the data frame being located after the control word, and to read the data based on the start position of the data frame.

[0110] In possible implementations, multiple bitstreams exist, multiple lanes exist on a wired serial link, the multiple bitstreams are received from the transmitting end through multiple corresponding lanes, the link information further includes the number of lanes for transmitting the multiple bitstreams, and the control word further includes a lane identifier field indicating the lane number. The processing unit 802 is specifically configured to read data from the bitstreams received through the corresponding lanes based on the number of lanes for transmitting the bitstreams and the lane identifier field.

[0111] In a possible implementation, the processing unit 802 is further configured to remove data skew between multiple lanes based on a sequence of multiple received bitstreams and the lane identifier field in each of the multiple control words within the multiple bitstreams.

[0112] In a possible implementation, the first field includes multiple groups of the same field, each group of fields includes multiple bits. The processing unit 802 is further configured to perform one of the following operations based on the clock frequency offset between the data transmission device and the transmitting end: namely, removing at least one group of fields from multiple groups of the same field, or adding at least one group of fields to multiple groups of the same field.

[0113] The data transmission device 800 provided in this embodiment is used in a data transmission method performed by the network interface card 11 and can achieve the same effects as the method or device of the implementation described above. Specifically, the module corresponding to Figure 8 may be implemented by software, hardware, or a combination thereof. For example, each module may be implemented in software form and correspond to the interface 111 and processor 112 corresponding to the module in Figure 1, and is configured to drive and operate the corresponding component. Alternatively, each module may include two parts, namely the corresponding component and the corresponding driver software, i.e., it may be implemented by using a combination of software and hardware. Thus, the data transmission device 500 may be considered to logically include the network interface card 11 shown in Figure 1 and Figures 4A and 4B, and each module may include a driver software program for at least the corresponding function. Details are not described in this embodiment.

[0114] Those skilled in the art will recognize, by referring to the examples described in the embodiments disclosed in this specification, that units and algorithmic steps may be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are performed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the functions described for each specific application. However, the implementation methods should not be considered to exceed the scope of this application.

[0115] In some embodiments provided in this application, it should be understood that the disclosed systems and devices may be implemented in other ways. For example, the embodiments of the devices described above are merely examples. For example, the division into units is merely a logical functional division, and other division methods may be used in actual implementations. For example, multiple units or components may be combined or integrated into other systems, or some features may be ignored or not performed. Furthermore, the mutual coupling, direct coupling, or communication connection indicated or discussed may be implemented through some interfaces. Indirect coupling or communication connection between devices or units may be implemented in electronic, mechanical, or other forms.

[0116] Units described as separate parts may or may not be physically separate, and parts shown as units may or may not be physical units, may be located in one location, or may be distributed across multiple network units. Some or all of the units may be selected based on actual requirements to achieve the objectives of the solution of the embodiment.

[0117] Furthermore, the functional units in the embodiments of this application may be integrated into a single processing unit, or each unit may exist physically independently, or two or more units may be integrated into a single unit.

[0118] When a function is implemented in the form of a software function unit and sold or used as an independent product, the function may be stored on a computer-readable storage medium. Based on this understanding, the technical solution of this application may be implemented in the form of a software product, either in essence or in part with respect to the prior art. A computer software product is stored on a storage medium and includes several instructions for instructing a computer device (which may be a personal computer, server, or network device) to perform all or part of the steps of the method described in embodiments of this application. The storage medium or memory may include any medium capable of storing program code, such as a USB flash drive, removable hard disk, ROM, RAM, magnetic disk, or optical disk.

[0119] Finally, it should be noted that the embodiments described above are intended not to limit this application, but merely to illustrate the technical solutions of this application. Although this application is described in detail with reference to the embodiments described above, those skilled in the art should understand that modifications may still be made to the technical solutions described in the embodiments above, or equivalent substitutions may be made to some or all of the technical features thereof, without departing from the scope of the technical solutions of the embodiments of this application.

Claims

1. A data transmission method over a wired serial link, which is applied at the transmitting end, A step of generating a bitstream, wherein the bitstream includes data and a control word, the control word includes a first field indicating the start position information of the control word, a second field indicating the end position information of the control word, and a third field used to carry link information indicating a wired serial link, the length of the first field being variable, and The steps of transmitting the bitstream over the wired serial link and A data transmission method that includes this.

2. The data transmission method according to claim 1, wherein the link information includes at least one of the following: the number of lanes for transmitting a bitstream, the power consumption status of the hardware in the link, the operating status of the circuit in the link, or the gain of the codec used in the link.

3. The data transmission method according to claim 1 or 2, wherein the first field and the second field instruct the receiving end to perform frame delimitation on the data.

4. Multiple bitstreams exist, multiple lanes exist on the wired serial link, and the multiple bitstreams correspond one-to-one with the multiple lanes. The step of transmitting the bitstream over the wired serial link is: A data transmission method according to any one of claims 1 to 3, specifically comprising the step of transmitting a plurality of corresponding bitstreams through the plurality of lanes.

5. The data transmission method according to claim 4, wherein the control word further includes a fourth field indicating a lane number.

6. The aforementioned first field includes a group of multiple identical fields, and each group of fields includes multiple bits. The data transmission method according to any one of claims 1 to 5, wherein the group of the same fields is used to compensate for the difference between the clock cycle of the transmitting end and the clock cycle of the receiving end.

7. The aforementioned data is either service data or training data. When the aforementioned data is training data, the step of generating a bitstream is: A data transmission method according to any one of claims 1 to 6, comprising the step of adding the control word after the data to generate the bitstream.

8. A data transmission method over a wired serial link, which is applied at the receiving end, A step of receiving a bitstream, wherein the bitstream includes data and a control word, the control word includes a first field indicating the start position information of the control word, a second field indicating the end position information of the control word, and a third field used to carry link information indicating a wired serial link, the length of the first field being variable, and A step of reading the control word from the bitstream based on the first field and the second field, A step of reading the data from the bitstream based on the control word. A data transmission method that includes this.

9. The data transmission method according to claim 8, further comprising the step of adjusting, based on the link information, at least one of the following: the power consumption state of the hardware in the link, the operating state of the circuit in the link, or the gain of the codec used in the link.

10. The step of reading the data from the bitstream based on the control word is: A step of determining the coding length of the control word based on the first field and the second field, A step of identifying the frame start position of the data from the bitstream based on the coding length of the control word, A step of reading the data based on the frame start position of the data. A data transmission method according to claim 8 or 9, including the method described in claim 8 or 9.

11. Multiple bitstreams exist, multiple lanes exist on the wired serial link, the multiple bitstreams are received from the transmitting end through multiple corresponding lanes, the link information further includes the number of lanes for transmitting the multiple bitstreams, and the control word further includes a fourth field indicating the lane number. The step of reading the data from the bitstream based on the control word is: A data transmission method according to any one of claims 8 to 10, comprising the step of reading the data from the bitstreams received through the corresponding lanes based on the number of lanes for transmitting the plurality of bitstreams and the fourth field.

12. The data transmission method according to claim 11, further comprising the step of removing data skew between the plurality of lanes based on the sequence of the plurality of received bitstreams and a fourth field in each of the plurality of control words in the plurality of bitstreams.

13. The aforementioned first field includes a group of multiple identical fields, and each group of fields includes multiple bits. A data transmission method according to any one of claims 8 to 12, further comprising the step of performing one of the following operations based on a clock frequency offset between the receiving end and the transmitting end: namely, removing at least one group of fields from the plurality of groups of the same fields, or adding at least one group of fields to the plurality of groups of the same fields.

14. A data transmission device including a processor and an interface, The processor is configured to generate a bitstream, the bitstream comprising data and a control word, the control word comprising a first field indicating the start position information of the control word, a second field indicating the end position information of the control word, and a third field used to carry link information indicating a wired serial link, the length of the first field being variable. The interface is a data transmission device that transmits the bitstream over the wired serial link.

15. The data transmission apparatus according to claim 14, wherein the link information includes at least one of the following: the number of lanes for transmitting a bitstream, the power consumption status of the hardware in the link, the operating status of the circuit in the link, or the gain of the codec used in the link.

16. The data transmission device according to claim 14 or 15, wherein the first field and the second field instruct the receiving end to perform frame delimitation on the data.

17. Multiple bitstreams exist, multiple lanes exist on the wired serial link, and the multiple bitstreams correspond one-to-one with the multiple lanes. The aforementioned interface is A data transmission device according to any one of claims 14 to 16, specifically configured to transmit a plurality of corresponding bitstreams through the plurality of lanes.

18. The data transmission device according to claim 17, wherein the control word further includes a fourth field indicating a lane number.

19. The aforementioned first field includes a group of multiple identical fields, and each group of fields includes multiple bits. The data transmission apparatus according to any one of claims 14 to 18, wherein the group of multiple identical fields is used to compensate for the difference between the clock cycle at the transmitting end and the clock cycle at the receiving end.

20. A data transmission device including a processor and an interface, The interface is configured to receive a bitstream, the bitstream comprising data and a control word, the control word comprising a first field indicating the start position information of the control word, a second field indicating the end position information of the control word, and a third field used to carry link information indicating a wired serial link, the length of the first field being variable, A data transmission device comprising a processor configured to read the control word from the bitstream based on the first field and the second field, and to read the data from the bitstream based on the control word.

21. The data transmission apparatus according to claim 20, wherein the processor is further configured to adjust, based on the link information, at least one of the following: the power consumption state of the hardware in the link, the operating state of the circuit in the link, or the gain of the codec used in the link.

22. The aforementioned processor, The coding length of the control word is determined based on the first field and the second field. Based on the coding length of the control word, the frame start position of the data is identified from the bitstream. The data transmission device according to claim 20 or 21, which is specifically configured to read the data based on the frame start position of the data.

23. Multiple bitstreams exist, multiple lanes exist on the wired serial link, the multiple bitstreams are received from the transmitting end through multiple corresponding lanes, the link information further includes the number of lanes for transmitting the multiple bitstreams, and the control word further includes a fourth field indicating the lane number. The aforementioned processor, A data transmission device according to any one of claims 20 to 22, specifically configured to read the data from the bitstreams received through the corresponding lanes based on the number of lanes for transmitting the plurality of bitstreams and the fourth field.

24. The aforementioned processor, The data transmission device according to claim 23, further configured to remove data skew between the plurality of lanes based on the sequence of the plurality of received bitstreams and a fourth field in each of the plurality of control words in the plurality of bitstreams.

25. The aforementioned first field includes a group of multiple identical fields, and each group of fields includes multiple bits. The aforementioned processor, The data transmission device according to any one of claims 20 to 24, further configured to perform one of the following operations based on a clock frequency offset between the data transmission device and the transmitting end: namely, removing at least one group of fields from a plurality of groups of the same fields, or adding at least one group of fields to a plurality of groups of the same fields.

26. A computer-readable storage medium configured to store computer programs, A computer-readable storage medium in which, when the computer program is executed by a processor, the method according to any one of claims 1 to 7 or the method according to any one of claims 8 to 13 is realized.

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