Method for manufacturing a display device and motherboard for a display device

Abstract

To provide a method for manufacturing a display device that can improve a yield rate.SOLUTION: A manufacturing method according to an embodiment includes: preparing a substrate including a panel section and a margin area; forming an organic insulating layer; forming a plurality of lower electrodes; forming a rib having a pixel opening; forming a first partition wall including a first lower portion and a first upper portion, in the margin area; forming a first lamination film including a first organic layer and a first upper electrode; and forming a first sealing layer covering the first lamination film. Forming the first partition wall includes: forming the first upper portion above the organic insulating layer; and removing a portion of the organic insulating layer exposed from the first upper portion and reducing a width of the organic insulating layer below the first upper portion to form the first lower portion. The first lamination film is formed over the entire substrate and is divided into a plurality of portions by the first partition wall, and the first sealing layer continuously covers the plurality of portions. An end part of the substrate and an end part of the first sealing layer are separated, and the first lamination film is exposed from the first sealing layer in an area between these end parts.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing a display device and a mother substrate for a display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. Such a display element includes a lower electrode, an organic layer covering the lower electrode, and an upper electrode covering the organic layer.

[0003] There are formed, on a large mother substrate, a plurality of panel portions each including a display area in which a large number of display elements are arranged. Further, by cutting out each panel portion, a display panel, which is a main element of the display device, is manufactured. In such a manufacturing process, a technique for improving the yield is required.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0005] One of the objectives of this invention is to provide a method for manufacturing a display device and a motherboard for a display device that can improve yield. [Means for solving the problem]

[0006] A method for manufacturing a display device according to an embodiment includes: preparing a substrate including a plurality of panel portions, each containing a display area, and a margin area surrounding the plurality of panel portions; forming an organic insulating layer made of an organic insulating material in the display area and the margin area; forming a plurality of lower electrodes, including a first lower electrode, in the display area; forming ribs having a plurality of pixel openings, including a first pixel opening that overlaps with the first lower electrode; forming a first partition wall in the margin area including a first lower part and a first upper part having an end protruding from the side surface of the first lower part; forming a first laminated film including a first organic layer that contacts the plurality of lower electrodes through the plurality of pixel openings, and a first upper electrode that covers the first organic layer; and forming a first sealing layer made of an inorganic insulating material that covers the first laminated film. The formation of the first partition wall includes forming the first upper part above the organic insulating layer, and forming the first lower part in the margin area by removing the portion of the organic insulating layer exposed from the first upper part and reducing the width of the organic insulating layer remaining below the first upper part. The first laminated film is formed over the entire substrate and is divided into multiple parts by the first partition wall. The first sealing layer continuously covers the multiple parts. In a plan view, the edges of the substrate and the edges of the first sealing layer are separated. Furthermore, in the region between the edges of the substrate and the edges of the first sealing layer, the first laminated film is exposed from the first sealing layer.

[0007] The mother board according to this embodiment includes a substrate including a plurality of panel portions, each containing a display area, and a margin area surrounding the plurality of panel portions; a lower electrode disposed in the display area; a rib having a pixel opening that overlaps with the lower electrode; a first partition wall formed in the margin area, including a first lower part made of an organic insulating material and a first upper part having an end protruding from the side surface of the first lower part; a laminated film including an organic layer that contacts the lower electrode through the pixel opening and an upper electrode covering the organic layer; and a sealing layer made of an inorganic insulating material covering the laminated film. The laminated film is formed in the plurality of panel portions and the margin area and is divided into a plurality of parts by the first partition wall. The sealing layer continuously covers the plurality of parts.

[0008] According to one aspect of the embodiment, in a plan view, the edge of the substrate and the edge of the sealing layer are separated. Furthermore, in the region between the edge of the substrate and the edge of the sealing layer, the laminated film is exposed from the sealing layer.

[0009] In another aspect of the embodiment, in a plan view, the edges of the laminated film and the edges of the sealing layer are aligned. Furthermore, in a plan view, the edges of the laminated film and the edges of the sealing layer are separated from the edges of the substrate. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 shows an example of the configuration of a display device according to the first embodiment. [Figure 2] Figure 2 is a schematic plan view showing an example of a sub-pixel layout. [Figure 3] Figure 3 is a schematic cross-sectional view of the display panel along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic plan view of the motherboard according to the first embodiment. [Figure 5] Figure 5 is a schematic plan view of a portion of the motherboard according to the first embodiment. [Figure 6] Figure 6 is a schematic cross-sectional view of the marginal area along the VI-VI line in Figure 5. [Figure 7] Figure 7 is a schematic cross-sectional view of the margin area along line VII-VII in Figure 5. [Figure 8] Figure 8 is a flowchart showing an example of a method for manufacturing a mother substrate and a display device according to the first embodiment. [Figure 9A] Figure 9A is a schematic cross-sectional view of the display area of the mother substrate during manufacturing. [Figure 9B] Figure 9B is a schematic cross-sectional view of the margin area of the mother substrate during manufacturing. [Figure 10A] Figure 10A is a schematic cross-sectional view of the display area showing the process following Figure 9A. <好 [Figure 10B] Figure 10B is a schematic cross-sectional view of the margin area showing the process following Figure 9B. [Figure 11A] r Figure 11A is a schematic cross-sectional view of the display area showing the process following Figure 10A. [Figure 11B] Figure 11B is a schematic cross-sectional view of the margin area showing the process following Figure 10B. [Figure 12A] Figure 12A is a schematic cross-sectional view of the display area showing the process following Figure 11A. [Figure 12B] Figure 12B is a schematic cross-sectional view of the margin area showing the process following Figure 11B. [Figure 13A] Figure I3A is a schematic cross-sectional view of the display area showing the process following Figure 12A. [Figure 13B] Figure 13B is a schematic cross-sectional view of the margin area showing the process following Figure 12B. [Figure 14A] Figure 14A is a schematic cross-sectional view of the display area showing the process following Figure 13A. [Figure 14B] Figure 14B is a schematic cross-sectional view of the margin area showing the process following Figure 13B. [Figure 15A] Figure 15A is a schematic cross-sectional view of the display area showing the process following Figure 14A. [Figure 15B] Figure 15B is a schematic cross-sectional view of the margin area showing the process following Figure 14B. [Figure 16A]Figure 16A is a schematic cross-sectional view of the display area showing the process following Figure 15A. [Figure 16B] Figure 16B is a schematic cross-sectional view of the margin area showing the process following Figure 15B. [Figure 17A] Figure 17A is a schematic cross-sectional view of the display area showing the process following Figure 16A. [Figure 17B] Figure 17B is a schematic cross-sectional view of the margin area showing the process following Figure 16B. [Figure 18A] Figure 18A is a schematic cross-sectional view of the display area showing the process following Figure 17A. [Figure 18B] Figure 18B is a schematic cross-sectional view of the margin area showing the process following Figure 17B. [Figure 19A] Figure 19A is a schematic cross-sectional view of the display area showing the process following Figure 18A. [Figure 19B] Figure 19B is a schematic cross-sectional view of the margin area showing the process following Figure 18B. [Figure 20] Figure 20 is a diagram illustrating the details of the process for forming the multilayer film and the sealing layer. [Figure 21] Figure 21 is a schematic cross-sectional view showing an example of the configuration near the edge of the substrate. [Figure 22] Figure 22 is a schematic cross-sectional view showing another example of the configuration near the edge of the substrate. [Figure 23] Figure 23 is a schematic cross-sectional view of the margin area of ​​the motherboard according to the comparative example. [Figure 24] Figure 24 is a schematic cross-sectional view of the margin area of ​​the motherboard according to the first embodiment. [Figure 25] Figure 25 is a diagram illustrating the details of the process for forming the laminated film and sealing layer according to the second embodiment. [Figure 26] Figure 26 is a schematic cross-sectional view showing another example of the configuration near the edge of the substrate according to the second embodiment. [Figure 27] Figure 27 is a schematic cross-sectional view of the margin area according to the third embodiment. [Figure 28]Figure 28 is a schematic cross-sectional view of the margin area according to the fourth embodiment. [Figure 29] Figure 29 is a schematic cross-sectional view showing the process of forming a partition wall in the margin area according to the fourth embodiment. [Figure 30] Figure 30 is a schematic cross-sectional view of the margin area showing the process following Figure 29. [Figure 31] Figure 31 is a schematic cross-sectional view of the margin area showing the process following Figure 30. [Figure 32] Figure 32 is a schematic cross-sectional view of the margin area showing the process following Figure 31. [Figure 33] Figure 33 is a schematic cross-sectional view of the margin area according to the fifth embodiment. [Modes for carrying out the invention]

[0011] Several embodiments will be described with reference to the drawings. The disclosure is merely an example, and any modifications that a person skilled in the art could easily conceive of while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part in order to clarify the explanation, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, the same reference numerals are used for components that perform the same or similar functions as those described above with respect to previously shown drawings, and redundant detailed explanations may be omitted as appropriate.

[0012] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X-axis will be referred to as the first direction X, the direction along the Y-axis as the second direction Y, and the direction along the Z-axis as the third direction Z. The third direction Z is the normal direction to the plane containing the first direction X and the second direction Y. Viewing the various elements parallel to the third direction Z is called a plan view.

[0013] Each embodiment of the display device is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0014] [First Embodiment] Figure 1 shows an example configuration of a display device DSP according to the first embodiment. The display device DSP includes a display panel PNL including an insulating substrate 10. The display panel PNL has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be glass or a flexible resin film.

[0015] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to a rectangle, and may be other shapes such as a square, circle, or ellipse.

[0016] The display area DA comprises multiple pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes multiple sub-pixels SP. In one example, pixel PX includes a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. Pixel PX may also include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of SP1, SP2, or SP3.

[0017] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0018] The gate electrode of pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to the power line PL and capacitor 4, and the other is connected to display element DE.

[0019] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0020] Figure 2 is a schematic plan view showing an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 2, sub-pixels SP2 and SP3 are aligned with sub-pixel SP1 in the first direction X. Furthermore, sub-pixels SP2 and SP3 are aligned in the second direction Y.

[0021] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP2 and SP3 are alternately arranged in the second direction Y, and columns in which multiple sub-pixels SP1 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X. Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2.

[0022] Ribs 5 are positioned in the display area DA. Ribs 5 have pixel apertures AP1, AP2, and AP3 (first to third pixel apertures) in sub-pixels SP1, SP2, and SP3, respectively. In the example in Figure 2, pixel aperture AP1 is larger than pixel aperture AP2, and pixel aperture AP2 is larger than pixel aperture AP3.

[0023] Sub-pixel SP1 comprises a lower electrode LE1 (first lower electrode), an upper electrode UE1 (first upper electrode), and an organic layer OR1 (first organic layer), which overlap with the pixel aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2 (second lower electrode), an upper electrode UE2 (second upper electrode), and an organic layer OR2 (second organic layer), which overlap with the pixel aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3 (third lower electrode), an upper electrode UE3 (third upper electrode), and an organic layer OR3 (third organic layer), which overlap with the pixel aperture AP3.

[0024] The portion of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlaps with the pixel aperture AP1 constitutes the display element DE1 (first display element) of the sub-pixel SP1. The portion of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlaps with the pixel aperture AP2 constitutes the display element DE2 (second display element) of the sub-pixel SP2. The portion of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlaps with the pixel aperture AP3 constitutes the display element DE3 (third display element) of the sub-pixel SP3. Display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. Rib 5 surrounds each of these display elements DE1, DE2, and DE3.

[0025] The lower electrode LE1 is connected to the pixel circuit 1 of the sub-pixel SP1 (see Figure 1) through the contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the sub-pixel SP2 through the contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the sub-pixel SP3 through the contact hole CH3.

[0026] A partition wall 6 (second partition wall) is positioned above rib 5. Partition wall 6 overlaps with rib 5 overall and has a similar planar shape to rib 5. Specifically, partition wall 6 has apertures AP61, AP62, and AP63 in sub-pixels SP1, SP2, and SP3, respectively. From another perspective, rib 5 and partition wall 6 are positioned between display elements DE1, DE2, and DE3, forming a grid in plan view.

[0027] Figure 3 is a schematic cross-sectional view of the display panel PNL along the line III-III in Figure 2. A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring, such as the pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1.

[0028] The circuit layer 11 is covered by an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11. Although not shown in the cross-section of Figure 3, the contact holes CH1, CH2, and CH3 described above are provided in the organic insulating layer 12.

[0029] The lower electrodes LE1, LE2, and LE3 are positioned on top of the organic insulating layer 12. The ribs 5 are positioned on top of the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the ribs 5.

[0030] The partition wall 6 includes a conductive lower section 61 (second lower section) positioned on the rib 5 and an upper section 62 (second upper section) positioned on top of the lower section 61. The upper section 62 has a greater width than the lower section 61. As a result, both ends of the upper section 62 protrude beyond the sides of the lower section 61. This shape of the partition wall 6 is called an overhang.

[0031] The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel aperture AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel aperture AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surface of the lower part 61 of the partition wall 6.

[0032] In the example shown in Figure 3, a cap layer CP1 (first cap layer) is placed on top of the upper electrode UE1, a cap layer CP2 (second cap layer) is placed on top of the upper electrode UE2, and a cap layer CP3 (third cap layer) is placed on top of the upper electrode UE3. The cap layers CP1, CP2, and CP3 each serve as optical adjustment layers that improve the efficiency of light extraction from the organic layers OR1, OR2, and OR3, respectively.

[0033] In the following explanation, a multilayer structure containing an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as the multilayer film FL1 (first multilayer film), a multilayer structure containing an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as the multilayer film FL2 (second multilayer film), and a multilayer structure containing an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as the multilayer film FL3 (third multilayer film).

[0034] A portion of the laminated film FL1 is located above the upper part 62. This portion is separated from the portion of the laminated film FL1 located below the partition wall 6 (the portion constituting the display element DE1). Similarly, a portion of the laminated film FL2 is located above the upper part 62, and this portion is separated from the portion of the laminated film FL2 located below the partition wall 6 (the portion constituting the display element DE2). Furthermore, a portion of the laminated film FL3 is located above the upper part 62, and this portion is separated from the portion of the laminated film FL3 located below the partition wall 6 (the portion constituting the display element DE3).

[0035] Sub-pixels SP1, SP2, and SP3 are each fitted with sealing layers SE1, SE2, and SE3 (first to third sealing layers). Sealing layer SE1 continuously covers the laminated film FL1 and the partition wall 6 surrounding sub-pixel SP1. Sealing layer SE2 continuously covers the laminated film FL2 and the partition wall 6 surrounding sub-pixel SP2. Sealing layer SE3 continuously covers the laminated film FL3 and the partition wall 6 surrounding sub-pixel SP3.

[0036] In the example shown in Figure 3, the laminated film FL1 and sealing layer SE1 on the partition wall 6 between sub-pixels SP1 and SP2 are spaced apart from the laminated film FL2 and sealing layer SE2 on the same partition wall 6. Furthermore, the laminated film FL1 and sealing layer SE1 on the partition wall 6 between sub-pixels SP1 and SP3 are spaced apart from the laminated film FL3 and sealing layer SE3 on the same partition wall 6.

[0037] The sealing layers SE1, SE2, and SE3 are covered by a resin layer 13. The resin layer 13 is covered by a sealing layer 14. The sealing layer 14 is covered by a resin layer 15. The resin layers 13, 15 and the sealing layer 14 are provided continuously over at least the entire display area DA, and a portion of them extends into the peripheral area SA.

[0038] A cover member, such as a polarizing plate, touch panel, protective film, or cover glass, may be further placed on top of the resin layer 15. Such a cover member may be bonded to the resin layer 15 via an adhesive layer, such as OCA (Optical Clear Adhesive).

[0039] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The ribs 5 and the sealing layers 14, SE1, SE2, SE3 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). In one example, the ribs 5 are formed of silicon oxynitride, and the sealing layers 14, SE1, SE2, SE3 are formed of silicon nitride. The resin layers 13, 15 are formed of resin materials (organic insulating materials) such as epoxy resin or acrylic resin.

[0040] The lower electrodes LE1, LE2, and LE3 each have a reflective layer formed of, for example, silver (Ag), and a pair of conductive oxide layers covering the upper and lower surfaces of this reflective layer, respectively. Each conductive oxide layer can be formed of a transparent conductive oxide such as ITO (IndiumTin Oxide), IZO (IndiumZinc Oxide), or IGZO (IndiumGalliumZinc Oxide).

[0041] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0042] The organic layers OR1, OR2, and OR3 have, for example, a laminated structure consisting of a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer. The organic layers OR1, OR2, and OR3 may also have a so-called tandem structure including multiple emissive layers.

[0043] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent thin films are stacked on top of each other. These multiple thin films may include thin films formed from inorganic materials and thin films formed from organic materials. Furthermore, these multiple thin films have different refractive indices. For example, the refractive indices of these thin films are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE1, SE2, and SE3. Note that at least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0044] The lower part 61 of the partition wall 6 is formed of, for example, aluminum. The lower part 61 may be formed of an aluminum alloy such as aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), and aluminum-silicon alloy (AlSi), or it may have a laminated structure of an aluminum layer and an aluminum alloy layer. Furthermore, the lower part 61 may have a bottom layer formed of a metallic material different from aluminum or an aluminum alloy below the aluminum layer or aluminum alloy layer. Examples of metallic materials that can form such a bottom layer include molybdenum (Mo), titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb).

[0045] For example, the upper part 62 of the partition wall 6 has a laminated structure consisting of a lower layer made of a metallic material and an upper layer made of a conductive oxide. Examples of metallic materials that can form the lower layer include titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy. Examples of conductive oxides that can form the upper layer include ITO or IZO. The upper part 62 may also have a single-layer structure of a metallic material.

[0046] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the side surface of the lower part 61. Pixel voltages are supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0047] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of organic layer OR1 emits light in the blue wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of organic layer OR2 emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of organic layer OR3 emits light in the red wavelength range.

[0048] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0049] During the manufacturing of a display device (DSP), a large motherboard is created in which multiple areas (panel sections) corresponding to the display panel PNL are formed. The following describes the configurations that can be applied to this motherboard.

[0050] Figure 4 is a schematic plan view of a motherboard MB (display device motherboard) according to this embodiment. The motherboard MB includes an insulating substrate 10a as a base. In the example in Figure 4, the substrate 10a is rectangular in shape, having linear ends Ea1, Ea2 parallel to the second direction Y and linear ends Ea3, Ea4 parallel to the first direction X. However, the shape of the motherboard MB is not limited to a rectangular shape.

[0051] The substrate 10a has a plurality of panel sections PP arranged in a matrix and a margin area BA surrounding these panel sections PP. The margin area BA includes an outer peripheral area FA along the edges Ea1, Ea2, Ea3, and Ea4. The outer peripheral area FA is, for example, the area from the edges Ea1, Ea2, Ea3, and Ea4 to a predetermined distance and does not include the partition wall 7 described later. The width Wf of the outer peripheral area FA is, for example, constant around the entire circumference, but is not limited to this example. In one example, the width Wf is 5 mm or more, and specifically can be about 10 mm.

[0052] Figure 5 is a schematic plan view of a portion of the motherboard MB. The outline of each panel section PP corresponds to the cut line CL used to cut out the panel section PP from the motherboard MB. Each panel section PP has the display area DA and peripheral area SA described above.

[0053] As shown in the enlarged view in Figure 5, a partition wall 7 (first partition wall) is located in the marginal area BA. The partition wall 7 has a plurality of first linear portions 7x arranged parallel to each other and a plurality of second linear portions 7y arranged parallel to each other.

[0054] Multiple first linear sections 7x extend in the second direction Y and are aligned in the first direction X. Multiple second linear sections 7y extend in the first direction X and are aligned in the second direction Y. In the example in Figure 5, each first linear section 7x and each second linear section 7y intersect. As a result, the partition wall 7 as a whole is lattice-shaped.

[0055] From another perspective, the partition wall 7 forms multiple closed regions CA. Each closed region CA is a square or rectangular area enclosed by two adjacent first linear sections 7x and two adjacent second linear sections 7y.

[0056] The first linear portion 7x has a width Wx1 in the first direction X. The second linear portion 7y has a width Wy1 in the second direction Y. The closed region CA has a width Wx2 in the first direction X and a width Wy2 in the second direction Y. The width Wx2 corresponds to the spacing between the multiple first linear portions 7x. The width Wy2 corresponds to the spacing between the multiple second linear portions 7y.

[0057] For example, width Wx2 is greater than the width of each sub-pixel SP1, SP2, and SP3 in the first direction X. Also, width Wy2 is greater than the width of each sub-pixel SP1, SP2, and SP3 in the second direction Y. In the example in Figure 5, widths Wx2 and Wy2 are greater than widths Wx1 and Wy1, respectively (Wx2>Wx1, Wy2>Wy1). As will be explained in more detail later, it is preferable that at least one of widths Wx2 and Wy2 is 200 μm or less (Wx2, Wy2 ≤ 200 μm).

[0058] The grid pattern on the motherboard MB in Figure 5 indicates the areas where partition walls 7 are provided. In other words, in the example in Figure 5, partition walls 7 are provided not only in the margin area BA but also in the peripheral area SA. The partition walls 7 provided in the peripheral area SA remain on the panel area PP (display panel PNL) even after the panel area PP is cut out along the cut line CL. Partition walls 7 are not provided in the display area DA. Also, partition walls 7 are not provided in the outer peripheral area FA of the margin area BA.

[0059] From the viewpoint of efficiently cutting out the panel portion PP, it is preferable that no partition wall 7 is provided at the cut line CL. In this case, the partition wall 7 provided in the peripheral region SA and the partition wall 7 provided in the margin region BA are separated at the boundary between the peripheral region SA and the margin region BA.

[0060] Furthermore, the partition wall 7 does not need to be provided over the entire surrounding area SA. Also, the marginal area BA may include areas other than the outer peripheral area FA where the partition wall 7 is not provided.

[0061] Figure 6 is a schematic cross-sectional view of the margin area BA along the VI-VI line in Figure 5. The motherboard MB includes the substrate 10a described above. When cutting out the panel portion PP from the motherboard MB, the substrate 10a is cut along the cut line CL. The substrate 10a of the cut-out panel portion PP corresponds to the substrate 10 shown in Figure 3, etc.

[0062] The motherboard MB includes an underlayment layer 11a positioned above the substrate 10a in the margin area BA. The underlayment layer 11a is, for example, part of the circuit layer 11 shown in Figure 3, and is also positioned in the display area DA. The underlayment layer 11a is formed of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0063] The partition wall 7 includes a lower part 71 (first lower part) positioned on the subsoil layer 11a and an upper part 72 (first upper part) positioned on the lower part 71. The upper part 72 has a greater width than the lower part 71. As a result, both ends of the upper part 72 protrude beyond the sides of the lower part 71. Thus, the partition wall 7 is overhanging, just like the partition wall 6 shown in Figure 3.

[0064] In this embodiment, the lower part 71 is made of the same organic insulating material as the organic insulating layer 12. The upper part 72 is made of the same inorganic insulating material as the rib 5.

[0065] Note that the structure of the margin area BA is not limited to the example in Figure 6. Other insulating or conductive layers may be interposed between the substrate 10a and the base layer 11a. Furthermore, the base layer 11a and the partition wall 7 may be covered by other insulating or conductive layers.

[0066] Figure 7 is a schematic cross-sectional view of the margin region BA along the line VII-VII in Figure 5. In the example in Figure 7, the underlayer 11a covers the entire substrate 10a. In another example, the substrate 10a may have a region near the edge Ea1 that is not covered by the underlayer 11a.

[0067] The same cross-sectional structure as in Figure 7 can be applied to the vicinity of the other ends Ea2, Ea3, and Ea4 of the substrate 10a. In the cross-section of Figure 7, the outer peripheral region FA corresponds to the region between the first linear portion 7x closest to end Ea1 and end Ea1, among the multiple first linear portions 7x of the partition wall 7. Similarly, other parts of the outer peripheral region FA correspond to the region between the first linear portion 7x or second linear portion 7y closest to ends Ea2, Ea3, and Ea4 and these ends Ea2, Ea3, and Ea4.

[0068] Next, we will explain the manufacturing methods for the motherboard (MB) and the display device (DSP). Figure 8 is a flowchart showing an example of a manufacturing method for a motherboard MB and a display device DSP. Figures 9A to 19A are schematic cross-sectional views of the display area DA on the motherboard MB during the manufacturing process. Figures 9B to 19B are schematic cross-sectional views of the margin area BA on the motherboard MB during the manufacturing process. The same manufacturing process as in Figures 9B to 19B can be applied to the peripheral area SA. Note that the elements below the base layer 11a are omitted in Figures 9A to 19A and Figures 9B to 19B.

[0069] In the manufacturing of a display device DSP, first a large substrate 10a is prepared, which includes multiple panel sections PP and areas corresponding to margin areas BA (step PR1). Next, a circuit layer 11 and an organic insulating layer 12 are formed on the substrate 10a (step PR2).

[0070] After step PR2, the lower electrodes LE1, LE2, LE3, rib 5, partition wall 6, and partition wall 7 are formed (step PR3). The flow of step PR3 in this embodiment is shown in Figures 9A to 13A and 9B to 13B.

[0071] Specifically, as shown in Figures 9A and 9B, a conductive layer CD for processing the lower electrodes LE1, LE2, and LE3 is first formed on the entire motherboard MB, including the display area DA, the margin area BA, and the peripheral area SA. The conductive layer CD covers the organic insulating layer 12. As described above, if the lower electrodes LE1, LE2, and LE3 have a pair of conductive oxide layers and a reflective layer between them, the conductive layer CD includes three layers corresponding to these conductive oxide and reflective layers, respectively.

[0072] Next, the conductive layer CD is patterned as shown in Figures 10A and 10B. This forms the lower electrodes LE1, LE2, and LE3 in the display area DA. On the other hand, the conductive layer CD is completely removed in the blank area BA and the surrounding area SA.

[0073] After patterning the conductive layer CD, an inorganic insulating layer 100 for processing into the rib 5 is formed over the entire motherboard MB, as shown in Figures 11A and 11B. Furthermore, a first layer 101 for processing into the lower part 61 is formed on top of the inorganic insulating layer 100, and a second layer 102 for processing into the upper part 62 is formed on top of the first layer 101.

[0074] Next, as shown in Figures 12A and 12B, the first layer 101 and the second layer 102 are patterned. This patterning includes etching to shape the second layer 102 into the shape of the upper part 62 and etching to shape the first layer 101 into the shape of the lower part 61. These etchings form a partition wall 6, including the lower part 61 and the upper part 62, in the display area DA. Meanwhile, in the blank area BA and the peripheral area SA, the first layer 101 and the second layer 102 are removed entirely. A conductive layer for connecting the partition wall 6 to a common voltage power supply line may be formed in the peripheral area SA using the first layer 101 and the second layer 102.

[0075] After the formation of the partition wall 6, the inorganic insulating layer 100 is patterned as shown in Figure 13A, and pixel apertures AP1, AP2, and AP3 are formed that overlap with the lower electrodes LE1, LE2, and LE3, respectively. As a result, ribs 5 are formed in the display area DA.

[0076] In this patterning process, as shown in Figure 13B(a), the portion of the inorganic insulating layer 100 corresponding to the closed region CA (see Figure 5) is removed. This forms an upper portion 72 made of inorganic insulating material in the margin region BA and the surrounding region SA. Subsequently, ashing is performed on the organic insulating layer 12. In this ashing process, as shown in Figure 13B(b), the portion of the organic insulating layer 12 exposed from the upper portion 72 is removed, and the width of the organic insulating layer 12 remaining below the upper portion 72 is reduced. This forms a lower portion 71 made of organic insulating material.

[0077] After step PR3 described above, a process for forming display elements DE1, DE2, and DE3 is carried out. In this embodiment, it is assumed that display element DE1 is formed first, display element DE2 is formed next, and display element DE3 is formed last. However, the formation order of display elements DE1, DE2, and DE3 is not limited to this example.

[0078] In forming the display element DE1, first, as shown in Figures 14A and 14B, a laminated film FL1 and a sealing layer SE1 are formed on each panel portion PP and margin area BA (step PR4). As shown in Figure 3, the laminated film FL1 includes an organic layer OR1 that contacts the lower electrode LE1 through the pixel aperture AP1, an upper electrode UE1 that covers the organic layer OR1, and a cap layer CP1 that covers the upper electrode UE1. The organic layer OR1, upper electrode UE1, and cap layer CP1 are formed by vapor deposition. The sealing layer SE1 is formed by CVD (Chemical Vapor Deposition).

[0079] The laminated film FL1 is divided into multiple parts by overhanging partitions 6 and 7. As shown in Figure 14A, the laminated film FL1 in the display area DA covers the exposed lower electrodes LE1, LE2, LE3, ribs 5, and partitions 6 through the pixel apertures AP1, AP2, AP3. Also, as shown in Figure 14B, the laminated film FL1 in the margin area BA and peripheral area SA covers the base layer 11a and partitions 7. The sealing layer SE1 continuously covers each divided part of the laminated film FL1 and the partitions 6 and 7.

[0080] After step PR4, the laminated film FL1 and the sealing layer SE1 are patterned (step PR5). In this patterning, as shown in Figure 14A, resist R1 is placed on top of the sealing layer SE1. Resist R1 covers the subpixel SP1 and a portion of the surrounding partition wall 6. Resist R1 is not placed in the blank area BA or the peripheral area SA.

[0081] Subsequently, etching using the resist R1 as a mask removes the portions of the multilayer film FL1 and the sealing layer SE1 that are exposed from the resist R1, as shown in Figure 15A. In other words, the portions of the multilayer film FL1 and the sealing layer SE1 that overlap with the lower electrode LE1 are left, and the other portions are removed. This forms the display element DE1 on the sub-pixel SP1. For example, this etching includes wet etching or dry etching performed sequentially on the sealing layer SE1, the cap layer CP1, the upper electrode UE1, and the organic layer OR1.

[0082] The margin region BA and the surrounding region SA are also exposed to the etching process. Therefore, as shown in Figure 15B, the multilayer film FL1 and the sealing layer SE1 located in the margin region BA and the surrounding region SA are removed. After the etching, the resist R1 is removed.

[0083] The display element DE2 is formed using the same procedure as the display element DE1. Specifically, in forming the display element DE2, the laminated film FL2 and the sealing layer SE2 are first formed on each panel portion PP and margin region BA, as shown in Figures 16A and 16B (step PR6). The laminated film FL2, as shown in Figure 3, includes an organic layer OR2 that contacts the lower electrode LE2 through the pixel aperture AP2, an upper electrode UE2 that covers the organic layer OR2, and a cap layer CP2 that covers the upper electrode UE2. The organic layer OR2, the upper electrode UE2, and the cap layer CP2 are formed by vapor deposition. The sealing layer SE2 is formed by CVD.

[0084] The laminated film FL2 is divided into multiple parts by overhanging partitions 6 and 7. The sealing layer SE2 continuously covers each divided part of the laminated film FL2 and the partitions 6 and 7.

[0085] After step PR6, the laminated film FL2 and the sealing layer SE2 are patterned (step PR7). In this patterning, as shown in Figure 16A, a resist R2 is placed on top of the sealing layer SE2. The resist R2 covers the subpixel SP2 and a portion of the surrounding partition wall 6. The resist R2 is not placed in the blank area BA or the peripheral area SA.

[0086] Subsequently, etching using the resist R2 as a mask removes the portions of the multilayer film FL2 and the sealing layer SE2 that are exposed from the resist R2, as shown in Figure 17A. In other words, the portions of the multilayer film FL2 and the sealing layer SE2 that overlap with the lower electrode LE2 are left, and the other portions are removed. This forms the display element DE2 on the sub-pixel SP2. For example, this etching includes wet etching or dry etching performed sequentially on the sealing layer SE2, the cap layer CP2, the upper electrode UE2, and the organic layer OR2.

[0087] The margin area BA is also exposed to the etching process. Therefore, as shown in Figure 17B, the laminated film FL2 and the sealing layer SE2 located in the margin area BA and the surrounding area SA are removed. After the etching, the resist R2 is removed.

[0088] The display element DE3 is formed using the same procedure as the display elements DE1 and DE2. Specifically, in forming the display element DE3, the laminated film FL3 and the sealing layer SE3 are first formed on each panel portion PP and margin region BA, as shown in Figures 18A and 18B (step PR8). The laminated film FL3, as shown in Figure 3, includes an organic layer OR3 that contacts the lower electrode LE3 through the pixel aperture AP3, an upper electrode UE3 that covers the organic layer OR3, and a cap layer CP3 that covers the upper electrode UE3. The organic layer OR3, upper electrode UE3, and cap layer CP3 are formed by vapor deposition. The sealing layer SE3 is formed by CVD.

[0089] The laminated film FL3 is divided into multiple parts by overhanging partitions 6 and 7. The sealing layer SE3 continuously covers each divided part of the laminated film FL3 and the partitions 6 and 7.

[0090] After step PR8, the laminated film FL3 and the sealing layer SE3 are patterned (step PR9). In this patterning, as shown in Figure 18A, a resist R3 is placed on top of the sealing layer SE3. The resist R3 covers the subpixel SP3 and a portion of the surrounding partition wall 6. The resist R3 is not placed in the blank area BA or the peripheral area SA.

[0091] Subsequently, etching using the resist R3 as a mask removes the portions of the multilayer film FL3 and the sealing layer SE3 that are exposed from the resist R3, as shown in Figure 19A. In other words, the portions of the multilayer film FL3 and the sealing layer SE3 that overlap with the lower electrode LE3 are left, and the other portions are removed. This forms the display element DE3 on the sub-pixel SP3. For example, this etching includes wet etching or dry etching performed sequentially on the sealing layer SE3, the cap layer CP3, the upper electrode UE3, and the organic layer OR3.

[0092] The margin region BA and the surrounding region SA are also exposed to the etching process. Therefore, as shown in Figure 19B, the multilayer film FL3 and the sealing layer SE3 located in the margin region BA and the surrounding region SA are removed. After the etching, the resist R3 is removed.

[0093] After the display elements DE1, DE2, and DE3 are formed, the resin layer 13, sealing layer 14, and resin layer 15 shown in Figure 3 are sequentially formed on each panel portion PP (step PR10). Furthermore, each panel portion PP is cut out from the motherboard MB (step PR11). The cut-out panel portion PP corresponds to the display panel PNL.

[0094] Figure 20 is a diagram illustrating the details of step PR4, which involves forming the multilayer film FL1 and the sealing layer SE1. Figures (a), (b), and (c) in Figure 20 are cross-sections of the mother substrate MB near the edge Ea1 of the substrate 10a.

[0095] Figure 20(a) shows the state before the laminated film FL1 and the sealing layer SE1 are formed, and illustrates the outer peripheral region FA and the partition wall 7 (first linear portion 7x) located near the outer peripheral region FA.

[0096] Figure 20(b) shows the process of forming the multilayer film FL1 by vapor deposition. The multilayer film FL1 is formed over the entire substrate 10a, including the outer peripheral region FA. Therefore, the edge Eb of the multilayer film FL1 aligns with the edge Ea1 of the substrate 10a in a plan view.

[0097] Figure 20(c) shows the process of forming the sealing layer SE1 by CVD. In this process, the mother substrate MB is placed in the vacuum chamber of the CVD apparatus, and the peripheral edges of the mother substrate MB are held down by the outer peripheral frame FM. For example, the outer peripheral frame FM holds down not only the peripheral edges near the illustrated end Ea1, but also the peripheral edges near ends Ea2, Ea3, and Ea4.

[0098] When CVD is performed with the outer frame FM positioned in this manner, the sealing layer SE1 is not formed in the mask region MA that overlaps with the outer frame FM. In the example in Figure 20, the mask region MA overlaps with the entire outer region FA. Furthermore, the mask region MA also overlaps with several first linear portions 7x near the end Ea1.

[0099] When the laminated film FL1 and the sealing layer SE1 are formed in this process, the edge Ea1 of the substrate 10a and the edge Ec of the sealing layer SE1 are separated in a plan view. In the region between these edges Ea1 and Ec, i.e., the mask region MA, the laminated film FL1 is exposed from the sealing layer SE1. Furthermore, the edge Ec of the sealing layer SE1 is located closer to the center of the substrate 10a (to the right in Figure 20) than the first linear portion 7x closest to the edge Ea1 of the substrate 10a. The sealing layer SE1 does not cover some of the first linear portions 7x that are close to the edge Ea1 of the substrate 10a.

[0100] Figure 21 is a schematic cross-sectional view showing an example of the configuration near the edges Ea1 and Ea2 of the substrate 10a. The configuration near edge Ea1, shown in the upper part of the figure, is the same as that in Figure 20(c). The configuration near edge Ea2, shown in the lower part of the figure, is substantially symmetrical to that in Figure 20(c).

[0101] In other words, even in the vicinity of edge Ea2, edge Eb of the multilayer film FL1 is aligned with edge Ea2. Furthermore, edge Ec of the sealing layer SE1 is separated from edge Ea2, and the multilayer film FL1 is exposed from the sealing layer SE1 in the region between edges Ec and Ea2 (mask region MA).

[0102] Figure 22 is a schematic cross-sectional view showing another example of the configuration near the edges Ea1 and Ea2 of the substrate 10a. Even when the outer peripheral frame FM should be positioned so that the mask region MA near edge Ea1 and the mask region MA near edge Ea2 have the same width, as shown in Figure 21, the positional relationship between the outer peripheral frame FM and the substrate 10a may be misaligned.

[0103] In the example shown in Figure 22, the positional relationship between the outer frame FM and the substrate 10a is shifted, resulting in a smaller mask area MA near edge Ea1 and a larger mask area MA near edge Ea2. In this case, the position of the sealing layer SE1 relative to the substrate 10a is also shifted. In the example shown in Figure 22, as shown in the upper panel, the sealing layer SE1 covers the first linear portion 7x closest to edge Ea1, and the edge Ec of the sealing layer SE1 is located between the first linear portion 7x and edge Ea1. On the other hand, as shown in the lower panel of Figure 22, near edge Ea2, the amount of the first linear portion 7x not covered by the sealing layer SE1 is greater than in the example shown in Figure 21.

[0104] Note that the area covered by the sealing layer SE1 is not limited to the examples in Figures 21 and 22. For example, the sealing layer SE1 may cover both the first linear portion 7x closest to end Ea1 and the first linear portion 7x closest to end Ea2.

[0105] Figures 20 to 22 mainly focus on the configuration near the edges Ea1 and Ea2 of the substrate 10a, but the laminated film FL1 and the sealing layer SE1 are formed in the vicinity of the edges Ea3 and Ea4 by a similar process. That is, the edge Ec of the sealing layer SE1 is separated from the edges Ea3 and Ea4 of the substrate 10a in a plan view. Furthermore, in the region between the edge Ec and the edges Ea3 and Ea4 (mask region MA), the laminated film FL1 is exposed from the sealing layer SE1. Multiple second linear portions 7y are arranged near the edges Ea3 and Ea4, and the sealing layer SE2 does not have to cover the second linear portion 7y closest to the edges Ea3 and Ea4, respectively. Alternatively, the sealing layer SE1 may cover at least one of the second linear portion 7y closest to the edge Ea3 and the second linear portion 7y closest to the edge Ea4.

[0106] Step PR6, which forms the multilayer film FL2 and the sealing layer SE2, and step PR8, which forms the multilayer film FL3 and the sealing layer SE3, are carried out in the same flow as step PR4 shown in Figure 20. Therefore, the edges of the multilayer film FL2 formed in step PR6 are aligned with the edges Ea1, Ea2, Ea3, and Ea4 of the substrate 10a, while the edges of the sealing layer SE2 are separated from these edges Ea1, Ea2, Ea3, and Ea4. Similarly, the edges of the multilayer film FL3 formed in step PR8 are aligned with the edges Ea1, Ea2, Ea3, and Ea4 of the substrate 10a, while the edges of the sealing layer SE3 are separated from these edges Ea1, Ea2, Ea3, and Ea4.

[0107] According to the motherboard MB and manufacturing method of this embodiment, it is possible to improve the yield during manufacturing. This effect will be explained below with reference to Figures 23 and 24.

[0108] Figure 23 is a schematic cross-sectional view of the margin region BA (or peripheral region SA) of a mother substrate MBc according to a comparative example. Mother substrate MBc differs from mother substrate MB according to this embodiment in that it does not have a partition wall 7 and the organic insulating layer 12 in the margin region BA is covered with an inorganic insulating layer 100. The cross-section in Figure 23(a) corresponds to the same process as in Figure 14B, and the laminated film FL1 and the sealing layer SE1 are formed in the margin region BA.

[0109] During the patterning of the laminated film FL1 and the sealing layer SE1 (step PR5 in Figure 8), the mother substrate MB is exposed to cleaning processes such as rinsing with water in the atmosphere and resist development processes. In addition, minute pinholes may occur in the sealing layer SE1, which is formed of inorganic insulating material. If moisture penetrates the laminated film FL1 through these pinholes during cleaning or other processes and reaches the interface between the organic layer OR1 and the inorganic insulating layer 100, a delamination area G may occur where the organic layer OR1 lifts away from the surface of the inorganic insulating layer 100.

[0110] When moisture travels through the organic layer OR1, the delamination area G expands as shown in Figure 23(b), weakening the adhesion between the laminated film FL1 and the inorganic insulating layer 100. As a result, as shown in Figure 23(c), a portion of the laminated film FL1 and the sealing layer SE1 may peel off. The peeled-off laminated film FL1 and sealing layer SE1 can contribute to contamination of chambers and other parts of the manufacturing line. Therefore, cleaning of the contaminated area becomes necessary, requiring the manufacturing line to be shut down.

[0111] Figure 24 is a schematic cross-sectional view of the margin area BA (or peripheral area SA) of the motherboard MB according to this embodiment. In Figure 24(a), the laminated film FL1 and sealing layer SE1 are formed in the margin area BA, as in Figure 23(a). In addition, moisture has penetrated the laminated film FL1, resulting in a delamination area G.

[0112] Furthermore, in Figure 24(b), the delamination area G is enlarged. However, in this embodiment, partition walls 7 are placed in the margin area BA and the surrounding area SA, and the laminated film FL1 is divided by these partition walls 7. Therefore, the enlargement of the delamination area G is suppressed.

[0113] Specifically, as shown in Figure 24, if a delamination area G occurs between the laminated film FL1 and the underlying layer 11a, the spread of this delamination area G is suppressed to remain within the closed region CA. Furthermore, if a delamination area G occurs in the laminated film FL1 located on the partition wall 7, the spread of this delamination area G is suppressed to remain on the partition wall 7.

[0114] Furthermore, as shown in Figure 24(b), at the location where delamination G occurs, the laminated film FL1 is held down by the sealing layer SE1. Therefore, the laminated film FL1 and the sealing layer SE1 are less likely to peel off.

[0115] As shown in Figure 5, when the partition wall 7 is composed of multiple first linear portions 7x and multiple second linear portions 7y, it is preferable that the spacing between adjacent first linear portions 7x (width Wx2 of the closed region CA) and the spacing between adjacent second linear portions 7y (width Wy2 of the closed region CA) are 200 μm or less. This keeps the width of the delamination portion G in the closed region CA within a narrow range of 200 μm or less, making it less likely for the laminated film FL1 and the sealing layer SE1 to peel off.

[0116] For example, sputtering is used to form the first layer 101 and the second layer 102 that are patterned on the partition wall 7 (see Figure 11B). When sputtering is performed, an area of ​​about 5 mm from the edge of the substrate to be processed is usually masked, and the film thickness is unstable in the area from the edge up to about 8 mm. In addition, the resist used in photolithography patterning can become thicker near the edge of the substrate. Therefore, normal patterning is difficult near the edge of the substrate, and generally the resist near the edge of the substrate is removed.

[0117] As a result of these considerations, it is not possible to form partition walls 7 near the edges Ea1, Ea2, Ea3, and Ea4 of the substrate 10a, resulting in the outer peripheral region FA shown in Figures 4 and 5. If the sealing layer SE1 is to be formed on the outer peripheral region FA as well, and a delamination area G occurs in the outer peripheral region FA, the delamination area G will spread over a wide area as shown in the example in Figure 23, and the laminated film FL1 and the sealing layer SE1 may peel off.

[0118] In contrast, in this embodiment, the sealing layer SE1 in the outer peripheral region FA is removed. If the sealing layer SE1, which is thicker and harder than the laminated film FL1, is absent, even if a delamination G occurs, it is less likely to spread to the surrounding area. Also, if the sealing layer SE1 is absent, peeling of the sealing layer SE1 itself will not occur. Therefore, according to the configuration of this embodiment, peeling of the laminated film FL1 and the sealing layer SE1 near the edges Ea1, Ea2, Ea3, Ea4 of the substrate 10a can be effectively suppressed.

[0119] Furthermore, as shown in Figure 21, if the sealing layer SE1 does not cover the first linear portion 7x closest to the ends Ea1 and Ea2, then even if the position of the sealing layer SE1 shifts as shown in Figure 22, the area of ​​the sealing layer SE1 formed in the outer peripheral region FA can be kept small. This reduces the risk of the aforementioned peeling. Similar effects can be obtained in the vicinity of the ends Ea3 and Ea4 by designing the sealing layer SE1 so that the outermost second linear portion 7y is not covered by the sealing layer SE1 when it is formed in the correct position.

[0120] Furthermore, the effects described above, focusing on the laminated film FL1 and the sealing layer SE1, also occur similarly for the laminated films FL2 and FL3 and the sealing layers SE2 and SE3. In other words, according to this embodiment, peeling of the laminated films FL2 and FL3 and the sealing layers SE2 and SE3 can be suppressed, and the yield can be improved.

[0121] [Second Embodiment] In the second embodiment, other examples applicable to steps PR4, PR6, and PR8 for forming the multilayer films FL1, FL2, FL3 and the sealing layers SE1, SE2, SE3 are disclosed. Configurations not specifically mentioned are the same as in the first embodiment.

[0122] Figure 25 is a diagram illustrating the details of step PR4 for forming the laminated film FL1 and the sealing layer SE1 according to the second embodiment. Figures (a), (b), (c), and (d) in Figure 25 are cross-sections of the mother substrate MB near the edge Ea1 of the substrate 10a. The steps in Figures 25(a), (b), and (c) are the same as the steps in Figures 20(a), (b), and (c). In this embodiment, step 25(d) is performed after the sealing layer SE1 is formed.

[0123] In the process shown in Figure 25(d), the laminated film FL1 is etched using the encapsulation layer SE1 as a mask. This etching removes the portion of the laminated film FL1 located between the edge Ea1 of the substrate 10a and the edge Ec of the encapsulation layer SE1. As a result, the edges Eb of the laminated film FL1 and Ec of the encapsulation layer SE1 are aligned in a plan view.

[0124] From another perspective, the edge Eb of the multilayer film FL1 and the edge Ec of the sealing layer SE1 are separated from the edge Ea1 of the substrate 10a in a plan view. The edges Eb and Ec are located closer to the center of the substrate 10a (to the right in Figure 25) than the first linear portion 7x that is closest to the edge Ea1. Note that the etching in Figure 25(d) is performed before the patterning in step PR5 (see Figure 8).

[0125] Figure 26 is a schematic cross-sectional view showing another example of the configuration near the edge Ea1 of the substrate 10a. In Figure 26, as in the example in Figure 22, the sealing layer SE1 covers the first linear portion 7x closest to the edge Ea1. The edge Ec of the sealing layer SE1 is located between the first linear portion 7x closest to the edge Ea1 and the edge Ea1.

[0126] When the laminated film FL1 is etched using such a sealing layer SE1 as a mask, the end Eb of the laminated film FL1 is located between the first linear portion 7x, which is closest to the end Ea1, and the end Ea1, just like the end Ec.

[0127] In Figures 25 and 26, we focused on the vicinity of edge Ea1 of the substrate 10a, but the same configuration can be applied to the vicinity of edges Ea2, Ea3, and Ea4. That is, the edge Eb of the multilayer film FL1 may be aligned with the edge Ec of the sealing layer SE1 around its entire circumference, and may be separated from the edges Ea1, Ea2, Ea3, and Ea4 of the substrate 10a.

[0128] As in this embodiment, by removing the laminated film FL1 exposed from the sealing layer SE1 at the peripheral edge of the substrate 10a, it is possible to reliably suppress the peeling of the laminated film FL1 in the outer peripheral region FA where the partition wall 7 is not formed. The same effect as with the laminated film FL2 and FL3 can be achieved by performing the same process as in Figure 25(d).

[0129] Figures 25 and 26 show an example in which the entire multilayer film FL1 exposed from the sealing layer SE1 is removed. In another example, at least one of the multiple layers constituting the multilayer film FL1 exposed from the sealing layer SE1 (each layer constituting the cap layer CP1, the upper electrode UE1, and the organic layer OR1) may be removed. Even in this case, the risk of peeling of the multilayer film FL1 can be reduced.

[0130] For example, after the formation of the sealing layer SE1, the cap layer CP1 may be etched while maintaining a vacuum around the motherboard MB. In this case, the organic layer OR1 and the upper electrode UE1 exposed from the cap layer CP1 may remain without being removed until the patterning in step PR5 (see Figure 8).

[0131] Similarly, with respect to the multilayer film FL2, the cap layer CP2 exposed from the sealing layer SE2 may be removed, while the organic layer OR2 and upper electrode UE2 exposed from the cap layer CP2 may remain until patterning in step PR7. Furthermore, similarly with respect to the multilayer film FL3, the cap layer CP3 exposed from the sealing layer SE3 may be removed, while the organic layer OR3 and upper electrode UE3 exposed from the cap layer CP3 may remain until patterning in step PR9.

[0132] [Third Embodiment] In the third embodiment, other configurations applicable to the partition wall 7 and its vicinity are disclosed. The configurations in this embodiment can be applied to either the first or second embodiment.

[0133] Figure 27 is a schematic cross-sectional view of the marginal region BA (or peripheral region SA) according to the third embodiment. In this example, a bottom portion 73 is formed on the base layer 11a in the closed region CA. The bottom portion 73 is formed of the same organic insulating material as the lower portion 71 and is connected to the lower portion 71.

[0134] Both the lower portion 71 and the bottom portion 73 are formed by processing the organic insulating layer 12. That is, in the ashing shown in Figure 13B(b), the bottom portion 73 can be formed by leaving a part of the organic insulating layer 12 in the closed region CA.

[0135] [Fourth Embodiment] In the fourth embodiment, further configurations applicable to the partition wall 7 and its vicinity are disclosed. The configurations according to this embodiment can be applied to either the first or second embodiment.

[0136] Figure 28 is a schematic cross-sectional view of the margin region BA (or peripheral region SA) according to the fourth embodiment. In this example, the upper part 72 is formed of the same conductive material as the lower electrodes LE1, LE2, and LE3. As described above, when the lower electrodes LE1, LE2, and LE3 have a pair of conductive oxide layers and a reflective layer between them, the upper part 72 includes three layers corresponding to these conductive oxide and reflective layers, respectively.

[0137] Figures 29 to 32 are schematic cross-sectional views showing the process of forming the partition wall 7 according to this embodiment. When manufacturing the display device DSP according to this embodiment, the processes shown in Figures 29 to 32 are carried out instead of the processes shown in Figures 10B to 13B.

[0138] In other words, when the lower electrodes LE1, LE2, and LE3 are formed (see Figure 10A), the conductive layer CD is patterned in the shape of the upper part 72 in the margin region BA and the surrounding region SA, as shown in Figure 29.

[0139] Next, as shown in Figure 30, the inorganic insulating layer 100, the first layer 101, and the second layer 102 are formed in the same way as in the process shown in Figure 11B. In the margin region BA and the surrounding region SA, these inorganic insulating layers 100, the first layer 101, and the second layer 102 are all removed as shown in Figure 31.

[0140] Subsequently, ashing is performed on the organic insulating layer 12, similar to the process shown in Figure 13B(b). This forms the lower part 71 as shown in Figure 32.

[0141] Even when the upper part 72 is formed from the same conductive material as the lower electrodes LE1, LE2, and LE3, as in this embodiment, the same effects as in the first embodiment can be obtained.

[0142] [Fifth Embodiment] In the fifth embodiment, further configurations applicable to the partition wall 7 and its vicinity are disclosed. The configurations according to this embodiment can be applied to either the first or second embodiment.

[0143] Figure 33 is a schematic cross-sectional view of the margin region BA (or peripheral region SA) according to the fifth embodiment. In this example, as in the third embodiment, a bottom portion 73 is formed in the closed region CA. Furthermore, as in the fourth embodiment, the upper portion 72 is formed by patterning the conductive layer CD.

[0144] In addition to the embodiments described above, various configurations can be applied to the partition wall 7. For example, the upper part 72 may include a layer formed of an inorganic insulating material, as in the first to third embodiments, and a layer formed of a conductive material, as in the fourth and fifth embodiments.

[0145] Furthermore, the planar shape of the partition wall 7 is not limited to that shown in Figure 5. For example, the partition wall 7 does not necessarily have to form a closed region CA. As another example, the partition wall 7 may be composed of multiple linear sections arranged parallel to each other, and these linear sections do not have to be connected to each other. Even with such a configuration, the spreading of the peeling section G in the direction of the arrangement of the linear sections is suppressed.

[0146] Furthermore, the partition wall 7 located in the marginal area BA and the partition wall 7 located in the surrounding area SA may have different shapes. As yet another example, the partition wall 7 may not be located in the surrounding area SA.

[0147] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0148] Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, any modifications made by a person skilled in the art to add, delete, or change the design of any of the above-described embodiments, or to add, omit, or change the conditions of any process, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0149] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0150] DSP...Display device, PNL...Display panel, DA...Display area, SA...Peripheral area, PX...Pixel, SP1, SP2, SP3...Sub-pixel, DE1, DE2, DE3...Display element, LE1, LE2, LE3...Lower electrode, OR1, OR2, OR3...Organic layer, UE1, UE2, UE3...Upper electrode, SE1, SE2, SE3...Sealing layer, CA...Closed area, 5...Rib, 6, 7...Partition wall, 61, 71...Lower part, 62, 72...Upper part.

Claims

1. A substrate is prepared that includes multiple panel sections, each containing a display area, and a marginal area surrounding the multiple panel sections. An organic insulating layer made of an organic insulating material is formed in the display area and the margin area. A plurality of lower electrodes, including a first lower electrode, are formed in the display area. A rib is formed having a plurality of pixel apertures, including a first pixel aperture that overlaps with the first lower electrode. A first partition wall is formed in the margin region, including a first lower part and a first upper part having an end protruding from the side surface of the first lower part. A first laminated film is formed, comprising a first organic layer that contacts each of the multiple lower electrodes through the multiple pixel apertures, and a first upper electrode that covers the first organic layer. A first sealing layer made of an inorganic insulating material is formed to cover the first laminated film. This includes, The formation of the first partition wall is The first upper part is formed above the organic insulating layer, In the margin region, the portion of the organic insulating layer exposed from the first upper part is removed, and the width of the organic insulating layer remaining below the first upper part is reduced to form the first lower part. This includes, The first laminated film is formed over the entire substrate and is divided into multiple parts by the first partition wall. The first sealing layer continuously covers the plurality of portions, In a plan view, the edge of the substrate and the edge of the first sealing layer are separated. In the region between the edge of the substrate and the edge of the first sealing layer, the first laminated film is exposed from the first sealing layer. A method for manufacturing a display device.

2. The method further includes forming an inorganic insulating layer made of an inorganic insulating material covering the lower electrode in the display area and the margin area, The ribs are formed by patterning the inorganic insulating layer in the display area. The first upper part is formed by patterning the inorganic insulating layer in the margin region. A method for manufacturing a display device according to claim 1.

3. The method further includes forming a conductive layer made of a conductive material covering the organic insulating layer in the display area and the margin area, The plurality of lower electrodes are formed by patterning the conductive layer in the display area. The first upper part is formed by patterning the conductive layer in the margin region. A method for manufacturing a display device according to claim 1.

4. The first partition wall has a plurality of linear portions arranged in the margin region, The end of the first sealing layer is located closer to the center of the substrate than the linear portion of the plurality of linear portions that is closest to the edge of the substrate. A method for manufacturing a display device according to claim 1.

5. The first partition wall has a plurality of linear portions arranged in the margin region, The end of the first sealing layer is located between the linear portion closest to the end of the substrate and the end of the substrate among the plurality of linear portions. A method for manufacturing a display device according to claim 1.

6. Using the first sealing layer as a mask, at least one of the multiple layers constituting the first laminated film is removed from the portion of the first laminated film located between the edge of the substrate and the edge of the first sealing layer. A method for manufacturing a display device according to claim 1, further comprising the above.

7. The first multilayer film further includes a first cap layer having a different refractive index from the first sealing layer and covering the first upper electrode. A method for manufacturing a display device according to claim 1.

8. Before forming the first laminated film, a second partition wall is formed in the display area, which includes a second lower portion located above the rib and a second upper portion having an end protruding from the side surface of the second lower portion. A method for manufacturing a display device according to any one of claims 1 to 7, further comprising the above.

9. The first laminated film and the first sealing layer are patterned, leaving the portion of the first laminated film and the first sealing layer that overlaps with the first lower electrode, and removing the other portions. A method for manufacturing a display device according to claim 1, further comprising the above.

10. The plurality of lower electrodes include a second lower electrode, The plurality of pixel apertures include a second pixel aperture, After patterning the first laminated film and the first sealing layer, a second laminated film is formed, which includes a second organic layer that contacts the second lower electrode through the second pixel aperture and a second upper electrode that covers the second organic layer. A second sealing layer made of an inorganic insulating material is formed to cover the second laminated film. A method for manufacturing a display device according to claim 9, further comprising the above.

11. The second laminated film and the second sealing layer are patterned, leaving the portion of the second laminated film and the second sealing layer that overlaps with the second lower electrode, and removing the other portions. A method for manufacturing a display device according to claim 10, further comprising the above.

12. The plurality of lower electrodes include a third lower electrode, The plurality of pixel apertures include a third pixel aperture, After patterning the second laminated film and the second sealing layer, a third laminated film is formed, which includes a third organic layer that contacts the third lower electrode through the third pixel aperture and a third upper electrode that covers the third organic layer. A third sealing layer made of an inorganic insulating material is formed to cover the third laminated film. A method for manufacturing a display device according to claim 11, further comprising the above.

13. A substrate including a plurality of panel sections, each containing a display area, and a marginal area surrounding the plurality of panel sections, The lower electrode located in the display area, A rib having a pixel aperture that overlaps with the lower electrode, It includes a first lower part made of an organic insulating material and a first upper part having an end protruding from the side surface of the first lower part, and a first partition wall formed in the margin region, A laminated film comprising an organic layer that contacts the lower electrode through the pixel aperture, and an upper electrode that covers the organic layer, A sealing layer made of an inorganic insulating material covering the laminated film, Equipped with, The laminated film is formed in the plurality of panel portions and the margin region and is divided into a plurality of parts by the first partition wall. The sealing layer continuously covers the plurality of portions, In a plan view, the edge of the substrate and the edge of the sealing layer are separated. In the region between the edge of the substrate and the edge of the sealing layer, the laminated film is exposed from the sealing layer. Motherboard for display devices.

14. The panel portion is formed of the same organic insulating material as the first lower portion and includes an organic insulating layer arranged in the display area. The lower electrode is positioned above the organic insulating layer. Mother board for display device according to claim 13.

15. The rib and the first upper part are formed of the same inorganic insulating material. Mother board for display device according to claim 13 or 14.

16. The lower electrode and the first upper part are formed of the same conductive material. Mother board for display device according to claim 13 or 14.

17. A substrate including a plurality of panel sections, each containing a display area, and a marginal area surrounding the plurality of panel sections, The lower electrode located in the display area, A rib having a pixel aperture that overlaps with the lower electrode, It includes a first lower part made of an organic insulating material and a first upper part having an end protruding from the side surface of the first lower part, and a first partition wall formed in the margin region, A laminated film comprising an organic layer that contacts the lower electrode through the pixel aperture, and an upper electrode that covers the organic layer, A sealing layer made of an inorganic insulating material covering the laminated film, Equipped with, The laminated film is formed in the plurality of panel portions and the margin region and is divided into a plurality of parts by the first partition wall. The sealing layer continuously covers the plurality of portions, In a plan view, the edges of the laminated film and the edges of the sealing layer are aligned. In a plan view, the edges of the laminated film and the edges of the sealing layer are separated from the edges of the substrate. Motherboard for display devices.

18. The panel portion is formed of the same organic insulating material as the first lower portion and includes an organic insulating layer arranged in the display area. The lower electrode is positioned above the organic insulating layer. Mother board for display device according to claim 17.

19. The rib and the first upper part are formed of the same inorganic insulating material. Mother board for display device according to claim 17 or 18.

20. The lower electrode and the first upper part are formed of the same conductive material. Mother board for display device according to claim 17 or 18.

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