Display apparatus

Abstract

The present invention provides a high-definition display apparatus. Provided is a display apparatus comprising a transistor, a light-emitting device, a first insulation layer, a second insulation layer, and a first conductive layer. The transistor has a semiconductor layer and a second conductive layer which is electrically connected to the semiconductor layer. The light-emitting device has a pixel electrode. The first insulation layer is provided on the transistor and has a first opening which reaches the second conductive layer. The first conductive layer covers the first opening. The second insulation layer is provided on the first insulation layer and has a second opening in a region overlapping the first opening. The pixel electrode covers the upper surface of the second insulation layer and the second opening. The pixel electrode is electrically connected to the second conductive layer via the first conductive layer. An end part of the first insulation layer is positioned above the second conductive layer. An end part of the second insulation layer is positioned above the first conductive layer. The end part of the second insulation layer is positioned further outward than the end part of the first insulation layer.

Description

display device

[0001] 1. Field of the Invention One embodiment of the present invention relates to a display device, a display module, and an electronic device. 2. Description of the Related Art One embodiment of the present invention relates to a manufacturing method of a display device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In recent years, display devices have been expected to be used in a variety of applications. For example, applications of large display devices include home television devices (also referred to as televisions or television receivers), digital signage, and public information displays (PIDs). Furthermore, development of mobile information terminals, such as smartphones and tablet terminals equipped with touch panels, is progressing.

[0004] There is also a demand for higher definition display devices. Devices requiring high-definition display devices, such as devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR), are being actively developed.

[0005] As a display device, for example, a light-emitting device having a light-emitting device (also referred to as a light-emitting element) has been developed. A light-emitting device (also referred to as an EL device or an EL element) utilizing an electroluminescence (hereinafter referred to as EL) phenomenon has features such as being easily thin and lightweight, being capable of high-speed response to an input signal, and being capable of being driven by a DC constant voltage power supply, and is therefore applied to a display device.

[0006] Patent Document 1 discloses a display device for VR that uses an organic EL device (also called an organic EL element).

[0007] International Publication No. 2018 / 087625

[0008] An object of one embodiment of the present invention is to provide a display device with high definition.An object of one embodiment of the present invention is to provide a display device with high resolution.An object of one embodiment of the present invention is to provide a display device with high display quality.An object of one embodiment of the present invention is to provide a display device with high reliability.An object of one embodiment of the present invention is to provide a novel display device.

[0009] An object of one embodiment of the present invention is to provide a method for manufacturing a high-resolution display device.An object of one embodiment of the present invention is to provide a method for manufacturing a display device with high resolution.An object of one embodiment of the present invention is to provide a method for manufacturing a display device with high display quality.An object of one embodiment of the present invention is to provide a method for manufacturing a highly reliable display device.An object of one embodiment of the present invention is to provide a method for manufacturing a display device with high yield.An object of one embodiment of the present invention is to provide a novel method for manufacturing a display device.

[0010] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0011] One embodiment of the present invention is a display device including a transistor, a light-emitting device, a first insulating layer, a second insulating layer, and a first conductive layer. The transistor includes a semiconductor layer and a second conductive layer electrically connected to the semiconductor layer. The light-emitting device includes a pixel electrode. The first insulating layer is provided over the transistor and has a first opening reaching the second conductive layer. The first conductive layer covers the first opening. The second insulating layer is provided over the first insulating layer and has a second opening in a region overlapping with the first opening. The pixel electrode covers an upper surface of the second insulating layer and the second opening. The pixel electrode is electrically connected to the second conductive layer through the first conductive layer. An end of the first insulating layer is located on the second conductive layer. An end of the second insulating layer is located on the first conductive layer. An end of the second insulating layer is located outside an end of the first insulating layer.

[0012] In the above-described display device, the first insulating layer and the second insulating layer each preferably contain an organic material.

[0013] The display device preferably includes a layer. The pixel electrode preferably includes a third conductive layer and a fourth conductive layer on the third conductive layer. The third conductive layer preferably covers the upper surface of the second insulating layer and the second opening. The third conductive layer preferably has a recess that conforms to the shape of the side surface of the second insulating layer and the upper surface of the second conductive layer. The layer is preferably provided so as to fill the recess. The fourth conductive layer preferably covers the upper surface of the third conductive layer and the upper surface of the layer. The fourth conductive layer preferably includes a material that is reflective to visible light.

[0014] In the display device described above, the layer is preferably an insulating layer, or alternatively, the layer is preferably a conductive layer.

[0015] The display device preferably includes a third insulating layer. The third insulating layer is preferably provided in contact with an upper surface of the second insulating layer. The third insulating layer preferably includes an inorganic material. The pixel electrode preferably has a region in contact with the upper surface of the third insulating layer.

[0016] The display device preferably includes a fourth insulating layer. The fourth insulating layer is preferably provided in contact with an upper surface of the first insulating layer. The fourth insulating layer preferably includes an inorganic material. The first conductive layer preferably has a region in contact with an upper surface of the fourth insulating layer.

[0017] The display device preferably includes a fifth insulating layer and a sixth insulating layer. The light-emitting device preferably includes a pixel electrode, a common electrode, and an EL layer sandwiched between the pixel electrode and the common electrode. The fifth insulating layer preferably covers a portion of the upper surface and side surfaces of the EL layer. The sixth insulating layer preferably covers a portion of the upper surface and side surfaces of the EL layer via the fifth insulating layer. The common electrode preferably covers the sixth insulating layer.

[0018] In the display device described above, the fifth insulating layer preferably contains an inorganic material, and the sixth insulating layer preferably contains an organic material.

[0019] The display device preferably includes a fifth insulating layer. The light-emitting device preferably includes a pixel electrode, a common electrode, and an EL layer sandwiched between the pixel electrode and the common electrode. The fifth insulating layer preferably covers a part of the upper surface and side surfaces of the pixel electrode. The EL layer preferably has a region in contact with the upper surface of the fifth insulating layer. The common electrode preferably covers the fifth insulating layer.

[0020] In the display device, the transistor includes a gate insulating layer sandwiched between a semiconductor layer and a gate electrode. The semiconductor layer preferably includes a metal oxide. The metal oxide in the gate insulating layer preferably has a concentration of a metal element of 2×10 or more. １９ atoms / cm ３ It is preferable that:

[0021] According to one embodiment of the present invention, a display device with high definition, high resolution, high display quality, high reliability, and a novel display device can be provided.

[0022] According to one embodiment of the present invention, a method for manufacturing a display device with high definition can be provided. Furthermore, a method for manufacturing a display device with high resolution can be provided. Furthermore, a method for manufacturing a display device with high display quality can be provided. Furthermore, a method for manufacturing a display device with high reliability can be provided. Furthermore, a method for manufacturing a display device with high yield can be provided. Furthermore, a method for manufacturing a novel display device can be provided.

[0023] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0024] FIG. 1 is a top view showing an example of a display device. FIG. 2 is a cross-sectional view showing an example of a display device. FIG. 3A is a cross-sectional view showing an example of a display device. FIGS. 3B and 3C are top views showing examples of openings. FIGS. 4A and 4B are diagrams showing band diagrams. FIG. 5A is a cross-sectional view showing an example of a display device. FIG. 5B is a top view showing an example of a light-emitting device. FIGS. 6A and 6B are cross-sectional views showing an example of a display device. FIGS. 7A and 7B are cross-sectional views showing an example of a display device. FIGS. 8A and 8B are cross-sectional views showing an example of a display device. FIGS. 9A and 9B are cross-sectional views showing an example of a display device. FIGS. 10A and 10B are cross-sectional views showing an example of a display device. FIGS. 11A and 11B are cross-sectional views showing an example of a display device. FIGS. 12A and 12B are cross-sectional views showing an example of a display device. FIG. 13 is a cross-sectional view showing an example of a display device. FIG. 14 is a cross-sectional view showing an example of a display device. FIG. 15 is a cross-sectional view showing an example of a display device. FIG. 16 is a cross-sectional view showing an example of a display device. FIG. 17 is a cross-sectional view showing an example of a display device. FIG. 18 is a cross-sectional view showing an example of a display device. FIG. 19 is a top view showing an example of a display device. FIG. 20 is a cross-sectional view showing an example of a display device. FIGS. 21A to 21D are cross-sectional views showing an example of a manufacturing method of a display device. FIGS. 22A to 22C are cross-sectional views showing an example of a manufacturing method of a display device. FIGS. 23A and 23B are cross-sectional views showing an example of a manufacturing method of a display device. FIGS. 24A and 24B are cross-sectional views showing an example of a manufacturing method of a display device. FIGS. 25A and 25B are cross-sectional views showing an example of a manufacturing method of a display device. FIGS. 26A and 26B are cross-sectional views showing an example of a manufacturing method of a display device. FIGS. 27A and 27B are cross-sectional views showing an example of a manufacturing method of a display device. FIG. 28 is a cross-sectional view showing an example of a manufacturing method of a display device. FIGS. 29A and 29B are cross-sectional views showing an example of a manufacturing method of a display device. FIGS. 30A and 30B are cross-sectional views showing an example of a manufacturing method of a display device. FIGS. 31A and 31B are cross-sectional views showing an example of a manufacturing method of a display device. FIGS. 32A and 32B are cross-sectional views showing an example of a manufacturing method of a display device. 33A and 33B are cross-sectional views showing an example of a method for manufacturing a display device.34A and 34B are cross-sectional views showing an example of a method for manufacturing a display device. FIGS. 35A and 35B are cross-sectional views showing an example of a method for manufacturing a display device. FIG. 36 is a cross-sectional view showing an example of a method for manufacturing a display device. FIGS. 37A and 37B are cross-sectional views showing an example of a method for manufacturing a display device. FIG. 38 is a cross-sectional view showing an example of a method for manufacturing a display device. FIGS. 39A and 39B are cross-sectional views showing an example of a method for manufacturing a display device. FIG. 40 is a cross-sectional view showing an example of a method for manufacturing a display device. FIG. 41 is a cross-sectional view showing an example of a method for manufacturing a display device. FIG. 42 is a cross-sectional view showing an example of a method for manufacturing a display device. FIGS. 43A to 43G are views showing an example of a pixel. FIGS. 44A to 44K are views showing an example of a pixel. FIG. 45 is a perspective view showing an example of a display device. FIG. 46 is a cross-sectional view showing an example of a display device. FIG. 47 is a cross-sectional view showing an example of a display device. FIG. 48 is a cross-sectional view showing an example of a display device. FIGS. 49A to 49F are views showing a structural example of a light-emitting device. FIGS. 50A to 50C are views showing a structural example of a light-emitting device. 51A and 51B are diagrams showing an example of the configuration of a light receiving device. FIGS. 51C to 51E are diagrams showing an example of the configuration of a display device. FIGS. 52A to 52D are diagrams showing an example of an electronic device. FIGS. 53A to 53F are diagrams showing an example of an electronic device. FIGS. 54A to 54G are diagrams showing an example of an electronic device. FIG. 55 is a diagram showing the amount of variation in the electrical characteristics of a transistor due to an NBTIS test. FIGS. 56A and 56C are diagrams showing the Id-Vg characteristics of a transistor. FIGS. 56B and 56D are diagrams showing the amount of variation in the electrical characteristics of a transistor due to an NBTIS test. FIGS. 57A to 57C are diagrams showing the metal concentration in an insulating layer. FIGS. 58A and 58C are diagrams showing a calculation model. FIGS. 58B and 58D are density of states diagrams obtained by calculation. FIGS. 59A to 59D are diagrams showing the amount of variation in the electrical characteristics of a transistor due to an NBTIS test. FIG. 60 is a cross-sectional STEM image of a sample according to an example.

[0025] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0026] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned.

[0027] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0028] The terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0029] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0030] In this specification and the like, a structure in which at least light-emitting layers are separately fabricated for light-emitting devices with different emission wavelengths may be referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting device, increasing the degree of freedom in the selection of materials and configurations, and facilitating improvements in brightness and reliability.

[0031] In this specification and the like, holes or electrons may be referred to as "carriers." Specifically, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable from each other depending on their cross-sectional shapes or characteristics. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0032] In this specification and the like, a light-emitting device (also referred to as a light-emitting element) has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer).

[0033] In this specification and the like, a light-receiving device (also referred to as a light-receiving element) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes.

[0034] In this specification, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like light-emitting layer refers to a state in which the light-emitting layer is physically separated from an adjacent light-emitting layer.

[0035] In this specification, the term "tapered shape" refers to a shape in which at least a portion of the side surface of the structure is inclined relative to the substrate surface. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface is less than 90°. Note that the side surface of the structure and the substrate surface do not necessarily need to be completely flat, and may be substantially planar with a slight curvature or a substantially planar with a slight unevenness.

[0036] In this specification and the like, the mask layer is located above at least the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers that constitute the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.

[0037] In this specification and the like, the term "step discontinuity" refers to a phenomenon in which a layer, film, or electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0038] Embodiment 1 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

[0039] One embodiment of the present invention is a display device including a transistor, a light-emitting device, a first insulating layer, a second insulating layer, and a first conductive layer. The first insulating layer is provided over the transistor, a second insulating layer is provided over the first insulating layer, and a light-emitting device is provided over the second insulating layer. The transistor includes a semiconductor layer and a second conductive layer electrically connected to the semiconductor layer. The second conductive layer functions as a source or drain of the transistor. The first insulating layer has a first opening reaching the second conductive layer. The first conductive layer is provided to cover the first opening. The second insulating layer has a second opening in a region overlapping with the first opening. A pixel electrode included in the light-emitting device is provided to cover an upper surface of the second insulating layer and the second opening. The pixel electrode is electrically connected to the second conductive layer through the first conductive layer.

[0040] The first insulating layer and the second insulating layer each function as a planarization layer. Preferably, the first insulating layer and the second insulating layer each contain an organic material. By stacking two or more insulating layers functioning as planarization layers on the transistor, unevenness caused by the transistor can be reduced, and the surface on which the light-emitting device is formed can be made flatter. Therefore, the processing accuracy of the light-emitting device can be improved, resulting in a display device with high definition.

[0041] The transistor constitutes a pixel circuit that controls a light-emitting device. The transistor is electrically connected to a pixel electrode that covers the second opening through a first conductive layer that covers the first opening. By providing the second opening in a region that overlaps the first opening, the area occupied by the pixel circuit can be reduced. This allows for a high-definition display device. Furthermore, the end of the first insulating layer on the first opening side is located on the second conductive layer, and the end of the second insulating layer on the second opening side is located on the first conductive layer. Furthermore, the end of the second insulating layer is located outside the end of the first insulating layer. In other words, the second insulating layer has a portion that protrudes beyond the end of the first insulating layer. That is, in a top view (also referred to as a plan view), the second opening is located inside the first opening. It can also be said that the first opening encompasses the second opening. This configuration allows for a smoother shape of the surface on which the pixel electrode is formed, preventing poor connection of the pixel electrode and increased electrical resistance. Therefore, a display device with high display quality can be obtained.

[0042] FIG. 1 shows a top view (also referred to as a plan view) of a display device 100 according to one embodiment of the present invention. The display device 100 includes a display portion in which a plurality of pixels 110 are arranged in a matrix and a connection portion 140 located outside the display portion. Each pixel 110 includes a plurality of subpixels. FIG. 1 illustrates two rows and two columns of pixels 110. Each pixel 110 includes three subpixels (subpixel 11R, subpixel 11G, and subpixel 11B), and two rows and six columns of subpixels are illustrated. The connection portion 140 can also be referred to as a cathode contact portion.

[0043] Each subpixel has a display device (also referred to as a display element). Examples of the display device include a liquid crystal device (also referred to as a liquid crystal element) and a light-emitting device (also referred to as a light-emitting element). It is preferable to use, for example, an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode) as the light-emitting device. Examples of the light-emitting material included in the light-emitting device include a fluorescent material (fluorescent material), a phosphorescent material (phosphorescent material), a material exhibiting thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF material), and an inorganic compound (quantum dot material, etc.). Furthermore, an LED such as a micro LED (light-emitting diode) can also be used as the light-emitting device.

[0044] The light emitting device can emit light of infrared, red, green, blue, cyan, magenta, yellow, white, etc. The color purity can be improved by providing the light emitting device with a microcavity structure.

[0045] In the following, a configuration in which a light-emitting device is used as a display device will be described as an example.

[0046] A display device according to one embodiment of the present invention includes light-emitting devices manufactured for different light-emitting colors and is capable of full-color display.

[0047] 1 corresponds to the top view shape of the light-emitting region of the light-emitting device. The top view shape of the subpixel can be, for example, a triangle, a quadrangle (including a rectangle and a square), a polygon such as a pentagon, a polygon with rounded corners, an ellipse, or a circle.

[0048] Each subpixel has a pixel circuit that controls the light-emitting device. The pixel circuit is not limited to the range of the subpixel shown in Figure 1, and circuit components may be located outside it. For example, a transistor included in the pixel circuit of subpixel 11R may be located within the range of subpixel 11G shown in Figure 1, or part or all of the transistor may be located outside the range of subpixel 11R.

[0049] 1 shows the subpixels 11R, 11G, and 11B as having the same or approximately the same aperture ratio (which may also be expressed as the sizes of their light-emitting regions being equal or approximately the same), but this is not a limitation of one embodiment of the present invention. The aperture ratios of the subpixels 11R, 11G, and 11B can be determined as appropriate. The aperture ratios of the subpixels 11R, 11G, and 11B may be different from one another, or two or more of them may be equal or approximately the same.

[0050] A stripe arrangement is applied to the pixel 110 shown in FIG. 1 . The pixel 110 shown in FIG. 1 is composed of three subpixels: subpixel 11R, subpixel 11G, and subpixel 11B. The subpixels 11R, 11G, and 11B each emit light of a different color. Examples of the subpixels 11R, 11G, and 11B include subpixels of three colors: red (R), green (G), and blue (B), and subpixels of three colors: yellow (Y), cyan (C), and magenta (M). The number of colors of the subpixels is not limited to three and may be four or more. Examples of four-color subpixels include subpixels of R, G, B, and white (W), subpixels of R, G, B, and Y, and subpixels of R, G, B, and infrared light (IR).

[0051] In this specification and the like, the row direction may be referred to as the X direction, and the column direction may be referred to as the Y direction. The X direction and the Y direction intersect, for example, perpendicularly (see FIG. 1 ). FIG. 1 shows an example in which subpixels of different colors are arranged side by side in the X direction, and subpixels of the same color are arranged side by side in the Y direction.

[0052] FIG. 1 shows an example in which the connection portion 140 is located on one side of the display unit when viewed from above, but the location of the connection portion 140 is not particularly limited. The connection portion 140 only needs to be located in at least one of the upper, right, left, and lower sides of the display unit when viewed from above, and may be located so as to surround all four sides of the display unit. The shape of the top surface of the connection portion 140 is not particularly limited, and may be strip-shaped, L-shaped, U-shaped, frame-shaped, or the like. Furthermore, the connection portion 140 may be singular or plural.

[0053] <Configuration Example 1 of Display Device> FIG. 2 shows a cross-sectional view taken along dashed dotted lines X1-X2 and Y1-Y2 in FIG.

[0054] 2, the display device 100 includes a light-emitting device 130R, a light-emitting device 130G, and a light-emitting device 130B provided on a layer 101, and a protective layer 131 provided to cover these light-emitting devices. A substrate 120 is bonded to the protective layer 131 with a resin layer 122.

[0055] The layer 101 includes a transistor 205R, a transistor 205G, and a transistor 205B. An insulating layer 214 and an insulating layer 235 on the insulating layer 214 are provided to cover the transistors 205R, 205G, and 205B. The insulating layer 214 has openings 191R, 191G, and 191B, and conductive layers 233R, 233G, and 233B are provided to cover the openings. The insulating layer 235 has openings 193R, 193G, and 193B, and electrodes of the light-emitting devices 130R, 130G, and 130B are provided to cover the openings. The light-emitting device 130R is electrically connected to the transistor 205R via the conductive layer 233R. The light-emitting device 130G is electrically connected to the transistor 205G via the conductive layer 233G. Light emitting device 130B is electrically connected to transistor 205B through conductive layer 233B.

[0056] When describing matters common to light-emitting device 130R, light-emitting device 130G, and light-emitting device 130B, the letters that distinguish them may be omitted and they may be referred to as light-emitting device 130. Similarly, when describing matters common to components that are distinguished by letters, such as transistor 205R, transistor 205G, and transistor 205B, they may be described using symbols without the letters.

[0057] Each of the light-emitting devices 130R, 130G, and 130B has a pair of electrodes and a layer sandwiched between the pair of electrodes. The layer has at least a light-emitting layer. Of the pair of electrodes that each light-emitting device has, one electrode functions as an anode and the other electrode functions as a cathode. In the following, an example in which the pixel electrode functions as the anode and the common electrode functions as the cathode may be described.

[0058] The light-emitting device 130R has a pixel electrode 111R on an insulating layer 235, an island-shaped layer 113R on the pixel electrode 111R, a common layer 114 on the island-shaped layer 113R, and a common electrode 115 on the common layer 114. In the light-emitting device 130R, the layer 113R and the common layer 114 can be collectively referred to as an EL layer.

[0059] The light-emitting device 130G has a pixel electrode 111G on an insulating layer 235, an island-shaped layer 113G on the pixel electrode 111G, a common layer 114 on the island-shaped layer 113G, and a common electrode 115 on the common layer 114. In the light-emitting device 130G, the layer 113G and the common layer 114 can be collectively referred to as an EL layer.

[0060] The light-emitting device 130B has a pixel electrode 111B on an insulating layer 235, an island-shaped layer 113B on the pixel electrode 111B, a common layer 114 on the island-shaped layer 113B, and a common electrode 115 on the common layer 114. In the light-emitting device 130B, the layer 113B and the common layer 114 can be collectively referred to as an EL layer.

[0061] In this specification and the like, among the EL layers included in the light-emitting devices, layers provided in an island shape for each light-emitting device are referred to as layer 113R, layer 113G, or layer 113B, and a layer shared by a plurality of light-emitting devices is referred to as common layer 114. Note that in this specification and the like, the layer 113R, layer 113G, and layer 113B may be referred to as an island-shaped EL layer, an EL layer formed in an island shape, or the like, without including the common layer 114.

[0062] The layers 113R, 113G, and 113B are each island-shaped and separated from one another. By providing an EL layer in an island shape for each light-emitting device, leakage current between adjacent light-emitting devices can be suppressed. This prevents crosstalk caused by unintended light emission, and realizes a display device with extremely high contrast. In particular, a display device with high current efficiency at low brightness can be realized.

[0063] The display device of one embodiment of the present invention may be any of a top emission type that emits light in a direction opposite to a substrate on which a light-emitting device is formed, a bottom emission type that emits light toward a substrate on which a light-emitting device is formed, and a dual emission type that emits light from both sides.

[0064] The layer 101 preferably includes a pixel circuit having a function of controlling the light-emitting device 130. The pixel circuit may include, for example, a transistor, a capacitor, and a wiring. Note that the layer 101 may include, in addition to the pixel circuit, one or both of a gate line driver circuit (gate driver) and a source line driver circuit (source driver). The layer 101 may further include one or both of an arithmetic circuit and a memory circuit.

[0065] The layer 101 can have a structure in which a pixel circuit is provided on a semiconductor substrate or an insulating substrate. The semiconductor substrate can be a single-crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, or an SOI substrate. The insulating substrate can be a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate. The semiconductor substrate and the insulating substrate can be circular or rectangular. The semiconductor substrate and the insulating substrate can be a substrate having heat resistance at least sufficient to withstand subsequent heat treatment.

[0066] The layer 101 can have, for example, a stacked structure in which a plurality of transistors are provided over the substrate 151 and an insulating layer is provided to cover these transistors. Figure 2 shows transistors 205R, 205G, and 205B as transistors included in the layer 101. Note that Figure 2 shows cross-sectional views of the transistors 205R, 205G, and 205B in the channel length direction.

[0067] A transistor 205R that can be used in a display device according to one embodiment of the present invention will be described as an example. FIG. 3A shows an enlarged view of the transistor 205R, the light-emitting device 130R, and their vicinity, which are shown in FIG.

[0068] The transistor 205R has a semiconductor layer 231, an insulating layer 218, and a conductive layer 223 stacked in this order. Part of the insulating layer 225 functions as a gate insulating layer of the transistor 205R. The conductive layer 223 functions as a gate electrode of the transistor 205R. The transistor 205R is a so-called top-gate transistor in which a gate electrode is provided over the semiconductor layer 231. The semiconductor layer 231 has a channel formation region 231i and a pair of low-resistance regions 231n. The channel formation region 231i has a region overlapping with the conductive layer 223 with the insulating layer 218 interposed therebetween.

[0069] The transistor 205R further includes an insulating layer 218 and conductive layers 222a and 222b. The insulating layer 218 is provided over the insulating layer 225 and the conductive layer 223. The insulating layer 218 and the insulating layer 225 have openings that reach the low-resistance regions 231n. The conductive layers 222a and 222b are provided to cover the openings. The conductive layer 222a is electrically connected to one of the pair of low-resistance regions 231n, and the conductive layer 222b is electrically connected to the other of the pair of low-resistance regions 231n. One of the conductive layers 222a and 222b functions as a source, and the other functions as a drain. The transistor 205R can be referred to as a TGSA (Top Gate Self Align) transistor.

[0070] The insulating layer 218 functions as a protective layer for the transistor 205R. The insulating layer 218 is preferably made of a material that does not easily diffuse impurities. Providing the insulating layer 218 can effectively prevent external impurities from diffusing into the transistor, thereby improving the reliability of the display device. Examples of impurities include water and hydrogen. The insulating layer 218 can be an insulating layer containing an inorganic material or an insulating layer containing an organic material. For example, an inorganic material such as an oxide or a nitride can be suitably used for the insulating layer 218. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used for the insulating layer 218. For example, one or more of an acrylic resin and a polyimide resin can be used for the organic material. A photosensitive material may be used as the organic material. Two or more of the above insulating films may be stacked. The insulating layer 218 may have a stacked structure of an insulating layer containing an inorganic material and an insulating layer containing an organic material.

[0071] 2 and 3A , the transistor 205R includes a conductive layer 221 and an insulating layer 211 between the substrate 151 and the semiconductor layer 231. The conductive layer 221 has a region overlapping with the semiconductor layer 231 with the insulating layer 211 interposed therebetween and a region overlapping with the conductive layer 223 with the semiconductor layer 231 interposed therebetween.

[0072] In the transistor 205R, the conductive layer 223 functions as a first gate electrode (also referred to as a top gate electrode), and the conductive layer 221 functions as a second gate electrode (also referred to as a bottom gate electrode). In the transistor 205R, part of the insulating layer 225 functions as a first gate insulating layer, and part of the insulating layer 211 functions as a second gate insulating layer. A portion of the semiconductor layer 231 that overlaps with at least one of the conductive layer 223 and the conductive layer 221 functions as a channel formation region of the transistor 205R. Note that for ease of description, a portion of the semiconductor layer 231 that overlaps with the conductive layer 223 may be referred to as a channel formation region below. However, in reality, a channel can also be formed in a portion that does not overlap with the conductive layer 223 but overlaps with the conductive layer 221 (a portion including the low-resistance region 231n).

[0073] The two gates may be connected and supplied with the same signal to drive the transistor, or the threshold voltage of the transistor may be controlled by applying a potential to one of the two gates for controlling the threshold voltage and a potential to the other for driving.

[0074] The transistor 205G and the transistor 205B can have the same structure as the transistor 205R. The description of the transistor 205R can be referred to for the transistor 205G and the transistor 205B, and detailed description thereof will be omitted. Note that the transistor 205R, the transistor 205G, and the transistor 205B may have different structures.

[0075] The semiconductor layer 231 of the transistor 205 included in the display device of one embodiment of the present invention preferably includes a metal oxide (also referred to as an oxide semiconductor or OS) exhibiting semiconductor characteristics. That is, the display device of this embodiment preferably includes a transistor using a metal oxide for a channel formation region (hereinafter also referred to as an OS transistor). The OS transistor has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, the OS transistor has significantly smaller source-drain leakage current in an off state (hereinafter also referred to as an off-state current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce power consumption of the display device.

[0076] Here, the display device may be used in a high-temperature environment or an environment with strong external light. Furthermore, within the display device, some of the light emitted from the light-emitting device 130 may reach the transistor 205. If the electrical characteristics of the transistor fluctuate due to high temperature or light, the display quality of the display device may be reduced. Therefore, it is preferable that the transistor 205 used in the display device has small fluctuations in its electrical characteristics due to high temperature and light, i.e., high reliability. By using a transistor with high reliability against high temperature and light in the display device, a display device with high display quality and high reliability can be obtained.

[0077] The mechanism of the change in the electrical characteristics of an OS transistor due to light will be described with reference to FIG. 4A. In FIG. 4A, the left side shows a band diagram of a metal oxide (OS) included in the semiconductor layer 231, and the right side shows a band diagram of an oxide containing silicon included in the insulating layer 225 that functions as a gate insulating layer (GI). In FIG. 4A, holes are represented by circles marked "h+" and electrons are represented by black circles.

[0078] The mechanism by which light changes the electrical characteristics of an OS transistor is presumed to be as follows. First, when a metal oxide is irradiated with light (hv), electrons (carriers) present in the valence band (Ev) or deep density of states (dDOS) of the metal oxide are excited to the conduction band (Ec). The deep levels of the metal oxide are formed by oxygen vacancies (V Ｏ ) is presumed to be a level derived from the metal oxide. Next, electrons are excited to the conduction band (Ec) of the metal oxide, generating holes in the valence band (Ev) or a deep level of the metal oxide. When a negative bias is applied between the gate and source, holes are accumulated at the interface between the metal oxide and the gate insulating layer and in the vicinity thereof. If a defect level ("GI defects" in FIG. 4A) exists at the interface and in the vicinity thereof, holes are trapped in the defect level ("Hole Injection" in FIG. 4A). This causes the threshold voltage of the OS transistor to shift in the negative direction.

[0079] The insulating layer 225 that functions as a gate insulating layer preferably has few defect levels. For example, an oxide containing silicon can be used as the insulating layer 225. Specifically, silicon oxide or silicon oxynitride can be used as the insulating layer 225. In this case, examples of defect levels in the gate insulating layer include an oxygen atom bonded to one silicon atom and a nitrogen atom bonded to two silicon atoms. Note that an oxygen atom bonded to one silicon atom is referred to as a non-bridging oxygen hole center (NBOHC), and a nitrogen atom bonded to two silicon atoms is referred to as a NBOHC. Ｏ It may be written as NBOHC and N Ｏ has dangling bonds, and holes are trapped in the dangling bonds, which may cause the threshold voltage to fluctuate. Ｏ It is preferable that the number of

[0080] The defect level of the insulating layer 225 can be a level derived from a defect formed by the diffusion of atoms contained in the metal oxide into the insulating layer 225. For example, a defect in which a silicon atom in the insulating layer 225 is replaced by a metal atom contained in the metal oxide can be mentioned. When the metal oxide is an In-Ga-Zn oxide, the defect can be a defect in which a silicon atom is replaced by an indium atom, a gallium atom, or a zinc atom. In this specification and the like, the defect in which a silicon atom is replaced by an indium atom is referred to as an In Ｓｉ and the defect where a silicon atom is replaced by a gallium atom is represented as Ga Ｓｉ and the defect where a silicon atom is replaced by a zinc atom is represented as Zn Ｓｉ From the first-principles calculation, Zn Ｓｉ The energy of formation of In Ｓｉ , and Ga Ｓｉ Therefore, the formation energy of Zn is higher than that of Ｓｉ In Ｓｉ , and Ga Ｓｉ In this specification and the like, defects in which silicon atoms in the insulating layer 225 are replaced by metal atoms contained in a metal oxide are collectively referred to as M Ｓｉ ("M" in FIG. 4B) Ｓｉ For example, when an In—Ga—Zn oxide is used for the semiconductor layer 231, In Ｓｉ , Ga Ｓｉ , and Zn Ｓｉ Collectively, M Ｓｉ It may be written as follows.

[0081] From the time dependency of the amount of change in threshold voltage in the NBTIS test, it is thought that there are two or more degradation factors with different time constants in NBTIS degradation. Ｓｉ The degradation factor with a small time constant is M Ｓｉ Other than (e.g., NBOHC and N Ｏ ) is due to the M Ｓｉ and the level due to M Ｓｉ Other than (e.g., NBOHC and N Ｏ4B ) are shown. Degradation with a small time constant, i.e., fast degradation ("Fast degradation" in FIG. 4B ), and degradation with a large time constant, i.e., slow degradation ("Slow degradation" in FIG. 4B ) are shown schematically with arrows.

[0082] The metal oxide contained in the semiconductor layer 231 preferably has high crystallinity. By increasing the crystallinity of the metal oxide, it is possible to suppress diffusion of metal elements contained in the metal oxide into the insulating layer 225. Ｓｉ , Ga Ｓｉ , and Zn Ｓｉ The formation of can be suppressed.

[0083] The concentration of the metal element contained in the metal oxide in the insulating layer 225 is preferably low. １９ atoms / cm ３ Preferably, it is equal to or less than 1×10 １９ atoms / cm ３ Preferably, it is equal to or less than 8×10 １８ atoms / cm ３ Preferably, it is less than 5×10 １８ atoms / cm ３ The following is preferable. The concentration of the metal element in the insulating layer 225 can be evaluated by, for example, secondary ion mass spectrometry (SIMS). For example, when an In—Ga—Zn oxide is used for the semiconductor layer 231, the indium concentration, gallium concentration, and zinc concentration in the insulating layer 225 are preferably in the above-described ranges. Note that since the lower the concentration of the metal element in the insulating layer 225, the more preferable it is, there is no need to set a lower limit for the concentration.

[0084] 2 and the like, the concentration of the metal element contained in the metal oxide in the insulating layer 225 functioning as the first gate insulating layer is preferably in the above-described range.Furthermore, the concentration of the metal element contained in the metal oxide in the insulating layer 211 functioning as the second gate insulating layer is preferably in the above-described range.

[0085] One of the indicators for evaluating the reliability of a transistor is a Gate Bias Temperature (GBT) stress test, in which the transistor is held in a state in which an electric field is applied to the gate. Among these, a test in which a positive potential (positive bias) is applied to the gate relative to the source potential and drain potential and the transistor is held at a high temperature is called a Positive Bias Temperature Stress (PBTS) test, and a test in which a negative potential (negative bias) is applied to the gate and the transistor is held at a high temperature is called a Negative Bias Temperature Stress (NBTS) test. The PBTS test and the NBTS test performed under light irradiation are called a PBTIS (Positive Bias Temperature Illumination Stress) test and an NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0086] It is preferable that the transistor used in the display device of one embodiment of the present invention has small fluctuation in electrical characteristics in an NBTIS test (hereinafter also referred to as NBTIS degradation).

[0087] Note that although a TGSA transistor is used as an example here, the structure of a transistor that can be applied to the display device of one embodiment of the present invention is not particularly limited.

[0088] An insulating layer 214 and an insulating layer 235 are provided over the transistor 205R, the transistor 205G, and the transistor 205B. The insulating layer 214 and the insulating layer 235 have a function of reducing unevenness caused by the transistor 205R, the transistor 205G, and the transistor 205B, respectively, and making the top surface of the layer 101 more flat. Note that in this specification and the like, the insulating layer 214 and the insulating layer 235 may each be referred to as a planarizing layer.

[0089] The insulating layer 214 and the insulating layer 235 can each be suitably an insulating layer containing an organic material. As the organic material, a photosensitive organic resin is preferably used, for example, a photosensitive resin composition containing an acrylic resin is preferably used. Note that in this specification and the like, the term "acrylic resin" does not refer only to polymethacrylic acid ester or methacrylic resin, but may refer to all acrylic polymers in a broad sense.

[0090] The insulating layer 214 and the insulating layer 235 may each be made of an acrylic resin, a polyimide resin, an epoxy resin, an imide resin, a polyamide resin, a polyimideamide resin, a silicone resin, a siloxane resin, a benzocyclobutene-based resin, a phenolic resin, or a precursor of these resins. The insulating layer 214 and the insulating layer 235 may each be made of an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or an alcohol-soluble polyamide resin. A photoresist may also be used as the photosensitive resin. Either a positive-type material or a negative-type material may be used as the photosensitive organic resin. The insulating layer 214 and the insulating layer 235 may use the same organic material, or different organic materials.

[0091] The insulating layer 214 may have a laminated structure of an organic insulating layer and an inorganic insulating layer. For example, the insulating layer 214 may have a laminated structure of an organic insulating layer and an inorganic insulating layer on the organic insulating layer. By providing an inorganic insulating layer on the outermost surface of the insulating layer 214, it can function as an etching protection layer. This prevents a portion of the insulating layer 214 from being etched during the formation of the conductive layer 233, which would result in a decrease in the flatness of the insulating layer 214. Similarly, the insulating layer 235 may have a laminated structure of an organic insulating layer and an inorganic insulating layer. This prevents a portion of the insulating layer 235 from being etched during the formation of the pixel electrode 111 and the layer 113, which would result in a decrease in the flatness of the insulating layer 235. Alternatively, the insulating layer 214 may have a laminated structure of an inorganic insulating layer and an organic insulating layer on the inorganic insulating layer. The same applies to the insulating layer 235.

[0092] By providing two or more insulating layers functioning as planarization layers over the transistor 205R, the transistor 205G, and the transistor 205B, the surface on which the light-emitting device 130 is to be formed (here, the insulating layer 235) can be made more flat.

[0093] Here, if the top surface of the insulating layer 235, on which the light-emitting device 130 is formed, is not flat, for example, there may be a connection failure due to a step disconnection in the common electrode, or the film thickness of the common electrode 115 may become locally thin, resulting in an increase in electrical resistance. Furthermore, if the top surface of the insulating layer 235 is not flat, there may be a decrease in the processing accuracy of the layer formed on the insulating layer 235.

[0094] In the display device of one embodiment of the present invention, two or more insulating layers functioning as planarization layers are provided over the transistor 205R, the transistor 205G, and the transistor 205B, whereby the surface on which the light-emitting device 130 is formed can be made more flat. Therefore, by planarizing the top surface of the insulating layer 235, the processing accuracy of the light-emitting device 130 and the like provided over the insulating layer 235 can be improved, and a display device with high definition can be provided. Furthermore, poor connection due to a step in the common electrode and an increase in electrical resistance due to a local thinning of the film thickness of the common electrode 115 can be prevented, and thus a display device with high display quality can be provided.

[0095] Note that although a structure in which the insulating layer functioning as a planarizing layer has a two-layer stacked structure (insulating layer 214 and insulating layer 235) is shown here, one embodiment of the present invention is not limited to this. The insulating layer functioning as a planarizing layer may have a stacked structure of three or more layers. Note that although the insulating layer 214 and the insulating layer 235 are each shown as a single-layer structure in FIG. 2 and the like, one embodiment of the present invention is not limited to this. The insulating layer 214 and the insulating layer 235 may each have a stacked structure.

[0096] The insulating layer 214 has an opening 191R, an opening 191G, and an opening 191B.

[0097] The opening 191R has a region overlapping with the conductive layer 222b of the transistor 205R, and the conductive layer 222b of the transistor 205R is exposed in the opening 191R. A conductive layer 233R is provided to cover the opening 191R. The conductive layer 233R has a region in contact with the side surface of the insulating layer 214 and the top surface of the conductive layer 222b of the transistor 205R. The conductive layer 233R may have a region in contact with the top surface of the insulating layer 214.

[0098] The opening 191G has a region overlapping with the conductive layer 222b of the transistor 205G, and the conductive layer 222b of the transistor 205G is exposed in the opening 191G. A conductive layer 233G is provided to cover the opening 191G. The conductive layer 233G has a region in contact with the side surface of the insulating layer 214 and the top surface of the conductive layer 222b of the transistor 205G. The conductive layer 233G may have a region in contact with the top surface of the insulating layer 214.

[0099] The opening 191B has a region overlapping with the conductive layer 222b of the transistor 205B, and the conductive layer 222b of the transistor 205B is exposed in the opening 191B. A conductive layer 233B is provided to cover the opening 191B. The conductive layer 233B has a region in contact with the side surface of the insulating layer 214 and the top surface of the conductive layer 222b of the transistor 205B. The conductive layer 233B may have a region in contact with the top surface of the insulating layer 214.

[0100] The insulating layer 235 has an opening 193R, an opening 193G, and an opening 193B.

[0101] The opening 193R has a region overlapping with the conductive layer 233R, and the conductive layer 233R is exposed in the opening 193R. A pixel electrode 111R is provided to cover the opening 193R. The pixel electrode 111R has regions in contact with the side surface of the insulating layer 235 and the top surface of the conductive layer 233R. In other words, the light-emitting device 130R is electrically connected to the transistor 205R via the conductive layer 233R.

[0102] The opening 193G has a region overlapping with the conductive layer 233G, and the conductive layer 233G is exposed in the opening 193G. A pixel electrode 111G is provided to cover the opening 193G. The pixel electrode 111G has regions in contact with the side surface of the insulating layer 235 and the top surface of the conductive layer 233G. In other words, the light-emitting device 130G is electrically connected to the transistor 205G via the conductive layer 233G.

[0103] The opening 193B has a region overlapping with the conductive layer 233B, and the conductive layer 233B is exposed in the opening 193B. The pixel electrode 111B is provided so as to cover the opening 193B. The pixel electrode 111B has regions in contact with the side surface of the insulating layer 235 and the top surface of the conductive layer 233B. In other words, the light-emitting device 130B is electrically connected to the transistor 205B via the conductive layer 233B.

[0104] The opening 191R is provided over the conductive layer 222b of the transistor 205R. Similarly, the opening 191G is provided over the conductive layer 222b of the transistor 205G. The opening 191B is provided over the conductive layer 222b of the transistor 205B. That is, the ends of the insulating layer 214 are preferably located over the conductive layer 222b of the transistor 205R, the conductive layer 222b of the transistor 205G, and the conductive layer 222b of the transistor 205B. In FIG. 3A , the width 191d of the opening 191R in a cross-sectional view is indicated by a double-headed arrow. The width 191d can also be referred to as the distance between the ends of the insulating layer 214 that face each other over the conductive layer 222b of the transistor 205R.

[0105] Opening 193R is provided on conductive layer 233R. Similarly, opening 193G is provided on conductive layer 233G. Opening 193B is provided on conductive layer 233B. In other words, it is preferable that the ends of insulating layer 235 are located on conductive layer 233R, conductive layer 233G, and conductive layer 233B. In FIG. 3A, width 193d of opening 193R in a cross-sectional view is indicated by a double-headed arrow. Width 193d can also be considered the distance between the ends of insulating layer 235 that face each other on conductive layer 233R.

[0106] The conductive layer 222b, the conductive layer 233R, and the pixel electrode 111R of the transistor 205R preferably overlap each other. Similarly, the conductive layer 222b, the conductive layer 233G, and the pixel electrode 111G of the transistor 205G preferably overlap each other. The conductive layer 222b, the conductive layer 233B, and the pixel electrode 111B of the transistor 205B preferably overlap each other. The opening 193R preferably overlaps with the opening 191R. The opening 193G preferably overlaps with the opening 191G. The opening 193B preferably overlaps with the opening 191B. By providing the openings 193R, 193G, and 193G in the regions overlapping with the openings 191R, 191G, and 191B, the area occupied by the pixel circuit can be reduced. Therefore, a high-resolution display device can be obtained.

[0107] The top surface shapes of openings 191R, 191G, 191B, 193R, 193G, and 193B can be, for example, a triangle, a quadrangle (including a rectangle or a square), a polygon, a shape with rounded corners, an ellipse, or a circle. Examples of the top surface shapes of openings 191R and 193R are shown in FIGS. 3B and 3C. FIGS. 3B and 3C each show an example in which openings 191R, 191G, 191B, 193R, 193G, and 193B have rounded corners when viewed from above. The top surface shapes of openings 191R, 191G, and 191B may be the same or different. The top surface shapes of openings 193R, 193G, and 193B may be the same or different. Furthermore, the top surface shapes of openings 191R, 191G, and 191B may be the same as or different from those of openings 193R, 193G, and 193B. For example, in a top view, openings 191R, 191G, and 191B may have rounded corners, and openings 193R, 193G, and 193B may have a circular shape.

[0108] As shown in FIGS. 3B and 3C , the opening 193R is preferably located inside the opening 191R. Similarly, the opening 193G is preferably located inside the opening 191G. The opening 193G is preferably located inside the opening 191G. In other words, the edge of the insulating layer 214 is preferably located outside the edge of the insulating layer 235. Compared to providing the opening 193R outside the opening 191R, providing the opening 193R inside the opening 191R reduces the unevenness of the surface on which the pixel electrode 111R is formed, allowing for a smoother shape, thereby preventing connection failures due to step disconnections in the pixel electrode 111R. Furthermore, an increase in electrical resistance due to a localized thinning of the film thickness of the pixel electrode 111R can be prevented. Similarly, providing the opening 193G inside the opening 191G allows for a smoother shape on the surface on which the pixel electrode 111G is formed, preventing connection failures and an increase in electrical resistance of the pixel electrode 111G. By providing the opening 193B inside the opening 191B, the shape of the surface on which the pixel electrode 111B is formed can be made smooth, preventing poor connection of the pixel electrode 111B and an increase in electrical resistance. Therefore, a display device with high display quality can be obtained. Furthermore, the areas occupied by the openings 193R, 193G, 193G, 191R, 191G, and 191B are reduced, thereby reducing the area occupied by the pixel circuit and enabling a high-definition display device.

[0109] The widths 191d and 193d are preferably small. By reducing the widths 191d and 193d, the area occupied by the pixel circuit can be reduced, resulting in a display device. The width 191d is preferably, for example, 6 μm or less, more preferably 4 μm or less, even more preferably 3 μm or less, and even more preferably 2 μm or less. The width 193d is preferably 6 μm or less, more preferably 4 μm or less, even more preferably 3 μm or less, and even more preferably 2 μm or less. By reducing the widths 191d and 193d, a high-definition display device can be achieved.

[0110] Furthermore, it is preferable that the width 193d is smaller than the width 191d. By making the width 193d smaller than the width 191d, the shape of the surface on which the pixel electrode 111 is formed can be made smoother, and connection failures due to step disconnections in the pixel electrode 111 can be suppressed. In addition, it is possible to suppress an increase in electrical resistance due to a localized thinning of the film thickness of the pixel electrode 111.

[0111] The top surface shape of opening 191 corresponds to the shape of the end of insulating layer 214 when viewed from above. Width 191d of opening 191 refers to the short side of the smallest rectangle circumscribing opening 191 when viewed from above. Similarly, the top surface shape of opening 193 corresponds to the shape of the end of insulating layer 235 when viewed from above. Width 193d of opening 193 refers to the short side of the smallest rectangle circumscribing opening 193 when viewed from above.

[0112] The pixel electrodes 111R, 111G, and 111B of the light-emitting devices 130R, 130G, and 130B will be described.

[0113] The pixel electrode 111R of the light-emitting device 130R has a layered structure of a conductive layer 112R, a conductive layer 126R on the conductive layer 112R, and a conductive layer 129R on the conductive layer 126R. Similarly, the pixel electrode 111G of the light-emitting device 130G has a layered structure of a conductive layer 112G, a conductive layer 126G on the conductive layer 112G, and a conductive layer 129G on the conductive layer 126G. The pixel electrode 111B of the light-emitting device 130B has a layered structure of a conductive layer 112B, a conductive layer 126B on the conductive layer 112B, and a conductive layer 129B on the conductive layer 126B.

[0114] The conductive layer 112R is electrically connected to the conductive layer 233R through an opening 193R provided in the insulating layer 235. The conductive layer 112R is electrically connected to the conductive layer 222b of the transistor 205 through the conductive layer 233R. An end of the conductive layer 112R is located outside an end of the conductive layer 126R. An end of the conductive layer 126R is located inside an end of the conductive layer 129R. An end of the conductive layer 112R is located inside an end of the conductive layer 129R. In other words, an end of the conductive layer 126R is located on the conductive layer 112R. An end of the conductive layer 129R is located on the conductive layer 112R. An upper surface and a side surface of the conductive layer 126R are covered with the conductive layer 129R.

[0115] The conductive layer 112R is not particularly limited in terms of transmittance and reflectance to visible light. A conductive layer that is transmissive to visible light or a conductive layer that is reflective to visible light can be used as the conductive layer 112R. For example, an oxide conductive layer can be used as the conductive layer that is transmissive to visible light. Specifically, In—Si—Sn oxide (also referred to as ITSO) can be suitably used as the conductive layer 112R. For example, a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, silver, tin, zinc, platinum, gold, molybdenum, tantalum, or tungsten, or an alloy containing any of these metals as a main component (for example, an alloy of silver, palladium, and copper (APC: Ag—Pd—Cu)) can be used as the conductive layer 112R. The conductive layer 112R may have a stacked structure of a conductive layer that is transmissive to visible light and a conductive layer that is reflective over the conductive layer. The conductive layer 112R is preferably made of a material that has high adhesion to the surface on which the conductive layer 112R is formed (here, the insulating layer 235), thereby preventing the conductive layer 112R from peeling off.

[0116] The conductive layer 126R can be a conductive layer that is reflective to visible light. The conductive layer 126R may have a stacked structure of a conductive layer that is transparent to visible light and a conductive layer that is reflective over the conductive layer. The conductive layer 126R can be made of a material that can be used for the conductive layer 112R. Specifically, the conductive layer 126R can be preferably made of a stacked structure of In—Si—Sn oxide (ITSO) and an alloy of silver, palladium, and copper (APC) on the In—Si—Sn oxide (ITSO).

[0117] The conductive layer 129R can be made of a material that can be used for the conductive layer 112R. For example, a conductive layer that is transparent to visible light can be used for the conductive layer 129R. Specifically, In—Si—Sn oxide (ITSO) can be used for the conductive layer 129R.

[0118] When a material that is easily oxidized is used for the conductive layer 126R, the conductive layer 129R is made of a material that is not easily oxidized, and by covering the conductive layer 126R with the conductive layer 129R, oxidation of the conductive layer 129R can be suppressed. Furthermore, deposition of metal components contained in the conductive layer 126R can be suppressed. For example, when a material containing silver is used for the conductive layer 126R, In—Si—Sn oxide (ITSO) can be suitably used for the conductive layer 126R. This can suppress oxidation of the conductive layer 126R and suppress deposition of silver.

[0119] The structure of the pixel electrode 111 that can be applied to the display device that is one embodiment of the present invention is not limited to the structure of the pixel electrode 111 illustrated in FIG. 2 and the like.

[0120] Conductive layer 112G, conductive layer 126G, conductive layer 129G in light-emitting device 130G, and conductive layer 112B, conductive layer 126B, and conductive layer 129B in light-emitting device 130B are similar to conductive layer 112R, conductive layer 126R, and conductive layer 129R in light-emitting device 130R, and therefore detailed description thereof will be omitted.

[0121] The conductive layers 112R, 112G, and 112B are formed to cover the openings 193R, 193G, and 193B provided in the insulating layer 235. A layer 128 is buried in the recesses of the conductive layers 112R, 112G, and 112B.

[0122] The layer 128 has a function of flattening the recesses of the conductive layer 112R, the conductive layer 112G, and the conductive layer 112B. The conductive layers 126R, 126G, and 126B, which are electrically connected to the conductive layers 112R, 112G, and 112B, are provided on the conductive layers 112R, 112G, and 112B and the layer 128. Therefore, the regions overlapping with the recesses of the conductive layers 112R, 112G, and 112B also function as light-emitting regions, and the aperture ratio of the pixel can be increased.

[0123] The conductivity of the layer 128 is not particularly limited, and the layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for the layer 128. In particular, the layer 128 is preferably formed using an insulating material, and more preferably using an organic insulating material. For example, the organic insulating material that can be used for the insulating layer 127 can be used for the layer 128.

[0124] Note that when the layer 128 is a conductive layer, the layer 128 can function as a part of a pixel electrode.

[0125] The upper surface of conductive layer 112R and the upper and side surfaces of conductive layer 129R are covered by layer 113R. Similarly, the upper surface of conductive layer 112G and the upper and side surfaces of conductive layer 129G are covered by layer 113G, and the upper surface of conductive layer 126B and the upper and side surfaces of conductive layer 129B are covered by layer 113B. Therefore, the entire regions where conductive layers 126R, 126G, and 126B are provided can be used as light-emitting regions for light-emitting device 130R, light-emitting device 130G, and light-emitting device 130B, thereby increasing the aperture ratio of the pixel.

[0126] It is preferable that the ends of the pixel electrodes 111R, 111G, and 111B each have a tapered shape. Specifically, it is preferable that the ends of the pixel electrodes 111R, 111G, and 111B each have a tapered shape with a taper angle of less than 90°. By tapering the side surfaces of the pixel electrodes 111R, 111G, and 111B, it is possible to improve the coverage of the EL layer provided along the top surfaces and side surfaces of the pixel electrodes 111R, 111G, and 111B.

[0127] Note that a part of the insulating layer 235 may be removed when forming the pixel electrodes 111R, 111G, and 111B. The insulating layer 235 may have a recess in a region that does not overlap with any of the pixel electrodes 111R, 111G, and 111B.

[0128] In some cases, a portion of the insulating layer 235 is removed when forming the layers 113R, 113G, and 113B. Fig. 2 shows an example in which the insulating layer 235 has a recess in an area that does not overlap with any of the layers 113R, 113G, and 113B.

[0129] 2, an insulating layer (also referred to as a partition wall, bank, or spacer) covering the upper end of the pixel electrode 111R is not provided between the pixel electrode 111R and the layer 113R. Furthermore, an insulating layer covering the upper end of the pixel electrode 111G is not provided between the pixel electrode 111G and the layer 113G. This allows the distance between adjacent light-emitting devices to be reduced. This allows a high-definition or high-resolution display device to be obtained. Furthermore, a mask for forming the insulating layer is not required, thereby reducing the manufacturing cost of the display device.

[0130] By using a structure in which an insulating layer covering an edge of the pixel electrode is not provided between the pixel electrode and the EL layer, in other words, by using a structure in which an insulating layer is not provided between the pixel electrode and the EL layer, light from the EL layer can be efficiently extracted. Therefore, the display device of one embodiment of the present invention can have a reduced viewing angle dependency. By reducing the viewing angle dependency, the visibility of images in the display device can be improved. For example, in the display device of one embodiment of the present invention, the viewing angle (the maximum angle at which a certain contrast ratio is maintained when the screen is viewed from an oblique direction) can be set to a range of 100° to less than 180°, preferably 150° to 170°. The above viewing angles can be applied to both the vertical and horizontal directions.

[0131] The light-emitting device of the present embodiment may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). The light-emitting unit has at least one light-emitting layer.

[0132] Light-emitting device 130R emits red (R) light, light-emitting device 130G emits green (G) light, and light-emitting device 130B emits blue (B) light. Layers 113R, 113G, and 113B each include at least an emitting layer. Layer 113R includes an emitting layer that emits red light, layer 113G includes an emitting layer that emits green light, and layer 113B includes an emitting layer that emits blue light. In other words, layer 113R includes an emitting material that emits red light, layer 113G includes an emitting material that emits green light, and layer 113B includes an emitting material that emits blue light.

[0133] When a light-emitting device with a tandem structure is used, it is preferable that layer 113R has a structure having a plurality of light-emitting units that emit red light, layer 113G has a structure having a plurality of light-emitting units that emit green light, and layer 113B has a structure having a plurality of light-emitting units that emit blue light. It is preferable to provide a charge generation layer between each of the light-emitting units.

[0134] Layer 113R, layer 113G, and layer 113B may each include one or more of a hole injection layer, a hole transport layer, a hole blocking layer, a charge generation layer, an electron blocking layer, an electron transport layer, and an electron injection layer.

[0135] For example, each of the layers 113R, 113G, and 113B may have a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer in this order. Alternatively, the layer 113R may have an electron blocking layer between the hole transport layer and the light-emitting layer. Alternatively, the layer 113G may have a hole blocking layer between the electron transport layer and the light-emitting layer. Alternatively, the layer 113B may have an electron injection layer on the electron transport layer.

[0136] For example, each of the layers 113R, 113G, and 113B may have an electron injection layer, an electron transport layer, an emitting layer, and a hole transport layer in this order. Alternatively, a hole blocking layer may be provided between the electron transport layer and the emitting layer. Alternatively, an electron blocking layer may be provided between the hole transport layer and the emitting layer. Alternatively, a hole injection layer may be provided on the hole transport layer.

[0137] As described above, the layers 113R, 113G, and 113B each preferably have a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. Alternatively, the layers 113R, 113G, and 113B each preferably have a light-emitting layer and a carrier block layer (hole block layer or electron block layer) on the light-emitting layer. Alternatively, the layers 113R, 113G, and 113B each preferably have a light-emitting layer, a carrier block layer on the light-emitting layer, and a carrier transport layer on the carrier block layer. Since the surfaces of the layers 113R, 113G, and 113B are exposed during the manufacturing process of the display device, providing one or both of the carrier transport layer and the carrier block layer on the light-emitting layer can prevent the light-emitting layer from being exposed to the outermost surface and reduce damage to the light-emitting layer. This can improve the reliability of the light-emitting device.

[0138] The heat resistance temperature of the compounds contained in the layers 113R, 113G, and 113B is preferably 100° C. or higher and 180° C. or lower, more preferably 120° C. or higher and 180° C. or lower, and more preferably 140° C. or higher and 180° C. or lower. For example, the glass transition point (Tg) of these compounds is preferably 100° C. or higher and 180° C. or lower, more preferably 120° C. or higher and 180° C. or lower, and more preferably 140° C. or higher and 180° C. or lower.

[0139] In particular, it is preferable that the heat resistance temperature of the functional layer provided on the light-emitting layer is high. Furthermore, it is even more preferable that the heat resistance temperature of the functional layer provided on and in contact with the light-emitting layer is high. The high heat resistance of the functional layer makes it possible to effectively protect the light-emitting layer and reduce damage to the light-emitting layer.

[0140] It is preferable that the light-emitting layer has a high heat resistance temperature, which can prevent the light-emitting layer from being damaged by heating, resulting in a decrease in light-emitting efficiency and a shortened lifespan.

[0141] The light-emitting layer includes a light-emitting substance (also referred to as a light-emitting material, a light-emitting organic compound, or a guest material) and an organic compound (also referred to as a host material). Since the light-emitting layer contains a larger amount of the organic compound than the light-emitting substance, the Tg of the organic compound can be used as an index of the heat resistance temperature of the light-emitting layer.

[0142] Layer 113R, layer 113G, and layer 113B may each include, for example, a first light-emitting unit, a charge generation layer on the first light-emitting unit, and a second light-emitting unit on the charge generation layer.

[0143] The second light-emitting unit preferably has an emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the emitting layer. Alternatively, the second light-emitting unit preferably has an emitting layer and a carrier block layer (hole block layer or electron block layer) on the emitting layer. Alternatively, the second light-emitting unit preferably has an emitting layer, a carrier block layer on the emitting layer, and a carrier transport layer on the carrier block layer. Since the surface of the second light-emitting unit is exposed during the manufacturing process of the display device, providing one or both of a carrier transport layer and a carrier block layer on the emitting layer can prevent the emitting layer from being exposed to the outermost surface and reduce damage to the emitting layer. This can improve the reliability of the light-emitting device. Note that when three or more emitting units are included, the uppermost emitting unit preferably has an emitting layer and one or both of a carrier transport layer and a carrier block layer on the emitting layer.

[0144] The common layer 114 may include, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may include a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer. The common layer 114 is shared by the light-emitting devices 130R, 130G, and 130B.

[0145] An insulating layer 125 and an insulating layer 127 on the insulating layer 125 are provided in the region between adjacent light-emitting devices 130. In Figure 2 and other figures, multiple cross sections of the insulating layer 125 and the insulating layer 127 are shown, but when the display device 100 is viewed from above, the insulating layer 125 and the insulating layer 127 are each connected to one another. In other words, the display device 100 can be configured to have, for example, one insulating layer 125 and one insulating layer 127. Note that the display device 100 may have multiple insulating layers 125 that are separated from one another, or may have multiple insulating layers 127 that are separated from one another.

[0146] 2 and other figures show an example in which the end of the layer 113R is positioned further outward than the end of the pixel electrode 111R. Note that although the pixel electrode 111R and the layer 113R are used as an example for explanation, the same can be said for the pixel electrode 111G and the layer 113G, and the pixel electrode 111B and the layer 113B.

[0147] 5A shows an enlarged view of the light-emitting device 130R, the transistor 205R, and their vicinity shown in FIG. 2 . FIG. 5B shows a top view of the layer 113R. The layer 113R is formed so as to cover the edge of the pixel electrode 111R. This configuration makes it possible to use the entire upper surface of the pixel electrode as a light-emitting region, which makes it easier to increase the aperture ratio compared to a configuration in which the edge of the island-shaped EL layer is located inside the edge of the pixel electrode.

[0148] Covering the side surfaces of the pixel electrodes 111 with the EL layer can prevent the pixel electrodes 111 from coming into contact with the common electrode 115, thereby preventing short circuits in the light-emitting device 130. Furthermore, the distance between the light-emitting region of the EL layer (i.e., the region overlapping with the pixel electrode 111) and the edge of the EL layer can be increased. Since the edge of the EL layer may be damaged by processing, using an area away from the edge of the EL layer as the light-emitting region can sometimes improve the reliability of the light-emitting device 130.

[0149] As shown in FIG. 5B , each of the layers 113R, 113G, and 113B preferably includes a first region 113_1, which is a light-emitting region, and a second region 113_2 outside the first region 113_1. In FIG. 5A , the first region 113_1 is located between the pixel electrode 111R and the common electrode 115. The first region 113_1 is a portion of the layer 113R that contacts the pixel electrode 111R and overlaps with the common electrode 115 via the common layer 114. The first region 113_1 is covered with a mask layer during the manufacturing process of the display device, reducing damage. Therefore, a light-emitting device with high light-emitting efficiency and a long lifetime can be realized. On the other hand, the second region 113_2 includes the edge of the EL layer and its vicinity, and includes a portion that may be damaged by exposure to plasma during the manufacturing process of the display device. By not using the second region as a light-emitting region, variation in the characteristics of the light-emitting device can be suppressed. The second region can be called a dummy region.

[0150] 5A and 5B, the width L1 of the first region 113_1, which is a light-emitting region in the layer 113R, is indicated by an arrow. The widths L2 and L3 of the second region 113_2, which is a dummy region in the layer 113R, are indicated by arrows. As shown in FIG. 5B, the second region 113_2 is provided to surround the first region 113_1. Therefore, in cross-sectional views such as FIG. 5A, the second region 113_2 can be confirmed at two locations on either side of the first region 113_1. The widths L1 to L3 can be confirmed in cross-sectional observation images, etc.

[0151] The second region 113_2 is a portion of the layer 113R where at least one of the mask layer 118R, the mask layer 119R, the insulating layer 125, and the insulating layer 127 overlaps.

[0152] The widths L2 and L3 of the second region 113_2 are preferably 1 nm or more, more preferably 5 nm or more, even more preferably 50 nm or more, and even more preferably 100 nm or more. The wider the width of the second region 113_2, which is a dummy region, the more uniform the quality of the light-emitting region can be and the more the variation in the characteristics of the light-emitting device can be suppressed, which is preferable.

[0153] On the other hand, the narrower the width of the second region 113_2, the wider the light-emitting region, and the higher the aperture ratio of the pixel. Therefore, the widths L2 and L3 of the second region 113_2 are preferably 50% or less of the width L1 of the first region 113_1, more preferably 40% or less, even more preferably 30% or less, even more preferably 20% or less, and even more preferably 10% or less. For example, in a small, high-resolution display device such as a display device for wearable devices, the widths L2 and L3 of the second region 113_2 are preferably 500 nm or less, even more preferably 300 nm or less, even more preferably 200 nm or less, and even more preferably 150 nm or less.

[0154] In the island-shaped EL layer, the first region (light-emitting region) is a region where EL (electroluminescence) light emission is obtained. Furthermore, in the island-shaped EL layer, both the first region (light-emitting region) and the second region (dummy region) are regions where PL (photoluminescence) light emission is obtained. From these facts, it can be said that the first region and the second region can be distinguished by checking the EL light emission and the PL light emission.

[0155] The common electrode 115 is shared by the light-emitting devices 130R, 130G, and 130B. The common electrode 115 shared by the plurality of light-emitting devices is electrically connected to a conductive layer 123 provided in the connection portion 140 (see FIG. 2). The conductive layer 123 is preferably formed using the same material and in the same process as the pixel electrodes 111R, 111G, and 111B. For example, the conductive layer 123 may have a stacked structure including a conductive layer 112p, a conductive layer 126p on the conductive layer 112p, and a conductive layer 129p on the conductive layer 126p. The conductive layer 112p may be formed in the same process as the conductive layers 112R, 112G, and 112B. The conductive layer 126p may be formed in the same process as the conductive layers 126R, 126G, and 126B. The conductive layer 129p can be formed in the same process as the conductive layers 129R, 129G, and 129B.

[0156] 2 shows a configuration in which the film thickness of the conductive layer 129p is different from the film thicknesses of the conductive layers 129R, 129G, and 129B. The film thicknesses of the conductive layers 129p, 129R, 129G, and 129B may be different depending on the resistivity of the materials used for these layers. When the film thicknesses are different, the conductive layer 129p may be formed in a different process from the conductive layers 129R, 129G, and 129B. Alternatively, the process of forming the conductive layer 129p may be partially common to the process of forming the conductive layers 129R, 129G, and 129B.

[0157] The common layer 114 does not have to be provided in the connection portion 140. FIG. 2 shows a structure in which the common electrode 115 is provided on the conductive layer 123. Note that a structure in which the common layer 114 is provided on the conductive layer 123 and the conductive layer 123 and the common electrode 115 are electrically connected to each other through the common layer 114 may also be used. For example, by using a mask for defining a film formation area (also called an area mask or a rough metal mask to distinguish it from a fine metal mask), the regions in which the common layer 114 and the common electrode 115 are formed can be changed.

[0158] As shown in FIG. 2 , mask layers 118R and 119R are located on the layer 113R of the light-emitting device 130R, mask layers 118G and 119G are located on the layer 113G of the light-emitting device 130G, and mask layers 118B and 119B are located on the layer 113B of the light-emitting device 130B. The mask layers 118 and 119 are provided to surround the first region 113_1 (light-emitting region). In other words, the mask layers have openings in the portions that overlap with the light-emitting region. The top surface shapes of the mask layers are identical, approximately identical, or similar to those of the second region 113_2. The mask layers 118R and 119R are remaining portions of the mask layer that was provided on the layer 113R when the layer 113R was formed. Similarly, the mask layers 118G and 119G are mask layers that are formed when the layer 113G is formed, and the mask layers 118B and 119B are mask layers that are formed when the layer 113B is formed. In this manner, in the display device of one embodiment of the present invention, the mask layers used to protect the EL layer during the manufacturing process may be partially left.

[0159] Any two or all of the mask layers 118R, 118G, and 118B may be made of the same material, or different materials may be used. Similarly, any two or all of the mask layers 119R, 119G, and 119B may be made of the same material, or different materials may be used. Note that the mask layers 118R, 118G, and 118B may be collectively referred to as mask layers 118. The mask layers 119R, 119G, and 119B may be collectively referred to as mask layers 119.

[0160] As shown in FIG. 2 , one end of mask layer 118R and one end of mask layer 119R (the end opposite the light-emitting region, the outer end) are aligned or approximately aligned with the end of layer 113R, and the other end of mask layer 118R and the other end of mask layer 119R (the end on the light-emitting region side, the inner end) are located on layer 113R. Here, the other end of mask layer 118R and the other end of mask layer 119R preferably overlap with layer 113R and pixel electrode 111R. In this case, the other end of mask layer 118R and the other end of mask layer 119R are likely to be formed on a flat or approximately flat surface of layer 113R. The same applies to mask layers 118G, 119G, 118B, and 119B. Furthermore, the mask layer 118 and the mask layer 119 remain between the insulating layer 125 and the upper surface of the EL layer (the layer 113R, the layer 113G, or the layer 113B) that has been processed into an island shape, for example.

[0161] In addition, when the edges are aligned or approximately aligned, and when the top surface shapes are the same or approximately aligned, it can be said that at least a portion of the contours of the stacked layers overlap when viewed from above. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, it is also said that the edges are approximately aligned, or the top surface shapes are approximately aligned.

[0162] The side surfaces of the layers 113R, 113G, and 113B are covered with the insulating layer 125. The insulating layer 127 overlaps the side surfaces of the layers 113R, 113G, and 113B with the insulating layer 125 interposed therebetween.

[0163] A portion of the upper surface of each of the layers 113R, 113G, and 113B is covered with a mask layer 118. A mask layer 119 is provided on the mask layer 118. The insulating layers 125 and 127 overlap a portion of the upper surface of each of the layers 113R, 113G, and 113B via the mask layers 118 and 119.

[0164] By covering part of the top surface and the side surfaces of the layers 113R, 113G, and 113B with at least one of the insulating layer 125, the insulating layer 127, the mask layer 118, and the mask layer 119, the common layer 114 (or the common electrode 115) is prevented from contacting the side surfaces of the pixel electrodes 111R, 111G, and 111B, the layers 113R, 113G, and 113B, and short-circuiting of the light-emitting device can be suppressed, thereby improving the reliability of the light-emitting device.

[0165] 2, layers 113R, 113G, and 113B are all shown with the same film thickness, but the present invention is not limited to this. Layers 113R, 113G, and 113B may have different film thicknesses. For example, it is preferable to set the film thicknesses so that the optical path length of each of layers 113R, 113G, and 113B intensifies the light emitted from them. This allows for a microcavity structure to be realized, and the color purity of the light emitted from each light-emitting device 130 to be improved.

[0166] The insulating layer 125 is preferably in contact with the side surfaces of the layers 113R, 113G, and 113B. By configuring the insulating layer 125 to be in contact with the layers 113R, 113G, and 113B, peeling of the layers 113R, 113G, and 113B can be prevented. The insulating layer 125 is in close contact with the layers 113B, 113G, or 113R, which has the effect of fixing or bonding adjacent layers 113B and the like by the insulating layer 125. This can improve the reliability of the light-emitting device. Furthermore, the manufacturing yield of the light-emitting device can be increased.

[0167] 2, the insulating layer 125 and the insulating layer 127 cover part of the top surface and both the side surfaces of the layers 113R, 113G, and 113B, which can further prevent peeling of the EL layer and improve the reliability of the light-emitting device and the manufacturing yield of the light-emitting device.

[0168] 2 shows an example in which a stacked structure of a layer 113R, a mask layer 118R, a mask layer 119R, an insulating layer 125, and an insulating layer 127 is provided on an end of a pixel electrode 111R. Similarly, a stacked structure of a layer 113G, a mask layer 118G, a mask layer 119G, an insulating layer 125, and an insulating layer 127 is provided on an end of a pixel electrode 111G, and a stacked structure of a layer 113B, a mask layer 118B, a mask layer 119B, an insulating layer 125, and an insulating layer 127 is provided on an end of a pixel electrode 111B.

[0169] 2 shows a configuration in which the end of the pixel electrode 111R is covered with the layer 113R, and the insulating layer 125 is in contact with the side surface of the layer 113R. Similarly, the end of the pixel electrode 111G is covered with the layer 113G, the end of the pixel electrode 111B is covered with the layer 113B, and the insulating layer 125 is in contact with the side surface of the layer 113G and the side surface of the layer 113B.

[0170] The insulating layer 127 is provided on the insulating layer 125 so as to fill the recesses formed in the insulating layer 125. The insulating layer 127 can be configured to overlap with a portion of the top surface and the side surfaces of the layers 113R, 113G, and 113B via the insulating layer 125. The insulating layer 127 preferably covers at least a portion of the side surfaces of the insulating layer 125.

[0171] By providing the insulating layers 125 and 127, the gaps between adjacent island-shaped layers can be filled, which reduces large unevenness in height on the surface on which layers (e.g., a carrier injection layer, a common electrode, etc.) are formed on the island-shaped layers, thereby making the surface flatter, thereby improving the coverage of the carrier injection layer, the common electrode, etc.

[0172] The common layer 114 and the common electrode 115 are provided over the layers 113R, 113G, and 113B, the mask layers 118 and 119, the insulating layer 125, and the insulating layer 127. Before the insulating layer 125 and the insulating layer 127 are provided, a step is generated between a region where the pixel electrode and the island-shaped EL layer are provided and a region where the pixel electrode and the island-shaped EL layer are not provided (a region between light-emitting devices). The display device of one embodiment of the present invention includes the insulating layers 125 and 127, which can reduce the step and improve the coverage of the common layer 114 and the common electrode 115. Therefore, poor connection due to a step can be suppressed. Furthermore, the step can suppress an increase in electrical resistance due to a local thinning of the thickness of the common electrode 115.

[0173] The upper surface of the insulating layer 127 preferably has a highly flat shape, but may have a convex portion, a convex curved surface, a concave curved surface, or a concave portion. For example, the upper surface of the insulating layer 127 preferably has a highly flat convex curved surface shape.

[0174] Next, examples of materials that can be used for the insulating layer 125 and the insulating layer 127 will be described.

[0175] The insulating layer 125 can be an insulating layer containing an inorganic material. For example, an inorganic insulating film such as an insulating oxide film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used for the insulating layer 125. The insulating layer 125 may have a single-layer structure or a stacked-layer structure. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film and an aluminum oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. In particular, aluminum oxide is preferable because it has a high etching selectivity with respect to the EL layer and has a function of protecting the EL layer in the formation of the insulating layer 127 described later. In particular, by using an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by atomic layer deposition (ALD) as the insulating layer 125, it is possible to form an insulating layer 125 that has few pinholes and has an excellent function of protecting the EL layer. The insulating layer 125 may also have a stacked structure of a film formed by ALD and a film formed by sputtering. For example, the insulating layer 125 may have a stacked structure of an aluminum oxide film formed by ALD and a silicon nitride film formed by sputtering.

[0176] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0177] The insulating layer 125 preferably functions as a barrier insulating layer against at least one of water and oxygen. The insulating layer 125 preferably has a function of suppressing diffusion of at least one of water and oxygen. The insulating layer 125 preferably has a function of capturing or fixing (also referred to as gettering) at least one of water and oxygen.

[0178] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. In addition, in this specification and the like, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing or fixing (also referred to as gettering) a corresponding substance.

[0179] The insulating layer 125 has a function as a barrier insulating layer or a gettering function, which makes it possible to suppress the intrusion of impurities (typically, at least one of water and oxygen) that may diffuse into each light-emitting device from the outside. With this configuration, it is possible to provide a highly reliable light-emitting device and further a highly reliable display device.

[0180] The insulating layer 125 preferably has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulating layer 125 and causing deterioration of the EL layer. Furthermore, by reducing the impurity concentration in the insulating layer 125, the barrier properties against at least one of water and oxygen can be improved. For example, it is desirable that the insulating layer 125 has a sufficiently low hydrogen concentration or a sufficiently low carbon concentration, or preferably both of them.

[0181] The same material may be used for the insulating layer 125 and the mask layers 118B, 118G, and 118R. In this case, the boundary between the insulating layer 125 and any of the mask layers 118B, 118G, and 118R may become unclear and may be difficult to distinguish.

[0182] The insulating layer 127 provided on the insulating layer 125 has the function of flattening large unevenness of the insulating layer 125 formed between adjacent light-emitting devices. In other words, the insulating layer 127 has the effect of improving the flatness of the surface on which the common electrode 115 is formed.

[0183] An insulating layer containing an organic material can be suitably used as the insulating layer 127. A photosensitive organic resin is preferably used as the organic material, and for example, a photosensitive resin composition containing an acrylic resin is preferably used. Note that in this specification and the like, the term "acrylic resin" does not refer only to polymethacrylic acid ester or methacrylic resin, but may refer to all acrylic polymers in a broad sense.

[0184] The insulating layer 127 may be made of an acrylic resin, a polyimide resin, an epoxy resin, an imide resin, a polyamide resin, a polyimideamide resin, a silicone resin, a siloxane resin, a benzocyclobutene-based resin, a phenolic resin, or a precursor of any of these resins. Alternatively, the insulating layer 127 may be made of an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or an alcohol-soluble polyamide resin. Alternatively, a photoresist may be used as the photosensitive resin. Either a positive-type material or a negative-type material may be used as the photosensitive organic resin.

[0185] The insulating layer 127 may be made of a material that absorbs visible light. The insulating layer 127 absorbs light emitted from the light-emitting device, thereby preventing light from leaking from the light-emitting device to an adjacent light-emitting device through the insulating layer 127 (stray light). This improves the display quality of the display device. Furthermore, since the display quality can be improved without using a polarizing plate in the display device, the display device can be made lighter and thinner.

[0186] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, light-absorbing resin materials (e.g., polyimide), and resin materials that can be used for color filters (color filter materials). In particular, using a resin material in which two or more color filter materials are laminated or mixed is preferable because it can enhance the visible light blocking effect. In particular, mixing three or more color filter materials makes it possible to form a black or nearly black resin layer.

[0187] Next, the structure of insulating layer 127 and its vicinity will be described. An enlarged cross-sectional view of the region including insulating layer 127 between light-emitting device 130R and light-emitting device 130G and its periphery is shown in FIG. 6A. The following description will be given using insulating layer 127 between light-emitting device 130R and light-emitting device 130G as an example, but the same can be said for insulating layer 127 between light-emitting device 130G and light-emitting device 130B, and insulating layer 127 between light-emitting device 130B and light-emitting device 130R.

[0188] As shown in FIG. 6A , a layer 113R is provided covering the pixel electrode 111R, and a layer 113G is provided covering the pixel electrode 111G. A mask layer 118R is provided in contact with a portion of the upper surface of the layer 113R, and a mask layer 118G is provided in contact with a portion of the upper surface of the layer 113G. An insulating layer 125 is provided in contact with the upper and side surfaces of the mask layer 118R, the side surfaces of the layer 113R, the upper surface of the insulating layer 235, the upper and side surfaces of the mask layer 118G, and the side surfaces of the layer 113G. The insulating layer 125 also covers a portion of the upper surface of the layer 113R and a portion of the upper surface of the layer 113G. An insulating layer 127 is provided in contact with the upper surface of the insulating layer 125. The insulating layer 127 overlaps a portion of the upper surface and side surfaces of the layer 113R and a portion of the upper surface and side surfaces of the layer 113G via the insulating layer 125, and is in contact with at least a portion of the side surfaces of the insulating layer 125. A common layer 114 is provided to cover the layer 113R, the mask layer 118R, the layer 113G, the mask layer 118G, the insulating layer 125, and the insulating layer 127, and a common electrode 115 is provided on the common layer 114.

[0189] The insulating layer 127 is formed in a region between two island-shaped EL layers (e.g., the region between the layer 113R and the layer 113G in FIG. 6A ). At this time, at least a portion of the insulating layer 127 is disposed at a position sandwiched between a side edge of one EL layer (e.g., the layer 113R in FIG. 6A ) and a side edge of the other EL layer (e.g., the layer 113G in FIG. 6A ). By providing such an insulating layer 127, it is possible to prevent the formation of divided portions and locally thin portions in the common layer 114 and the common electrode 115 formed on the island-shaped EL layers and the insulating layer 127.

[0190] In a cross-sectional view of the display device, the end of the insulating layer 127 is preferably tapered. The angle between the side surface of the insulating layer 127 and the surface on which the insulating layer 127 is formed is preferably less than 90°, more preferably 60° or less, even more preferably 45° or less, and even more preferably 20° or less. By tapering the end of the insulating layer 127 in this manner, the coverage of the common layer 114 and the common electrode 115 provided on the insulating layer 127 can be improved, and the occurrence of discontinuities or local thinning can be suppressed. This improves the in-plane uniformity of the common layer 114 and the common electrode 115, thereby improving the display quality of the display device.

[0191] 6A , in a cross-sectional view of the display device, the upper surface of the insulating layer 127 preferably has a convex curved shape. The convex curved shape of the upper surface of the insulating layer 127 preferably bulges gently toward the center. Furthermore, the convex curved portion in the center of the upper surface of the insulating layer 127 preferably has a shape that is continuously connected to the tapered portions at the edges. By forming the insulating layer 127 in this shape, the common layer 114 and the common electrode 115 can be formed with good coverage over the entire insulating layer 127.

[0192] In a cross-sectional view of the display device, the end of the insulating layer 125 is preferably tapered. The angle formed between the side surface of the insulating layer 125 and the surface on which the insulating layer 125 is formed is preferably less than 90°, more preferably 60° or less, even more preferably 45° or less, and still more preferably 20° or less.

[0193] In a cross-sectional view of the display device, the end of the mask layer 118R is preferably tapered. The angle between the side of the mask layer 118R and the surface on which the mask layer 118R is to be formed is preferably less than 90°, more preferably 60° or less, even more preferably 45° or less, and even more preferably 20° or less. The end of the mask layer 118G and the mask layer 118B are also preferably tapered, and the angle between the side of these and the surface on which the mask layer 118R is to be formed is preferably within the above-mentioned range.

[0194] In a cross-sectional view of the display device, the end of the mask layer 119R is preferably tapered. The angle between the side of the mask layer 119R and the surface on which the mask layer 119R is to be formed is preferably less than 90°, more preferably 60° or less, even more preferably 45° or less, and even more preferably 20° or less. The end of the mask layer 119G and the mask layer 119B are also preferably tapered, and the angle between the side of these and the surface on which the mask layer 119R is to be formed is preferably within the above-mentioned range.

[0195] By tapering the ends of the mask layer 118R and the mask layer 119R in this manner, the coverage of the common layer 114 and the common electrode 115 provided on the mask layer 118G and the mask layer 119R can be improved.

[0196] The ends of the mask layers 118R and 119R are preferably positioned outside the ends of the insulating layer 125. This reduces the unevenness of the surfaces on which the common layer 114 and the common electrode 115 are formed, and improves the coverage of the common layer 114 and the common electrode 115.

[0197] The insulating layer 127 may cover at least a portion of the side surfaces of the insulating layer 125, the side surfaces of the mask layer 118R, the side surfaces of the mask layer 119R and the mask layer 118G, and the side surfaces of the mask layer 119G. Fig. 6B shows a configuration in which the insulating layer 127 covers the side surfaces of the insulating layer 125, a portion of the side surfaces of the mask layer 118R, a portion of the side surfaces of the mask layer 119R and the mask layer 118G, and the side surfaces of the mask layer 119G. It is preferable that the end of the insulating layer 127 be located outside the end of the insulating layer 125. This reduces unevenness on the surfaces on which the common layer 114 and the common electrode 115 are formed, and improves the coverage of the common layer 114 and the common electrode 115.

[0198] 7A shows an example in which the insulating layer 127 covers the entire side surfaces of the insulating layer 125, the entire side surfaces of the mask layer 118R, the entire side surfaces of the mask layer 119R, the entire side surfaces of the mask layer 118G, and the entire side surfaces of the mask layer 119G. This is preferable because it can further reduce unevenness on the surfaces on which the common layer 114 and the common electrode 115 are formed. Also, as shown in FIG. 7A, the insulating layer 127 may be in contact with the layer 113R and the layer 113G.

[0199] 7B shows an example in which the insulating layer 127 has a concave curved shape (also referred to as a constricted portion, recess, dent, or depression) on the side surface. Depending on the material and forming conditions (heating temperature, heating time, heating atmosphere, etc.) of the insulating layer 127, the concave curved shape may be formed on the side surface of the insulating layer 127.

[0200] It is preferable that one end of the insulating layer 127 overlaps the upper surface of the pixel electrode 111R, and the other end of the insulating layer 127 overlaps the upper surface of the pixel electrode 111G. By adopting such a structure, the ends of the insulating layer 127 can be formed on flat or approximately flat regions of the layer 113R and the layer 113G.

[0201] The insulating layer 127 does not have to overlap with the upper surface of the pixel electrode 111. The smaller the overlapping portion between the upper surface of the pixel electrode 111 and the insulating layer 127, the wider the light-emitting region of the light-emitting device becomes, which is preferable because it can increase the aperture ratio.

[0202] As shown in FIG. 8A, in a cross-sectional view of the display device, the upper surface of the insulating layer 127 may have a flat portion.

[0203] As shown in Figure 8B, in a cross-sectional view of the display device, the upper surface of the insulating layer 127 may have a concave curved shape. In Figure 8B, the upper surface of the insulating layer 127 has a shape that gently bulges toward the center, i.e., a convex curved surface, and a shape that is recessed in the center and its vicinity, i.e., a concave curved surface. Also, in Figure 8B, the convex curved portion of the upper surface of the insulating layer 127 has a shape that is continuously connected to the tapered portions at the ends. Even if the insulating layer 127 has such a shape, the common layer 114 and the common electrode 115 can be formed with good coverage over the entire insulating layer 127.

[0204] To form the insulating layer 127 having a concave curved surface in the center as shown in FIG. 8B , an exposure method using a multi-tone mask (typically a half-tone mask or a gray-tone mask) can be applied. A multi-tone mask is a mask that can perform exposure at three exposure levels: an exposed portion, an intermediate exposed portion, and an unexposed portion, and transmits light with multiple intensities. A single photomask (a single exposure and development process) can be used to form the insulating layer 127 having regions with multiple thicknesses (typically two types).

[0205] The method for forming the concave curved surface in the center of insulating layer 127 is not limited to the above. For example, two photomasks may be used to separately form an exposed portion and an intermediately exposed portion. Alternatively, the viscosity of the resin material used for insulating layer 127 may be adjusted. Specifically, the viscosity of the material used for insulating layer 127 may be set to 10 cP or less, preferably 1 cP or more and 5 cP or less.

[0206] Although not shown, the concave curved surface in the center of the insulating layer 127 does not necessarily have to be continuous, and may be interrupted between adjacent light-emitting devices. In this case, a portion of the insulating layer 127 disappears in the center of the insulating layer 127 shown in Fig. 8B, exposing the surface of the insulating layer 125. In this case, the insulating layer 127 may have a shape that can cover the common layer 114 and the common electrode 115.

[0207] As described above, by providing insulating layer 127, insulating layer 125, mask layer 118R, mask layer 118G, mask layer 119R, and mask layer 119G, common layer 114 and common electrode 115 can be formed with high coverage from the flat or substantially flat region of layer 113R to the flat or substantially flat region of layer 113G. This prevents the formation of disconnected portions and locally thin portions in common layer 114 and common electrode 115. This prevents poor connection between light-emitting devices in common layer 114 and common electrode 115 due to disconnected portions and increased electrical resistance due to locally thin portions. This allows the display device according to one embodiment of the present invention to improve display quality.

[0208] It is preferable to provide a protective layer 131 on the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B. Providing the protective layer 131 can improve the reliability of the light-emitting device 130. The protective layer 131 may have a single-layer structure or a laminated structure of two or more layers.

[0209] There is no restriction on the conductivity of the protective layer 131. The protective layer 131 can be made of at least one of an insulating film, a semiconductor film, and a conductive film.

[0210] The protective layer 131 having an inorganic film can prevent the common electrode 115 from being oxidized and prevent impurities (such as moisture and oxygen) from entering the light-emitting device, thereby preventing deterioration of the light-emitting device and improving the reliability of the display device.

[0211] For the protective layer 131, for example, an inorganic insulating film such as an insulating oxide film, an insulating nitride film, an insulating oxynitride film, or an insulating nitride oxide film can be used. Specific examples of these inorganic insulating films are as given in the description of the insulating layer 125. In particular, the protective layer 131 preferably has an insulating nitride film or an insulating nitride oxide film, and more preferably has an insulating nitride film.

[0212] The protective layer 131 may be formed using an inorganic film containing In—Sn oxide (also referred to as ITO), In—Zn oxide, Ga—Zn oxide, Al—Zn oxide, indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), or the like. The inorganic film preferably has high resistance, specifically, preferably has higher resistance than the common electrode 115. The inorganic film may further contain nitrogen.

[0213] When light emitted from the light-emitting device is extracted through the protective layer 131, it is preferable that the protective layer 131 has high transparency to visible light. For example, ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.

[0214] For example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used as the protective layer 131. By using such a stacked structure, impurities (water, oxygen, etc.) can be prevented from entering the EL layer side.

[0215] Furthermore, the protective layer 131 may include an organic film. For example, the protective layer 131 may include both an organic film and an inorganic film. Examples of organic materials that can be used for the protective layer 131 include the organic insulating materials that can be used for the insulating layer 127.

[0216] The protective layer 131 may have a two-layer structure formed by using different film formation methods. Specifically, the first layer of the protective layer 131 may be formed by the ALD method, and the second layer of the protective layer 131 may be formed by the sputtering method.

[0217] A light-shielding layer 117 may be provided on the surface of the substrate 120 facing the resin layer 122. The light-shielding layer 117 can be provided between adjacent light-emitting devices 130 and in the connection section 140. By providing the light-shielding layer 117, light emitted from adjacent sub-pixels can be blocked, preventing color mixing. Furthermore, external light can be prevented from reaching the transistor 205, thereby suppressing deterioration of the transistor 205. Note that a configuration without providing the light-shielding layer 117 is also possible.

[0218] Various optical members can be disposed on the outside of the substrate 120. Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light-collecting film. In addition, a surface protection layer such as an anti-static film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, or an impact absorbing layer may be disposed on the outside of the substrate 120. For example, a glass layer or a silica layer (SiO ｘ The surface protection layer can be preferably formed of a material such as DLC (diamond-like carbon), aluminum oxide (AlO ｘ), polyester-based materials, or polycarbonate-based materials may also be used. Note that it is preferable to use a material with high transmittance to visible light for the surface protection layer. It is also preferable to use a material with high hardness for the surface protection layer.

[0219] The substrate 120 can be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting device is extracted. Using a flexible material for the substrate 120 can increase the flexibility of the display device. Alternatively, a polarizing plate may be used as the substrate 120.

[0220] The substrate 120 can be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. The substrate 120 can also be made of glass having a thickness sufficient to provide flexibility.

[0221] When a circularly polarizing plate is superimposed on a display device, it is preferable that the display device has a substrate with high optical isotropy. A substrate with high optical isotropy has small birefringence (or a small amount of birefringence).

[0222] The absolute value of the retardation (phase difference) of a substrate having high optical isotropy is preferably 30 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less.

[0223] Examples of films with high optical isotropy include triacetyl cellulose (TAC, also known as cellulose triacetate) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic films.

[0224] When a film is used as a substrate, the film may absorb water, which may cause changes in shape, such as wrinkles, in the display device. Therefore, it is preferable to use a film with low water absorption as the substrate. For example, it is preferable to use a film with a water absorption rate of 1% or less, more preferably 0.1% or less, and even more preferably 0.01% or less.

[0225] The resin layer 122 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet curable adhesive), a reactive curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, a material with low moisture permeability, such as epoxy resin, is preferable. Alternatively, a two-component resin may be used. Alternatively, an adhesive sheet or the like may be used.

[0226] 9A and 9B show examples of a configuration different from that of the pixel electrode 111R shown in FIG. 2 and the like.

[0227] 9A, the ends of the conductive layers 129R, 126R, and 112R are aligned or substantially aligned with one another. The layer 113R contacts the side surfaces of the conductive layers 129R, 126R, and 112R.

[0228] For example, after forming a first conductive film to be the conductive layer 129R, the layer 128, a second conductive film to be the conductive layer 126R, and a third conductive film to be the conductive layer 112R, a resist mask is formed on the third conductive film, and the first conductive film, the second conductive film, and the third conductive film are processed using the resist mask, thereby forming the conductive layer 129R, the conductive layer 126R, and the conductive layer 112R. The process can be simplified by processing the first conductive film, the second conductive film, and the third conductive film in the same step to form the conductive layer 129R, the conductive layer 126R, and the conductive layer 112R.

[0229] 9B, the pixel electrode 111R includes a conductive layer 129R and a conductive layer 126R covered with a conductive layer 112R. The ends of the conductive layer 129R are aligned or substantially aligned with the ends of the conductive layer 126R. The conductive layer 112R contacts the side surface of the conductive layer 129R and the top and side surfaces of the conductive layer 126R. The layer 113R contacts the side surface of the conductive layer 129R and the top and side surfaces of the conductive layer 112R.

[0230] For example, after forming a first conductive film, layer 128, and a second conductive film, which will become conductive layer 129R, and then forming a resist mask on the second conductive film, the first conductive film and the second conductive film are processed using the resist mask to form conductive layer 129R and conductive layer 126R. Then, a third conductive film, which will become conductive layer 112R, is formed to cover conductive layer 129R and conductive layer 126R, and the third conductive film is processed to form conductive layer 112R. The process can be simplified by processing the first conductive film and the second conductive film in the same process to form conductive layer 129R and conductive layer 126R. Furthermore, even when a material that easily diffuses, such as silver, is used for conductive layer 112R or conductive layer 126R, diffusion can be suppressed by covering the top and side surfaces of conductive layer 112R and conductive layer 126R with conductive layer 129R.

[0231] 9A and other figures show a configuration in which the top surface of layer 128 has a convex shape in cross section, i.e., a shape with a convex curved surface, but the shape of layer 128 is not particularly limited. The top surface of layer 128 may have a concave shape in cross section, i.e., a shape with a concave curved surface, in which the top surface of layer 128 has a concave shape in cross section. Furthermore, the top surface of layer 128 may have one or both of a convex curved surface and a concave curved surface. Furthermore, the number of convex curved surfaces and concave curved surfaces on the top surface of layer 128 is not limited, and may be one or more.

[0232] The height of the upper surface of layer 128 and the height of the upper surface of conductive layer 112R may be the same or approximately the same, or may be different from each other. For example, the height of the upper surface of layer 128 may be lower or higher than the height of the upper surface of conductive layer 112R.

[0233] There is no particular limitation on the structure of a transistor that can be applied to a display device of one embodiment of the present invention. Examples different from the transistor 205 shown in FIG. 2 and the like are shown in FIGS.

[0234] The transistor 205R shown in FIGS. 10A to 11A differs from the transistor 205 shown in FIG. 2 and the like mainly in the configuration of the insulating layer 225.

[0235] 10A , the end of the insulating layer 225 is formed to coincide with or substantially coincide with the end of the conductive layer 223. It can also be said that the top surface shape of the insulating layer 225 coincides with or substantially coincides with that of the conductive layer 223. The insulating layer 225 overlaps with the channel formation region 231i of the semiconductor layer 231 but does not overlap with the low-resistance region 231n. The insulating layer 225 can be formed, for example, by processing using a resist mask for processing the conductive layer 223.

[0236] The insulating layer 218 is in contact with the top surface and side surfaces of the semiconductor layer 231, the side surfaces of the insulating layer 225, and the top surface and side surfaces of the conductive layer 223. Through the openings in the insulating layer 218, the conductive layers 222a and 222b are electrically connected to the low-resistance region 231n, respectively.

[0237] 10B , the end of the insulating layer 225 is located on the semiconductor layer 231. The end of the insulating layer 225 is located outside the end of the conductive layer 223. In other words, the insulating layer 225 has a portion on the semiconductor layer 231 that protrudes outside the end of the conductive layer 223.

[0238] The semiconductor layer 231 has a pair of regions 231l sandwiching a channel formation region 231i and a pair of low-resistance regions 231n outside the regions 231l. The regions 231l are regions of the semiconductor layer 231 that overlap with the insulating layer 225 but do not overlap with the conductive layer 223.

[0239] The region 231l functions as a buffer region for alleviating the drain electric field. Since the region 231l does not overlap with the conductive layer 223, a channel is hardly formed in the region 231l even when a gate voltage is applied to the conductive layer 223. The region 231l preferably has a higher carrier concentration than the channel formation region 231i. This allows the region 231l to function as an LDD (Lightly Doped Drain) region.

[0240] Compared to the channel formation region 231i, the region 231l can also be described as a region with the same or lower resistance, a region with the same or higher carrier concentration, a region with the same or higher oxygen defect density, or a region with the same or higher impurity concentration.

[0241] Compared to the low-resistance region 231n, the region 231l can also be described as a region with the same or higher resistance, a region with the same or lower carrier concentration, a region with the same or lower oxygen defect density, and a region with the same or lower impurity concentration.

[0242] The insulating layer 218 is in contact with the top surface and side surfaces of the semiconductor layer 231 , the insulating layer 225 , and the conductive layer 223 .

[0243] 11A shows a structure in which the conductive layer 222a and the conductive layer 222b are formed in the same process as the conductive layer 223. That is, the conductive layer 222a and the conductive layer 222b have the same material as the conductive layer 223. Forming the conductive layer 222a and the conductive layer 222b in the same process as the conductive layer 223 can simplify the process.

[0244] An insulating layer 218 may be provided over the transistor 205R. An insulating layer 214 is provided over the insulating layer 218. A conductive layer 233R is provided to cover the insulating layer 218 and an opening 191R provided in the insulating layer 214. The conductive layer 222b of the transistor 205R is electrically connected to the pixel electrode 111R through the conductive layer 233R. The width 191d can be said to be the distance between the ends of the insulating layer 214 that face each other on the insulating layer 218. Note that a configuration in which the insulating layer 218 is not provided is also possible.

[0245] 11B includes a metal oxide layer 227 between the insulating layer 225 and the conductive layer 223. The conductive layer 223 and the metal oxide layer 227 are processed so that their top surfaces are substantially the same. The metal oxide layer 227 can be formed by processing the conductive layer 223 using a resist mask used for processing the conductive layer 223, for example.

[0246] The metal oxide layer 227 has a function of supplying oxygen into the insulating layer 225. When a conductive film containing a metal or alloy that is easily oxidized is used as the conductive layer 223, the metal oxide layer 227 can also function as a barrier layer that prevents the conductive layer 223 from being oxidized by oxygen in the insulating layer 225. Note that the metal oxide layer 227 may be removed before the conductive layer 223 is formed, so that the conductive layer 223 and the insulating layer 225 are in contact with each other. Note that the metal oxide layer 227 may not be provided if it is not necessary.

[0247] The metal oxide layer 227 located between the insulating layer 225 and the conductive layer 223 functions as a barrier film that prevents oxygen contained in the insulating layer 225 from diffusing toward the conductive layer 223. Furthermore, the metal oxide layer 227 also functions as a barrier film that prevents impurities, including hydrogen elements, contained in the conductive layer 223 from diffusing toward the insulating layer 225. Examples of impurities that include hydrogen elements include hydrogen and water. For example, the metal oxide layer 227 is preferably made of a material that is less permeable to oxygen and hydrogen than the insulating layer 225.

[0248] The metal oxide layer 227 can prevent oxygen from diffusing from the insulating layer 225 to the conductive layer 223, even when a metal material that easily absorbs oxygen is used for the conductive layer 223. Furthermore, even when the conductive layer 223 contains hydrogen, it can prevent hydrogen from diffusing from the conductive layer 223 to the semiconductor layer 231 through the insulating layer 225. As a result, the carrier concentration in the channel formation region of the semiconductor layer 231 can be made extremely low. Note that examples of metal materials that easily absorb oxygen include aluminum and copper.

[0249] An insulating material or a conductive material can be used for the metal oxide layer 227. When the metal oxide layer 227 has insulating properties, the metal oxide layer 227 functions as a part of the gate insulating layer. On the other hand, when the metal oxide layer 227 has conductive properties, the metal oxide layer 227 functions as a part of the gate electrode.

[0250] It is preferable to use an insulating material having a higher dielectric constant than silicon oxide as the metal oxide layer 227. In particular, it is preferable to use an aluminum oxide film, a hafnium oxide film, a hafnium aluminate film, or the like, because the driving voltage can be reduced.

[0251] A conductive oxide such as indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can also be used as the metal oxide layer 227. In particular, conductive oxides containing indium are preferred because of their high conductivity.

[0252] The metal oxide layer 227 is preferably made of an oxide material containing one or more of the same elements as those of the semiconductor layer 231. In particular, it is preferable to use an oxide semiconductor material that can be applied to the semiconductor layer 231. In this case, it is preferable to use a metal oxide film formed using the same sputtering target as that of the semiconductor layer 231 as the metal oxide layer 227, because this allows the use of common equipment.

[0253] The metal oxide layer 227 is preferably formed using a sputtering apparatus. For example, when an oxide film is formed using a sputtering apparatus, oxygen can be suitably added to one or both of the insulating layer 225 and the semiconductor layer 231 by forming the oxide film in an atmosphere containing oxygen gas.

[0254] Note that a metal oxide film that can be used for the metal oxide layer 227 may be formed, and then the metal oxide film may be removed after oxygen is supplied to the insulating layer 225. Furthermore, the metal oxide layer 227 or a metal oxide film that can be used for the metal oxide layer 227 does not have to be provided if it is not necessary.

[0255] The metal oxide layer 227 can also be applied to other configuration examples.

[0256] 12A includes a conductive layer 221, an insulating layer 211, and a semiconductor layer 231 stacked in this order. The transistor 205R is a so-called bottom-gate transistor in which a gate electrode is provided under the semiconductor layer 231. Part of the insulating layer 211 functions as a gate insulating layer of the transistor 205R. The conductive layer 221 functions as a gate electrode of the transistor 205R.

[0257] A conductive layer 222a and a conductive layer 222b functioning as a source or a drain are provided over the semiconductor layer 231. The transistor 205R can be referred to as a bottom gate top contact (BGTC) transistor.

[0258] An insulating layer 218 may be provided over the transistor 205R. An insulating layer 214 is provided over the insulating layer 218. A conductive layer 233R is provided to cover the insulating layer 218 and an opening 191R provided in the insulating layer 214. The conductive layer 222b of the transistor 205R is electrically connected to the pixel electrode 111R through the conductive layer 233R. Note that a structure in which the insulating layer 218 is not provided is also possible.

[0259] The transistor 205R shown in FIG. 12B includes a conductive layer 230 that functions as a back gate. The conductive layer 230 overlaps with a semiconductor layer 231 through an insulating layer 218. The conductive layer 230 overlaps with a conductive layer 221 that functions as a gate through the semiconductor layer 231. An insulating layer 215 may be provided to cover the conductive layer 230 and the insulating layer 218. An insulating layer 214 is provided over the insulating layer 215. A conductive layer 233R is provided to cover an opening 191R provided in the insulating layer 218, the insulating layer 215, and the insulating layer 214. The conductive layer 222b of the transistor 205R is electrically connected to the pixel electrode 111R through the conductive layer 233R. Note that the insulating layer 215 may not be provided.

[0260] The insulating layer 215 functions as a protective layer for the transistor 205R. The insulating layer 215 is preferably made of a material that is less susceptible to impurity diffusion. By providing the insulating layer 215, it is possible to effectively prevent impurities from diffusing into the transistor from the outside, thereby improving the reliability of the display device. The insulating layer 215 can be made of a material that can be used for the insulating layer 218. The width 191d can be said to be the distance between the ends of the insulating layer 214 that face each other on the insulating layer 215.

[0261] 13 includes a semiconductor layer 231, an insulating layer 211, and a conductive layer 221 stacked in this order. The transistor 205R is a so-called top-gate transistor in which a gate electrode is provided over the semiconductor layer 231. Part of the insulating layer 211 functions as a gate insulating layer of the transistor 205R. The conductive layer 221 functions as a gate electrode of the transistor 205R.

[0262] A conductive layer 222a and a conductive layer 222b functioning as a source or a drain are provided over the semiconductor layer 231. The transistor 205R can be said to be a top gate top contact (TGTC) transistor.

[0263] An insulating layer 215 may be provided over the transistor 205R. An insulating layer 214 is provided over the insulating layer 215. A conductive layer 233R is provided to cover the insulating layer 211, the insulating layer 215, and the opening 191R provided in the insulating layer 214. The conductive layer 222b of the transistor 205R is electrically connected to the pixel electrode 111R through the conductive layer 233R. Note that a structure in which the insulating layer 215 is not provided is also possible.

[0264] The following describes examples of configurations different from the display device described above. Note that descriptions of parts that overlap with the display device described above may be omitted. Also, in the drawings shown below, parts that have the same functions as the display device described above may be hatched with the same pattern and may not be assigned reference numerals.

[0265] <Configuration Example 2 of Display Device> A cross-sectional view of a display device according to one embodiment of the present invention is shown in Fig. 14. Fig. 14 is a cross-sectional view taken along dashed dotted lines X1-X2 and Y1-Y2 in Fig. 1A.

[0266] The display device shown in FIG. 14 differs from the display device shown in FIG. 2 mainly in that an insulating layer 239 is provided between the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B and the insulating layer 235.

[0267] The insulating layer 239 is provided on the insulating layer 235 and has an opening in a region overlapping with the opening 193 of the insulating layer 235. The pixel electrode 111 is provided on the insulating layer 235. The pixel electrode 111 is provided so as to cover the opening of the insulating layer 235 and the opening 193R of the insulating layer 235. The pixel electrode 111 is electrically connected to the conductive layer 233 through the opening of the insulating layer 235 and the opening 193R of the insulating layer 235.

[0268] The insulating layer 239 can function as an etching protection film when the layer 113, the mask layer 118, and the mask layer 119 are formed. By providing the insulating layer 239, it is possible to prevent part of the insulating layer 235 from being etched when the layer 113, the mask layer 118, and the mask layer 119 are formed, thereby preventing unevenness from occurring in the insulating layer 235. In other words, the step on the surface on which the insulating layer 125 is formed is reduced, and the coverage of the insulating layer 125 can be improved. Therefore, the side surface of the layer 113 is covered with the insulating layer 125, and peeling of the layer 113 can be prevented.

[0269] The insulating layer 239 can be an insulating layer containing an inorganic material. For example, an inorganic insulating film such as an insulating oxide film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used for the insulating layer 239. The insulating layer 239 may have a single-layer structure or a stacked-layer structure. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film and an aluminum oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. For example, a silicon oxide film or a silicon oxynitride film can be suitably used for the insulating layer 239.

[0270] For the insulating layer 239, a material having a high etching rate (also referred to as a high selectivity) relative to the layer 113, the mask layer 118, and the film to be the mask layer 119 is preferably selected when the film is etched.

[0271] A portion of the insulating layer 239 may be removed in a region that does not overlap with any of the layers 113R, 113G, and 113B. The thickness of the insulating layer 239 in a region that does not overlap with any of the layers 113R, 113G, and 113B may be thinner than the thickness of the insulating layer 239 in a region that overlaps with the layer 113R, 113G, or 113B.

[0272] The insulating layer 239 can also be applied to other configuration examples.

[0273] <Configuration Example 3 of Display Device> A cross-sectional view of a display device according to one embodiment of the present invention is shown in Fig. 15. Fig. 15 is a cross-sectional view taken along dashed dotted lines X1-X2 and Y1-Y2 in Fig. 1A.

[0274] The display device shown in Figure 15 differs from the display device shown in Figure 2 mainly in that it has insulating layer 239 between light-emitting device 130R, light-emitting device 130G, and light-emitting device 130B and insulating layer 235, and in that it has insulating layer 238 between insulating layer 235 and insulating layer 214.

[0275] The insulating layer 239 can be described above, and therefore detailed description thereof will be omitted.

[0276] The insulating layer 238 is provided over the insulating layer 214 and has an opening in a region overlapping with the opening 191 of the insulating layer 214. The conductive layer 233 is provided over the insulating layer 238. The conductive layer 233 is provided so as to cover the opening of the insulating layer 238 and the opening 191R of the insulating layer 214. The conductive layer 233 is electrically connected to the conductive layer 222b of the transistor 205 through the opening of the insulating layer 238 and the opening 191R of the insulating layer 214.

[0277] The insulating layer 238 can function as an etching protection film when the conductive layer 233 is formed. By providing the insulating layer 238, it is possible to prevent part of the insulating layer 214 from being etched when the conductive layer 233 is formed, thereby preventing unevenness from occurring in the insulating layer 214. This can reduce the step on the surface on which the insulating layer 235 is to be formed, and improve the flatness of the insulating layer 235. Therefore, the flatness of the surface on which the light-emitting device 130 is to be formed is improved, and connection defects due to step disconnection of the common electrode and an increase in electrical resistance due to a local thinning of the film thickness of the common electrode 115 can be prevented, thereby providing a display device with high display quality.

[0278] The insulating layer 238 can be formed using the same material as the insulating layer 239. For example, the insulating layer 238 can be preferably formed using a silicon oxide film or a silicon oxynitride film.

[0279] For the insulating layer 238, a material is preferably selected that has a large etching rate ratio (large selectivity) with respect to the film that will become the conductive layer 233 when the film is etched.

[0280] A portion of the insulating layer 235 may be removed in a region that does not overlap with any of the conductive layers 233R, 233G, and 233B. The thickness of the insulating layer 235 in a region that does not overlap with any of the conductive layers 233R, 233G, and 233B may be thinner than the thickness of the insulating layer 235 in a region that overlaps with the conductive layer 233R, 233G, or 233B.

[0281] 15 illustrates a structure in which the insulating layer 238 is provided between the insulating layer 214 and the insulating layer 235, but one embodiment of the present invention is not limited to this. As illustrated in FIG. 16 , a structure may be employed in which the insulating layer 238 is provided in a region overlapping with any of the conductive layers 233R, 233G, and 233B, and the insulating layer 238 is not provided in a region overlapping with none of the conductive layers 233R, 233G, and 233B. The insulating layer 238 is provided in a region sandwiched between the conductive layer 233R and the insulating layer 214, a region sandwiched between the conductive layer 233G and the insulating layer 214, and a region sandwiched between the conductive layer 233B and the insulating layer 214. For example, when the conductive layers 233R, 233G, and 233B are formed, the insulating layer 238 may be removed from a region overlapping with none of the conductive layers 233R, 233G, and 233B. Alternatively, the insulating layer 238 may remain in an island shape in a region that does not overlap with any of the conductive layers 233R, 233G, and 233B. In this way, the insulating layer 235 is provided in contact with a part of the top surface of the insulating layer 214.

[0282] The insulating layer 238 can also be applied to other configuration examples.

[0283] <Configuration Example 4 of Display Device> A cross-sectional view of a display device according to one embodiment of the present invention is shown in Fig. 17. Fig. 17 is a cross-sectional view taken along dashed dotted lines X1-X2 and Y1-Y2 in Fig. 1A.

[0284] The display device shown in FIG. 17 differs from the display device shown in FIG. 2 mainly in that the configurations of the light-emitting devices 130R, 130G, and 130B are different.

[0285] Light-emitting device 130R has layer 113W instead of layer 113R. Light-emitting device 130G has layer 113W instead of layer 113G. Light-emitting device 130B has layer 113W instead of layer 113B. Layer 113W can be configured to emit, for example, white light.

[0286] Conductive layers that are transparent to visible light may be used for conductive layers 129R, 129G, and 129B, and the respective film thicknesses may be different. Conductive layers 129R, 129G, and 129B can function as optical adjustment layers. By adjusting the film thicknesses of conductive layers 129R, 129G, and 129B to optimize the optical path length, it is possible to obtain enhanced light of a desired wavelength from light-emitting device 130, even when layer 113W that emits white light is used.

[0287] A coloring layer 132R that transmits red light, a coloring layer 132G that transmits green light, and a coloring layer 132B that transmits blue light may be provided on the surface of the substrate 120 facing the resin layer 122. The coloring layer 132R is provided in a region overlapping the light-emitting device 130R. The coloring layer 132G is provided in a region overlapping the light-emitting device 130G. The coloring layer 132B is provided in a region overlapping the light-emitting device 130B. For example, the coloring layer 132R can block light of unnecessary wavelengths emitted from the red light-emitting device 130R. This configuration can improve the color purity of the light emitted from each light-emitting device. Note that the same effect can be achieved with the combination of the light-emitting device 130G and the coloring layer 132G, and the combination of the light-emitting device 130B and the coloring layer 132B.

[0288] The colored layers 132R, 132G, and 132B can also be applied to other configuration examples.

[0289] <Configuration Example 5 of Display Device> A cross-sectional view of a display device according to one embodiment of the present invention is shown in Fig. 18. Fig. 18 is a cross-sectional view taken along dashed dotted lines X1-X2 and Y1-Y2 in Fig. 1A.

[0290] The display device shown in FIG. 18 differs from the display device shown in FIG. 16 mainly in that it has an insulating layer 237 instead of the mask layers 118, 119, and the insulating layers 125 and 127.

[0291] The insulating layer 237 covers the upper surface end portions of the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B. The insulating layer 237 functions as a partition wall (also called a bank or a spacer).

[0292] By providing the insulating layer 237, it is possible to prevent the pixel electrode 111 from coming into contact with the common layer 114 and the common electrode 115, and to prevent the light-emitting device 130 from shorting out.

[0293] For example, the layers 113R, 113G, and 113B can be formed using a fine metal mask (FMM) after forming the insulating layer 237 that covers the upper surface end of the pixel electrode 111. By forming the island-shaped layers 113R, 113G, and 113B using a fine metal mask (FMM), the process can be simplified.

[0294] The layer 113R, the layer 113G, and the layer 113B may be provided over the insulating layer 237. Note that although FIG. 18 illustrates a structure in which the adjacent layers 113 are not in contact with each other, one embodiment of the present invention is not limited to this. The adjacent layers 113 may be in contact with each other over the insulating layer 237. The adjacent layers 113 may overlap with each other over the insulating layer 237. For example, the layer 113R and the layer 113G may be in contact with each other or may overlap with each other over the insulating layer 237.

[0295] The insulating layer 237 can also be applied to other configuration examples.

[0296] <Configuration Example 6 of Display Device> Fig. 19 shows a top view of a display device 100 different from that shown in Fig. 1A. The pixel 110 shown in Fig. 19 is made up of four types of subpixels: subpixel 11R, subpixel 11G, subpixel 11B, and subpixel 11S.

[0297] The subpixels 11R, 11G, 11B, and 11S may each have a light-emitting device that emits a different color light. For example, the subpixels 11R, 11G, 11B, and 11S may be subpixels of four colors R, G, B, and W, subpixels of four colors R, G, B, and Y, or subpixels of R, G, B, and IR.

[0298] The display device according to one embodiment of the present invention may include a light-receiving device in a pixel.

[0299] Of the four sub-pixels included in the pixel 110 shown in FIG. 19, three may be configured to have a light-emitting device, and the remaining one may be configured to have a light-receiving device.

[0300] The light receiving device may be, for example, a pn-type or pin-type photodiode. The light receiving device functions as a photoelectric conversion device (also called a photoelectric conversion element) that detects light incident on the light receiving device and generates electric charges. The amount of electric charges generated by the light receiving device is determined based on the amount of light incident on the light receiving device.

[0301] The light-receiving device can detect either or both of visible light and infrared light. When detecting visible light, it can detect one or more of colors such as blue, purple, blue-purple, green, yellow-green, yellow, orange, and red. When detecting infrared light, it is preferable because it enables detection of an object even in a dark place.

[0302] In particular, it is preferable to use an organic photodiode having a layer containing an organic compound as the light-receiving device. Organic photodiodes can be easily made thin, lightweight, and large in area, and have a high degree of freedom in shape and design, making them applicable to a variety of display devices.

[0303] In one embodiment of the present invention, an organic EL device is used as the light-emitting device, and an organic photodiode is used as the light-receiving device. The organic EL device and the organic photodiode can be formed on the same substrate. Therefore, the organic photodiode can be built into a display device using the organic EL device.

[0304] The light-receiving device is driven by applying a reverse bias between the pixel electrode and the common electrode, so that it can detect light incident on the light-receiving device, generate electric charges, and extract them as a current.

[0305] The same manufacturing method as for the light-emitting device can be applied to the light-receiving device. The island-shaped active layer (also called a photoelectric conversion layer) of the light-receiving device is formed by depositing a film to become the active layer on the entire surface and then processing it, rather than using a fine metal mask. Therefore, the island-shaped active layer can be formed with a uniform thickness. Furthermore, by providing a mask layer on the active layer, damage to the active layer during the manufacturing process of the display device can be reduced, thereby improving the reliability of the light-receiving device.

[0306] The sixth embodiment can be referred to for the configuration and materials of the light receiving device.

[0307] A cross-sectional view taken along dashed dotted line X3-X4 in Fig. 19 is shown in Fig. 20. Note that Fig. 2 can be referred to for cross-sectional views taken along dashed dotted line X1-X2 and dashed dotted line Y1-Y2 in Fig. 19.

[0308] 20 , in the display device 100, an insulating layer is provided on a layer 101 including transistors, a light-emitting device 130R and a light-receiving device 150 are provided on the insulating layer, a protective layer 131 is provided so as to cover the light-emitting device and the light-receiving device, and the substrate 120 is bonded by a resin layer 122. In addition, an insulating layer 125 and an insulating layer 127 on the insulating layer 125 are provided in the region between the adjacent light-emitting device and light-receiving device.

[0309] FIG. 20 shows an example in which the light emitting device 130R emits light toward the substrate 120 side, and light is incident on the light receiving device 150 from the substrate 120 side (see light Lem and light Lin).

[0310] The configuration of the light-emitting device 130R is as described above.

[0311] The light-receiving device 150 has a pixel electrode 111S on an insulating layer 235, a layer 113S on the pixel electrode 111S, a common layer 114 on the layer 113S, and a common electrode 115 on the common layer 114. The layer 113S includes at least an active layer.

[0312] Here, the layer 113S includes at least an active layer and preferably has multiple functional layers. Examples of functional layers include a carrier transport layer (hole transport layer and electron transport layer) and a carrier block layer (hole block layer and electron block layer). It is also preferable to have one or more layers on the active layer. Having another layer between the active layer and the mask layer can prevent the active layer from being exposed to the outermost surface during the manufacturing process of the display device, thereby reducing damage to the active layer. This can improve the reliability of the light-receiving device 150. Therefore, the layer 113S preferably has an active layer and a carrier block layer (hole block layer or electron block layer) or a carrier transport layer (electron transport layer or hole transport layer) on the active layer.

[0313] The layer 113S is a layer provided in the light-receiving device 150 but not in the light-emitting device. However, functional layers other than the active layer included in the layer 113S may have the same material as functional layers other than the light-emitting layers included in the layers 113B to 113R. On the other hand, the common layer 114 is a continuous layer shared by the light-emitting device and the light-receiving device.

[0314] Here, a layer shared by a light-receiving device and a light-emitting device may have different functions in the light-emitting device and in the light-receiving device. In this specification, components may be referred to based on their functions in the light-emitting device. For example, a hole injection layer functions as a hole injection layer in the light-emitting device and as a hole transport layer in the light-receiving device. Similarly, an electron injection layer functions as an electron injection layer in the light-emitting device and as an electron transport layer in the light-receiving device. Furthermore, a layer shared by a light-receiving device and a light-emitting device may have the same functions in the light-emitting device and in the light-receiving device. For example, a hole transport layer functions as a hole transport layer in both the light-emitting device and the light-receiving device, and an electron transport layer functions as an electron transport layer in both the light-emitting device and the light-receiving device.

[0315] Mask layers 118R and 119R are located between layer 113R and insulating layer 125, and mask layers 118S and 119S are located between layer 113S and insulating layer 125. Mask layers 118R and 119R are remaining portions of a mask layer that was provided on layer 113R when processing layer 113R. Mask layers 118S and 119S are remaining portions of a mask layer that was provided in contact with the top surface of layer 113S, which is a layer including an active layer, when processing layer 113S. Mask layers 118R and 118S may be made of the same material or different materials. Mask layers 119R and 119S may be made of the same material or different materials.

[0316] The light-receiving device 150 is electrically connected to the transistor 205S through the conductive layer 233S. The conductive layer 233S can be formed in the same process as the conductive layers 233R, 233G, and 233B. The transistor 205S can be formed in the same process as the transistors 205R, 205G, and 205B. The conductive layer 222b, which functions as the source or drain of the transistor 205S, has a region overlapping with the opening 191S of the insulating layer 214. The opening 191S can be formed in the same process as the openings 191R, 191G, and 191B. The conductive layer 233S is provided to cover the opening 191S. The conductive layer 222b is electrically connected to the conductive layer 233S in the opening 191S. The conductive layer 233S has a region overlapping with the opening 193S of the insulating layer 235. The opening 193S can be formed in the same process as the openings 193R, 193G, and 193B. The opening 193S is preferably located inside the opening 191S. The pixel electrode 111S of the light-receiving device 150 is provided so as to cover the opening 193S. The pixel electrode 111S can be formed in the same process as the pixel electrodes 111R, 111G, and 111B.

[0317] 19 shows an example in which the aperture ratio (which can also be referred to as the size, the size of the light-emitting region, or the size of the light-receiving region) of the subpixel 11S is larger than that of the subpixels 11R, 11G, and 11B, but this embodiment of the present invention is not limited to this. The aperture ratios of the subpixels 11R, 11G, 11B, and 11S can each be determined appropriately. The aperture ratios of the subpixels 11R, 11G, 11B, and 11S may be different from each other, or two or more of them may be equal or approximately equal.

[0318] The subpixel 11S may have a higher aperture ratio than at least one of the subpixels 11R, 11G, and 11B. A larger light-receiving area of ​​the subpixel 11S may make it easier to detect an object. For example, depending on the resolution of the display device and the circuit configuration of the subpixels, the aperture ratio of the subpixel 11S may be higher than the aperture ratios of the other subpixels.

[0319] The subpixel 11S may have a lower aperture ratio than at least one of the subpixels 11R, 11G, and 11B. If the light-receiving area of ​​the subpixel 11S is small, the imaging range is narrowed, which makes it possible to suppress blurring in the imaging result and improve the resolution. This is preferable because it enables high-definition or high-resolution imaging.

[0320] In this way, the sub-pixel 11S can have a detection wavelength, resolution, and aperture ratio suited to the application.

[0321] In a display device according to one embodiment of the present invention, an EL layer is provided in an island shape for each light-emitting device, thereby suppressing leakage current between subpixels. This prevents crosstalk due to unintended light emission and realizes a display device with high contrast. Furthermore, the edges of the island-shaped EL layer, which may be damaged during the manufacturing process of the display device, and their vicinity are used as dummy regions and are not used as light-emitting regions, thereby suppressing variations in the characteristics of the light-emitting devices. Furthermore, by providing an insulating layer having a tapered edge between adjacent island-shaped EL layers, discontinuities during the formation of a common electrode can be suppressed and locally thin portions of the common electrode can be prevented. This suppresses connection defects due to disconnected portions in the common layer and common electrode and increases in electrical resistance due to locally thin portions. This enables the display device according to one embodiment of the present invention to achieve both high resolution and high display quality.

[0322] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0323] 21 to 42. Note that with regard to materials and formation methods of elements, descriptions of the same parts as those described in Embodiment 1 may be omitted. In addition, details of the structure of a light-emitting device will be described in Embodiment 5.

[0324] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting display devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc. CVD methods include a plasma enhanced chemical vapor deposition (PECVD) method and a thermal CVD method. One type of thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0325] The thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the display device can be formed by a wet film formation method such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0326] In particular, vacuum processes such as vapor deposition and solution processes such as spin coating and inkjet printing can be used to fabricate light-emitting devices. Vapor deposition methods include physical vapor deposition (PVD) methods such as sputtering, ion plating, ion beam deposition, molecular beam deposition, and vacuum deposition, and chemical vapor deposition (CVD). In particular, functional layers included in the EL layer (hole injection layer, hole transport layer, hole blocking layer, light-emitting layer, electron blocking layer, electron transport layer, electron injection layer, charge generation layer, etc.) can be formed by vapor deposition (vacuum deposition, etc.), coating methods (dip coating, die coating, bar coating, spin coating, spray coating, etc.), printing methods (inkjet printing, screen (stencil printing), offset (lithographic printing), flexography (relief printing), gravure, microcontact printing, etc.), etc.

[0327] When processing the thin film that constitutes the display device, it can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, the island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0328] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0329] In photolithography, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0330] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0331] <Manufacturing Method Example 1> Here, a manufacturing method of the display device shown in FIG. 16 will be described.

[0332] First, the transistors 205R, 205G, and 205B are manufactured over the substrate 151. Here, the transistor 205R is used as an example and described with reference to Figures 21A to 22C. Note that Figures 21A to 22C show cross sections of the transistor 205R in the channel length direction and the channel width direction at each stage of the manufacturing process.

[0333] A conductive film to be the conductive layer 221 is formed over the substrate 151 and then processed by etching to form the conductive layer 221. It is preferable to process the conductive layer 221 so that the end portion thereof has a tapered shape. This can improve the step coverage of the insulating layer 211 to be formed next.

[0334] Wiring resistance can be reduced by using a conductive film containing copper as the conductive film to be the conductive layer 221. For example, when the device is applied to a large display device or a display device with high resolution, it is preferable to use a conductive film containing copper. Even when a conductive film containing copper is used for the conductive layer 221, the insulating layer 211 prevents copper from diffusing toward the semiconductor layer 231, so that a highly reliable transistor can be realized.

[0335] Subsequently, an insulating layer 211 is formed to cover the substrate 151 and the conductive layer 221 ( FIG. 21A ). The insulating layer 211 can be formed by a PECVD method, an ALD method, a sputtering method, or the like. Here, the insulating layer 211 is formed by stacking an insulating film 211 a and an insulating film 211 b. In particular, each insulating film constituting the insulating layer 211 is preferably formed by a PECVD method.

[0336] The insulating film 211a can be, for example, an insulating film containing nitrogen, such as a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or a hafnium nitride film. In particular, it is preferable to use a dense silicon nitride film formed using a PECVD apparatus as the insulating film 211a. By using such an insulating film containing nitrogen, even if the film is thin, it is possible to suitably suppress the diffusion of impurities from the surface on which the film is to be formed.

[0337] By using an insulating film containing nitrogen as the insulating film 211a, it is possible to prevent oxygen in the insulating film 211b from diffusing into the conductive layer 221, etc., thereby preventing a decrease in the oxygen contained in the insulating film 211b and preventing the conductive layer 221, etc. from being oxidized.

[0338] The insulating film 211b in contact with the semiconductor layer 231 is preferably formed using an insulating film containing oxide. In particular, an oxide film is preferably used for the insulating film 211b. The insulating film 211b is preferably a dense insulating film whose surface is less likely to adsorb impurities such as water. Furthermore, the insulating film 211b is preferably an insulating film with as few defects as possible and with reduced impurities including hydrogen elements.

[0339] The insulating film 211b can be, for example, an insulating film containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film. In particular, it is preferable to use a silicon oxide film or a silicon oxynitride film as the insulating film 211b.

[0340] The insulating film 211b preferably has a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating film 211b is preferably an insulating film that can release oxygen by heating. For example, oxygen can be supplied to the insulating film 211b by forming the insulating film 211b in an oxygen-containing atmosphere, performing heat treatment on the formed insulating film 211b in an oxygen-containing atmosphere, performing plasma treatment or the like in an oxygen-containing atmosphere after the formation of the insulating film 211b, or forming an oxide film on the insulating film 211b in an oxygen-containing atmosphere. Note that in each of the above oxygen-supplying treatments, an oxidizing gas may be used instead of or in addition to oxygen. Alternatively, oxygen may be supplied to the insulating film 211b from an insulating film that can release oxygen by heating by forming the insulating film on the insulating film 211b and then performing heat treatment. Alternatively, oxygen may be supplied to the insulating film 211b by plasma ion doping or ion implantation.

[0341] Here, the insulating film 211b is preferably formed thicker than the insulating film 211a. This increases the amount of oxygen that can be released from the insulating film 211b by heating, and reduces the amount of hydrogen released from the insulating film 211a. This makes it possible to supply a large amount of oxygen to the semiconductor layer 231 later while suppressing the supply of hydrogen, thereby achieving a highly reliable transistor. The thickness of the insulating film 211b is preferably from 2 to 50 times, preferably from 3 to 30 times, more preferably from 5 to 20 times, even more preferably from 7 to 15 times, and typically about 10 times that of the insulating film 211a.

[0342] When the metal oxide film to be the semiconductor layer 231 is formed by a sputtering method in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 211b. After the metal oxide film to be the semiconductor layer is formed, heat treatment may be performed. By the heat treatment, oxygen in the insulating film 211b can be more effectively supplied to the metal oxide film, and oxygen vacancies in the metal oxide film can be reduced.

[0343] When the insulating layer 211 is formed using a PECVD apparatus, after the insulating layer 211 is formed, plasma treatment may be performed in a treatment chamber at a lower power than that used for forming the insulating layer 211 to remove static electricity accumulated on the substrate 151. This plasma treatment can be called a discharge treatment. The discharge treatment can be performed in an atmosphere containing one or more of nitrogen, nitrous oxide, nitrogen dioxide, hydrogen, ammonia, and noble gases. For example, an argon gas atmosphere can be suitably used for the discharge treatment. Alternatively, the discharge treatment can be performed using a mixed gas containing the above-mentioned gases.

[0344] After the insulating layer 211 is formed, the surface of the insulating layer 211 may be removed. The above-described static elimination treatment may cause defects on the surface of the insulating layer 211. If defects exist in the insulating layer 211 that functions as the first gate insulating layer of the transistor 205, they may become carrier trap sites, which may deteriorate the reliability of the transistor 205. Therefore, by removing the surface of the insulating layer 211 that has defects, the reliability of the transistor 205 can be improved. To remove the surface of the insulating layer 211, for example, cleaning with a cleaning solution containing hydrofluoric acid can be used.

[0345] Heat treatment may be performed after the insulating layer 211 is formed. The heat treatment can reduce defects in the insulating layer 211. Furthermore, impurities containing hydrogen elements can be reduced in the insulating layer 211. Examples of impurities containing hydrogen elements include hydrogen and water.

[0346] The temperature of the heat treatment is preferably 150° C. or higher and lower than the strain point of the substrate, more preferably 250° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 450° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA) may be used. Note that the atmosphere preferably contains as little hydrogen, water, or the like as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. Using an atmosphere with as little hydrogen, water, or the like as possible can prevent hydrogen, water, or the like from being taken into the insulating layer 211. The heat treatment can be performed using an oven, a rapid thermal annealing (RTA) apparatus, or the like. Using an RTA apparatus can shorten the heat treatment time.

[0347] The heat treatment may be performed after the surface of the insulating layer 211 is removed.

[0348] Subsequently, a process for supplying oxygen to the insulating layer 211 may be performed. The oxygen supply process supplies oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, or the like to the insulating layer 211 by ion doping, ion implantation, plasma treatment, or the like. Alternatively, a film that suppresses oxygen desorption may be formed on the insulating layer 211, and then oxygen may be added to the insulating layer 211 through the film. The film is preferably removed after oxygen is added. The film that suppresses oxygen desorption may be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten.

[0349] Subsequently, a metal oxide film 231f (FIG. 21B) is formed on the insulating layer 211. The metal oxide film 231f is preferably formed by sputtering using a metal oxide target.

[0350] The metal oxide film 231f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 231f is preferably a high-purity film in which impurities including hydrogen are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 231f.

[0351] It is preferable to use oxygen gas when forming the metal oxide film 231f. By using oxygen gas when forming the metal oxide film 231f, oxygen can be suitably supplied into the insulating layer 211. For example, when an oxide is used for the insulating film 211a, oxygen can be suitably supplied into the insulating film 211a. By supplying oxygen to the insulating layer 211, oxygen is supplied to the semiconductor layer 231 in a later step, and oxygen vacancies (V Ｏ ), and oxygen deficiency (V Ｏ ) with hydrogen (hereinafter referred to as V Ｏ H) can be reduced.

[0352] When forming a metal oxide film, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film can be, and a transistor with a large on-state current can be obtained.

[0353] When forming a metal oxide film, the higher the substrate temperature, the higher the crystallinity and density of the metal oxide film, whereas the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film.

[0354] The deposition conditions for the metal oxide film are that the substrate temperature is from room temperature to 250° C., preferably from room temperature to 200° C., and more preferably from room temperature to 140° C. For example, a substrate temperature of from room temperature to less than 140° C. is preferable because productivity is increased. Furthermore, by depositing the metal oxide film at room temperature or without heating the substrate, the crystallinity can be reduced.

[0355] Before forming the metal oxide film 231f, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 211 and a treatment for supplying oxygen into the insulating layer 211. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment may be performed in an atmosphere containing oxygen. Alternatively, dinitrogen monoxide (N ２ Oxygen may be supplied to the insulating layer 211 by plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (NO). When plasma treatment containing nitrous oxide gas is performed, oxygen can be supplied while suitably removing organic substances from the surface of the insulating layer 211. After such treatment, it is preferable to form a metal oxide film 231f without exposing the surface of the insulating layer 211 to the air.

[0356] In addition, when the semiconductor layer 231 has a stacked structure in which a plurality of semiconductor layers are stacked, it is preferable to form a metal oxide film first, and then form a next metal oxide film in succession without exposing the surface of the first metal oxide film to the air.

[0357] Subsequently, a part of the metal oxide film 231f is etched to form an island-shaped semiconductor layer 231. The metal oxide film 231f may be processed by wet etching or dry etching, or both. At this time, a part of the insulating layer 211 that does not overlap with the semiconductor layer 231 may be etched and thinned. For example, the insulating film 211b of the insulating layer 211 may be removed by etching, and the surface of the insulating film 211a may be exposed.

[0358] Here, heat treatment is preferably performed after the metal oxide film 231f is formed or after the metal oxide film 231f is processed into the semiconductor layer 231. The heat treatment can remove hydrogen or water contained in or adsorbed on the surface of the metal oxide film 231f or the semiconductor layer 231. Furthermore, the heat treatment may improve the film quality of the metal oxide film 231f or the semiconductor layer 231 (for example, reduce defects or improve crystallinity).

[0359] By the heat treatment, oxygen can also be supplied from the insulating layer 211 to the metal oxide film 231f or the semiconductor layer 231. In this case, it is more preferable to perform the heat treatment before processing into the semiconductor layer 231.

[0360] The temperature of the heat treatment can typically be 150°C or higher and lower than the strain point of the substrate, or 200°C or higher and 500°C or lower, or 250°C or higher and 450°C or lower, or 300°C or higher and 450°C or lower. The heat treatment can be performed in an atmosphere containing a noble gas or nitrogen. Alternatively, the substrate may be heated in the noble gas or nitrogen atmosphere and then heated in an oxygen-containing atmosphere. Alternatively, the substrate may be heated in a dry air atmosphere. Note that it is preferable that the atmosphere for the heat treatment contains as little hydrogen, water, or the like as possible. The heat treatment can be performed using an electric furnace, an RTA apparatus, or the like. Using an RTA apparatus can shorten the heat treatment time.

[0361] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, there are cases where a high-temperature treatment in a later step (e.g., a film formation step) can also serve as the heat treatment.

[0362] Subsequently, an insulating layer 225 is formed to cover the insulating layer 211 and the semiconductor layer 231 (FIG. 21C). The insulating layer 225 is preferably formed by a PECVD method. The insulating layer 225 may have a stacked structure.

[0363] It is preferable to perform plasma treatment on the surface of the semiconductor layer 231 before forming the insulating layer 225. The plasma treatment can reduce impurities such as water adsorbed on the surface of the semiconductor layer 231. Therefore, impurities at the interface between the semiconductor layer 231 and the insulating layer 225 can be reduced, resulting in a highly reliable transistor. This is particularly suitable when the surface of the semiconductor layer 231 is exposed to the air between the formation of the semiconductor layer 231 and the formation of the insulating layer 225. The plasma treatment can be performed in an atmosphere containing, for example, oxygen, ozone, nitrogen, nitrous oxide, argon, or the like. It is also preferable to perform the plasma treatment and the formation of the insulating layer 225 successively without exposure to the air.

[0364] Here, it is preferable that the substrate temperature during deposition of the insulating layer 225 is high. By increasing the substrate temperature during deposition of the insulating layer 225, the insulating layer 225 can be formed with fewer defects. On the other hand, if the substrate temperature during deposition of the insulating layer 225 is high, metal atoms contained in the semiconductor layer 231 may diffuse into the insulating layer 225, causing defects in the insulating layer 225. For example, when an In-Ga-Zn oxide is used for the semiconductor layer 231 and an oxide containing silicon is used for the insulating layer 225, defects in which silicon atoms contained in the insulating layer 225 are replaced by metal atoms contained in the semiconductor layer 231 may occur. Ｓｉ , Ga Ｓｉ , and Zn Ｓｉmay be generated, which may increase NBTIS degradation. The substrate temperature during deposition of the insulating layer 225 is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 200° C. or higher and 400° C. or lower, further preferably 250° C. or higher and 400° C. or lower, further preferably 250° C. or higher and 350° C. or lower, further preferably 300° C. or higher and 350° C. or lower, and further preferably. By setting the substrate temperature during deposition of the insulating layer 225 within the above range, a highly reliable transistor can be obtained.

[0365] It is preferable to perform heat treatment after the insulating layer 225 is formed. The heat treatment can remove hydrogen or water contained in the insulating layer 225 or adsorbed on the surface. Furthermore, defects in the insulating layer 225 can be reduced. The conditions for the heat treatment can be described above. Note that the heat treatment does not have to be performed if it is unnecessary. Alternatively, the heat treatment may not be performed here, and may serve as a heat treatment performed in a later step. Alternatively, the heat treatment may serve as a high-temperature treatment in a later step (e.g., a film formation step).

[0366] Subsequently, the insulating layer 225 and a part of the insulating layer 211 are etched to form an opening 147 that reaches the conductive layer 221. This allows the conductive layer 221 to be electrically connected to a conductive layer 223 to be formed later through the opening 147.

[0367] Subsequently, a conductive film that will become the conductive layer 223 is formed on the insulating layer 225, and then processed by etching to form the conductive layer 223 (FIG. 21D).

[0368] The conductive film to be the conductive layer 223 is preferably formed by, for example, a sputtering method using a sputtering target containing a metal or an alloy. The conductive film is preferably made of a low-resistance metal or alloy material.

[0369] A material that releases little hydrogen and through which hydrogen does not easily diffuse is preferably used for the conductive film that becomes the conductive layer 223. A material that is not easily oxidized is preferably used for the conductive film. For example, the conductive film is preferably a stacked film in which a conductive film that is not easily oxidized and through which hydrogen does not easily diffuse and a conductive film with low resistance are stacked.

[0370] The conductive film to be the conductive layer 223 may be processed by one or both of a wet etching method and a dry etching method.

[0371] In this way, by forming a structure in which the insulating layer 225 covers the top and side surfaces of the semiconductor layer 231 and the insulating layer 211 without etching the insulating layer 225, it is possible to prevent the semiconductor layer 231 and the insulating layer 211 from being partially etched and the film thickness from being reduced when the conductive layer 223 is formed.

[0372] Next, using the conductive layer 223 as a mask, the impurity element 145 is supplied (also referred to as addition or injection) to the semiconductor layer 231 through the insulating layer 225 ( FIG. 22A ). As a result, a low-resistance region 231n can be formed in a region of the semiconductor layer 231 that is not covered with the conductive layer 223. At this time, it is preferable to determine conditions for the supplying process of the impurity element 145 in consideration of the material and thickness of the conductive layer 223 or the like that serves as the mask so that the impurity element 145 is not supplied to a region of the semiconductor layer 231 that overlaps with the conductive layer 223 as much as possible. As a result, a channel formation region with a sufficiently reduced impurity concentration can be formed in the region of the semiconductor layer 231 that overlaps with the conductive layer 223.

[0373] The impurity element 145 can be preferably supplied by plasma ion doping or ion implantation. These methods allow the concentration profile in the depth direction to be controlled with high precision by adjusting the ion acceleration voltage, dose, and the like. The use of plasma ion doping can improve productivity. The use of ion implantation using mass separation can also improve the purity of the supplied impurity element.

[0374] In the supplying treatment of the impurity element 145, it is preferable to control the treatment conditions so that the concentration is highest at the interface between the semiconductor layer 231 and the insulating layer 225, or at a portion close to the interface in the semiconductor layer 231, or at a portion close to the interface in the insulating layer 225. This allows the impurity element 145 to be supplied at an optimum concentration to both the semiconductor layer 231 and the insulating layer 225 in one treatment.

[0375] Examples of the impurity element 145 include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gases. Typical examples of noble gases include helium, neon, argon, krypton, and xenon. In particular, it is preferable to use boron, phosphorus, aluminum, magnesium, or silicon.

[0376] The source gas of the impurity element 145 can be a gas containing the above impurity element. ２ H ６ Gas, or BF ３ In addition, when phosphorus is supplied, one or more of the following gases can be used: PH ３ A mixed gas obtained by diluting these source gases with a noble gas may also be used.

[0377] Other raw material gases include CH ４ , N ２ , N.H. ３ , AlH ３ , AlCl ３ , SiH ４ , Si ２ H ６ , F ２ , H.F., H. ２ , (C ５ H ５ ) ２ Mg, noble gases, etc. can be used. The ion source is not limited to gas, and a solid or liquid vaporized by heating may also be used.

[0378] The addition of the impurity element 145 can be controlled by setting conditions such as acceleration voltage and dose amount in consideration of the composition, density, thickness, and the like of the insulating layer 225 and the semiconductor layer 231 .

[0379] For example, when boron is added by ion implantation or plasma ion doping, the acceleration voltage can be set to, for example, 5 kV or more and 100 kV or less, preferably 7 kV or more and 70 kV or less, and more preferably 10 kV or more and 50 kV or less. The dose can be set to, for example, 1×10 １３ ions / cm ２ 1x10 or more １７ ions / cm ２ Below 1 × 10, preferably １４ ions / cm ２ 5x10 or more １６ ions / cm ２ or less, more preferably 1 × 10 １５ ions / cm ２ That's it, 3 x 10 １６ ions / cm ２ The range can be as follows:

[0380] When phosphorus ions are added by ion implantation or plasma ion doping, the acceleration voltage can be set to, for example, 10 kV or more and 100 kV or less, preferably 30 kV or more and 90 kV or less, and more preferably 40 kV or more and 80 kV or less. The dose can be set to, for example, 1×10 １３ ions / cm ２ 1x10 or more １７ ions / cm ２ Below 1 × 10, preferably １４ ions / cm ２ 5x10 or more １６ ions / cm ２ or less, more preferably 1 × 10 １５ ions / cm ２ 3x10 or more １６ ions / cm ２ The range can be as follows:

[0381] Note that the method for supplying the impurity element 145 is not limited to this, and for example, plasma treatment, treatment using thermal diffusion by heating, or the like may be used. In the case of plasma treatment, the impurity element can be added by generating plasma in a gas atmosphere containing the impurity element to be added and performing the plasma treatment. As an apparatus for generating the plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, or the like may be used.

[0382] For example, by performing plasma treatment in an atmosphere containing hydrogen gas using a plasma CVD apparatus, hydrogen can be supplied as the impurity element 145 to a region of the semiconductor layer 231 that does not overlap with the conductive layer 223. Furthermore, by using a plasma CVD apparatus for the supply treatment of the impurity element 145 and the formation of the insulating layer 218, the supply treatment of the impurity element 145 and the formation of the insulating layer 218 can be performed successively within the apparatus, thereby improving productivity.

[0383] In one embodiment of the present invention, the impurity element 145 can be supplied to the semiconductor layer 231 through the insulating layer 225. Therefore, even when the semiconductor layer 231 has crystallinity, damage to the semiconductor layer 231 when the impurity element 145 is supplied can be reduced, and loss of crystallinity can be suppressed. Therefore, this is suitable for cases where electrical resistance increases due to a decrease in crystallinity.

[0384] Subsequently, an insulating layer 218 is formed to cover the insulating layer 225 and the conductive layer 223 (FIG. 22B).

[0385] If the deposition temperature of the insulating layer 218 is too high, impurities contained in the low-resistance region 231n and the like may diffuse into the peripheral portion including the channel formation region of the semiconductor layer 231, and the electrical resistance of the low-resistance region 231n may increase. Therefore, the deposition temperature of the insulating layer 218 may be determined taking these factors into consideration.

[0386] For example, the deposition temperature of the insulating layer 218 is preferably 150° C. to 400° C., preferably 180° C. to 360° C., more preferably 200° C. to 250° C. By depositing the insulating layer 218 at a low temperature, good electrical characteristics can be imparted even to a transistor with a short channel length.

[0387] After the insulating layer 218 is formed, heat treatment may be performed. The heat treatment may make the low-resistance region 231n more stable and low-resistance. For example, the heat treatment may cause the impurity element 145 to diffuse appropriately and become locally uniform, thereby forming the low-resistance region 231n having an ideal impurity element concentration gradient. Note that if the temperature of the heat treatment is too high (for example, 500° C. or higher), the impurity element 145 may diffuse into the channel formation region, which may result in deterioration of the electrical characteristics and reliability of the transistor.

[0388] The conditions for the heat treatment can be as described above.

[0389] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, if there is a high-temperature treatment (e.g., a film formation step) in a later step, this heat treatment may be combined with the heat treatment.

[0390] Subsequently, the insulating layer 218 and the insulating layer 225 are partially etched to form openings 141a and 141b that reach the low-resistance region 231n.

[0391] Subsequently, a conductive film is formed over the insulating layer 218 so as to cover the openings 141a and 141b, and the conductive film is processed to form conductive layers 222a and 222b (FIG. 22C).

[0392] Through the above steps, the transistor 205R can be manufactured. The transistors 205G and B can be formed over the same substrate through the same steps as the transistor 205R.

[0393] The following description will be made with reference to Figures 23A to 38. Figures 23A to 38 show a transistor 205R, a transistor 205G, and a transistor 205B. Figures 23A to 38 show a cross-sectional view taken along dashed dotted line X1-X2 and a cross-sectional view taken along dashed dotted line Y1-Y2 shown in Figure 16 side by side.

[0394] Subsequently, an insulating film 214f ​​that will become the insulating layer 214 is formed so as to cover the transistor 205R, the transistor 205G, and the transistor 205B.

[0395] For example, when a photosensitive organic material is used for the insulating film 214f, a composition containing the organic material is applied by spin coating, and then selectively exposed and developed to form the insulating layer 214. As other formation methods, one or more of a sputtering method, a vapor deposition method, a droplet discharge method (inkjet method), screen printing, and offset printing may be used.

[0396] Figure 23A schematically shows how a photosensitive organic material is used for the insulating film 214f, and the region overlapping with the conductive layer 222b of the transistor 205R, the region overlapping with the conductive layer 222b of the transistor 205G, and the region overlapping with the conductive layer 222b of the transistor 205B are exposed to light.

[0397] The light used for exposure preferably includes i-line. The light used for exposure may also include at least one of g-line and h-line. In Fig. 23A, the light is indicated by arrows, and the region where the insulating layer 214 is not to be formed is exposed to light, while the region where the insulating layer 214 is to be formed is shielded from light using a mask 132a.

[0398] By adjusting the amount of exposure light, the widths 191d of the openings 191R, 191G, and 191B can be controlled.

[0399] Subsequently, development is performed to remove the exposed regions of the insulating film 214f, thereby forming the insulating layer 214 having the openings 191R, 191G, and 191B (FIG. 23B). The conductive layers 222b of the transistors 205R, 205G, and 205B are exposed in the openings 191R, 191G, and 191B.

[0400] Here, an example has been shown in which a positive photosensitive resin is used for the insulating film 214f, but the present invention is not limited to this. For example, a negative photosensitive resin may be used for the insulating film 214f. In this case, the region where the insulating layer 214 is to be formed is exposed to light, and the region where the insulating layer 214 is not to be formed is shielded from light using a mask. During development, the insulating layer 214 is formed in the exposed region of the insulating film 214f.

[0401] Heat treatment is preferably performed after the insulating layer 214 is formed. In the case where an organic material is used for the insulating layer 214, the organic material can be cured by the heat treatment.

[0402] The temperature of the heat treatment is preferably lower than the heat resistance temperature of the organic material. For example, the temperature of the heat treatment is preferably 150°C or higher and 350°C or lower, more preferably 180°C or higher and 300°C or lower, even more preferably 200°C or higher and 270°C or lower, even more preferably 200°C or higher and 250°C or lower, and even more preferably 220°C or higher and 250°C or lower.

[0403] The heat treatment can be performed in an atmosphere containing a noble gas or nitrogen. Alternatively, the heat treatment can be performed in a dry air atmosphere. Note that it is preferable that the heat treatment atmosphere contains as little hydrogen, water, or the like as possible. The heat treatment can be performed using an electric furnace, an RTA apparatus, or the like.

[0404] Subsequently, an insulating film 238f that will become the insulating layer 238 is formed so as to cover the insulating layer 214, the opening 191R, the opening 191G, and the opening 191B.

[0405] Next, a resist mask 195a is formed on the insulating film 238f (FIG. 24A). The resist mask 195a may be either a positive resist or a negative resist. The resist mask 195a is not provided in the openings 191R, 191G, and 191B.

[0406] Next, the insulating film 238f is processed using the resist mask 195a as a mask to form an insulating layer 238. As a result, the conductive layers 222b of the transistors 205R, 205G, and 205B are exposed. The insulating film 238f can be processed by wet etching or dry etching, or both.

[0407] Subsequently, the resist mask 195a is removed.

[0408] Subsequently, a conductive film 233f to be the conductive layer 233 is deposited so as to cover the insulating layer 238, the insulating layer 214, and the conductive layer 222b.

[0409] Next, a resist mask 195b is formed over the conductive film 233f (FIG. 24B). The resist mask 195b may be either a positive resist or a negative resist. The resist mask 195b has regions overlapping with the conductive layers 222b of the transistors 205R, 205G, and 205B.

[0410] Next, the conductive film 233f is processed using the resist mask 195b as a mask to form a conductive layer 233. As a result, the conductive layer 233 in contact with the conductive layer 222b of the transistor 205R, the transistor 205G, and the transistor 205B is formed. The conductive film 233f can be processed by one or both of a wet etching method and a dry etching method.

[0411] When the conductive film 233f is processed, the insulating layer 238 in a region that does not overlap with the resist mask 195b may be removed ( FIG. 25A ). The insulating layer 238 remains between the conductive layer 233 and the insulating layer 214. Note that the insulating layer 238 in a region that does not overlap with the resist mask 195b may remain. In this case, the structure shown in FIG. 15 can be obtained.

[0412] Subsequently, the resist mask 195b is removed.

[0413] Subsequently, an insulating film 235f to be the insulating layer 235 is formed so as to cover the insulating layer 214, the insulating layer 238, and the conductive layer 233. The insulating film 235f can be formed using a method similar to that for the insulating film 214f.

[0414] 25B schematically shows how a photosensitive organic material is used for the insulating film 235f, and the region overlapping with the conductive layer 233 is exposed to light. In Fig. 25B, arrows indicate light, and the region where the insulating layer 235 is not to be formed is exposed to light, while the region where the insulating layer 235 is to be formed is shielded from light using a mask 132b.

[0415] The widths 193d of the openings 193R, 193G, and 193B can be controlled by adjusting the exposure dose. Here, the width 193d of the opening 193R is preferably smaller than the width 191d of the opening 191R. Similarly, the width 193d of the opening 193G is preferably smaller than the width 191d of the opening 191G. The width 193d of the opening 193B is preferably smaller than the width 191d of the opening 191B. The exposure dose is preferably adjusted so that the widths 193d of the openings 193R, 193G, and 193B are smaller than the widths 191d of the openings 191R, 191G, and 191B. For example, if the insulating film 214f ​​and the insulating film 235f are made of the same material and have approximately the same thickness, the exposure dose of the insulating film 235f is preferably less than the exposure dose of the insulating film 214f. For example, the exposure time of the insulating film 235f may be shorter than the exposure time of the insulating film 214f.

[0416] Subsequently, development is performed to remove the exposed regions of the insulating film 235f, thereby forming the insulating layer 235 having the openings 193R, 193G, and 193B (FIG. 26A). The conductive layer 233 is exposed in the openings 193R, 193G, and 193B.

[0417] Although the insulating film 235f is formed of a positive photosensitive resin in this example, the present invention is not limited to this. For example, the insulating film 235f may be formed of a negative photosensitive resin.

[0418] Heat treatment is preferably performed after the insulating layer 235 is formed. The detailed description of the heat treatment performed after the insulating layer 214 can be referred to; therefore, the detailed description of the heat treatment is omitted.

[0419] Subsequently, an insulating film 239 f that will become the insulating layer 239 is formed so as to cover the insulating layer 235 and the conductive layer 233 .

[0420] Next, a resist mask 195c is formed on the insulating film 239f (FIG. 26B). The resist mask 195c may be either a positive resist or a negative resist. The resist mask 195c is not provided in the openings 193R, 193G, and 193B.

[0421] Subsequently, the insulating film 239f is processed using the resist mask 195c as a mask to form an insulating layer 239. This exposes the conductive layer 233. The insulating film 239f can be processed by one or both of a wet etching method and a dry etching method.

[0422] Subsequently, the resist mask 195c is removed.

[0423] Subsequently, a conductive film 112f that will become the conductive layers 112R, 112G, 112B, and 112p is formed so as to cover the insulating layer 239, the insulating layer 235, and the conductive layer 233.

[0424] Next, a resist mask 195d is formed over the conductive film 112f (FIG. 27A). The resist mask 195d may be either a positive resist or a negative resist. The resist mask 195d has a region overlapping with the conductive layer 223.

[0425] Next, the conductive film 112f is processed using the resist mask 195d as a mask to form the conductive layers 112R, 112G, 112B, and 112p. As a result, the conductive layers 112R, 112G, and 112B in contact with the conductive layer 223 are formed. The conductive film 112f can be processed by one or both of a wet etching method and a dry etching method.

[0426] When the conductive film 233f is processed, a part of the insulating layer 238 may be removed. For example, the thickness of the insulating layer 238 in a region overlapping with any of the conductive layers 112R, 112G, and 112B may be thinner than the thickness of the insulating layer 238 in a region not overlapping with any of the conductive layers 112R, 112G, and 112B.

[0427] Subsequently, the resist mask 195d is removed (FIG. 27B).

[0428] Subsequently, a film 128f to be the layer 128 is formed so as to cover the insulating layer 239, the conductive layer 112R, the conductive layer 112G, the conductive layer 112B, and the conductive layer 112p. The film 128f can be formed by the same method as the insulating film 214f.

[0429] 28 schematically shows how a photosensitive organic material is used for the film 128f, and the region overlapping with the conductive layer 233 is exposed to light. In FIG. 28, arrows indicate light, and the region where the layer 128 is not to be formed is exposed to light, while the region where the layer 128 is to be formed is shielded from light using a mask 132c. At this time, the shape of the layer 128 can be controlled by adjusting the amount of exposure.

[0430] Development is then performed to remove the exposed areas of film 128f, forming layer 128 (Figure 29A).

[0431] Although the example in which a positive photosensitive resin is used for the film 128f has been described here, the present invention is not limited to this. For example, a negative photosensitive resin may be used for the film 128f.

[0432] Heat treatment is preferably performed after the formation of the layer 128. The detailed description of the heat treatment performed after the formation of the insulating layer 214 can be referred to, and therefore, will not be repeated.

[0433] Next, a conductive film 126f that will become the conductive layers 126R, 126G, 126B, and 126p is deposited so as to cover the insulating layer 239, the conductive layers 112R, 112G, 112B, 112p, and the layer 128.

[0434] Here, the conductive film 126f is provided over the insulating layer 239, the conductive layer 112R, the conductive layer 112G, the conductive layer 112B, the conductive layer 112p, and the layer 128. If the adhesiveness between the conductive film 126f and these films is low, film peeling may occur. It is preferable to use a material that has high adhesiveness to the surface on which the conductive film 126f is formed. For example, an alloy of silver, palladium, and copper (APC) has low adhesiveness to an insulating layer containing an inorganic material, and if the conductive film 126f is provided on the insulating layer, film peeling may occur. Therefore, when an inorganic material is used for the insulating layer 239, it is preferable to use a material that has high adhesiveness to the insulating layer 239 on the side of the conductive film 126f that is in contact with the insulating layer 239. For example, a stacked structure of In—Si—Sn oxide (ITSO) and an alloy of silver, palladium, and copper (APC) on the In—Si—Sn oxide (ITSO) can be suitably used as the conductive film 126f. By using In-Si-Sn oxide (ITSO) for the layer of the conductive film 126f that is in contact with the insulating layer 239, peeling of the conductive film 126f can be suppressed even when an inorganic material is used for the insulating layer 239.

[0435] Note that a structure may be adopted in which the insulating layer 239 is not provided, and the conductive film 126f is provided over the insulating layer 235, the conductive layer 112R, the conductive layer 112G, the conductive layer 112B, the conductive layer 112p, and the layer 128 (see FIG. 2). When an organic material is used for the insulating layer 235, the conductive film 126f may have a single-layer structure of an alloy of silver, palladium, and copper (APC).

[0436] Next, a resist mask 195e is formed over the conductive film 126f (FIG. 29B). Either a positive resist or a negative resist may be used as the resist mask 195e. The resist mask 195e is provided in a region overlapping with the conductive layer 112R, the conductive layer 112G, the conductive layer 112B, and the conductive layer 112p.

[0437] Next, the conductive film 126f is processed using the resist mask 195e as a mask to form the conductive layers 126R, 126G, 126B, and 126p. The conductive film 126f can be processed by wet etching or dry etching, or both.

[0438] Subsequently, the resist mask 195e is removed.

[0439] Next, the conductive layer 129R, the conductive layer 129G, the conductive layer 129B, and the conductive layer 129p are formed. Here, a manufacturing method is described in which the conductive layer 129R, the conductive layer 129G, and the conductive layer 129B have a stacked structure and the conductive layer 129p has a single-layer structure. Note that one embodiment of the present invention is not limited to this. The conductive layer 129R, the conductive layer 129G, and the conductive layer 129B may have a single-layer structure or a stacked structure. Furthermore, the conductive layer 129p may have a single-layer structure or a stacked structure.

[0440] A conductive film 129af that will become part of the conductive layer 129R, the conductive layer 129G, and the conductive layer 129B is formed so as to cover the insulating layer 239, the conductive layer 112R, the conductive layer 112G, the conductive layer 112B, the conductive layer 112p, the conductive layer 126R, the conductive layer 126G, the conductive layer 126B, and the conductive layer 126p.

[0441] Next, a resist mask 195f is formed over the conductive film 129af (FIG. 30A). The resist mask 195g may be either a positive resist or a negative resist. The resist mask 195f is provided in a region overlapping with the conductive layer 112R, a region overlapping with the conductive layer 112G, and a region overlapping with the conductive layer 112B. Here, an example is shown in which a resist mask is not provided in a region overlapping with the conductive layer 112p.

[0442] Next, the conductive film 129af is processed using the resist mask 195f as a mask to form a conductive layer 129aR, a conductive layer 129aG, and a conductive layer 129aB. The conductive film 129af can be processed by wet etching or dry etching, or both.

[0443] Subsequently, the resist mask 195f is removed.

[0444] Next, a conductive film 129bf that will become conductive layer 129R, conductive layer 129G, and part of conductive layer 129B, as well as conductive layer 129p, is formed so as to cover insulating layer 239, conductive layer 112R, conductive layer 112G, conductive layer 112B, conductive layer 112p, conductive layer 126R, conductive layer 126G, conductive layer 126B, conductive layer 129aR, conductive layer 129aG, conductive layer 129aB, and conductive layer 126p.

[0445] Next, a resist mask 195g is formed over the conductive film 129bf (FIG. 30B). The resist mask 195g may be a positive resist or a negative resist. The resist mask 195g is provided in a region overlapping with the conductive layer 112R, the conductive layer 112G, the conductive layer 112B, and the conductive layer 112p.

[0446] Next, the conductive film 129bf is processed using the resist mask 195g as a mask to form a conductive layer 129bR, a conductive layer 129bG, a conductive layer 129bB, and a conductive layer 129p. The conductive film 129bf can be processed by wet etching or dry etching, or both.

[0447] Subsequently, the resist mask 195g is removed (FIG. 31A).

[0448] This makes it possible to form a conductive layer 129R having a stacked structure of conductive layers 129aR and 129bR, a conductive layer 129G having a stacked structure of conductive layers 129aG and 129bG, and a conductive layer 129B having a stacked structure of conductive layers 129aB and 129bB. Furthermore, the film thickness of the conductive layer 129p can be made thinner than the film thicknesses of the conductive layers 129R, 129G, and 129B. These conductive films can be formed by, for example, sputtering or vacuum deposition.

[0449] Next, it is preferable to perform a hydrophobic treatment on the pixel electrodes. The hydrophobic treatment can change the surface of the treatment target from hydrophilic to hydrophobic, or can increase the hydrophobicity of the surface of the treatment target. By performing the hydrophobic treatment on the pixel electrodes, the adhesion between the pixel electrodes and the film (here, the film 113Rf) formed in a later process can be increased, and film peeling can be suppressed. Note that the hydrophobic treatment does not have to be performed.

[0450] The hydrophobic treatment can be performed by, for example, fluorine modification of the pixel electrodes. The fluorine modification can be performed by, for example, treatment with a fluorine-containing gas, heat treatment, plasma treatment in a fluorine-containing gas atmosphere, or the like. As the fluorine-containing gas, for example, fluorine gas can be used, and for example, fluorocarbon gas can be used. As the fluorocarbon gas, for example, carbon tetrafluoride (CF ４ ) Gas, C ４ F ６ Gas, C ２ F ６ Gas, C ４ F ８ Gas, C ５ F ８ As a gas containing fluorine, for example, SF ６ Gas, NF ３ Gas, CHF ３ Gases such as helium gas, argon gas, or hydrogen gas can be added to these gases as appropriate.

[0451] The surface of the pixel electrode can be hydrophobized by performing a plasma treatment on the surface of the pixel electrode in a gas atmosphere containing a Group 18 element such as argon, followed by a treatment using a silylating agent. Examples of the silylating agent that can be used include hexamethyldisilazane (HMDS) and trimethylsilylimidazole (TMSI). Furthermore, the surface of the pixel electrode can also be hydrophobized by performing a plasma treatment on the surface of the pixel electrode in a gas atmosphere containing a Group 18 element such as argon, followed by a treatment using a silane coupling agent.

[0452] By performing plasma treatment on the surface of the pixel electrode in a gas atmosphere containing a Group 18 element such as argon, it is possible to damage the surface of the pixel electrode. This makes it easier for methyl groups contained in a silylating agent such as HMDS to bond to the surface of the pixel electrode. Also, silane coupling by a silane coupling agent is more likely to occur. As described above, by performing plasma treatment on the surface of the pixel electrode in a gas atmosphere containing a Group 18 element such as argon, and then performing treatment using a silylating agent or a silane coupling agent, it is possible to hydrophobize the surface of the pixel electrode.

[0453] Treatment using a silylating agent or a silane coupling agent can be performed by applying the silylating agent or the silane coupling agent using, for example, a spin coating method or a dipping method. Treatment using a silylating agent or a silane coupling agent can also be performed by, for example, using a vapor phase method to form a film containing a silylating agent or a film containing a silane coupling agent on a pixel electrode or the like. In the vapor phase method, first, a material containing a silylating agent or a material containing a silane coupling agent is volatilized to incorporate the silylating agent or the silane coupling agent into an atmosphere. Next, a substrate on which a pixel electrode or the like is formed is placed in this atmosphere. This allows a film containing the silylating agent or the silane coupling agent to be formed on the pixel electrode, thereby hydrophobizing the surface of the pixel electrode.

[0454] Next, the layer 113R, the layer 113G, and the layer 113B are formed. Here, a method of forming the layer 113R, the layer 113G, and the layer 113B in this order is described, but one embodiment of the present invention is not limited to this. For example, the layers 113R, 113G, and 113B can be formed in order of increasing heat resistance of the materials contained therein. The layer formed first preferably has high heat resistance because it also undergoes steps in which other layers are formed. By forming the layer containing a material with low heat resistance last, damage during the process can be reduced.

[0455] A film 113Rf that will become the layer 113R is formed on the pixel electrode 111 (FIG. 31B).

[0456] 31B , in the cross-sectional view taken along the dashed dotted line Y1-Y2, the film 113Rf is not formed on the conductive layer 123. For example, by using an area mask, the film 113Rf can be formed only in a desired region. By employing a film formation process using an area mask and a processing process using a resist mask, a light-emitting device can be fabricated through a relatively simple process.

[0457] As described in Embodiment 1, in the display device of one embodiment of the present invention, a material with high heat resistance is used for the light-emitting device. Specifically, the heat resistance temperature of each compound contained in the film 113Rf is preferably 100° C. or higher and 180° C. or lower, preferably 120° C. or higher and 180° C. or lower, and more preferably 140° C. or higher and 180° C. or lower. This can improve the reliability of the light-emitting device. Furthermore, the upper limit of the temperature that can be applied in the manufacturing process of the display device can be increased. Therefore, the range of choices for materials and formation methods used in the display device can be expanded, and the manufacturing yield and reliability can be improved.

[0458] The film 113Rf can be formed by, for example, a vapor deposition method, specifically a vacuum deposition method. Alternatively, the film 113Rf may be formed by a transfer method, a printing method, an inkjet method, a coating method, or the like.

[0459] Subsequently, a mask film 118Rf to become the mask layer 118R and a mask film 119Rf to become the mask layer 119R are formed in this order on the film 113Rf and the conductive layer 123 (FIG. 31B).

[0460] In this embodiment, an example is shown in which the mask film is formed with a two-layer structure of mask film 118Rf and mask film 119Rf, but the mask film may be a single-layer structure of mask film 118Rf or mask film 119Rf, or may be a laminated structure of three or more layers.

[0461] By providing a mask layer on the film 113Rf, damage to the film 113Rf during the manufacturing process of the display device can be reduced, and the reliability of the light-emitting device can be improved.

[0462] The mask film 118Rf is made of a film that is highly resistant to the processing conditions of the film 113Rf, specifically, a film that has a large etching selectivity with respect to the film 113Rf.The mask film 119Rf is made of a film that has a large etching selectivity with respect to the mask film 118Rf.

[0463] The mask films 118Rf and 119Rf are formed at a temperature lower than the heat-resistant temperature of the film 113Rf. The substrate temperature when forming the mask films 118Rf and 119Rf is preferably 200° C. or lower, more preferably 150° C. or lower, even more preferably 120° C. or lower, still more preferably 100° C. or lower, and even more preferably 80° C. or lower.

[0464] Examples of the heat resistance temperature index include a glass transition point, a softening point, a melting point, a thermal decomposition temperature, a 5% weight loss temperature, etc. The heat resistance temperatures of the layers 113R, 113G, and 113B can be any of these indicative temperatures, preferably the lowest temperature among them.

[0465] As described above, in the display device of one embodiment of the present invention, a material with high heat resistance is used for the light-emitting device. Therefore, the substrate temperature during the formation of the mask film can be set to 100° C. or higher, 120° C. or higher, or 140° C. or higher. For example, the inorganic insulating film can be made denser and have a higher barrier property as the film formation temperature increases. Therefore, by forming the mask film at such a temperature, damage to the film 113Rf can be further reduced, and the reliability of the light-emitting device can be improved.

[0466] It is preferable to use a film that can be removed by wet etching for the mask film 118Rf and the mask film 119Rf. By using the wet etching method, damage to the film 113Rf during processing of the mask film 118Rf and the mask film 119Rf can be reduced compared to when using the dry etching method.

[0467] The mask films 118Rf and 119Rf can be formed by, for example, sputtering, ALD (thermal ALD, PEALD), CVD, or vacuum deposition. Alternatively, they may be formed by the wet film formation method described above.

[0468] The mask film 118Rf formed on and in contact with the film 113Rf is preferably formed using a formation method that causes less damage to the film 113Rf than the mask film 119Rf. For example, it is preferable to form the mask film 118Rf using the ALD method or the vacuum deposition method rather than the sputtering method.

[0469] The mask film 118Rf and the mask film 119Rf may each be made of one or more of a metal film, an alloy film, a metal oxide film, a semiconductor film, an organic insulating film, an inorganic insulating film, or the like.

[0470] The mask films 118Rf and 119Rf can each be made of a metal material such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, titanium, aluminum, yttrium, zirconium, or tantalum, or an alloy material containing such a metal material. It is particularly preferable to use a low-melting-point material such as aluminum or silver. Using a metal material capable of blocking ultraviolet rays for one or both of the mask films 118Rf and 119Rf is preferable because it can prevent ultraviolet rays from being irradiated onto the film 113Rf and suppress deterioration of the film 113Rf.

[0471] Using a metal film or an alloy film for one or both of the mask films 118Rf and 119Rf is preferable because it is possible to prevent plasma damage to the film 113Rf and to prevent deterioration of the film 113Rf. Specifically, it is possible to prevent plasma damage to the film 113Rf in processes using a dry etching method and ashing processes. In particular, it is preferable to use a metal film or an alloy film such as a tungsten film as the mask film 119Rf.

[0472] The mask film 118Rf and the mask film 119Rf may each be made of a metal oxide such as In—Ga—Zn oxide, indium oxide, In—Zn oxide, In—Sn oxide, indium titanium oxide (In—Ti oxide), indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide), or indium tin oxide containing silicon.

[0473] Instead of the gallium, an element M (wherein M is one or more elements selected from aluminum, silicon, boron, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) may be used. In particular, it is preferable that M is one or more elements selected from gallium, aluminum, and yttrium.

[0474] As the mask film, a film containing a material having light-shielding properties, particularly against ultraviolet light, can be used. For example, a film having ultraviolet light-reflecting properties or a film absorbing ultraviolet light can be used. As the light-shielding material, various materials such as metals, insulators, semiconductors, and semimetals having light-shielding properties against ultraviolet light can be used. However, since part or all of the mask film will be removed in a later process, it is preferable that the mask film be a film that can be processed by etching, and particularly preferable that the processability is good.

[0475] For example, semiconductor materials such as silicon or germanium can be used as materials that are highly compatible with semiconductor manufacturing processes. Alternatively, oxides or nitrides of the above semiconductor materials can be used. Alternatively, non-metallic materials such as carbon or compounds thereof can be used. Alternatively, metals such as titanium, tantalum, tungsten, chromium, and aluminum, or alloys containing one or more of these, can be used. Alternatively, oxides containing the above metals, such as titanium oxide or chromium oxide, or nitrides such as titanium nitride, chromium nitride, or tantalum nitride can be used.

[0476] By using a film containing a material having ultraviolet light blocking properties as the mask film, it is possible to prevent the EL layer from being exposed to ultraviolet light during the exposure process, etc. By preventing the EL layer from being damaged by ultraviolet light, the reliability of the light-emitting device can be improved.

[0477] The same effect can be achieved when a film containing a material that blocks ultraviolet light is used as the material for the insulating film 125f described later.

[0478] The mask films 118Rf and 119Rf can each be made of various inorganic insulating films that can be used for the protective layer 131. In particular, oxide insulating films are preferable because they have higher adhesion to the film 113Rf than nitride insulating films. For example, inorganic insulating materials such as aluminum oxide, hafnium oxide, and silicon oxide can each be used for the mask films 118Rf and 119Rf. For example, aluminum oxide films can be formed as the mask films 118Rf and 119Rf using the ALD method. Using the ALD method is preferable because it can reduce damage to the underlying layer (especially the EL layer).

[0479] For example, the mask film 118Rf can be an inorganic insulating film (e.g., an aluminum oxide film) formed using the ALD method, and the mask film 119Rf can be an inorganic film (e.g., an In-Ga-Zn oxide film, a silicon film, or a tungsten film) formed using the sputtering method.

[0480] The same inorganic insulating film can be used for both the mask film 118Rf and the insulating layer 125 to be formed later. For example, an aluminum oxide film formed using an ALD method can be used for both the mask film 118Rf and the insulating layer 125. The mask film 118Rf and the insulating layer 125 may be formed under the same or different film-forming conditions. For example, by forming the mask film 118Rf under the same conditions as the insulating layer 125, the mask film 118Rf can be an insulating layer with high barrier properties against at least one of water and oxygen. On the other hand, since the mask film 118Rf is a layer that will be largely or completely removed in a later process, it is preferable that it be easily processed. Therefore, it is preferable that the mask film 118Rf be formed under conditions where the substrate temperature during film formation is lower than that of the insulating layer 125.

[0481] An organic material may be used for one or both of the mask films 118Rf and 119Rf. For example, the organic material may be a material that is soluble in a solvent that is chemically stable with respect to at least the film located at the top of the film 113Rf. In particular, a material that dissolves in water or alcohol is preferably used. When forming a film of such a material, it is preferable to apply the material dissolved in a solvent such as water or alcohol by a wet film formation method, and then perform a heat treatment to evaporate the solvent. In this case, performing the heat treatment under a reduced pressure atmosphere is preferable because it allows the solvent to be removed at a low temperature and in a short time, thereby reducing thermal damage to the film 113Rf.

[0482] The mask film 118Rf and the mask film 119Rf may each be made of an organic resin such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, alcohol-soluble polyamide resin, or a fluororesin such as a perfluoropolymer.

[0483] For example, the mask film 118Rf may be an organic film (e.g., a PVA film) formed using either a vapor deposition method or the above-mentioned wet film formation method, and the mask film 119Rf may be an inorganic film (e.g., a silicon nitride film) formed using a sputtering method.

[0484] As described in Embodiment 1, in the display device of one embodiment of the present invention, part of the mask film may remain as a mask layer.

[0485] Subsequently, a resist mask 190a is formed on the mask film 119Rf (FIG. 31B). Either a positive resist or a negative resist may be used as the resist mask 190a.

[0486] The resist mask 190a is provided in a position overlapping with the pixel electrode 111R. The resist mask 190a is preferably provided also in a position overlapping with the conductive layer 123. This can prevent the conductive layer 123 from being damaged during the manufacturing process of the display device. Note that the resist mask 190a does not necessarily have to be provided on the conductive layer 123.

[0487] Next, using the resist mask 190a as a mask, a portion of the mask film 119Rf is removed to form a mask layer 119R (FIG. 32A). The mask layer 119R remains on the pixel electrode 111R and on the conductive layer 123. Thereafter, the resist mask 190a is removed (FIG. 32B). Next, using the mask layer 119R as a mask (also referred to as a hard mask), a portion of the mask film 118Rf is removed to form a mask layer 118R.

[0488] The mask films 118Rf and 119Rf can be processed by wet etching or dry etching, respectively, and are preferably processed by anisotropic etching.

[0489] By using the wet etching method, damage to the film 113Rf during processing of the mask films 118Rf and 119Rf can be reduced compared to when using the dry etching method. When using the wet etching method, it is preferable to use, for example, a developer, a tetramethylammonium hydroxide (TMAH) aqueous solution, dilute hydrofluoric acid, oxalic acid, phosphoric acid, acetic acid, nitric acid, or a mixed solution containing two or more of these.

[0490] In processing the mask film 119Rf, the film 113Rf is not exposed, and therefore the range of processing methods to be selected is wider than in processing the mask film 118Rf. Specifically, even when a gas containing oxygen is used as an etching gas in processing the mask film 119Rf, deterioration of the film 113Rf can be further suppressed.

[0491] When dry etching is used to process the mask film 118Rf, deterioration of the film 113Rf can be suppressed by not using a gas containing oxygen as the etching gas. ４ , C ４ F ８ , S.F. ６ , CHF ３ , Cl ２ , H ２ O, BCl ３ It is preferable to use a gas containing a noble gas such as He as the etching gas.

[0492] For example, when an aluminum oxide film formed by the ALD method is used as the mask film 118Rf, CHF ３ and He or CHF ３ and He and CH ４ The mask film 118Rf can be processed by dry etching using a diluted phosphoric acid. When an In—Ga—Zn oxide film formed by sputtering is used as the mask film 119Rf, the mask film 119Rf can be processed by wet etching using a diluted phosphoric acid. ４The mask film 119Rf may be processed by dry etching using diluted phosphoric acid and Ar. Alternatively, the mask film 119Rf may be processed by wet etching using diluted phosphoric acid. When a tungsten film formed by sputtering is used as the mask film 119Rf, SF ６ , C.F. ４ and O ２ , or CF ４ and Cl ２ and O ２ The mask film 119Rf can be processed by dry etching using the above.

[0493] The resist mask 190a can be removed by, for example, ashing using oxygen plasma. Alternatively, ashing using oxygen gas and CF ４ , C ４ F ８ , SF ６ , CHF ３ , Cl ２ , H ２ O, BCl ３ Alternatively, a noble gas such as He may be used. Alternatively, the resist mask 190a may be removed by wet etching. At this time, the mask film 118Rf is located on the outermost surface and the film 113Rf is not exposed, so that damage to the film 113Rf can be suppressed in the process of removing the resist mask 190a. This also broadens the range of options for removing the resist mask 190a.

[0494] Subsequently, the film 113Rf is processed to form a layer 113R. For example, the mask layer 119R and the mask layer 118R are used as hard masks to remove a portion of the film 113Rf, thereby forming the layer 113R (FIG. 33A).

[0495] 33A, a laminated structure of the layer 113R, the mask layer 118R, and the mask layer 119R remains on the pixel electrode 111R, and the pixel electrode 111G and the pixel electrode 111G are exposed.

[0496] When processing the film 113Rf, the surfaces of the pixel electrodes 111G and 111B are exposed to etching gas or etching solution. On the other hand, the surface of the pixel electrode 111R is not exposed to etching gas or etching solution. In this way, in the light-emitting device of the color to be formed first, the surface of the pixel electrode is not damaged by the etching process, and the state of the interface between the pixel electrode and the EL layer can be maintained in good condition.

[0497] The film 113Rf is preferably processed by anisotropic etching, particularly anisotropic dry etching, or wet etching may be used.

[0498] When processing the film 113Rf by dry etching, the exposed surface is exposed to plasma. Using a metal film or an alloy film for one or both of the mask layers 118R and 119R is preferable because it can prevent damage caused by plasma to the region of the film 113Rf that will become the layer 113R, thereby preventing deterioration of the layer 113R. It is particularly preferable to use a metal film or an alloy film, such as a tungsten film, as the mask layer 119R.

[0499] When dry etching is used, deterioration of the film 113Rf can be suppressed by not using a gas containing oxygen as the etching gas.

[0500] A gas containing oxygen may be used as the etching gas. When the etching gas contains oxygen, the etching rate can be increased. Therefore, etching can be performed under low power conditions while maintaining a sufficiently high etching rate. This makes it possible to suppress damage to the film 113Rf. Furthermore, it is possible to suppress problems such as adhesion of reaction products that occur during etching.

[0501] When dry etching is used, for example, H ２ , C.F. ４ , C ４ F ８ , SF ６ , CHF ３ , Cl ２ , H ２ O, BCl ３It is preferable to use a gas containing one or more of the noble gases such as He and Ar as the etching gas. Alternatively, it is preferable to use a gas containing one or more of these and oxygen as the etching gas. Alternatively, oxygen gas may be used as the etching gas. Specifically, for example, H ２ and a gas containing Ar, or CF ４ A gas containing CF and He can be used as an etching gas. ４ A gas containing H, He, and oxygen can be used as the etching gas. ２ A gas containing Ar and a gas containing oxygen can be used as the etching gas.

[0502] The dry etching apparatus may be a dry etching apparatus having a high-density plasma source. Examples of the dry etching apparatus having a high-density plasma source include an inductively coupled plasma (ICP) etching apparatus. Alternatively, a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes may be used. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes.

[0503] 33A shows an example in which the edge of the layer 113R is positioned outside the edge of the pixel electrode 111R. This configuration can increase the aperture ratio of the pixel. Furthermore, the insulating layer 239 can function as an etching protection film when forming the layer 113, the mask layer 118, and the mask layer 119. By providing the insulating layer 239 on the insulating layer 235, it is possible to prevent a portion of the insulating layer 235 from being removed when forming the layer 113, the mask layer 118, and the mask layer 119.

[0504] Because the layer 113R covers the top and side surfaces of the pixel electrode 111R, subsequent processes can be performed without exposing the pixel electrode 111R. If the edges of the pixel electrode 111R are exposed, corrosion may occur during etching processes, etc. Products resulting from corrosion of the pixel electrode 111R may be unstable. For example, in wet etching, they may dissolve in the solution, and in dry etching, they may disperse into the atmosphere. If the products dissolve in the solution or disperse into the atmosphere, they may adhere to the processed surface and the side surfaces of the layer 113B, adversely affecting the characteristics of the light-emitting device or forming leak paths between multiple light-emitting devices. Furthermore, in areas where the edges of the pixel electrode 111R are exposed, the adhesion between adjacent layers may be reduced, potentially making the layer 113R or the pixel electrode 111R more susceptible to peeling.

[0505] Therefore, by configuring the layer 113R to cover the upper and side surfaces of the pixel electrode 111R, it is possible to improve, for example, the yield and characteristics of the light-emitting device.

[0506] By covering the upper and side surfaces of the pixel electrode 111R with the layer 113R, a dummy region is provided in the layer 113R outside the light-emitting region (the region located between the pixel electrode 111R and the common electrode 115). Here, the edge of the layer 113R may be damaged during processing of the film 113Rf. Furthermore, the edge of the layer 113R may also be damaged by exposure to plasma in a later process. Because the edge of the layer 113R and its vicinity serve as a dummy region and are not used for light emission, even if damage occurs, it is unlikely to adversely affect the characteristics of the light-emitting device. Meanwhile, because the light-emitting region of the layer 113R is covered with the mask layer, it is not exposed to plasma and plasma damage is sufficiently reduced. It is preferable that the mask layer be provided so as to cover not only the upper surface of the flat portion of the layer 113R that overlaps the upper surface of the pixel electrode 111R, but also the upper surfaces of the inclined and flat portions located outside the upper surface of the pixel electrode 111R. In this way, the portion of the layer 113R that is less susceptible to damage during the manufacturing process is used as the light-emitting region, so that a light-emitting device with high luminous efficiency and long life can be realized.

[0507] In the region corresponding to the connection portion 140, the laminated structure of the mask layer 118R and the mask layer 119R remains on the conductive layer 123.

[0508] As described above, in one embodiment of the present invention, the resist mask 190a is formed over the mask film 119Rf, and part of the mask film 119Rf is removed using the resist mask 190a to form the mask layer 119R. Then, part of the film 113Rf is removed using the mask layer 119R as a hard mask to form the layer 113R. Therefore, it can be said that the layer 113R is formed by processing the film 113Rf using photolithography. Note that part of the film 113Rf may be removed using the resist mask 190a. Then, the resist mask 190a may be removed.

[0509] Next, it is preferable to perform a hydrophobic treatment on the pixel electrode. When processing the film 113Rf, the surface state of the pixel electrode may change to a hydrophilic state. By performing a hydrophobic treatment on the pixel electrode, it is possible to improve the adhesion between the pixel electrode and a film (here, the film 113Gf) formed in a later process and suppress film peeling. Note that the hydrophobic treatment is not necessarily required.

[0510] Subsequently, a film 113Gf that will become the layer 113G is formed on the pixel electrodes 111G and 111B and on the mask layer 119R (FIG. 33B).

[0511] The film 113Gf can be formed by a method similar to that used to form the film 113Rf.

[0512] Next, a mask film 118Gf that will become the mask layer 118G and a mask film 119Gf that will later become the mask layer 119G are formed in this order on the film 113Gf, and then a resist mask 190b is formed (FIG. 15C). The materials and formation methods of the mask films 118Gf and 119Gf are the same as those applicable to the mask films 118Rf and 119Rf. The materials and formation methods of the resist mask 190b are the same as those applicable to the resist mask 190a.

[0513] The resist mask 190b is provided at a position overlapping the pixel electrode 111G.

[0514] Next, a resist mask 190b is used to remove a portion of the mask film 119Gf to form a mask layer 119G. The mask layer 119G remains on the pixel electrode 111G. Then, the resist mask 190b is removed. Next, using the mask layer 119G as a mask, a portion of the mask film 118Gf is removed to form a mask layer 118G. Next, the film 113Gf is processed to form a layer 113G. For example, using the mask layer 119G and the mask layer 118G as a hard mask, a portion of the film 113Gf is removed to form the layer 113G ( FIG. 34A ).

[0515] Here, when processing the film 113Gf, the surface of the pixel electrode 111B is exposed to etching gas or etching solution, etc. Meanwhile, the surfaces of the pixel electrodes 111R and 111G are not exposed to etching gas or etching solution, etc. In other words, in the light-emitting device of the second color to be formed, the surface of the pixel electrode is exposed in one etching process, and in the light-emitting device of the third color to be formed, the surface of the pixel electrode is exposed in two etching processes. Therefore, it is preferable to form the island-shaped EL layer earlier for light-emitting devices whose characteristics are more likely to be affected by the surface condition of the pixel electrode. This allows for improved characteristics of the light-emitting devices of each color.

[0516] 17A, a laminated structure of the layer 113G, the mask layer 118G, and the mask layer 119G remains on the pixel electrode 111G, and the mask layer 119R and the pixel electrode 111B are exposed.

[0517] Next, it is preferable to perform a hydrophobic treatment on the pixel electrode. During processing of the film 113Gf, the surface state of the pixel electrode may change to a hydrophilic state. By performing a hydrophobic treatment on the pixel electrode, it is possible to improve the adhesion between the pixel electrode and a film (here, the film 113Bf) formed in a later process, and to suppress film peeling. However, the hydrophobic treatment is not necessarily required.

[0518] Subsequently, a film 113Bf that will become the layer 113B is formed on the pixel electrode 111B, the mask layer 119R, and the mask layer 119G (FIG. 34B).

[0519] The film 113Bf can be formed by a method similar to that used to form the film 113Rf.

[0520] Next, a mask film 118Bf that will become the mask layer 118B and a mask film 119Bf that will become the mask layer 119B are formed in this order on the film 113Bf, and then a resist mask 190c is formed (FIG. 34B). The materials and formation methods of the mask films 118Bf and 119Bf are the same as those applicable to the mask films 118Rf and 119Rf. The materials and formation methods of the resist mask 190c are the same as those applicable to the resist mask 190a.

[0521] The resist mask 190c is provided at a position overlapping the pixel electrode 111B.

[0522] Next, using the resist mask 190c as a mask, a portion of the mask film 119Bf is removed to form a mask layer 119B. The mask layer 119B remains on the pixel electrode 111B. Then, the resist mask 190c is removed. Next, using the mask layer 119B as a mask, a portion of the mask film 118Bf is removed to form a mask layer 118B. Next, the film 113Bf is processed to form a layer 113B. For example, using the mask layer 119B and the mask layer 118B as a hard mask, a portion of the film 113Bf is removed to form a layer 113B ( FIG. 35A ).

[0523] 35A, a laminated structure of the layer 113B, the mask layer 118B, and the mask layer 119B remains on the pixel electrode 111B, and the mask layers 119R and 119G are exposed.

[0524] The side surfaces of the layers 113R, 113G, and 113B are preferably perpendicular or substantially perpendicular to the surface on which they are to be formed. For example, the angle between the surface on which they are to be formed and these side surfaces is preferably 60 degrees or more and 90 degrees or less.

[0525] As described above, the distance between any two adjacent layers of the layer 113R, the layer 113G, and the layer 113B formed by photolithography can be narrowed to 8 μm or less, 5 μm or less, 3 μm or less, 2 μm or less, or 1 μm or less. Here, the distance can be defined, for example, as the distance between the opposing ends of any two adjacent layers of the layer 113B, the layer 113G, and the layer 113R. By narrowing the distance between the island-shaped EL layers in this way, a display device with high definition and a large aperture ratio can be provided.

[0526] Subsequently, the mask layers 119B, 119G, and 119R may be removed. For example, when the mask layers 119R, 119G, and 119B contain a material that blocks ultraviolet light, it is preferable to leave them instead of removing them, because this can protect the island-shaped EL layer from ultraviolet light.

[0527] When removing the mask layer, the same method as in the mask layer processing step can be used. In particular, by using a wet etching method, damage to the layers 113R, 113G, and 113B when removing the mask layer can be reduced compared to when using a dry etching method.

[0528] By using a metal film or an alloy film for the mask layers 119R, 119G, and 119B, damage to the EL layer caused by plasma can be suppressed. Therefore, a dry etching method can be used in the manufacturing process of the light-emitting device. When removing the mask layers 119R, 119G, and 119B, the film that suppresses damage to the EL layer caused by plasma disappears as the mask layers 119R, 119G, and 119B are removed and in each process after the removal, so it is preferable to process the film by a method that does not use plasma, such as a wet etching method.

[0529] The mask layer may be removed by dissolving it in a solvent such as water or alcohol, including ethyl alcohol, methyl alcohol, isopropyl alcohol (IPA), or glycerin.

[0530] After removing the mask layers, drying treatment may be performed to remove water contained in the layers 113R, 113G, and 113B and water adsorbed on the surfaces of the layers 113R, 113G, and 113B. For example, heat treatment can be performed in an inert gas atmosphere such as a nitrogen atmosphere or a reduced-pressure atmosphere. The heat treatment can be performed at a substrate temperature of 50° C. or higher and 200° C. or lower, preferably 60° C. or higher and 150° C. or lower, and more preferably 70° C. or higher and 120° C. or lower. A reduced-pressure atmosphere is preferable because drying can be performed at a lower temperature.

[0531] Next, an insulating film 125f that will become the insulating layer 125 is formed to cover the insulating layer 239, the layer 113R, the layer 113G, the layer 113B, the mask layer 118R, the mask layer 118G, the mask layer 118B, the mask layer 119R, the mask layer 119G, the mask layer 119B, and the conductive layer 123 (Figure 35B).

[0532] Thereafter, an insulating film 127f that will become the insulating layer 127 is formed in contact with the upper surface of the insulating film 125f. Therefore, it is preferable that the upper surface of the insulating film 125f has high adhesion to the resin composition (e.g., a photosensitive resin composition containing an acrylic resin) used for the insulating film 127f. To improve adhesion, it is preferable to hydrophobize (or increase the hydrophobicity of) the upper surface of the insulating film 125f by performing a surface treatment. For example, it is preferable to perform the treatment using a silylating agent such as hexamethyldisilazane (HMDS). By hydrophobizing the upper surface of the insulating film 125f in this manner, the insulating film 127f that will become the insulating layer 127 can be formed with good adhesion. The surface treatment may also be the hydrophobization treatment described above.

[0533] Subsequently, an insulating film 127f that will become the insulating layer 127 is formed on the insulating film 125f (FIG. 36).

[0534] The insulating films 125f and 127f are preferably formed by a formation method that causes less damage to the layers 113R, 113G, and 113B. In particular, since the insulating film 125f is formed in contact with the side surfaces of the layers 113R, 113G, and 113B, it is preferably formed by a formation method that causes less damage to the layers 113R, 113G, and 113B than the insulating film 127f.

[0535] The insulating films 125f and 127f are formed at a temperature lower than the heat-resistant temperatures of the layer 113R, the layer 113G, and the layer 113B, respectively. By increasing the substrate temperature during film formation, the insulating film 125f can have a low impurity concentration and a high barrier property against at least one of water and oxygen, even if it is thin.

[0536] The substrate temperature when forming the insulating films 125f and 127f is preferably 60°C or higher, 80°C or higher, 100°C or higher, or 120°C or higher, and 200°C or lower, 180°C or lower, 160°C or lower, 150°C or lower, or 140°C or lower.

[0537] As described above, in the display device of one embodiment of the present invention, a material with high heat resistance is used for the light-emitting device. Therefore, the substrate temperatures during the formation of the insulating films 125f and 127f can be set to 100° C. or higher, 120° C. or higher, or 140° C. or higher, respectively. For example, the higher the deposition temperature of an inorganic insulating film, the denser the film can be and the higher the barrier property can be. Therefore, by depositing the insulating film 125f at such a temperature, damage to the layers 113B, 113G, and 113R can be further reduced, and the reliability of the light-emitting device can be improved.

[0538] The insulating film 125f is preferably formed to a thickness of 3 nm or more, 5 nm or more, or 10 nm or more, and 200 nm or less, 150 nm or less, 100 nm or less, or 50 nm or less, within the above substrate temperature range.

[0539] The insulating film 125f is preferably formed by, for example, an ALD method. The ALD method is preferable because it can reduce film formation damage and form a film with high coverage. The insulating film 125f is preferably formed as an aluminum oxide film by, for example, an ALD method.

[0540] Alternatively, the insulating film 125f may be formed by a sputtering method, a CVD method, or a PECVD method, which have a faster film formation rate than an ALD method. This enables a highly reliable display device to be manufactured with high productivity.

[0541] The insulating film 127f is preferably formed by the wet film formation method described above. The insulating film 127f is preferably formed by, for example, spin coating using a photosensitive resin, more specifically, using a photosensitive resin composition containing an acrylic resin.

[0542] After the insulating film 127f is formed, heat treatment (also referred to as pre-baking) is preferably performed. The heat treatment is performed at a temperature lower than the upper temperature limit of the layers 113R, 113G, and 113B. The substrate temperature during the heat treatment is preferably 50° C. to 200° C., more preferably 60° C. to 150° C., and still more preferably 70° C. to 120° C. This allows the solvent contained in the insulating film 127f to be removed.

[0543] 36 schematically shows how a photosensitive organic material is used for the insulating film 127f, and how the region overlapping with the pixel electrode 111R, the region overlapping with the pixel electrode 111G, the region overlapping with the pixel electrode 111B, and the region overlapping with the conductive layer 123 are exposed to light. In Fig. 36, arrows indicate light, and the region where the insulating layer 127 is not to be formed is exposed to light, while the region where the insulating layer 127 is to be formed is shielded from light using a mask 132d.

[0544] Here, by adjusting the exposure amount, it is possible to control the shape of the insulating layer 127. It is preferable to process the insulating layer 127 so that it has a portion overlapping with the top surface of the pixel electrode 111.

[0545] Subsequently, development is performed to remove the exposed areas of the insulating film 127f, thereby forming the insulating layer 127 ( FIG. 37A ). The insulating layer 127 is provided in the areas between adjacent pixel electrodes 111 and in the area surrounding the conductive layer 123. For example, when an acrylic resin is used for the insulating film 127f, it is preferable to use an alkaline solution as the developer, such as a tetramethylammonium hydroxide (TMAH) aqueous solution.

[0546] Although the insulating film 127f is formed of a positive photosensitive resin in this example, the present invention is not limited to this. For example, the insulating film 127f may be formed of a negative photosensitive resin.

[0547] After development, a step of removing residues (so-called scum) generated during development may be performed. For example, the residues can be removed by ashing using oxygen plasma. A step of removing residues may also be performed after each of the development steps described below.

[0548] Etching may be performed to adjust the height of the surface of the insulating layer 127. The insulating layer 127 may be processed by ashing using oxygen plasma, for example.

[0549] After development and before post-baking, the entire substrate may be exposed to visible light or ultraviolet light to irradiate the insulating layer 127. The energy density of the exposure is 0 mJ / cm. ２ Larger than 800 mJ / cm ２ It is preferable that the dose is 0 mJ / cm or less. ２ Greater than 500 mJ / cm ２ By performing such exposure after development, the transparency of the insulating layer 127 can be improved in some cases. Furthermore, the insulating layer 127 can be deformed into a tapered shape at a low temperature in some cases.

[0550] On the other hand, by not exposing the insulating layer 127 to light, it may be easier to change the shape of the insulating layer 127 or to deform the insulating layer 127 into a tapered shape in a later step. Therefore, it may be preferable not to expose the insulating layer 127 to light after development.

[0551] Subsequently, heat treatment (also referred to as post-baking) may be performed. The heat treatment can deform the side surfaces of the insulating layer 127. Specifically, the taper angle of the insulating layer 127 can be reduced. The heat treatment is performed at a temperature lower than the upper temperature limit of the EL layer. The heat treatment can be performed at a substrate temperature of 50° C. to 200° C., preferably 60° C. to 150° C., and more preferably 70° C. to 130° C. The heating atmosphere may be an air atmosphere or an inert gas atmosphere. The heating atmosphere may be an atmospheric pressure atmosphere or a reduced-pressure atmosphere. A reduced-pressure atmosphere is preferable because drying can be performed at a lower temperature. The heat treatment in this step is preferably performed at a higher substrate temperature than the heat treatment (pre-baking) performed after the formation of the insulating film 127f. This can improve adhesion between the insulating layer 127 and the insulating layer 125 and also improve the corrosion resistance of the insulating layer 127.

[0552] 6A and 6B, depending on the material of the insulating layer 127 and the temperature, time, and atmosphere of the post-baking, a concave curved shape may be formed on the side surface of the insulating layer 127. For example, the higher the temperature or the longer the post-baking time, the more likely the shape of the insulating layer 127 is to change, and a concave curved shape may be formed. Furthermore, as described above, if the developed insulating layer 127 is not exposed to light, the shape of the insulating layer 127 may be more likely to change during post-baking.

[0553] Next, using the insulating layer 127 as a mask, portions of the insulating film 125f, the mask layer 119R, the mask layer 119G, the mask layer 119B, the mask layer 118R, the mask layer 118G, and the mask layer 118B are removed, thereby forming the insulating layer 125, and openings are formed in the mask layers 119R, 119G, 119B, the mask layers 118R, 118G, and 118B, respectively, exposing portions of the top surfaces of the layers 113G, 113G, 113R, and the conductive layer 123 ( FIG. 37B ).

[0554] The insulating film 125f, the mask layer 119R, the mask layer 119G, the mask layer 119B, the mask layer 118R, the mask layer 118G, and the mask layer 118B may be processed by wet etching or dry etching, or both. Using wet etching can reduce damage to the layers 113B, 113G, and 113R compared to using dry etching. For example, an aqueous solution of tetramethylammonium hydroxide (TMAH), which is an alkaline solution, is preferably used for wet etching of an aluminum oxide film. For wet etching of an In—Ga—Zn oxide film, phosphoric acid or an etchant containing phosphoric acid is preferably used.

[0555] When dry etching is used, it is preferable to use a chlorine-based gas. ２ , BCl ３ , SiCl ４ , and CCl ４ These can be used alone or in combination of two or more gases. The chlorine-based gas can also be mixed with one or more gases such as oxygen gas, hydrogen gas, helium gas, and argon gas.

[0556] When dry etching is used, by-products generated by the dry etching may be deposited on the upper surface and side surfaces of insulating layer 127. Therefore, insulating layer 127 may contain components contained in the etching gas, components contained in insulating film 125f, and components contained in mask layers 118R, 118G, 118B, 119R, 119G, and 119B.

[0557] As described above, by providing the insulating layer 127, the insulating layer 125, the mask layer 118R, the mask layer 118G, the mask layer 118B, the mask layer 119R, the mask layer 119G, and the mask layer 119B, it is possible to prevent poor connection between the light-emitting devices due to disconnection of the common layer 114 and the common electrode 115 and an increase in electrical resistance due to a locally thin portion of the film thickness. As a result, the display device of one embodiment of the present invention can have improved display quality.

[0558] After exposing portions of the layers 113B, 113G, and 113R, further heat treatment may be performed. This heat treatment can remove water contained in the EL layer and water adsorbed to the surface of the EL layer. Furthermore, this heat treatment may change the shape of the insulating layer 127. Specifically, the insulating layer 127 may expand to cover at least one of the ends of the insulating layer 125, the mask layer 118R, the mask layer 118G, the mask layer 118B, the mask layer 119R, the mask layer 119G, and the mask layer 119B (see FIG. 6B). Furthermore, the insulating layer 127 may expand to cover at least one of the top surfaces of the layers 113R, 113G, and 113B (see FIGS. 6B to 8B). For example, heat treatment can be performed in an inert gas atmosphere or a reduced-pressure atmosphere. The heat treatment can be performed at a substrate temperature of 50°C or higher and 200°C or lower, preferably 60°C or higher and 150°C or lower, and more preferably 70°C or higher and 120°C or lower. A reduced pressure atmosphere is preferred because it allows dehydration at a lower temperature. However, it is preferable to appropriately set the temperature range for the heat treatment, taking into consideration the heat resistance temperature of the EL layer. Note that, when taking into consideration the heat resistance temperature of the EL layer, a temperature of 70°C or higher and 120°C or lower is particularly suitable within the above temperature range.

[0559] Here, if the insulating layer 125 and the mask layer are etched together after post-baking, side etching may cause the insulating layer 125 and the mask layer below the edge of the insulating layer 127 to disappear, forming a cavity. Such a cavity may cause unevenness on the surface on which the common layer 114 and the common electrode 115 are formed, making it more likely that discontinuities will occur in the common layer 114 and the common electrode 115. Therefore, it is preferable to perform the etching of the insulating layer 125 and the mask layer separately, before and after post-baking.

[0560] Subsequently, the common layer 114, the common electrode 115, and the protective layer 131 are formed on the insulating layer 127, the layer 113R, the layer 113G, and the layer 113B (FIG. 38).

[0561] The common layer 114 can be formed by a method such as a vapor deposition method (including a vacuum deposition method), a transfer method, a printing method, an inkjet method, or a coating method.

[0562] For example, sputtering or vacuum deposition can be used to form the common electrode 115. Alternatively, a film formed by deposition and a film formed by sputtering may be stacked.

[0563] The protective layer 131 can be formed by vacuum deposition, sputtering, CVD, ALD, or the like.

[0564] Next, a substrate 120 is prepared, and a light-shielding layer 117 is formed on the substrate 120. Next, the substrate 120 and the light-shielding layer 117 are bonded to a protective layer 131 using a resin layer 122, thereby manufacturing a display device (FIG. 16).

[0565] By providing the insulating layer 214 and the insulating layer 235 which function as planarizing layers, unevenness of the surface on which the light-emitting device 130 and the like are formed is reduced. Therefore, the processing accuracy of the light-emitting device 130 and the like provided on the insulating layer 235 is improved, and a display device with high definition can be provided.

[0566] By forming the films that will become layers 113R, 113G, and 113R on the entire surface and then processing them, island-shaped layers 113R, 113G, and 113R are formed, allowing the island-shaped layers to be formed with uniform thicknesses. This allows for the realization of a high-resolution display device or a display device with a high aperture ratio. Furthermore, even when the resolution or aperture ratio is high and the distance between subpixels is extremely short, the layers 113R, 113G, and 113B can be prevented from contacting each other in adjacent subpixels. This prevents leakage current from occurring between subpixels. This prevents crosstalk due to unintended light emission, allowing for the realization of a display device with high contrast.

[0567] By providing the insulating layer 127 having a tapered edge between adjacent island-shaped EL layers, it is possible to suppress the occurrence of a step during the formation of the common electrode 115 and to prevent the formation of a locally thin portion in the common electrode 115. This can suppress the occurrence of a connection failure due to the disconnected portion in the common layer 114 and the common electrode 115 and an increase in electrical resistance due to the locally thin portion. Therefore, the display device of one embodiment of the present invention can achieve both high resolution and high display quality.

[0568] <Manufacturing Method Example 2> A method for manufacturing the display device shown in Fig. 18 will be described. Note that descriptions of parts that overlap with those described above will be omitted, and only different parts will be described.

[0569] First, the pixel electrodes 111R, 111G, 111B, and the conductive layer 123 are formed ( FIG. 31A ) in the same manner as in Manufacturing Method Example 1. Since the above description can be referred to for the formation of the pixel electrodes 111R, 111G, 111B, and the conductive layer 123, detailed description thereof will be omitted.

[0570] Next, an insulating layer 237 is formed to cover the edges of the pixel electrodes 111R, 111G, and 111B and the conductive layer 123 ( FIG. 39A ). The insulating layer 237 can be an organic insulating film or an inorganic insulating film. The edges of the insulating layer 237 are preferably tapered. Tapering the edges of the insulating layer 237 can improve the coverage of films to be formed later. In particular, using a photosensitive material as the organic insulating film is preferable because it is easy to control the shape of the edges by adjusting the exposure and development conditions. Note that an inorganic insulating film may also be used as the insulating layer 237. Using an inorganic insulating film as the insulating layer 237 can make the display device 100 a high-definition display device.

[0571] Subsequently, an island-shaped layer 113R is formed on the surface of the pixel electrode 111R (FIG. 39B).

[0572] The layer 113R is preferably formed by vacuum deposition using a fine metal mask. Alternatively, the island-shaped layer 113R may be formed by sputtering using a fine metal mask or by ink-jet printing.

[0573] 39B shows a schematic diagram of the formation of layer 113R using fine metal mask 151R, in which layer 113R is formed by a so-called face-down method, in which the substrate is inverted so that the surface on which layer 113R is to be formed faces downward.

[0574] In vacuum deposition using a fine metal mask, deposition is often performed over an area wider than the opening of the fine metal mask. As shown by the dashed line in Figure 39B, layer 113R can be formed over an area wider than the opening of fine metal mask 151R. In addition, the edge of layer 113R has a tapered shape. Layer 113R may also be formed on the surface of insulating layer 237.

[0575] Next, a layer 113G is formed on the surface of the pixel electrode 111G using a fine metal mask 151G (FIG. 40). The end of the layer 113G is tapered. The layer 113G may also be formed on the surface of the insulating layer 237.

[0576] Next, a layer 113B is formed on the surface of the pixel electrode 111B using a fine metal mask 151B (FIG. 41). The end of the layer 113B has a tapered shape. The layer 113B may also be formed on the surface of the insulating layer 237.

[0577] It is preferable that the layer 113R, the layer 113G, and the layer 113B are not formed on the surface of the conductive layer 123.

[0578] Note that although an example in which the layer 113R, the layer 113G, and the layer 113B are formed in this order is shown here, one embodiment of the present invention is not limited to this. The order in which the layers 113R, 113G, and 113B are formed is not particularly limited. Furthermore, in FIG. 41 and other examples, the layers 113R, 113G, and 113B are separated from one another, that is, adjacent layers 113 are not in contact with each other and are separated, but one embodiment of the present invention is not limited to this. Adjacent layers 113 may be in contact with each other. For example, over the insulating layer 237, the layer 113R may have a region overlapping with the layer 113G, the layer 113G may have a region overlapping with the layer 113B, and the layer 113R may have a region overlapping with the layer 113B.

[0579] Next, the common layer 114, the common electrode 115, and the protective layer 131 are formed on the insulating layer 127, the layer 113R, the layer 113G, and the layer 113B (FIG. 42). The above description can be referred to for the formation of the common layer 114, the common electrode 115, and the protective layer 131, and therefore detailed description thereof will be omitted.

[0580] Next, a substrate 120 is prepared, and a light-shielding layer 117 is formed on the substrate 120. Next, the substrate 120 and the light-shielding layer 117 are bonded to a protective layer 131 using a resin layer 122, thereby manufacturing a display device (FIG. 18).

[0581] By providing the insulating layer 214 and the insulating layer 235 that function as planarizing layers, unevenness of the surface on which the light-emitting device 130 and the like are formed can be reduced. Therefore, poor connection due to step disconnection of the common electrode and an increase in electrical resistance due to a local thinning of the film thickness of the common electrode 115 can be prevented, and a display device with high display quality can be obtained.

[0582] This embodiment mode can be combined with other embodiment modes as appropriate.

[0583] Embodiment 3 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

[0584] [Pixel Layout] In this embodiment, pixel layouts different from that shown in Fig. 1 will be mainly described. There are no particular limitations on the arrangement of sub-pixels, and various methods can be applied. Examples of sub-pixel arrangements include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0585] The top surface shape of the sub-pixels shown in the drawings in this embodiment corresponds to the top surface shape of the light-emitting region (or the light-receiving region). Note that in this specification and the like, the top surface shape refers to the shape in a plan view, that is, the shape seen from above.

[0586] The top surface shape of the subpixel may be, for example, a triangle, a quadrangle (including a rectangle and a square), a polygon such as a pentagon, a polygon with rounded corners, an ellipse, or a circle.

[0587] The circuit layout constituting the subpixel is not limited to the range of the subpixel shown in the figure, and the circuit components may be arranged outside of it.

[0588] An S-stripe arrangement is applied to the pixel 110 shown in Fig. 43A. The pixel 110 shown in Fig. 43A is made up of three types of subpixels: subpixel 110a, subpixel 110b, and subpixel 110c.

[0589] The pixel 110 shown in Figure 43B has subpixels 110a and 110b each having a substantially trapezoidal or triangular top surface shape with rounded corners, and subpixel 110c having a substantially rectangular or hexagonal top surface shape with rounded corners. Furthermore, subpixel 110b has a larger light-emitting area than subpixel 110a. In this manner, the shape and size of each subpixel can be determined independently. For example, the more reliable the light-emitting device, the smaller the size of the subpixel can be.

[0590] The Pentile arrangement is applied to the pixels 124a and 124b shown in Fig. 43C. Fig. 43C shows an example in which a pixel 124a having sub-pixels 110a and 110b and a pixel 124b having sub-pixels 110b and 110c are arranged alternately.

[0591] The pixels 124a and 124b shown in Figures 43D to 43F are arranged in a delta arrangement. The pixel 124a has two subpixels (subpixels 110a and 110b) in the top row (first row) and one subpixel (subpixel 110c) in the bottom row (second row). The pixel 124b has one subpixel (subpixel 110c) in the top row (first row) and two subpixels (subpixels 110a and 110b) in the bottom row (second row).

[0592] Figure 43D shows an example in which each subpixel has an approximately rectangular top surface shape with rounded corners, Figure 43E shows an example in which each subpixel has a circular top surface shape, and Figure 43F shows an example in which each subpixel has an approximately hexagonal top surface shape with rounded corners.

[0593] In Figure 43F, each subpixel is arranged inside a closely packed hexagonal region. Each subpixel is arranged so that it is surrounded by six other subpixels when focusing on one subpixel. Furthermore, subpixels that emit light of the same color are arranged so that they are not adjacent to each other. For example, when focusing on subpixel 110a, three subpixels 110b and three subpixels 110c are arranged alternately to surround it.

[0594] 43G shows an example in which subpixels of each color are arranged in a zigzag pattern. Specifically, when viewed from above, the positions of the upper sides of two subpixels aligned in the row direction (for example, subpixels 110a and 110b, or subpixels 110b and 110c) are misaligned.

[0595] 43A to 43G, it is preferable that the subpixel 110a be the subpixel R that emits red light, the subpixel 110b be the subpixel G that emits green light, and the subpixel 110c be the subpixel B that emits blue light. Note that the configuration of the subpixels is not limited to this, and the colors that the subpixels emit and their arrangement order can be determined appropriately. For example, the subpixel 110b may be the subpixel R that emits red light, and the subpixel 110a may be the subpixel G that emits green light.

[0596] In photolithography, the finer the pattern to be processed, the more significant the effect of light diffraction becomes. This reduces the fidelity of the photomask pattern when it is transferred by exposure, making it difficult to process the resist mask into the desired shape. Therefore, even if the photomask pattern is rectangular, it is likely to have rounded corners. As a result, the top surface shape of the subpixel may become a polygon with rounded corners, an ellipse, a circle, or the like.

[0597] Furthermore, in a manufacturing method of a display device according to one embodiment of the present invention, the EL layer is processed into an island shape using a resist mask. The resist film formed on the EL layer needs to be cured at a temperature lower than the heat resistance temperature of the EL layer. Therefore, depending on the heat resistance temperature of the material for the EL layer and the curing temperature of the resist material, the resist film may not be cured sufficiently. A resist film that is not cured sufficiently may have a shape that deviates from the desired shape during processing. As a result, the top surface shape of the EL layer may become a polygon with rounded corners, an ellipse, a circle, or the like. For example, when a resist mask with a square top surface shape is formed, a resist mask with a circular top surface shape may be formed, resulting in a circular top surface shape of the EL layer.

[0598] In order to form the top surface of the EL layer into a desired shape, a technique for correcting a mask pattern in advance (OPC (Optical Proximity Correction) technique) may be used so that the design pattern and the transfer pattern coincide with each other. Specifically, the OPC technique adds a correction pattern to the corners of figures on the mask pattern.

[0599] As shown in Figures 44A to 44I, a pixel can be configured to have four types of sub-pixels.

[0600] The pixels 110 shown in FIGS. 44A to 44C are arranged in a stripe pattern.

[0601] Figure 44A is an example in which each subpixel has a rectangular top surface shape, Figure 44B is an example in which each subpixel has a top surface shape that is a combination of two semicircles and a rectangle, and Figure 44C is an example in which each subpixel has an elliptical top surface shape.

[0602] The pixels 110 shown in FIGS. 44D to 44F are arranged in a matrix.

[0603] Figure 44D is an example in which each subpixel has a square top surface shape, Figure 44E is an example in which each subpixel has an approximately square top surface shape with rounded corners, and Figure 44F is an example in which each subpixel has a circular top surface shape.

[0604] 44G and 44H show an example in which one pixel 110 is configured in two rows and three columns.

[0605] 44G has three subpixels (subpixels 110a, 110b, and 110c) in the top row (first row) and one subpixel (subpixel 110d) in the bottom row (second row). In other words, pixel 110 has subpixel 110a in the left column (first column), subpixel 110b in the center column (second column), subpixel 110c in the right column (third column), and subpixels 110d across these three columns.

[0606] The pixel 110 shown in FIG. 44H has three subpixels (subpixels 110a, 110b, and 110c) in the top row (first row) and three subpixels 110d in the bottom row (second row). In other words, the pixel 110 has subpixels 110a and 110d in the left column (first column), subpixels 110b and 110d in the center column (second column), and subpixels 110c and 110d in the right column (third column). By aligning the subpixels in the top and bottom rows as shown in FIG. 44H, it is possible to efficiently remove dust and other particles that may occur during the manufacturing process. Therefore, a display device with high display quality can be provided.

[0607] FIG. 44I shows an example in which one pixel 110 is configured in three rows and two columns.

[0608] 44I has subpixel 110a in the top row (first row), subpixel 110b in the middle row (second row), subpixel 110c across the first and second rows, and one subpixel (subpixel 110d) in the bottom row (third row). In other words, pixel 110 has subpixels 110a and 110b in the left column (first column), subpixel 110c in the right column (second column), and subpixel 110d across these two columns.

[0609] The pixel 110 shown in FIGS. 44A to 44I is composed of four subpixels: 110a, 110b, 110c, and 110d.

[0610] The sub-pixels 110a, 110b, 110c, and 110d may each have a light-emitting device that emits a different color light, such as sub-pixels of four colors R, G, B, and white (W), sub-pixels of four colors R, G, B, and Y, or sub-pixels of R, G, B, and infrared (IR).

[0611] In each pixel 110 shown in Figures 44A to 44I, it is preferable that, for example, the subpixel 110a is the subpixel R that emits red light, the subpixel 110b is the subpixel G that emits green light, the subpixel 110c is the subpixel B that emits blue light, and the subpixel 110d is any one of the subpixels W that emit white light, Y that emit yellow light, and IR that emit near-infrared light. With such a configuration, the pixel 110 shown in Figures 44G and 44H has a stripe layout of R, G, and B, thereby improving display quality. Furthermore, the pixel 110 shown in Figure 44I has a so-called S-stripe layout of R, G, and B, thereby improving display quality.

[0612] The pixel 110 may have sub-pixels that include light-receiving devices.

[0613] In each pixel 110 shown in FIGS. 44A to 44I, any one of the subpixels 110a to 110d may be a subpixel having a light-receiving device.

[0614] 44A to 44I , it is preferable that, for example, the subpixel 110a be the subpixel R that emits red light, the subpixel 110b be the subpixel G that emits green light, the subpixel 110c be the subpixel B that emits blue light, and the subpixel 110d be the subpixel S that has a light-receiving device. With this configuration, the pixels 110 shown in FIGS. 44G and 44H have a stripe layout of R, G, and B, which can improve display quality. Furthermore, the pixel 110 shown in FIG. 44I has a so-called S-stripe layout of R, G, and B, which can improve display quality.

[0615] The wavelength of light detected by the subpixel S having the light receiving device is not particularly limited. The subpixel S can be configured to detect either or both of visible light and infrared light.

[0616] As shown in Figures 44J and 44K, a pixel can be configured to have five types of sub-pixels.

[0617] FIG. 44J shows an example in which one pixel 110 is configured in two rows and three columns.

[0618] 44J has three subpixels (subpixels 110a, 110b, and 110c) in the top row (first row) and two subpixels (subpixels 110d and 110e) in the bottom row (second row). In other words, pixel 110 has subpixels 110a and 110d in the left column (first column), subpixel 110b in the center column (second column), subpixel 110c in the right column (third column), and subpixel 110e from the second column to the third column.

[0619] FIG. 44K shows an example in which one pixel 110 is configured in three rows and two columns.

[0620] 44K has subpixel 110a in the top row (first row), subpixel 110b in the middle row (second row), subpixel 110c across rows 1 and 2, and two subpixels (subpixels 110d and 110e) in the bottom row (third row). In other words, pixel 110 has subpixels 110a, 110b, and 110d in the left column (first column), and subpixels 110c and 110e in the right column (second column).

[0621] 44J and 44K, it is preferable that the subpixel 110a be the subpixel R that emits red light, the subpixel 110b be the subpixel G that emits green light, and the subpixel 110c be the subpixel B that emits blue light. With this configuration, the pixel 110 shown in FIG. 44J has a stripe layout of R, G, and B, which can improve display quality. Furthermore, the pixel 110 shown in FIG. 44K has a so-called S-stripe layout of R, G, and B, which can improve display quality.

[0622] 44J and 44K, it is preferable to use a subpixel S having a light-receiving device in at least one of the subpixels 110d and 110e. When light-receiving devices are used in both the subpixels 110d and 110e, the configurations of the light-receiving devices may be different from each other. For example, the wavelength ranges of light detected may differ at least partially. Specifically, one of the subpixels 110d and 110e may have a light-receiving device that mainly detects visible light, and the other may have a light-receiving device that mainly detects infrared light.

[0623] 44J and 44K, it is preferable that one of the subpixels 110d and 110e is a subpixel S having a light-receiving device, and the other is a subpixel having a light-emitting device that can be used as a light source. For example, it is preferable that one of the subpixels 110d and 110e is a subpixel IR that emits infrared light, and the other is a subpixel S having a light-receiving device that detects infrared light.

[0624] In a pixel having sub-pixels R, G, B, IR, and S, an image can be displayed using the sub-pixels R, G, and B, while the sub-pixel IR can be used as a light source to detect reflected infrared light emitted by the sub-pixel IR at the sub-pixel S.

[0625] As described above, the display device of one embodiment of the present invention can employ various layouts for a pixel having a subpixel including a light-emitting device. Furthermore, the display device of one embodiment of the present invention can employ a pixel having both a light-emitting device and a light-receiving device. In this case, various layouts can also be employed.

[0626] This embodiment mode can be combined with other embodiment modes as appropriate.

[0627] Embodiment 4 In this embodiment, a display device according to one embodiment of the present invention will be described.

[0628] The display device of the present embodiment can be a high-definition display device, and can therefore be used, for example, as a display unit for a wristwatch-type or bracelet-type information terminal (wearable device), as well as a display unit for a wearable device that can be worn on the head, such as a head-mounted display (HMD) for VR, or a glasses-type AR device.

[0629] The display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used as a display unit for electronic devices having relatively large screens, such as television devices, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

[0630] [Display Device 100G] FIG. 45 shows a perspective view of the display device 100G, and FIG. 46 shows a cross-sectional view of the display device 100G.

[0631] The display device 100G has a configuration in which a substrate 152 and a substrate 151 are bonded together. In Fig. 45, the substrate 152 is indicated by a dashed line.

[0632] The display device 100G includes a display portion 162, a connection portion 140, a circuit 164, wiring 165, and the like. Fig. 45 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 100G. Therefore, the configuration shown in Fig. 45 can also be said to be a display module including the display device 100G, an IC (integrated circuit), and an FPC.

[0633] The connection portion 140 is provided on the outside of the display portion 162. The connection portion 140 can be provided along one side or multiple sides of the display portion 162. There may be one or multiple connection portions 140. FIG. 45 shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion. The connection portion 140 electrically connects the common electrode of the light-emitting device and the conductive layer, and can supply a potential to the common electrode.

[0634] The circuit 164 can be, for example, a scanning line driver circuit.

[0635] The wiring 165 has a function of supplying signals and power to the display portion 162 and the circuit 164. The signals and power are input to the wiring 165 from the outside via the FPC 172 or input to the wiring 165 from the IC 173.

[0636] 45 shows an example in which an IC 173 is provided on a substrate 151 by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like. The IC 173 may be, for example, an IC having a scanning line driver circuit or a signal line driver circuit. The display device 100G and the display module may not necessarily include an IC. Alternatively, the IC may be mounted on an FPC by a COF method or the like.

[0637] Figure 46 shows an example of a cross section of the display device 100G when a portion of the area including the FPC 172, a portion of the circuit 164, a portion of the display unit 162, a portion of the connection portion 140, and a portion of the area including the end portion are cut away.

[0638] A display device 100G shown in FIG. 46 includes a transistor 201, a transistor 205, a light-emitting device 130R, a light-emitting device 130G, and a light-emitting device 130B between a substrate 151 and a substrate 152.

[0639] Part of the top surface and side surfaces of layers 113R, 113G, and 113B are covered with insulating layers 125 and 127, respectively. Mask layers 118R and 119R are located between layer 113R and insulating layer 125. Mask layers 118G and 119G are located between layer 113G and insulating layer 125, and mask layers 118B and 119B are located between layer 113B and insulating layer 125. A common layer 114 is provided on layers 113B, 113G, 113R, insulating layer 125, and insulating layer 127, and a common electrode 115 is provided on common layer 114. Common layer 114 and common electrode 115 are each continuous films provided in common to multiple light-emitting devices.

[0640] A protective layer 131 is provided on the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B. The protective layer 131 and the substrate 152 are bonded via an adhesive layer 142. A light-shielding layer 117 is provided on the substrate 152. A solid sealing structure, a hollow sealing structure, or the like can be applied to seal the light-emitting devices. In FIG. 46 , the space between the substrates 152 and 151 is filled with the adhesive layer 142, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 142 may be provided so as not to overlap the light-emitting device. Alternatively, the space may be filled with a resin different from the frame-shaped adhesive layer 142.

[0641] The protective layer 131 is preferably provided in at least the display portion 162 and is provided so as to cover the entire display portion 162. The protective layer 131 is preferably provided so as to cover not only the display portion 162 but also the connection portion 140 and the circuit 164. The protective layer 131 is preferably provided up to the edge of the display device 100G. On the other hand, in the connection portion 204, the FPC 172 and the conductive layer 166 are electrically connected to each other, so that a portion where the protective layer 131 is not provided is generated.

[0642] A connection portion 204 is provided in a region of the substrate 151 where the substrate 152 does not overlap. In the connection portion 204, the wiring 165 is electrically connected to the FPC 172 via the conductive layer 233t, the conductive layer 166, and the connection layer 242. The conductive layer 233t is electrically connected to the wiring 165 through an opening provided in the insulating layer 214. The conductive layer 233t can be formed in the same process as the conductive layer 233R, the conductive layer 233G, and the conductive layer 233B. The conductive layer 166 can be formed in the same process as the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B. The conductive layer 166 is exposed on the top surface of the connection portion 204. This allows the connection portion 204 and the FPC 172 to be electrically connected via the connection layer 242.

[0643] For example, after the protective layer 131 is formed over the entire surface of the display device 100G, a mask is used to remove the region of the protective layer 131 that overlaps with the conductive layer 166, thereby exposing the conductive layer 166.

[0644] A laminated structure of at least one organic layer and a conductive layer may be provided on the conductive layer 166, and the protective layer 131 may be provided on the laminated structure. A peeling initiation point (a portion that triggers peeling) may then be formed on the laminated structure using a laser or a sharp blade (e.g., a needle or cutter), selectively removing the laminated structure and the protective layer 131 thereon to expose the conductive layer 166. For example, the protective layer 131 can be selectively removed by pressing an adhesive roller against the substrate 151 and moving the roller relative to the substrate while rotating. Alternatively, adhesive tape may be attached to the substrate 151 and peeled off. Because of poor adhesion between the organic layer and the conductive layer, or between the organic layers themselves, separation occurs at the interface between the organic layer and the conductive layer or within the organic layer. This allows selective removal of the region of the protective layer 131 that overlaps with the conductive layer 166. If an organic layer or the like remains on the conductive layer 166, it can be removed using an organic solvent or the like.

[0645] The organic layer can be, for example, at least one organic layer (a layer functioning as a light-emitting layer, a carrier blocking layer, a carrier transport layer, or a carrier injection layer) used in any of the layers 113B, 113G, and 113R. The organic layer can be formed simultaneously with the formation of any of the layers 113B, 113G, and 113R, or can be provided separately. The conductive layer can be formed in the same process and with the same material as the common electrode 115. For example, it is preferable to form an ITO film as the common electrode 115 and the conductive layer. Note that when a stacked structure is used for the common electrode 115, at least one of the layers constituting the common electrode 115 is provided as the conductive layer.

[0646] The upper surface of the conductive layer 166 may be covered with a mask so that the protective layer 131 is not formed on the conductive layer 166. As the mask, for example, a metal mask (area metal mask) or an adhesive or adhesive tape or film may be used. By forming the protective layer 131 with the mask in place and then removing the mask, the conductive layer 166 can be kept exposed even after the protective layer 131 is formed.

[0647] By using such a method, a region where the protective layer 131 is not provided can be formed in the connection portion 204, and in this region, the conductive ...

Claims

1. a transistor, a light emitting device, a first insulating layer, a second insulating layer, a first conductive layer, and a layer; the transistor includes a semiconductor layer and a second conductive layer electrically connected to the semiconductor layer; the light-emitting device has a pixel electrode; the first insulating layer is provided on the transistor; the first insulating layer has a first opening reaching the second conductive layer; the first conductive layer covers the first opening; the second insulating layer is provided on the first insulating layer; the second insulating layer has a second opening in a region overlapping with the first opening; the pixel electrode covers an upper surface of the second insulating layer and the second opening; the pixel electrode is electrically connected to the second conductive layer via the first conductive layer; an end of the first insulating layer is located on the second conductive layer; an end of the second insulating layer is located on the first conductive layer; an end of the second insulating layer is located outside an end of the first insulating layer; the pixel electrode has a third conductive layer and a fourth conductive layer on the third conductive layer; the third conductive layer covers an upper surface of the second insulating layer and the second opening; the third conductive layer has a recess that conforms to the shape of a side surface of the second insulating layer and a top surface of the second conductive layer; the layer is provided so as to fill the recess, the fourth conductive layer covers the top surface of the third conductive layer and the top surface of the layer; The fourth conductive layer includes a material that is reflective to visible light.

2. In claim 1, The display device, wherein the first insulating layer and the second insulating layer each comprise an organic material.

3. In claim 1 or claim 2, The display device, wherein the layer is an insulating layer.

4. In claim 1 or claim 2, The display device wherein the layer is a conductive layer.

5. In claim 1 or claim 2, a third insulating layer; the third insulating layer is provided in contact with an upper surface of the second insulating layer, the third insulating layer comprises an inorganic material; The pixel electrode has a region in contact with an upper surface of the third insulating layer.

6. In claim 1 or claim 2, a fourth insulating layer; the fourth insulating layer is provided in contact with an upper surface of the first insulating layer, the fourth insulating layer comprises an inorganic material; The first conductive layer has a region in contact with an upper surface of the fourth insulating layer.

7. In claim 1 or claim 2, a fifth insulating layer and a sixth insulating layer; the light-emitting device includes the pixel electrode, a common electrode, and an EL layer sandwiched between the pixel electrode and the common electrode; the fifth insulating layer covers a part of an upper surface and a side surface of the EL layer, the sixth insulating layer covers a part of an upper surface and a side surface of the EL layer via the fifth insulating layer; The common electrode covers the sixth insulating layer.

8. In claim 7, the fifth insulating layer comprises an inorganic material; The sixth insulating layer comprises an organic material.

9. In claim 1 or claim 2, a fifth insulating layer; the light-emitting device includes the pixel electrode, a common electrode, and an EL layer sandwiched between the pixel electrode and the common electrode; the fifth insulating layer covers a part of an upper surface and a side surface of the pixel electrode; the EL layer has a region in contact with an upper surface of the fifth insulating layer, The common electrode covers the fifth insulating layer.

10. In claim 1 or claim 2, the transistor has a gate insulating layer sandwiched between the semiconductor layer and a gate electrode, the semiconductor layer comprises a metal oxide; The concentration of the metal element contained in the metal oxide in the gate insulating layer is 2×10 １９ atoms / cm ３ A display device that is: