Semiconductor device

Abstract

Provided is a semiconductor device capable of achieving a high-integrated or minute arrangement. This semiconductor device has a first transistor with a first oxide, a second transistor with a second oxide, and a third oxide. The first oxide has a channel forming region for the first transistor. The second oxide has a channel forming region for the second transistor. The third oxide has the same material as the first oxide and the second oxide. The third oxide is isolated from the first oxide and the second oxide. In top view, the third oxide is positioned between the first oxide and the second oxide. The third oxide is arranged in the same layer as the first oxide and the second oxide.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a transistor, a semiconductor device, a display device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device and a method for manufacturing a display device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification and the like, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Another embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0004] In recent years, the development of semiconductor devices has progressed, and large scale integration (LSI), central processing units (CPU), memories, etc. are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed on chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] Furthermore, in recent years, with the trend toward smaller and lighter electronic devices, there has been an increasing demand for higher density integrated circuits. Therefore, there is a demand for technology to miniaturize transistors. Non-Patent Documents 1 and 2 disclose a transistor (junctionless-FET) that uses silicon for the channel and has a channel length of 3 nm and has no p / n junction. Non-Patent Document 3 discloses a transistor that uses an oxide semiconductor for the channel and has a gate length of 12 nm or less.

[0009] JP 2012-257187 A JP 2011-151383 A

[0010] S. Migita, et al., “Electrical Performances of Junctionless-FETs at the Scaling Limit (L▲CH▼=3nm)”, IEDM Tech. Dig. , pp. 191-194, 2012. S. Migita, et al, “Experimental Demonstration of Ultrashort-Channel (3nm) Junctionless FETs Utilizing Atomically Sharp V-Grooves on SOI”, IEEE Trans. Nanotechnol. , 13, pp. 208-215, 2014. S. Subhechha, et al, “First demonstration of sub-12nm L▲g▼ gate last IGZO-TFTs with oxygen tunnel architecture for front gate devices”, Symposium on VLSI Technology Digest of Technical Papers, T10-5, 2021.

[0011] An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object is to provide a semiconductor device with favorable electrical characteristics. Another object is to provide a semiconductor device with little variation in the electrical characteristics of transistors. Another object is to provide a semiconductor device with favorable reliability. Another object is to provide a semiconductor device with large on-state current. Another object is to provide a semiconductor device with low power consumption.

[0012] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc.

[0013] One embodiment of the present invention is a semiconductor device including a first transistor having a first oxide, a second transistor having a second oxide, and a third oxide. The first oxide includes a channel formation region of the first transistor. The second oxide includes a channel formation region of the second transistor. The third oxide includes the same material as the first oxide and the second oxide. The third oxide is separated from the first oxide and the second oxide. In a top view, the third oxide is located between the first oxide and the second oxide. The third oxide is disposed in the same layer as the first oxide and the second oxide.

[0014] In the above semiconductor device, it is preferable that the gate electrode of the first transistor has a region whose width is 1 nm to 20 nm in cross section in the channel length direction of the first transistor, and the gate electrode of the second transistor has a region whose width is 1 nm to 20 nm in cross section in the channel length direction of the second transistor.

[0015] In the above semiconductor device, the third oxide preferably does not function as a channel formation region of a transistor.

[0016] Another embodiment of the present invention is a semiconductor device having a circuit. The circuit includes a transistor and a first region including the transistor. The transistor includes a first oxide in a channel formation region. A second oxide is provided in the first region. The second oxide includes the same material as the first oxide. The second oxide is separated from the first oxide. The first region is divided into a square shape in a top view so as to include at least the channel formation region of the transistor. The area of ​​the first region is equal to the area occupied by one transistor calculated from the transistor density of the circuit. In a top view, the first region overlaps with at least a portion of the first oxide and the second oxide.

[0017] In the semiconductor device, the gate electrode of the transistor preferably has a region with a width of 1 nm to 20 nm in a cross section of the transistor in a channel length direction.

[0018] In the above semiconductor device, the second oxide preferably does not function as a channel formation region of a transistor.

[0019] Another embodiment of the present invention is a semiconductor device having a circuit. The circuit includes a transistor and a first region including the transistor. The transistor includes a first conductor functioning as a gate electrode and an oxide having a channel formation region. A second conductor not overlapping with the oxide is provided in the first region. The second conductor has the same material as the first conductor. The second conductor is separated from the first conductor. The first region is divided into a square shape in a top view so as to include at least the channel formation region of the transistor. The area of ​​the first region is equal to the area occupied by one transistor calculated from the transistor density of the circuit. In a top view, the first region overlaps with at least a portion of the first conductor and the second conductor.

[0020] In the semiconductor device, the first conductor preferably has a region with a width of 1 nm to 20 nm in a cross section taken along a channel length direction of the transistor.

[0021] In the semiconductor device, the transistor density of the circuit is 1 / μm ２ More than 1000 pieces / μm ２ It is preferable that:

[0022] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, a semiconductor device with high reliability can be provided. Alternatively, a semiconductor device with little variation in electrical characteristics of transistors can be provided. Alternatively, a semiconductor device with good electrical characteristics can be provided. Alternatively, a semiconductor device with large on-state current can be provided. Alternatively, a semiconductor device with low power consumption can be provided.

[0023] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc.

[0024] FIGS. 1A, 1D, and 1E are top views of a semiconductor device according to one embodiment of the present invention. FIGS. 1B and 1C are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 2A is a top view of a semiconductor device according to one embodiment of the present invention. FIG. 2B is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 3A is a top view of a semiconductor device according to one embodiment of the present invention. FIGS. 3B and 3C are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIGS. 4A to 4D are top views of a semiconductor device according to one embodiment of the present invention. FIGS. 5A, 5C, and 5E are top views of a semiconductor device according to one embodiment of the present invention. FIGS. 5B, 5D, and 5F are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 6A is a top view of a semiconductor device according to one embodiment of the present invention. FIGS. 6B to 6D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 7 shows calculation results of Id-Vg characteristics of a transistor. FIG. 8 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIGS. 9A to 9E are cross-sectional views of a semiconductor device according to one embodiment of the present invention. 10A to 10D are schematic diagrams of aluminum concentration profiles in metal oxides. FIG. 11 is a graph showing stresses of various films. FIGS. 12A and 12B are cross-sectional views of semiconductor devices according to embodiments of the present invention. FIGS. 13A and 13B are cross-sectional views of semiconductor devices according to embodiments of the present invention. FIG. 14A is a cross-sectional TEM image of an oxide semiconductor according to an embodiment of the present invention, and FIG. 14B is a plan-view TEM image of an oxide semiconductor according to an embodiment of the present invention. FIG. 15A is a plan-view TEM image of an oxide semiconductor according to an embodiment of the present invention, and FIG. 15B is a mapping image of an oxide semiconductor according to an embodiment of the present invention. FIGS. 16A to 16H are enlarged views of an oxide semiconductor according to an embodiment of the present invention. FIGS. 17A to 17C are plan-view TEM images of an oxide semiconductor according to an embodiment of the present invention. FIGS. 18A to 18C are mapping images of an oxide semiconductor according to an embodiment of the present invention. FIGS. 19A to 19C are mapping images of an oxide semiconductor according to an embodiment of the present invention. 20A to 20C are histograms showing Voronoi polygon distributions of an oxide semiconductor according to one embodiment of the present invention, and FIG. 21A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.21B to 21D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 22A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 22B to 22D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 23A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 23B to 23D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 24A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 24B to 24D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 25A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 25B to 25D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 26A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 26B to 26D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 27A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 27B to 27D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 28A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 28B to 28D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 29A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 29B to 29D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 30A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 30B to 30D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 31A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 31B to 31D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 32 is a top view illustrating a microwave processing apparatus according to one embodiment of the present invention. FIG. 33 is a schematic cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. FIG. 34 is a schematic cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. FIG. 35 is a schematic view illustrating a microwave processing apparatus according to one embodiment of the present invention. FIG. 36A is a top view of a semiconductor device according to one embodiment of the present invention.36B to 36D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 37A is a top view of a semiconductor device according to one embodiment of the present invention. FIGS. 37B to 37D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 38A is a top view of a semiconductor device according to one embodiment of the present invention. FIGS. 38B to 38D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 39A is a top view of a semiconductor device according to one embodiment of the present invention. FIGS. 39B to 39D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 40A is a plan view of a semiconductor device according to one embodiment of the present invention. FIGS. 40B and 40C are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 41 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. FIG. 42 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. FIG. 43 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIGS. 44A and 44B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 45 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 46A is a block diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. FIG. 46B is a perspective view illustrating a configuration example of a memory device according to one embodiment of the present invention. 47A to 47H are circuit diagrams illustrating an example configuration of a memory device according to one embodiment of the present invention. FIGS. 48A and 48B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. FIGS. 49A and 49B are diagrams illustrating an example of an electronic component. FIGS. 50A to 50E are schematic diagrams of a memory device according to one embodiment of the present invention. FIGS. 51A to 51H are diagrams illustrating electronic equipment according to one embodiment of the present invention. FIG. 52 is a diagram illustrating an example of space equipment. FIGS. 53A and 53B show Id-Vg characteristics of a transistor. FIGS. 54A and 54B are cross-sectional STEM images of a fabricated sample. FIG. 55 is a diagram illustrating a normal probability plot of Vth. FIGS. 56A and 56B show Id-Vg characteristics of a transistor. FIGS. 57A to 57D are planar SEM images of a fabricated sample. FIG. 58 is a diagram illustrating the relationship between process node and transistor density.

[0025] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0026] In addition, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, they are not necessarily limited to the scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers or resist masks may unintentionally be thinned by processes such as etching, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same symbols are used for identical parts or parts having similar functions in different drawings, and repeated explanations may be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular symbol may be assigned.

[0027] In order to make the invention easier to understand, particularly in top views (also called "plan views") or perspective views, some components may be omitted from the drawings, and some hidden lines may be omitted.

[0028] In addition, in this specification and the like, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc., for explanation. Furthermore, the ordinal numbers used to identify one embodiment of the present invention may not match the ordinal numbers used in this specification and the like.

[0029] Furthermore, in this specification, terms indicating arrangement such as "above" and "below" are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0030] For example, if it is explicitly stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0031] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0032] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0033] Note that the channel length refers to, for example, the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or in a channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be determined to a single value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0034] The channel width refers to, for example, the length of a channel formation region in a region where a semiconductor (or a portion of the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or the length of the channel formation region in a direction perpendicular to the channel length direction. Note that the channel width of a single transistor does not necessarily have the same value in all regions. That is, the channel width of a single transistor may not be determined to a single value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0035] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers the side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may become unnegligible. For example, in a fine transistor in which a gate electrode covers the side surface of a semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In such a case, the effective channel width is larger than the apparent channel width.

[0036] In such cases, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0037] In this specification, when simply referred to as a channel width, it may refer to an apparent channel width. Alternatively, when simply referred to as a channel width, it may refer to an effective channel width. Note that the values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, for example.

[0038] In this specification, the apparent channel width may be referred to as the gate width. The gate width may refer to, for example, the length of the top surface of a semiconductor, the length of the bottom surface of a semiconductor, or the length at any position in a semiconductor when viewed in a cross section of the transistor in the channel width direction. Furthermore, when a semiconductor has a stacked structure, the gate width may refer to, for example, the length of the interface between a first layer and a second layer of the stacked structure when viewed in a cross section of the transistor in the channel width direction.

[0039] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities can, for example, increase the defect state density of the semiconductor, reduce the crystallinity, and so on. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiency (V) in the oxide semiconductor. Ｏ In some cases, oxygen vacancies (also called oxygen vacancies) may be formed.

[0040] In this specification and the like, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0041] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0042] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0043] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0044] Furthermore, in this specification and the like, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 −２０ A or less, 1 x 10 at 85°C −１８ A or less, or 1 x 10 at 125°C −１６ This means that it is A or below.

[0045] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0046] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as “_1”, “[n]”, or “[m, n]” may be added to the symbol.

[0047] In addition, in this specification, when upper and lower limit values ​​are specified, it is also considered that a configuration in which the upper limit values ​​and the lower limit values ​​are freely combined is also disclosed.

[0048] In this specification, "having the same or approximately the same height" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as a substrate surface) are equal in cross-sectional view. For example, in a semiconductor device manufacturing process, a planarization process (typically a CMP process) may be performed to expose the surface of a single layer or multiple layers. In this case, the surfaces processed by the CMP process have the same height from the reference surface. However, the heights of multiple layers may differ depending on the processing equipment, processing method, or material of the processed surface during the CMP process. In this specification, this case is also treated as "having the same or approximately the same height." For example, when there are two layers (here, a first layer and a second layer) with different heights relative to the reference surface, and the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less, this is also referred to as "having the same or approximately the same height."

[0049] In this specification, "edges that coincide or approximately coincide" means that, when viewed from above, at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the term "edges that coincide or approximately coincide" is also used.

[0050] 1A to 5F , an example of a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device according to one embodiment of the present invention includes a transistor. The transistor includes an oxide semiconductor including a channel formation region.

[0051] The oxide semiconductor may be a metal oxide containing indium. For example, a metal oxide such as In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, tin, boron, silicon, vanadium, beryllium, copper, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or cobalt) may be used. Alternatively, an In—Ga oxide or an In—Zn oxide may be used as the oxide semiconductor. Metal oxides applicable to oxide semiconductors will be described in detail in Embodiment 2.

[0052] For example, a transistor using an oxide semiconductor for a channel formation region has an extremely small off-state current when it is off, which makes it possible to provide a semiconductor device with low power consumption. Note that the off-state current refers to a current that flows between the source and drain of a transistor when it is off.

[0053] Since an oxide semiconductor can be deposited by a sputtering method or the like, transistors can be stacked and integrated three-dimensionally by using an oxide semiconductor for the channel formation region. That is, a three-dimensional integrated circuit can be formed in which circuits are not only laid out on the plane of a substrate but also laid out in the vertical direction.

[0054] Note that the electrical characteristics of a transistor using an oxide semiconductor may vary due to oxygen vacancies or impurities (typically, hydrogen, water, or the like) in the oxide semiconductor. For example, the more oxygen vacancies or impurities there are in the oxide semiconductor, the more likely the transistor is to have normally-on characteristics (characteristics in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, it is preferable to use an oxide semiconductor with few oxygen vacancies or impurities for the transistor.

[0055] In a semiconductor device, multiple circuits having different functions may be arranged on the same substrate. Here, the density of elements or wiring required to configure the circuits varies depending on the desired circuit configuration. Specifically, there is a difference in density between a highly integrated circuit region with an ordered arrangement of elements and wiring (hereinafter also referred to as the layout in the circuit region) typified by a memory cell or pixel region and a circuit region whose layout is determined as needed, such as a driver circuit or correction circuit.

[0056] Each structure of a transistor can be manufactured by repeatedly forming a film using a material suitable for each structure and processing and shaping the film.

[0057] The above-mentioned film is formed by, for example, a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or an atomic layer deposition (ALD) method.

[0058] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (photo-CVD), which uses light. CVD methods can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0059] The plasma CVD method can produce high-quality films at relatively low temperatures. However, the wiring, electrodes, elements (transistors, capacitors, etc.) included in the semiconductor device may receive electric charge from the plasma generated during film formation, resulting in a charging phenomenon (charging is also called "charging up"). In this case, the accumulated electric charge may destroy the wiring, electrodes, or elements included in the semiconductor device.

[0060] Techniques for processing and shaping the above-mentioned films include dry etching, wet etching, and chemical mechanical polishing (also known as CMP). Dry etching using plasma is commonly used to perform fine processing as device sizes shrink. However, even in dry etching, plasma can cause charge-up.

[0061] For example, in the process of forming wiring, the wiring is likely to be separated, causing each wiring to be in an electrically floating state. After separation, each wiring will be charged up in subsequent processes, causing electrostatic discharge (ESD) of the element. In particular, if each electrode of a transistor is charged to a different potential, there is a high probability that the gate insulator will be destroyed.

[0062] In particular, in a three-dimensional integrated circuit (3D integrated circuit) in which the circuit is expanded vertically, the number of steps required for film formation and processing of the film increases as the vertical integration density increases. In other words, the probability of electrostatic breakdown due to charge-up tends to increase in proportion to the number of steps required for film formation and processing of the film.

[0063] On the other hand, in the above-mentioned film formation process and the above-mentioned processing process, it is preferable that the plasma be uniformly distributed on the substrate in order to suppress variations. However, in a layout with differences in density, if a uniform plasma charge is induced on the substrate, there is a problem that the amount of plasma charge differs between a location of elements in a region where elements are arranged at high density and a location of elements in a region where elements are arranged at low density.

[0064] Furthermore, charge buildup during the etching process can cause shape abnormalities or microloading phenomena in elements. For example, the narrower the pattern width, the higher the probability of charge buildup near the surface of the mask. When charge buildup occurs near the surface of the mask, the speed of ions reaching the surface of the mask changes depending on the charged potential, causing variations in the etching rate within the surface and resulting in shape abnormalities.

[0065] In a transistor including an oxide semiconductor, oxygen in the oxide semiconductor may be absorbed by a conductor included in the transistor or a conductor used in a plug or a wiring connected to the transistor, which may result in oxygen vacancies in the oxide semiconductor. For example, when heat treatment is performed during the manufacture of a transistor, oxygen in the oxide semiconductor may be absorbed by a conductor included in the transistor due to the heat treatment.

[0066] In addition, oxygen vacancies may be formed in the oxide semiconductor due to process damage during the fabrication of a transistor.Furthermore, oxygen in the oxide semiconductor may be absorbed by a conductor included in the transistor or a conductor used for a plug or wiring connected to the transistor during a heating step or the like during the fabrication of the transistor, thereby forming oxygen vacancies in the oxide semiconductor.

[0067] In order to reduce oxygen vacancies, an oxide containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) may be provided near the oxide semiconductor included in the transistor. This allows oxygen to be supplied to the oxide semiconductor, thereby reducing the amount of oxygen vacancies in the oxide semiconductor. However, if there is a difference in density between the layouts in the circuit region, the amount of oxygen supplied varies within the substrate surface, which causes variations in the characteristics of the semiconductor device including the transistor.

[0068] In view of this, in one embodiment of the present invention, a structure including at least one of an oxide semiconductor, a conductor, and an insulator is provided near a transistor included in a semiconductor device. Note that the oxide semiconductor includes the same material as the oxide semiconductor included in the transistor and is provided in the same layer as the oxide semiconductor included in the transistor. The conductor includes the same material as the conductor included in the transistor and is provided in the same layer as the conductor included in the transistor. The insulator includes the same material as the insulator included in the transistor and is provided in the same layer as the insulator included in the transistor. With this structure, the pattern density (also referred to as average density) of at least one of the oxide semiconductor, the conductor, and the insulator can be made uniform.

[0069] In this specification, the pattern density refers to the area ratio of the structures formed in a given region. For example, if a conductive film is formed over the entire surface of a given region, the pattern density is 100%. On the other hand, if a portion of the conductive film is removed to form multiple conductors, the pattern density of the conductors can be calculated by dividing the area of ​​the remaining conductors by the area of ​​the given region.

[0070] In one embodiment of the present invention, when a circuit region has a sparse layout and a dense layout, dummy elements (hereinafter also referred to as sacrificial elements) are provided in the sparse circuit region so that the density of elements or wirings in the sparse circuit region is equal to that in the dense circuit region. This configuration can reduce the difference in the density of the layout in the circuit region. Here, the dummy elements refer to elements that do not affect the circuit.

[0071] The density of the layout in the circuit region is reduced to a level that minimizes differences in the amount of excess oxygen diffused per element arranged in each region, or the pattern density in the circuit region is made equal. With this configuration, the amount of oxygen supplied to each element in each of the multiple regions can be controlled.

[0072] Alternatively, by reducing the density of the layout in the circuit region to a level that makes processing abnormalities or electrostatic breakdown unlikely to occur, or by equalizing the pattern density in the circuit region, plasma damage to the element, electrostatic breakdown, and shape abnormalities can be reduced. Note that in this specification, when a value is described as being equal to another value, this does not necessarily mean that they strictly match. It means values ​​that are approximately the same, equivalent, or approximate within the scope of technical common sense.

[0073] For example, for a certain structure, even if the average pattern density of the entire substrate is 40%, the pattern density may be 70% in one region of the substrate and 10% in another region. Therefore, since the region with a pattern density of 10% is a sparse region, it is advisable to form dummy elements so that the pattern density is approximately 70%. In other words, when no dummy elements are arranged, the average pattern density of the entire substrate is d ａｖｅ Percent, d ａｖｅ The pattern density of the area denser than d ｈｉｇｈ Percent, d ａｖｅ The pattern density of the area sparser than the percentage is d ｌｏｗ percent. The pattern density is d ｌｏｗ By providing a dummy element in the region of d ａｖｅ percent or more, preferably d ｈｉｇｈ It is best to use a percentage.

[0074] The dummy elements are fabricated in the same process as the elements having circuit functions. Therefore, the dummy elements are provided in the same layer as the elements having circuit functions. At least one of the structures constituting the dummy elements is made of the same material as the structure constituting the elements having circuit functions.

[0075] The dummy element may have the same structure as the element having the circuit function. Furthermore, the dummy element only needs to have at least one of the same structures as the element having the circuit function. Therefore, the number of structures constituting the dummy element may be less than the number of structures constituting the element having the circuit function. In other words, the element constituting the circuit may have a conductor, an insulator, a semiconductor, or the like in addition to the structure constituting the dummy element.

[0076] As an element having a circuit function, a capacitance element, an inductance element, a resistance element (a switching element such as a transistor, a light-emitting element, a memory element, etc.), or the like can be used.

[0077] <Structural Example 1 of Semiconductor Device> An example of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIGS. 1A to 3C. FIG.

[0078] FIG. 1A is a top view of a semiconductor device including a transistor 200. The x direction in FIG. 1A is parallel to the channel length direction of the transistor 200, and the y direction is perpendicular to the x direction. FIGS. 1B and 1C are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 1A. FIG. 1C is a cross-sectional view of a portion indicated by a dashed dotted line A5-A6 in FIG. 1A. Note that some elements are omitted in FIG. 1A for clarity.

[0079] 1A includes a plurality of transistors 200 arranged in a matrix. Note that FIG. 1A is a top view of a region including one of the plurality of transistors 200 arranged in a matrix and the transistors 200 arranged around it.

[0080] As shown in FIG. 1B , the transistor 200 is provided over a substrate 10. The transistor 200 includes at least a conductor 260 functioning as a gate electrode and an oxide 230 having a channel formation region. Although not shown in FIG. 1B , an insulator functioning as a gate insulator is provided between the conductor 260 and the oxide 230. Note that the transistor 200 may include a conductor functioning as a source electrode or a drain electrode, a conductor functioning as a back gate electrode, an insulator functioning as a back gate insulator, and the like. Note that a structure and a manufacturing method of the transistor 200 will be described in detail in Embodiment 2.

[0081] 1A, the conductor 260 is provided extending in the y direction. Therefore, the conductor 260 is shared by multiple transistors 200 arranged in the y direction. The conductor 260 can also function as a wiring. Note that the conductor 260 may be provided for each transistor 200. Alternatively, a conductor that functions as a wiring may be provided on the conductor 260.

[0082] 1B, the transistor 200 is electrically connected to the conductors 240a and 240b that function as plugs. When the conductors 240a and 240b are electrically connected to wiring in a circuit, the transistor 200 functions as a transistor that constitutes the circuit.

[0083] 1A, an oxide containing excess oxygen is provided in the semiconductor device, which allows oxygen to be supplied to the oxide 230 of the transistor 200. Note that the oxide corresponds to the insulator 224, the insulator 250, the insulator 280, or the like described in Embodiment 2.

[0084] 1A includes an oxide 230d between transistors 200 adjacent to each other in the y direction. That is, the semiconductor device includes an oxide 230d between a first transistor and a second transistor adjacent to the first transistor in the y direction. The semiconductor device includes a first transistor, a second transistor, and an oxide 230d, and the first transistor, the oxide 230d, and the second transistor are arranged in this order in the y direction. The semiconductor device includes a first oxide included in the first transistor, a second oxide included in the second transistor adjacent to the first transistor in the y direction, and the oxide 230d, and the oxide 230d is located between the first oxide and the second oxide.

[0085] The oxide 230d is formed in the same process as the oxide 230 of the transistor 200. Therefore, the oxide 230d contains the same material as the oxide 230. In this case, it can be said that the oxide 230d contains the elements that constitute the oxide 230. For example, when an In-M-Zn oxide is used as the oxide 230, the oxide 230d becomes an In-M-Zn oxide. The oxide 230d is disposed in the same layer as the oxide 230. For example, the oxide 230d contacts the first layer that the oxide 230 contacts. Note that the case where the oxide 230 is adjacent to the first layer with a second layer sandwiched therebetween also includes the case where the oxide 230d is adjacent to the first layer with a third layer formed in the same process as the second layer sandwiched therebetween. Alternatively, for example, the bottom surface of the oxide 230d is flush or approximately flush with the bottom surface of the oxide 230.

[0086] The oxide 230 and the oxide 230d are each formed in an island shape. In this specification, the term "island shape" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. In other words, the oxide 230d is separated from the oxide 230.

[0087] Furthermore, the oxide 230d is not electrically connected to wiring in the circuit, and therefore does not function as a channel formation region of the transistor.

[0088] The above-described structure can make the arrangement or pattern density of the oxide semiconductor made of the oxide 230 and the oxide 230d more uniform. Therefore, the amount of oxygen supplied to the oxide 230 from the oxide having excess oxygen arranged near the transistor 200 can be made more uniform. Therefore, the transistor 200 can be provided with reduced variations in transistor characteristics and excellent reliability. Furthermore, by forming the oxide 230 and the oxide 230d in the same process, shape abnormalities due to processing can be reduced.

[0089] Note that the distance from the first oxide of the first transistor to the oxide 230d is preferably equal to the distance from the second oxide of the second transistor adjacent to the first transistor in the y direction to the oxide 230d. With this structure, the arrangement or pattern density of the oxide semiconductor including the oxide 230 and the oxide 230d can be made more uniform.

[0090] 1A also shows a configuration in which the area of ​​oxide 230d in a top view is smaller than the area of ​​oxide 230 in a top view. In order to achieve high integration of the semiconductor device, it is preferable that the area of ​​oxide 230d in a top view is smaller than the area of ​​oxide 230 in a top view. However, the present invention is not limited to this. As long as high integration of the semiconductor device is possible, the area of ​​oxide 230d in a top view may be the same as the area of ​​oxide 230 in a top view, or may be larger than the area of ​​oxide 230 in a top view.

[0091] A semiconductor device according to one embodiment of the present invention includes a circuit. One or more transistors are arranged in the circuit. Here, the number of transistors arranged per unit area is defined as transistor density. In this specification and the like, the transistor density is defined as 1 μm ２ The number of transistors per μm is ２ , Tr / μm ２ , or μm −２ The transistor density of a circuit included in a semiconductor device of one embodiment of the present invention is expressed as 1 Tr / μm ２ or more, 3000Tr / μm２ Below, 2000Tr / μm ２ or less than 1000Tr / μm ２ The following is the result.

[0092] It should be noted that not all of the transistors counted when calculating the transistor density of a circuit function as transistors that constitute that circuit. For example, transistors that are counted when calculating the transistor density of a circuit may include transistors that are arranged in the circuit area but do not function as transistors that constitute that circuit, and dummy elements that have the same configuration as transistors that function as transistors that constitute that circuit. Therefore, the transistor density is expressed as the number of transistors / μm ２ Rule, Tr / μm ２ Rule, or μm −２ It may be referred to as a rule.

[0093] The area occupied by one transistor can be calculated by converting the transistor density. Specifically, the area occupied by one transistor is taken as the reciprocal of the transistor density.

[0094] 1A is defined as a region 13. The circuit has a transistor 200 and a region 13 including the transistor 200.

[0095] Region 13 is divided into a square shape in top view so as to include at least the channel formation region of transistor 200. The shape of region 13 in top view may be rectangular, circular, or the like. The area of ​​region 13 is equal to the area occupied by one transistor calculated from the transistor density. In other words, one side of region 13 is equal to the square root of the area occupied by one transistor calculated from the transistor density.

[0096] In a top view of the semiconductor device, the oxide 230d is preferably arranged inside the region 13 together with at least a part of the oxide 230. In this case, the region 13 overlaps with at least a part of the oxide 230 and the oxide 230d. More specifically, in a top view of the semiconductor device, the oxide 230d is preferably arranged inside the region 13 together with the channel formation region of the oxide 230 or a region of the oxide 230 that overlaps with the conductor 260. In this case, the region 13 overlaps with the channel formation region of the oxide 230 or a region of the oxide 230 that overlaps with the conductor 260, and the oxide 230d. With this structure, the arrangement or pattern density of the oxide semiconductor consisting of the oxide 230 and the oxide 230d can be made more uniform.

[0097] 1A illustrates a configuration in which the oxide 230d is provided between the first transistor and the second transistor adjacent to the first transistor in the y-direction, but the present invention is not limited to this. The oxide 230d may be provided between the first transistor and the third transistor adjacent to the first transistor in the x-direction.

[0098] As described above, the arrangement of the oxide 230d is not particularly limited as long as the oxide 230d does not function as a channel formation region of a transistor. The oxide 230d may be arranged to have a region overlapping with the conductor 260 as shown in FIG. 1A or may be arranged in a region not overlapping with the conductor 260 as shown in FIG. 1D.

[0099] Furthermore, as long as the oxide 230d does not function as a channel formation region of a transistor, the top surface shape of the oxide 230d is not particularly limited. The top surface shape of the oxide 230d may be rectangular as shown in FIG. 1A , or may be polygonal, such as a triangle, a quadrangle (including a rectangle and a square), or a pentagon, or a shape with rounded corners of these polygons, an ellipse, a circle, or a shape combining multiple polygons. Furthermore, as shown in FIG. 1A , multiple oxides 230d may be arranged in the x direction, or as shown in FIG. 1E , the oxide 230d may be provided as a continuous layer extending in the x direction.

[0100] 1A, a plurality of transistors 200 are arranged in a matrix, but the arrangement of the plurality of transistors 200 is designed appropriately depending on the desired circuit. For example, as shown in FIG. 2A, a plurality of transistors 200 may be arranged in a zigzag pattern.

[0101] 2A is a top view of a semiconductor device including a transistor 200. The x direction in FIG. 2A is parallel to the channel length direction of the transistor 200, and the y direction is perpendicular to the x direction. FIG. 2B is a cross-sectional view of the semiconductor device, and is also a cross-sectional view of a portion indicated by the dashed dotted line A1-A2 in FIG. 2A. Note that some elements are omitted in FIG. 2A for clarity.

[0102] The semiconductor device shown in Fig. 2A differs from the semiconductor device shown in Fig. 1A in the arrangement of the transistor 200 and the arrangement of the oxide 230d. Hereinafter, differences from the semiconductor device shown in Fig. 1A will be mainly described, and descriptions of overlapping parts may be omitted.

[0103] 2A has an oxide 230d between the transistors 200 adjacent to each other in the x direction and between the transistors 200 adjacent to each other in the y direction. With this structure, the arrangement or pattern density of the oxide semiconductor including the oxide 230 and the oxide 230d can be made more uniform.

[0104] 1A and 2A show a configuration in which the oxide 230d is provided in a region where a circuit included in the semiconductor device is provided, but the present invention is not limited to this. For example, a structure that is formed in the same process as at least a part of the structure that constitutes the transistor 200 and that does not constitute the transistor 200 may be provided in the region where a circuit included in the semiconductor device is provided.

[0105] Fig. 3A is a top view of a semiconductor device. Fig. 3B and Fig. 3C are cross-sectional views of the semiconductor device. Fig. 3B is a cross-sectional view of a portion indicated by dashed dotted line A1-A2 in Fig. 3A. Fig. 3C is a cross-sectional view of a portion indicated by dashed dotted line A3-A4 in Fig. 3A. Note that some elements have been omitted in Fig. 3A for clarity.

[0106] 3A differs from the semiconductor device shown in Fig. 1A in that it does not have oxide 230d but has conductor 260d. Hereinafter, differences from the semiconductor device shown in Fig. 1A will be mainly described, and descriptions of overlapping parts may be omitted.

[0107] 3A has a conductor 260d between conductors 260 that are close to each other in the x direction. In other words, the semiconductor device has the conductor 260d between a first conductor and a second conductor that is close to the first conductor in the x direction. In this case, the conductor 260d is provided in a region where a circuit of the semiconductor device is provided.

[0108] The conductor 260d is formed in the same process as the conductor 260 of the transistor 200. Therefore, the conductor 260d has the same material as the conductor 260. In this case, it can be said that the conductor 260d has the elements that constitute the conductor 260. Furthermore, the conductor 260d is disposed in the same layer as the conductor 260. For example, the conductor 260d is in contact with the first layer that the conductor 260 is in contact with. Note that when the conductor 260 is adjacent to the first layer with a second layer sandwiched therebetween, the conductor 260d may also be adjacent to the first layer with a third layer formed in the same process as the second layer sandwiched therebetween. Alternatively, for example, the bottom surface of the conductor 260d is flush or approximately flush with the bottom surface of the conductor 260. Furthermore, the conductor 260d is separated from the conductor 260.

[0109] The conductor 260d is preferably in a floating state, or preferably does not overlap with the oxide 230. In this case, the conductor 260d does not function as a gate electrode of a transistor.

[0110] The above-described configuration allows for more uniform arrangement or pattern density of the conductors consisting of the conductor 260 and the conductor 260d. Therefore, by providing the conductor 260d in the same process as the formation of the conductor 260, charge-up of the conductor 260 can be suppressed. Therefore, electrostatic breakdown of the insulator disposed between the conductor 260 and the oxide 230 can be suppressed. Furthermore, variations in the shape and characteristics of the elements can be suppressed.

[0111] Furthermore, impurities (typically, hydrogen, water, and the like) in the oxide semiconductor might be absorbed by the conductor 260d due to heat treatment in the process of manufacturing the transistor. That is, the conductor 260d captures the impurities, which can prevent the impurities from diffusing into the transistor 200. Therefore, the reliability of the transistor 200 can be improved.

[0112] Note that the distance from the first conductor of the first transistor to the conductor 260d is preferably equal to the distance from the second conductor of the second transistor adjacent to the first transistor in the x-direction to the conductor 260d. With this configuration, the arrangement or pattern density of the conductors consisting of the conductors 260 and 260d can be made more uniform.

[0113] In a top view of the semiconductor device, the conductor 260d is preferably arranged inside the region 13 together with at least a portion of the conductor 260. In this case, the region 13 overlaps with at least a portion of the conductor 260 and the conductor 260d. More specifically, in a top view of the semiconductor device, the conductor 260d is preferably arranged inside the region 13 together with a region of the conductor 260 that functions as the gate electrode or a region of the conductor 260 that overlaps with the oxide 230. In this case, the region 13 overlaps with the region of the conductor 260 that functions as the gate electrode or a region of the conductor 260 that overlaps with the oxide 230, and the conductor 260d. With this configuration, the arrangement or pattern density of the conductors consisting of the conductor 260 and the conductor 260d can be made more uniform.

[0114] Furthermore, as long as the conductor 260d does not function as a gate electrode of a transistor, the top surface shape of the conductor 260d is not particularly limited. The top surface shape of the conductor 260d may be a square as shown in FIG. 3A , or a polygon such as a triangle, a quadrangle (including a rectangle and a square), or a pentagon, or a shape with rounded corners of such a polygon, an ellipse, a circle, or a shape combining multiple polygons. Furthermore, as shown in FIG. 3A , multiple conductors 260d may be arranged in the y direction, or the conductor 260d may be provided as a continuous layer extending in the y direction.

[0115] As a result, variations in the electrical characteristics of transistors can be suppressed, highly reliable transistors can be provided, and shape abnormalities and electrostatic breakdown of transistors can be suppressed. As a result, yields can be improved, and productivity of semiconductor devices can be increased.

[0116] <Structural Example 2 of Semiconductor Device> Another example of a semiconductor device that is one embodiment of the present invention will be described below with reference to FIGS. 4A to 5F.

[0117] 4A to 4D are top views of a semiconductor device, and some elements are omitted in order to clarify the drawings.

[0118] As shown in FIG. 4A , the semiconductor device has regions 11 and 12 on a substrate 10. Region 11 has transistors 200 and a plurality of dummy elements 200d arranged at low density. For ease of viewing, hatched patterns are applied to a plurality of structures representing the dummy elements 200d. On the other hand, region 12 has a plurality of transistors 200 arranged at high density. By arranging a plurality of dummy elements 200d in region 11, the pattern density of region 11 can be made equivalent to (hereinafter also referred to as an approximate value) the pattern density of region 12.

[0119] 4A , an oxide having excess oxygen is disposed across the region 11 and the region 12. This allows the amount of oxygen supplied per transistor 200 to be the same between the transistor 200 disposed in the region 11 and the multiple transistors 200 disposed in the region 12. Therefore, variations in transistor characteristics are suppressed in the region 11 and the region 12, and highly reliable transistors 200 can be provided. Note that the oxide corresponds to the insulator 224, the insulator 250, the insulator 280, or the like, which will be described in the second embodiment.

[0120] Furthermore, by providing the dummy element 200d, impurities (typically hydrogen, water, etc.) in the oxide semiconductor may be absorbed by the conductor of the dummy element 200d due to heat treatment in the process of fabricating the transistor. That is, the dummy element 200d captures the impurities, thereby preventing the impurities from diffusing into the transistor 200. Therefore, the reliability of the transistor 200 can be improved.

[0121] Furthermore, when the structures included in the plurality of transistors 200 and the structures included in the plurality of dummy elements 200d are formed by processing the film using a dry etching method, the amount of plasma charge per transistor 200 is equivalent in region 11 and region 12. That is, in region 11, plasma charge is induced not only in the transistors 200 but also in the dummy elements 200d, so the amount of plasma charge per transistor 200 is reduced. Therefore, plasma damage to the transistors 200 in region 11 is reduced, and electrostatic breakdown can be suppressed.

[0122] Furthermore, the microloading phenomenon can be suppressed, thereby suppressing variations in the shape and characteristics of the elements.

[0123] The dummy elements 200d may be arranged in the region 11 so that the arrangement of the transistors 200 and the dummy elements 200d in the region 11 is equivalent to the arrangement of the plurality of transistors 200 in the region 12. For example, as shown in FIG. 4B , even in a configuration in which the plurality of transistors 200 are arranged in a matrix in the region 11, the dummy elements 200d may be arranged in the region 11 so that the arrangement is equivalent to the arrangement of the plurality of transistors 200 in the region 12. Furthermore, for example, as shown in FIG. 4C , even in a configuration in which the arrangement of the transistors 200 in the first direction in the region 11 is the same as in the region 12, the dummy elements 200d may be arranged in the region 11 so that the arrangement is equivalent to the arrangement of the plurality of transistors 200 in the region 12.

[0124] 4A illustrates a configuration in which a plurality of transistors 200 are arranged in a matrix in region 12, but the layout in the circuit region is not limited to this and may be appropriately designed depending on the desired circuit. For example, as shown in FIG. 4D, a plurality of transistors 200 may be arranged in a zigzag pattern. In this case, dummy elements 200d may be provided in region 11 so that the transistors 200 and dummy elements 200d are also arranged in a zigzag pattern.

[0125] Next, a configuration example of a semiconductor device having the region 11 shown in FIG. 4C will be described with reference to FIGS. 5A to 5F.

[0126] FIG. 5A is a top view of a semiconductor device having a transistor 200. The semiconductor device shown in FIG. 5A has a region 11 where elements are arranged sparsely and a region 12 where elements are arranged densely. Note that FIG. 5A illustrates a portion of region 11 shown in FIG. 4C , but does not illustrate region 12 shown in FIG. 4A . Region 11 includes dummy elements in addition to the transistor 200 that functions as a transistor, thereby having an element pattern density equivalent to that of region 12. Note that the x direction shown in FIG. 5A is parallel to the channel length direction of the transistor 200, and the y direction is perpendicular to the x direction. Note that some elements are omitted in FIG. 5A for clarity.

[0127] Fig. 5A is a top view of a region including one transistor 200 among a plurality of transistors 200 arranged in a matrix, and transistors 200 and dummy elements 200d arranged around the one transistor 200 in region 11. Fig. 5B is a cross-sectional view of the semiconductor device, and is also a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in Fig. 5A.

[0128] 5A and 5B has the same structure as the transistor 200 shown in Fig. 1B. Therefore, the description of <Structural example 1 of semiconductor device> can be referred to for the transistor 200 shown in Fig. 5A and 5B.

[0129] The transistor 200 is electrically connected to the conductors 240 a and 240 b that function as plugs. When the conductors 240 a and 240 b are electrically connected to wiring in a circuit, the transistor 200 functions as a transistor that constitutes the circuit.

[0130] 5A and 5B includes an oxide 230d. The oxide 230d is formed in the same process as the oxide 230 of the transistor 200. Therefore, the oxide 230d includes the same material as the oxide 230. Furthermore, the oxide 230d is disposed in the same layer as the oxide 230.

[0131] The above-described structure can make the arrangement or pattern density of the oxide semiconductor made of the oxide 230 and the oxide 230d more uniform. Therefore, the amount of oxygen supplied to the oxide 230 from the oxide having excess oxygen arranged near the transistor 200 can be made more uniform. Furthermore, by forming the oxide 230 and the oxide 230d in the same process, shape abnormalities due to processing can be suppressed.

[0132] 5A and 5B has the same configuration as the oxide 230d shown in Fig. 1C. Therefore, for the oxide 230d shown in Fig. 5A and 5B, the description of <Configuration Example 1 of Semiconductor Device> can be referred to.

[0133] 5A and 5B show a configuration in which the dummy element 200d includes the oxide 230d, but the present invention is not limited to this. The dummy element 200d may include at least a part or all of the structures that make up the transistor 200.

[0134] 5C to 5F show examples of the configuration of a semiconductor device having a dummy element different from the dummy element 200d shown in FIGS. 5A and 5B.

[0135] Fig. 5C is a top view of the semiconductor device. Fig. 5D is a cross-sectional view of the semiconductor device, and is also a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in Fig. 5C. Note that some elements have been omitted in Fig. 5C for clarity.

[0136] Note that the transistor 200 shown in FIGS. 5C and 5D is the same as the transistor 200 shown in FIGS. 5A and 5B, and therefore the above description can be referred to.

[0137] 5C and 5D includes a conductor 260d. Note that the conductor 260d is formed in the same process as the conductor 260 of the transistor 200. Therefore, the conductor 260d includes the same material as the conductor 260. Furthermore, the conductor 260d is disposed in the same layer as the conductor 260.

[0138] The above-described configuration allows for more uniform arrangement or pattern density of the conductors consisting of the conductor 260 and the conductor 260d. Furthermore, providing the conductor 260d in the same process as forming the conductor 260 can suppress charge-up of the conductor 260. Therefore, electrostatic breakdown of the insulator disposed between the conductor 260 and the oxide 230 can be prevented.

[0139] 5C and 5D has the same configuration as the conductor 260d shown in Fig. 3A and 3C. Therefore, for the conductor 260d shown in Fig. 5C and 5D, the description of <Configuration example 1 of semiconductor device> can be referred to.

[0140] Fig. 5E is a top view of the semiconductor device. Fig. 5F is a cross-sectional view of the semiconductor device, and is also a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in Fig. 5E. Note that some elements have been omitted in Fig. 5E for clarity.

[0141] Note that the transistor 200 shown in FIGS. 5E and 5F is the same as the transistor 200 shown in FIGS. 5A and 5B, and therefore the above description can be referred to.

[0142] The dummy element 200d shown in FIGS. 5E and 5F has an oxide 230d and a conductor 260d. The oxide 230d is formed in the same process as the oxide 230 of the transistor 200. Therefore, the oxide 230d has the same material as the oxide 230. The oxide 230d is also disposed in the same layer as the oxide 230. The conductor 260d is also formed in the same process as the conductor 260 of the transistor 200. Therefore, the conductor 260d has the same material as the conductor 260. The conductor 260d is also disposed in the same layer as the conductor 260.

[0143] The above-described structure can make the arrangement or pattern density of the oxide semiconductor including the oxide 230 and the oxide 230d, and the arrangement or pattern density of the conductor including the conductor 260 and the conductor 260d, more uniform. Therefore, the amount of oxygen supplied to the oxide 230 from the oxide having excess oxygen arranged near the transistor 200 can be made more uniform. Furthermore, by forming the oxide 230 and the oxide 230d in the same process, shape abnormalities due to processing can be suppressed. Furthermore, by providing the conductor 260d in the same process as the formation of the conductor 260, charge-up of the conductor 260 can be suppressed. Therefore, electrostatic breakdown of the insulator arranged between the conductor 260 and the oxide 230 can be prevented.

[0144] 5A, the transistor 200 is adjacent to another transistor 200 in the y direction and adjacent to a dummy element 200d in the x direction. The arrangement of the transistors 200 and the dummy elements 200d is not limited to this. It is sufficient that at least one of the elements adjacent to the transistor 200 is the dummy element 200d.

[0145] As a result, variations in the electrical characteristics of transistors can be suppressed, highly reliable transistors can be provided, and shape abnormalities and electrostatic breakdown of transistors can be suppressed. As a result, yields can be improved, and productivity of semiconductor devices can be increased.

[0146] Note that this embodiment may be implemented by combining the configuration of the semiconductor device described in <Configuration Example 1 of Semiconductor Device> with the configuration of the semiconductor device described in <Configuration Example 2 of Semiconductor Device>. Specifically, the semiconductor device may have at least one of the oxide 230d and the conductor 260d, and the dummy element 200d.

[0147] This embodiment may be implemented in combination with the structure of the semiconductor device described in Embodiment 2. By using the transistor 200 described in Embodiment 2 as the transistor 200 included in the semiconductor device of this embodiment, miniaturization and high integration of the semiconductor device can be achieved. For example, in a cross-sectional view in the channel length direction, the gate electrode of the transistor 200 can have a region with a width of 1 nm to 20 nm.

[0148] In addition to the above, the spacing dimension (pitch) of the oxide 230 is set to 120 nm or less, 90 nm or less, or 75 nm or less. Also, the spacing dimension (pitch) of the conductor 260 is set to 180 nm or less, 120 nm or less, or 105 nm or less. By adopting such a configuration, the transistor density of the semiconductor device can be increased to 1 Tr / μm ２ Above, 10Tr / μm ２ or more, or 100Tr / μm ２ It can be more than that.

[0149] At least part of the structures, methods, and the like described in this embodiment mode can be implemented in appropriate combination with other embodiment modes and examples described in this specification.

[0150] 6A to 40C, an example of a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described. The semiconductor device according to one embodiment of the present invention includes a transistor.

[0151] <Structural Example of Semiconductor Device> The structure of a semiconductor device including a transistor 200 will be described with reference to FIGS. 6A to 6D . FIGS. 6A to 6D are top views and cross-sectional views of a semiconductor device including a transistor 200. FIG. 6A is a top view of the semiconductor device. FIGS. 6B to 6D are cross-sectional views of the semiconductor device. FIG. 6B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 6A and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 6C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 6A and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 6D is a cross-sectional view of a portion indicated by a dashed dotted line A5-A6 in FIG. 6A . Note that some elements are omitted from the top view of FIG. 6A for clarity.

[0152] A semiconductor device of one embodiment of the present invention includes an insulator 212 over a substrate (not shown), an insulator 214 over the insulator 212, a transistor 200 over the insulator 214, an insulator 280 over the transistor 200, an insulator 282 over the insulator 280, an insulator 283 over the insulator 282, an insulator 274 over the insulator 283, and an insulator 285 over the insulators 283 and 274. The insulators 212, 214, 280, 282, 283, 274, and 285 function as interlayer films. The semiconductor device also includes a conductor 240a and a conductor 240b that are electrically connected to the transistor 200 and function as plugs. Note that an insulator 241a is provided in contact with a side surface of the conductor 240a, and an insulator 241b is provided in contact with a side surface of the conductor 240b. Furthermore, a conductor 246a electrically connected to the conductor 240a is provided on the insulator 285 and the conductor 240a, and a conductor 246b electrically connected to the conductor 240b is provided on the insulator 285 and the conductor 240b. The insulator 283 contacts a part of the top surface of the insulator 214, the side surface of the insulator 280, and the side surface and top surface of the insulator 282.

[0153] Insulator 241a is provided in contact with the inner walls of the openings of insulators 280, 282, 283, and 285, and conductor 240a is provided in contact with the side surface of insulator 241a. Insulator 241b is provided in contact with the inner walls of the openings of insulators 280, 282, 283, and 285, and conductor 240b is provided in contact with the side surface of insulator 241b. Each of insulators 241a and 241b has a structure in which a first insulator is provided in contact with the inner wall of the opening, and a second insulator is provided further inward. Conductor 240a has a structure in which a first conductor is provided in contact with the side surface of insulator 241a, and a second conductor is provided further inward. Furthermore, the conductor 240b has a structure in which a first conductor is provided in contact with the side surface of the insulator 241b, and a second conductor is provided further inward. Here, the height of the top surface of the conductor 240a can be made approximately the same as the height of the top surface of the insulator 285 in the region overlapping with the conductor 246a. Furthermore, the height of the top surface of the conductor 240b can be made approximately the same as the height of the top surface of the insulator 285 in the region overlapping with the conductor 246b.

[0154] Although the transistor 200 illustrates a configuration in which the insulators 241a and 241b are stacked with a first insulator and a second insulator, respectively, the present invention is not limited thereto. For example, the insulators 241a and 241b may each be configured as a single layer or a stacked structure of three or more layers. Furthermore, the transistor 200 illustrates a configuration in which the conductors 240a and 240b are stacked with a first conductor and a second conductor, respectively, the present invention is not limited thereto. For example, the conductors 240a and 240b may each be configured as a single layer or a stacked structure of three or more layers. When a structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to the order of formation.

[0155] [Transistor 200] As shown in FIGS. 6A to 6D , the transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductors 205a and 205b) disposed so as to be embedded in the insulator 216, an insulator 222 on the insulator 216 and the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, conductors 242a and 242b on the oxide 230b, an insulator 271a on the conductor 242a, and an oxide 271b on the conductor 242b. The transistor 200 includes an insulator 271b, an insulator 252 located on the oxide 230b and between the conductors 242a and 242b, an insulator 250 on the insulator 252, an insulator 254 on the insulator 250, a conductor 260 (conductors 260a and 260b) located on the insulator 254 and overlapping with part of the oxide 230b, and an insulator 275 located on the insulators 222, 224, the oxide 230a, the oxide 230b, the conductors 242a, 242b, the insulators 271a, and 271b. The transistor 200 also includes an insulator 244a located between the conductor 242a and the insulator 252 and an insulator 244b located between the conductor 242b and the insulator 252.

[0156] In the following, the oxide 230a and the oxide 230b may be collectively referred to as the oxide 230. The conductor 242a and the conductor 242b may be collectively referred to as the conductor 242. The insulator 271a and the insulator 271b may be collectively referred to as the insulator 271.

[0157] The insulator 280 is located on the insulator 275. Therefore, it can be said that the insulator 280 is located above the conductor 242a and the conductor 242b. Openings that reach the oxide 230b are provided in the insulator 280 and the insulator 275. In other words, it can be said that the openings are between the conductors 242a and 242b and have a region that overlaps with the oxide 230b. Furthermore, it can be said that the insulator 275 has an opening that overlaps with the opening in the insulator 280. Furthermore, the insulators 252, 250, 254, and conductor 260 are arranged within the openings. In other words, the conductor 260 has a region that overlaps with the oxide 230b via the insulators 252, 250, and 254. Furthermore, the conductor 260, the insulator 252, the insulator 250, and the insulator 254 are provided between the insulator 271a and the conductor 242a and between the insulator 271b and the conductor 242b in the channel length direction of the transistor 200. The insulator 254 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260.

[0158] The conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode. The insulators 252, 250, and 254 function as first gate insulators, and the insulators 222 and 224 function as second gate insulators. The gate insulators may also be referred to as a gate insulating layer or a gate insulating film. The conductor 242a functions as one of a source electrode and a drain electrode, and the conductor 242b functions as the other of the source electrode and the drain electrode. At least a part of a region of the oxide 230 that overlaps with the conductor 260 functions as a channel formation region.

[0159] To miniaturize or highly integrate transistors, it is necessary to thin the gate insulator. However, as the gate insulator becomes thinner, problems such as an increase in the parasitic capacitance between the source electrode and the gate electrode, and between the drain electrode and the gate electrode, and an increase in the leakage current between the source electrode and the gate electrode, and between the drain electrode and the gate electrode, may occur.

[0160] Therefore, in this embodiment, an insulator 244a is provided between the conductor 242a functioning as one of the source electrode and the drain electrode and the conductor 260 functioning as the top gate electrode, and an insulator 244b is provided between the conductor 242b functioning as the other of the source electrode and the drain electrode and the conductor 260. By providing the insulators 244a and 244b, the distance between the conductor 242a and the conductor 260 and the distance between the conductor 242b and the conductor 260 can be increased, and the parasitic capacitance between the conductor 242a and the conductor 260 and the parasitic capacitance between the conductor 242b and the conductor 260 can be reduced. Therefore, the switching speed of the transistor 200 can be improved, and the transistor can have high frequency characteristics.

[0161] In the transistor 200, a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide 230 including the channel formation region.

[0162] The band gap of the metal oxide functioning as a semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. Use of a metal oxide with a wide band gap can reduce the off-state current of a transistor.

[0163] In the oxide 230, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, and the source and drain regions preferably have high carrier concentrations and are n-type. Such a structure makes it possible to provide a semiconductor device with excellent electrical characteristics. In the oxide 230, at least a portion of the channel formation region overlaps with the conductor 260. In other words, the channel formation region is provided in a region between the conductor 242a and the conductor 242b. One of the source and drain regions overlaps with the conductor 242a, and the other of the source and drain regions overlaps with the conductor 242b.

[0164] In a transistor using an oxide semiconductor, impurities and oxygen vacancies are likely to exist in a channel formation region of the oxide semiconductor, which may cause fluctuations in electrical characteristics and decrease reliability. Ｏ H) and generate electrons that become carriers. Ｏ When H is formed, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may vary. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to have normally-on characteristics. Therefore, in the channel formation region of the oxide semiconductor, impurities, oxygen vacancies, and V Ｏ It is preferable that H is reduced as much as possible.

[0165] In response to this problem, an insulator containing excess oxygen is provided near the oxide semiconductor and heat treatment is performed, whereby oxygen is supplied from the insulator to the oxide semiconductor, and oxygen vacancies and V Ｏ H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor may decrease. Furthermore, if the amount of oxygen supplied to the source region or the drain region varies within the substrate surface, the characteristics of a semiconductor device including the transistor may vary. Furthermore, if oxygen supplied from the insulator to the oxide semiconductor diffuses into a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor may be oxidized, and the conductivity may be impaired, which may adversely affect the electrical characteristics and reliability of the transistor.

[0166] From the above, in the channel formation region, oxygen vacancies and V Ｏ It is preferable to reduce H. Therefore, it is preferable to supply oxygen to the channel formation region and prevent excessive oxygen from being supplied to the source region and the drain region. Furthermore, it is preferable to suppress the diffusion of hydrogen into the channel formation region.

[0167] <Relationship Between Donor Concentration and Threshold Voltage Variation> This section describes how the electrical characteristics of a transistor change when the donor concentration in the channel formation region of the transistor is changed. In particular, the relationship between the donor concentration in the channel formation region and the variation in threshold voltage is described using the results of device simulation. Specifically, the Id-Vg characteristics of the transistor were calculated using a device simulator when the donor concentration in the semiconductor layer of the transistor was changed.

[0168] The device simulation was performed using a device simulator Atlas3D manufactured by Silvaco, Inc. In the device simulation, a transistor structure corresponding to Fig. 6A to Fig. 6D was used.

[0169] In the above device simulation, the donor concentration Nd in the channel formation region is set to 1×10 １０ cm −３ , 1 x 10 １５ cm −３ , 1 x 10 １６ cm −３ , 1×10 １７ cm −３ , 1×10 １８ cm −３ , 5 x 10 １８ cm −３ , or 1 × 10 １９ cm −３ The donor concentration in the source region and the donor concentration in the drain region were set to 1×10 ２０ cm −３ It was decided.

[0170] In the device simulation, the Id-Vg characteristics were calculated when the back gate voltage was set to 0V and the drain voltage Vd was set to 1.2V.

[0171] The results of the device simulation are shown in Fig. 7. In Fig. 7, the vertical axis represents the drain current Id [A], and the horizontal axis represents the gate voltage Vg and the donor concentration Nd of the channel formation region (1 × 10 １０ cm −３ The difference in threshold voltage (Vsh) when １０ cm −３)) [V]. Here, the threshold voltage (Vsh) is defined as the gate voltage Vg when the drain current becomes 1 pA.

[0172] From FIG. 7, the donor concentration Nd in the channel forming region is 1×10 １０ cm −３ Id-Vg characteristics when １５ cm −３ and 1×10 １６ cm −３ Furthermore, it can be observed that as the donor concentration Nd in the channel formation region increases, the threshold voltage shifts in the negative direction.

[0173] The above is an explanation of the relationship between the donor concentration in the channel forming region and the variation in threshold voltage.

[0174] To supply oxygen to the channel formation region, it is preferable to use an insulator that is easily permeable to oxygen as the insulator 250. It is also preferable to use an insulator containing excess oxygen as the insulator 280. With this structure, oxygen contained in the insulator 280 can be supplied to the channel formation region of the oxide 230 through the insulator 250.

[0175] The insulator 250 can be, for example, silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat. In this case, the insulator 250 contains at least oxygen and silicon.

[0176] It is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 be reduced.

[0177] The thickness of the insulator 250 is preferably 1 nm to 20 nm, more preferably 0.5 nm to 15 nm. In particular, to manufacture a miniaturized transistor (e.g., a transistor with a gate length of 10 nm or less), the thickness of the insulator 250 is preferably 0.5 nm to 10 nm, more preferably 0.5 nm to 5 nm. In this case, it is sufficient that at least a portion of the insulator 250 has a region with the above thickness.

[0178] The insulator 250 is provided in contact with the upper surface of the insulator 252 .

[0179] It is preferable to use an insulator containing excess oxygen as the insulator 280. For example, it is preferable to use an oxide containing silicon, such as silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide with vacancies, for the insulator 280. Silicon oxide and silicon oxynitride are particularly preferable because they are thermally stable. Furthermore, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferable because they can easily form a region containing oxygen that is released by heating.

[0180] Since the insulator 280 functions as an interlayer film, it is preferable that the insulator 280 has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. The above-mentioned oxide containing silicon is preferable because it is a material with a low dielectric constant.

[0181] It is preferable that the concentration of impurities such as water and hydrogen in insulator 280 be reduced.

[0182] The insulator 280 is provided on the insulator 275 and has openings in the regions where the insulators 252, 250, 254, and conductor 260 are provided. The top surface of the insulator 280 may be planarized.

[0183] If an excessive amount of oxygen is supplied to the channel formation region of the oxide 230, the source and drain regions may be excessively oxidized through the channel formation region, which may result in a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200.

[0184] Therefore, it is preferable to provide an insulator 252 having a barrier property against oxygen between the insulator 250 and the oxide 230b. The insulator 252 is provided in contact with the bottom surface of the insulator 250, the top surface of the oxide 230b, and the side surface of the oxide 230b. The insulator 252 having a barrier property against oxygen can supply oxygen contained in the insulator 250 to the channel formation region and prevent excessive supply of oxygen contained in the insulator 250 to the channel formation region. This can prevent excessive supply of oxygen to the source and drain regions through the channel formation region, which would result in a decrease in the on-state current or field-effect mobility of the transistor 200. Furthermore, oxygen can be prevented from being released from the oxide 230 during heat treatment or the like, thereby preventing the formation of oxygen vacancies in the oxide 230. As a result, the electrical characteristics and reliability of the transistor 200 can be improved.

[0185] Furthermore, the insulator 252 is provided between the insulator 280 and the insulator 250 and has a region in contact with the sidewall of the opening of the insulator 280. With this configuration, oxygen contained in the insulator 280 can be supplied to the insulator 250, and excessive supply of oxygen contained in the insulator 280 to the insulator 250 can be suppressed.

[0186] The insulator 252 preferably contains an oxide of one or both of aluminum and hafnium. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, aluminum oxide is used as the insulator 252. In this case, the insulator 252 contains at least oxygen and aluminum. Note that the insulator 252 only needs to be less permeable to oxygen than the insulator 250, for example. Alternatively, the insulator 252 may be made of a material that is less permeable to oxygen than the insulator 250, for example. Alternatively, the insulator 252 may be made of, for example, magnesium oxide, gallium oxide, gallium zinc oxide, or indium gallium zinc oxide, for example.

[0187] It is preferable that the thickness of the insulator 252 be thin. If the thickness of the insulator 252 is too thick, the amount of oxygen supplied to the oxide 230 through the insulator 250 decreases. Specifically, the thickness of the insulator 252 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and less than 3.0 nm. In this case, the insulator 252 only needs to have a region with the above-mentioned thickness in at least a portion. For example, it is preferable that the thickness of the insulator 252 be thinner than the thickness of the insulator 250 in a region. In this case, the insulator 252 only needs to have a region with a thickness thinner than the insulator 250 in at least a portion.

[0188] To thin the insulator 252 as described above, it is preferable to form the film using the ALD method. The ALD method includes a thermal ALD method in which a precursor and a reactant react using only thermal energy, and a plasma enhanced ALD method in which a plasma excited reactant is used. The PEALD method may be preferable because it uses plasma, which allows film formation at a lower temperature.

[0189] The ALD method can deposit atoms layer by layer, and therefore has the advantages of enabling the formation of extremely thin films, the formation of films on structures with high aspect ratios, the formation of films with few defects such as pinholes, the formation of films with excellent coverage, the formation of films at low temperatures, etc. Therefore, the insulator 252 can be formed with good coverage on the side surfaces of openings formed in the insulator 280 or the like, and with the thin film thickness as described above.

[0190] Note that some precursors used in the ALD method contain carbon and the like. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the quantity of impurities can be determined using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0191] Reducing the thickness of the insulator 252 enables miniaturization of the transistor 200. This is because the insulator 252, together with the insulator 254, the insulator 250, and the conductor 260, is provided in an opening formed in the insulator 280 or the like. With the above structure, a semiconductor device that can be miniaturized or highly integrated can be provided.

[0192] Furthermore, the insulator 252 is provided between the insulator 250 and the conductor 242a, and between the insulator 250 and the conductor 242b. By thinning the film thickness of the insulator 252, the side surface of the conductor 242a is oxidized to form the insulator 244a. Similarly, the side surface of the conductor 242b is oxidized to form the insulator 244b. In other words, the transistor 200 has the insulator 244a located between the conductor 242a and the insulator 252, and the insulator 244b located between the conductor 242b and the insulator 252.

[0193] Note that the lengths of the insulators 244a and 244b in the channel length direction can be controlled by adjusting the film thickness of the insulator 252. For example, increasing the film thickness of the insulator 252 reduces the amount of oxygen contained in the insulator 250 that diffuses into the conductors 242a and 242b, suppressing oxidation of the side surfaces of the conductors 242a and 242b and reducing the lengths of the insulators 244a and 244b in the channel length direction. This can suppress a decrease in the on-state current or a decrease in field-effect mobility of the transistor 200.

[0194] Although the details will be described later, the insulators 244a and 244b are formed in a self-aligned manner when the conductors 242a and 242b are formed or in a process after the conductors 242a and 242b are formed. Therefore, the parasitic capacitance between the conductors 242a and 260 and the parasitic capacitance between the conductors 242b and 260 can be reduced in a self-aligned manner.

[0195] Furthermore, the insulator 244a contains oxygen as well as the elements contained in the conductor 242a. Similarly, the insulator 244b contains oxygen as well as the elements contained in the conductor 242b. For example, when a material containing a metal element is used as the conductors 242a and 242b, the insulators 244a and 244b each contain the metal element and oxygen. For example, when a conductive material containing a metal element and nitrogen is used as the conductors 242a and 242b, the insulators 244a and 244b each contain the metal element, oxygen, and nitrogen.

[0196] In order to suppress diffusion of hydrogen into the channel formation region, an insulator having a function of suppressing diffusion of hydrogen is preferably provided near the oxide 230. In the semiconductor device described in this embodiment, the insulator is, for example, the insulator 252 and the insulator 254.

[0197] Aluminum oxide, which can be suitably used as the insulator 252, has the function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules). Therefore, impurities such as hydrogen contained in the insulator 250 can be prevented from diffusing into the oxide 230. Note that the insulator 252 may be made of any material that is less permeable to hydrogen than the insulator 250, for example. The insulator 252 may be made of any material that is less permeable to hydrogen than the insulator 250, for example.

[0198] The insulator 254 preferably has a barrier property against hydrogen. This can prevent impurities such as hydrogen contained in the conductor 260 from diffusing into the insulator 250 and the oxide 230. The insulator 254 may be, for example, silicon nitride formed by a PEALD method. In this case, the insulator 254 contains at least nitrogen and silicon. The insulator 254 may also be, for example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, or silicon nitride oxide. Note that the insulator 254 may be less permeable to hydrogen than the insulator 250, for example. The insulator 254 may be, for example, a material less permeable to hydrogen than the insulator 250, for example.

[0199] The insulator 254 may further have a barrier property against oxygen. The insulator 254 is provided between the insulator 250 and the conductor 260. Therefore, oxygen contained in the insulator 250 can be prevented from diffusing into the conductor 260, and oxidation of the conductor 260 can be suppressed. Furthermore, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Note that the insulator 254 may be, for example, less permeable to oxygen than the insulator 250. Furthermore, the insulator 254 may be made of a material that is, for example, less permeable to oxygen than the insulator 250.

[0200] The insulator 254, together with the insulator 252, the insulator 250, and the conductor 260, needs to be provided in an opening formed in the insulator 280 or the like. To miniaturize the transistor 200, it is preferable that the insulator 254 be thin. The thickness of the insulator 254 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, the insulator 254 only needs to have a region with the above-described thickness in at least a portion thereof. Furthermore, it is preferable that the thickness of the insulator 254 is thinner than the thickness of the insulator 250. In this case, it is preferable that the insulator 254 only needs to have a region with a thickness thinner than the insulator 250 in at least a portion thereof.

[0201] Here, FIG. 8 shows an enlarged view of the vicinity of the channel formation region in FIG. 6B. As shown in FIG. 8, the length of the insulator 244a in the channel length direction is defined as length D1. Note that length D1 is also the distance from the conductor 242a to the insulator 252 in a cross-sectional view in the channel length direction. Length D1 is also the distance from the side surface of the conductor 242a to the surface of the insulator 252 that contacts the insulator 244a. For example, length D1 is defined as the difference between the position of the interface between the conductor 242a and the insulator 244a and the position of the interface between the insulator 244a and the insulator 252. Furthermore, the length of the insulator 244b in the channel length direction is equal to or approximately equal to length D1.

[0202] The length D1 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, or 10 nm or less. Alternatively, the length D1 is preferably greater than or equal to the film thickness of the insulator 252 and less than or equal to the distance from the conductor 260 to the oxide 230. Here, the distance from the conductor 260 to the oxide 230b refers to, for example, the distance from the bottom surface of the conductor 260a to the top surface of the oxide 230b in a cross-sectional view in the channel length direction. Note that the distance from the conductor 260 to the oxide 230b is also the sum of the film thicknesses of the insulator 252, the insulator 250, and the insulator 254. In other words, the distance from the conductor 260 to the oxide 230b can also be considered the physical film thickness of the first gate insulator. With this configuration, the transistor 200 can obtain good electrical characteristics.

[0203] The length D1 may be measured by observing the cross-sectional shape of the insulator 244a and its surrounding area using a transmission electron microscope (TEM) or the like.

[0204] Furthermore, the length D1 can sometimes be calculated by performing a line analysis of the composition of the insulator 244a and its surroundings using energy dispersive X-ray spectroscopy (EDX). For example, to calculate the length D1, first, an EDX line analysis is performed with the channel length direction as the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth (position) of the interface between the insulator 244a and the insulator 252 is set to the depth at which the quantitative value of an element that is the main component of the insulator 252 but is not the main component of the conductor 242a is half-value. Furthermore, the depth (position) of the interface between the conductor 242a and the insulator 244a is set to the depth at which the quantitative value of oxygen is half-value. From the above, the length D1 can be calculated.

[0205] 8 , the oxide 230b includes a region 230bc that functions as a channel formation region of the transistor 200, and regions 230ba and 230bb that are provided on either side of the region 230bc and function as source and drain regions. The region 230bc at least partially overlaps with the conductor 260. In other words, the region 230bc is provided in a region between the conductor 242a and the conductor 242b. The region 230ba is provided overlapping with the conductor 242a, and the region 230bb is provided overlapping with the conductor 242b.

[0206] The region 230bc has fewer oxygen vacancies or a lower impurity concentration than the regions 230ba and 230bb, and is therefore a high-resistivity region with a low carrier concentration. Therefore, the region 230bc can be said to be i-type (intrinsic) or substantially i-type.

[0207] Furthermore, regions 230ba and 230bb are regions with a high carrier concentration and low resistance due to a large number of oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements. That is, regions 230ba and 230bb are n-type regions with a high carrier concentration and low resistance compared to region 230bc.

[0208] Here, the carrier concentration of the region 230bc is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ The lower limit of the carrier concentration of the region 230bc that functions as a channel formation region is not particularly limited, but is preferably, for example, 1×10 −９ cm −３ It can be said that:

[0209] The transistor 200 includes the insulator 244a, which results in the formation of a region 230bd in the oxide 230b below the insulator 244a. The region 230bd has a carrier concentration equal to or lower than that of the region 230ba and equal to or higher than that of the region 230bc. The region 230bd is located between the regions 230bc and 230ba, and therefore functions as a junction or offset region between the regions 230bc and 230ba. The region 230bd may have a hydrogen concentration equal to or lower than that of the region 230ba and equal to or higher than that of the region 230bc. Similarly, the transistor 200 includes the insulator 244b, which results in the formation of a region 230be in the oxide 230b below the insulator 244b. Like the region 230bd, the region 230be functions as a junction region or an offset region between the regions 230bc and 230bb.

[0210] Furthermore, because region 230bd is located below insulator 244a, oxygen contained in insulator 250 and the like may be supplied to region 230bd via insulator 244a. Therefore, region 230bd may have oxygen vacancies equal to or less than those in region 230ba and equal to or more than those in region 230bc. Similarly, region 230be may have oxygen vacancies equal to or less than those in region 230bb and equal to or more than those in region 230bc.

[0211] 8 shows an example in which the regions 230ba, 230bb, 230bc, 230bd, and 230be are formed in the oxide 230b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in the oxide 230b but also in the oxide 230a.

[0212] Furthermore, it may be difficult to clearly detect the range of each region in the oxide 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not necessarily vary stepwise from region to region, but may also vary continuously within each region. In other words, it is sufficient that the concentrations of impurity elements such as hydrogen and nitrogen decrease in regions closer to the channel formation region.

[0213] 6C , the insulator 252 is provided in contact with the top surface and side surfaces of the oxide 230b, the side surfaces of the oxide 230a, the side surfaces of the insulator 224, and the top surface of the insulator 222. In other words, the regions of the oxide 230a, the oxide 230b, and the insulator 224 that overlap with the conductor 260 are covered with the insulator 252 in a cross section in the channel width direction. The insulator 252 also has a region in contact with the side surface of the insulator 271a, a region in contact with the side surface of the insulator 271b, and a region in contact with the side wall of the opening of the insulator 275.

[0214] By using the above structure, the region 230bc functioning as a channel formation region can be made i-type or substantially i-type, and the regions 230ba and 230bb functioning as source and drain regions can be made n-type. Furthermore, the parasitic capacitance between the conductor 260 and the conductor 242a and the parasitic capacitance between the conductor 260 and the conductor 242b can be reduced in a self-aligned manner. Therefore, a semiconductor device with excellent electrical characteristics can be provided. Furthermore, by using the above structure, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. For example, even when the gate length is 20 nm or less, 15 nm or less, 10 nm or less, or 7 nm or less, and 1 nm or more, 3 nm or more, or 5 nm or more, excellent electrical characteristics can be obtained. The gate length will be described later.

[0215] Furthermore, miniaturization of the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved. When the gate length is within any of the above ranges, the cutoff frequency of the transistor can be set to 50 GHz or higher, or 100 GHz or higher, for example, in a room temperature environment.

[0216] When aluminum oxide is used as the insulator 252, silicon oxide or silicon oxynitride is used as the insulator 250, and silicon nitride is used as the insulator 254, the insulators 252 and 250 each contain oxygen, and the insulators 250 and 254 each contain silicon. When the adjacent layers contain a common element as a main component, the density of defect states at the interface between the layers can be reduced. Therefore, carrier traps due to the defect states are suppressed, and a highly reliable transistor 200 and semiconductor device with favorable characteristics can be manufactured.

[0217] Furthermore, when titanium nitride or tantalum nitride is used as the conductor 260 a, the insulator 254 and the conductor 260 a each contain nitrogen. With this structure, as described above, the transistor 200 and the semiconductor device can be manufactured with favorable characteristics and high reliability.

[0218] Note that the oxide 230b contains oxygen as a main component, which can reduce the density of defect states at the interface between the oxide 230b and the insulator 252. Therefore, carrier trapping due to the defect states can be suppressed, and the transistor 200 and the semiconductor device having favorable characteristics and high reliability can be manufactured.

[0219] In a cross-sectional view in the channel length direction, the bottom surface of the conductor 260a is preferably located between the bottom surface and the top surface of the conductor 242a. This structure makes it easier for the electric field of the conductor 260 to act on the channel formation region of the oxide 230b. This increases the on-state current of the transistor 200 and improves its frequency characteristics. Depending on the thickness of the gate insulator or the amount of the upper portion of the oxide 230b removed, the bottom surface of the conductor 260a may be located below the bottom surface of the conductor 242a or above the top surface of the conductor 242a in a cross-sectional view in the channel length direction.

[0220] Here, the gate length will be explained.

[0221] 9A shows an enlarged view of the vicinity of the channel formation region in FIG. 6B. FIG. 9A is a cross-sectional view in the channel length direction of the transistor 200. As described above, the insulator 252, the insulator 250, and the insulator 254 function as a first gate insulator.

[0222] Hereinafter, the insulators 252, 250, and 254 may be collectively referred to as an insulator 256. In this case, the insulator 256 includes the insulator 252, the insulator 250 over the insulator 252, and the insulator 254 over the insulator 250. The insulator 256 also functions as a first gate insulator.

[0223] 9B is a cross-sectional view in which the insulators 252, 250, and 254 shown in FIG. 9A are replaced with an insulator 256. For simplicity of the drawing, the conductor 260 is shown as a single layer in FIG. 9B. As described above, the conductor 260 may have a layered structure of the conductor 260a and the conductor 260b, or may have a layered structure of three or more layers.

[0224] 9A and 9B is the width of the bottom surface of the conductor 260 in the region overlapping with the oxide 230b in a cross-sectional view in the channel length direction. Hereinafter, the bottom surface of the conductor 260 in the region overlapping with the oxide 230b in a cross-sectional view in the channel length direction may be simply referred to as the bottom surface of the conductor 260 in the region overlapping with the oxide 230b. In other words, the bottom surface of the conductor 260 in the region overlapping with the oxide 230b described below may be interpreted as the bottom surface of the conductor 260 in the region overlapping with the oxide 230b in a cross-sectional view in the channel length direction.

[0225] The gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region during transistor operation, and refers to the width of the bottom surface of the gate electrode in a top view of the transistor. In this specification, the gate length is defined as the width of the bottom surface of the conductor 260 in a region overlapping with the oxide 230b in a cross-sectional view in the channel length direction. That is, the gate length is the width Lg shown in FIGS. 9A and 9B . Note that the conductor 260 is provided inside an opening formed by the insulators 275 and 280. The sidewalls of the openings are perpendicular to the substrate surface or inclined with respect to the substrate surface. In particular, when the angle between the sidewalls of the openings and the substrate surface is 90° or less, the minimum width of the conductor 260 in the region overlapping with the oxide 230b is the width Lg. Therefore, it can be said that the conductor 260 has a region with a width Lg in a cross-sectional view in the channel length direction.

[0226] The bottom surface of the conductor 260 in the region overlapping with the oxide 230b preferably has a flat region. As shown in Figures 9A and 9B, when the bottom surface of the conductor 260 in the region overlapping with the oxide 230b has a flat region, the width Lg is the width of the flat region. By having the bottom surface of the conductor 260 in the region overlapping with the oxide 230b have a flat region, a uniform electric field can be generated in the channel formation region of the oxide 230.

[0227] 9A and 9B show a configuration in which the bottom surface of the conductor 260 in the region overlapping with the oxide 230b has a flat region, but the present invention is not limited to this. In a cross-sectional view in the channel length direction, the bottom surface of the conductor 260 in the region overlapping with the oxide 230b may have a curved shape.

[0228] FIG. 9C shows a modification of the transistor 200 shown in FIG. 9B . FIG. 9C is a cross-sectional view of the transistor 200 in the channel length direction. For example, as shown in FIG. 9C , the bottom surface of the conductor 260 overlapping with the oxide 230b may have a flat region and a curved region. The curved regions are located at both ends of the bottom surface. Here, the point where the curve of the bottom surface on the conductor 242a side contacts the side surface of the conductor 260 on the conductor 242a side is defined as point Qa. The point where the curve of the bottom surface on the conductor 242b side contacts the side surface of the conductor 260 on the conductor 242b side is defined as point Qb. In this configuration, the width Lg is the length of the line segment connecting point Qa and point Qb.

[0229] FIG. 9D shows a modified example of the transistor 200 shown in FIG. 9B . FIG. 9D is a cross-sectional view of the transistor 200 in the channel length direction. For example, as shown in FIG. 9D , the conductor 260 may have an arc-shaped bottom surface. Note that the center of curvature P of the arc is located within the conductor 260, and the arc has a radius r. In such a configuration, the width Lg is the width of a region where the conductor 260 overlaps with a line that includes the center of curvature P and is parallel to the bottom surface of the oxide 230b in the cross-sectional view in the channel length direction. In other words, the width Lg is twice the radius r. Note that the dashed line in FIG. 9D is a line that includes the center of curvature P and is parallel to the bottom surface of the oxide 230b.

[0230] 9D , if the radius r is large (for example, if the radius r is larger than the channel length), the distance from the center of curvature P to the channel formation region of the oxide 230b becomes large. In this case, the width Lg shown in FIG. 9C may be applied as the gate length of the shape. In other words, points Qa and Qb may be determined for the shape of the bottom surface of the conductor 260 shown in FIG. 9D , and the width Lg may be calculated.

[0231] Furthermore, it may be difficult to determine points Qa and Qb in the shape of the bottom surface of the conductor 260 shown in Fig. 9C. In this case, the width Lg shown in Fig. 9D may be applied as the gate length of the shape. In other words, the center of curvature P may be determined for the shape of the bottom surface of the conductor 260 shown in Fig. 9C, and the width Lg may be calculated.

[0232] The above is the explanation of the gate length. Next, the channel length will be explained.

[0233] The insulator 244a has lower conductivity than the conductor 242a, and the insulator 244b has lower conductivity than the conductor 242b. Therefore, when the transistor 200 includes the insulator 244a and the insulator 244b, the distance between the bottom end of the conductor 242a and the bottom end of the conductor 242b can be considered as the channel length, as shown in FIGS. 9A to 9D . In other words, the formation of the insulators 244a and 244b can increase the channel length. This improves the source-drain breakdown voltage of the transistor 200, resulting in a highly reliable transistor. Therefore, even when the transistor is miniaturized, favorable electrical characteristics can be obtained. Note that the distance between the bottom end of the conductor 242a and the bottom end of the conductor 242b is defined as the distance L.

[0234] The channel length is set according to the material used for the conductor 260, the gate length, and the material and film thickness used for the first gate insulator. When the gate length is in any of the above ranges, the channel length may be, for example, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less, and may be 5 nm or more, 10 nm or more, 15 nm or more, or 20 nm or more.

[0235] The length D1 of the insulator 244a in the channel length direction is preferably smaller than the width Lg and preferably falls within any of the above ranges. With this configuration, the transistor 200 can have good electrical characteristics even when the gate length is within any of the above ranges. Note that if the width Lg is very small (for example, less than 5 nm), the length D1 may be larger than the width Lg.

[0236] When forming openings in the insulator 280 and the insulator 275, the upper portion of the oxide 230b in the region overlapping with the openings may be removed. In this case, as shown in Figure 9E, the film thickness of the oxide 230b in the region overlapping with the conductor 260 is smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242a. Note that the transistor 200 shown in Figure 9E is a modified example of the transistor 200 shown in Figure 9B. Figure 9E is a cross-sectional view of the transistor 200 in the channel length direction.

[0237] 9E, the difference between the film thickness of the oxide 230b in the region overlapping with the conductor 260 and the film thickness of the oxide 230b in the region overlapping with the conductor 242a is defined as the difference Lt. If the difference Lt is small, the distance L may be regarded as the channel length.

[0238] As a result, a semiconductor device with good reliability can be provided. Also, a semiconductor device with good electrical characteristics can be provided. Also, a semiconductor device that can be miniaturized or highly integrated can be provided. Also, a semiconductor device with good electrical characteristics and that can be miniaturized or highly integrated can be provided.

[0239] In this embodiment, in a state where the conductors 242a and 242b are provided on the oxide 230b, microwave treatment is performed in an atmosphere containing oxygen, and oxygen vacancies in the region 230bc and V Ｏ The microwave treatment is to be described in detail later in the section <Method for manufacturing a semiconductor device>.

[0240] At least one of the insulators 212, 214, 271, 275, 282, 283, and 285 preferably functions as a barrier insulating film that suppresses impurities such as water and hydrogen from diffusing into the transistor 200 from the substrate side or from above the transistor 200. Therefore, at least one of the insulators 212, 214, 271, 275, 282, 283, and 285 preferably suppresses diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (e.g., copper atoms ...

[0241] In this specification, a barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0242] For the insulators 212, 214, 271, 275, 282, 283, and 285, it is preferable to use insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable to use silicon nitride, which has a higher hydrogen barrier property, for the insulators 212, 275, and 283. Furthermore, it is preferable to use aluminum oxide or magnesium oxide, which has a high function of capturing and fixing hydrogen, for the insulators 214, 271, 282, and 285. This can suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through the insulators 212 and 214. Alternatively, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film disposed outside the insulator 285 toward the transistor 200 via the insulators 283 and 282. Alternatively, oxygen contained in the insulator 224 or the like can be prevented from diffusing toward the substrate via the insulators 212 and 214. Alternatively, oxygen contained in the insulator 280 or the like can be prevented from diffusing upward from the transistor 200 via the insulator 282. In this way, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 271, 275, 282, 283, and 285, which have the function of preventing the diffusion of impurities such as water and hydrogen, and oxygen.

[0243] Here, it is preferable to use an oxide having an amorphous structure as the insulators 212, 214, 271, 275, 282, 283, and 285. For example, AlO ｘ (x is any number greater than 0), or MgO ｙ(y is an arbitrary number greater than 0) is preferably used. In such a metal oxide having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, hydrogen contained in the transistor 200 or hydrogen present around the transistor 200 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 200. By using a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, a highly reliable transistor 200 and a semiconductor device can be manufactured.

[0244] Furthermore, the insulators 212, 214, 271, 275, 282, 283, and 285 preferably have an amorphous structure, but may have a polycrystalline structure region formed in a portion thereof. Furthermore, the insulators 212, 214, 271, 275, 282, 283, and 285 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, they may have a stacked structure in which a polycrystalline layer is formed on an amorphous layer.

[0245] The insulators 212, 214, 271, 275, 282, 283, and 285 can be formed by, for example, a sputtering method. Sputtering does not require the use of molecules containing hydrogen in the film formation gas, and therefore can reduce the hydrogen concentrations of the insulators 212, 214, 271, 275, 282, 283, and 285. Note that the film formation method is not limited to sputtering, and CVD, MBE, PLD, ALD, or the like may also be used as appropriate.

[0246] It may also be preferable to reduce the resistivity of the insulators 212, 275, and 283. For example, it may be preferable to reduce the resistivity of the insulators 212, 275, and 283 to approximately 1×10 １３ By setting the resistivity to Ωcm, the insulators 212, 275, and 283 may be able to reduce charge-up of the conductor 205, the conductor 242, the conductor 260, the conductor 246a, or the conductor 246b in a process using plasma or the like in a semiconductor device manufacturing process. The resistivity of the insulators 212, 275, and 283 is preferably 1×10 １０ Ωcm or more 1×10 １５ Ωcm or less.

[0247] The insulators 216, 274, 280, and 285 preferably have a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, silicon oxide, silicon oxynitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like can be used as appropriate for the insulators 216, 274, 280, and 285.

[0248] The conductor 205 is arranged to overlap the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216. In addition, a part of the conductor 205 may be embedded in the insulator 214.

[0249] The conductor 205 includes a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and sidewall of the opening. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the height of the upper surface of the conductor 205b is the same as or approximately the same as the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216.

[0250] Here, the conductor 205a is composed of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２It is preferable to use a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0251] By using a conductive material for the conductor 205a that has the function of reducing hydrogen diffusion, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulators 216 and 224. Furthermore, by using a conductive material for the conductor 205a that has the function of suppressing oxygen diffusion, it is possible to suppress oxidation of the conductor 205b and a decrease in conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, it is preferable to use the above conductive materials in a single layer or a stacked layer for the conductor 205a. For example, titanium nitride may be used for the conductor 205a.

[0252] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0253] The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to when no negative potential is applied.

[0254] Furthermore, the electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. Furthermore, the film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby reducing the diffusion of the impurities into the oxide 230.

[0255] As shown in FIG. 6A , the conductor 205 is preferably larger than the area of ​​the oxide 230 that does not overlap with the conductors 242 a and 242 b. In particular, as shown in FIG. 6C , the conductor 205 preferably extends to an area outside the end of the oxide 230 in the channel width direction. That is, outside the side surface of the oxide 230 in the channel width direction, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator. With this structure, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is referred to as a surrounded channel (S-channel) structure.

[0256] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like is different from the Fin structure and the planar structure. On the other hand, the S-channel structure disclosed in this specification and the like can also be regarded as a type of Fin structure. In this specification and the like, the Fin structure refers to a structure in which the gate electrode is disposed so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By employing the Fin structure and the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to obtain a transistor in which the short channel effect is less likely to occur.

[0257] By configuring the transistor 200 as a normally-off transistor and having the above-described S-channel structure, the channel formation region can be electrically surrounded. Note that the S-channel structure electrically surrounds the channel formation region, and therefore can be said to be substantially equivalent to a Gate All Around (GAA) structure or a Lateral Gate All Around (LGAA) structure. By configuring the transistor 200 as an S-channel structure, a GAA structure, or an LGAA structure, the channel formation region formed at or near the interface between the oxide 230 and the gate insulator can be the entire bulk of the oxide 230. Therefore, the current density flowing through the transistor can be improved, which is expected to result in an improvement in the on-state current of the transistor or an improvement in the field-effect mobility of the transistor.

[0258] 6B illustrates an example of a transistor with an S-channel structure, but the semiconductor device of one embodiment of the present invention is not limited to this. For example, the transistor structure that can be used in one embodiment of the present invention may be one or more selected from a planar structure, a Fin structure, and a GAA structure.

[0259] 6C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Furthermore, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0260] Note that although the conductor 205 in the transistor 200 has a stacked structure of the conductor 205a and the conductor 205b, the present invention is not limited to this. For example, the conductor 205 may have a single layer structure or a stacked structure of three or more layers.

[0261] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules). The insulator 222 also preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0262] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. Alternatively, an oxide containing hafnium and zirconium, such as hafnium zirconium oxide, is preferably used. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the oxide 230 to the substrate and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, the insulator 222 can suppress the diffusion of impurities such as hydrogen into the oxide 230 and the generation of oxygen vacancies in the oxide 230. Furthermore, the conductor 205 can be prevented from reacting with the insulator 224 and the oxygen contained in the oxide 230.

[0263] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on the insulator. For example, the insulator 222 may have a two-layer structure in which silicon nitride and silicon oxide are stacked in this order, or a three-layer structure in which silicon nitride, silicon oxide, and aluminum oxide are stacked in this order.

[0264] The insulator 222 may be a single layer or a multilayer insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium zirconium oxide. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinner gate insulators. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. The insulator 222 may be made of lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), (Ba,Sr)TiO ３ In some cases, a material with a high dielectric constant such as (BST) can be used.

[0265] The insulator 224 in contact with the oxide 230 may be made of, for example, silicon oxide, silicon oxynitride, or the like as appropriate.

[0266] One or both of the insulators 222 and 224 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials. The insulator 224 may be formed in an island shape by overlapping with the oxide 230a. In this case, the insulator 275 is configured to contact the side surface of the insulator 224 and the top surface of the insulator 222.

[0267] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, boron, silicon, vanadium, beryllium, copper, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or cobalt) can be used as the oxide 230. It is particularly preferable to use a metal oxide containing indium, zinc, and one or more elements selected from gallium, aluminum, and tin. Note that, for example, In—Ga oxide, In—Zn oxide, or indium oxide may also be used as the oxide 230.

[0268] The oxide 230 preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to the metal element that is the main component is preferably larger than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 230b. Also, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. This configuration can suppress the diffusion of impurities and oxygen from structures formed below the oxide 230a to the oxide 230b.

[0269] In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. With this structure, the transistor 200 can have a large on-state current and high frequency characteristics.

[0270] Furthermore, since the oxide 230 a and the oxide 230 b contain a common element other than oxygen as a main component, the defect state density at the interface between the oxide 230 a and the oxide 230 b can be reduced, which reduces the effect of interface scattering on carrier conduction, and the transistor 200 can achieve a large on-state current and high frequency characteristics.

[0271] Specifically, the oxide 230a may be a metal oxide having an atomic ratio of In:M:Zn = 1:3:4 or a similar composition, an atomic ratio of In:M:Zn = 1:3:2 or a similar composition, or an atomic ratio of In:M:Zn = 1:1:0.5 or a similar composition. The oxide 230b may be a metal oxide having an atomic ratio of In:M:Zn = 1:1:1 or a similar composition, an atomic ratio of In:M:Zn = 1:1:1.2 or a similar composition, an atomic ratio of In:M:Zn = 1:1:2 or a similar composition, an atomic ratio of In:M:Zn = 4:2:3 or a similar composition, or an atomic ratio of In:M:Zn = 5:1:3 or a similar composition. Note that the term "similar compositions" includes a range of ±30% of the desired atomic ratio. Moreover, it is preferable to use gallium or aluminum as the element M.

[0272] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0273] Note that when the transistor 200 is used in, for example, a pixel circuit of a display device, part of light emitted from a light-emitting element of the display device (stray light) may enter the transistor 200. In this case, the stray light may deteriorate transistor characteristics and adversely affect pixel operation.

[0274] The amount of degradation of transistor characteristics due to stray light can be evaluated using, for example, the amount of change in the threshold voltage or the amount of change in the shift voltage (Vsh) of a transistor measured in a negative bias temperature illumination stress (NBTIS) test. The shift voltage (Vsh) is defined as the Vg at which the tangent to the maximum slope of the drain current (Id)-gate voltage (Vg) curve of the transistor intersects with the line where Id = 1 pA. Here, degradation in which the threshold voltage or Vsh of a transistor changes in the NBTIS test is sometimes referred to as negative bias light degradation.

[0275] For the above reasons, when the transistor 200 is used in, for example, a pixel circuit of a display device, it is preferable that the transistor 200 be less susceptible to the effects of stray light. For example, it is preferable that the transistor 200 be less susceptible to degradation of transistor characteristics due to stray light. Specifically, it is preferable that the transistor 200 be highly resistant to the NBTIS test (that is, that negative bias light degradation is reduced).

[0276] Therefore, when the transistor 200 is used, for example, in a pixel circuit of a display device, the metal oxide functioning as a semiconductor of the transistor 200 preferably has a band gap of 3.1 eV or more, and even more preferably 3.3 eV or more. The energy of light having a wavelength of 400 nm or more is 3.1 eV or less. In other words, even if light having a wavelength of 400 nm or more is incident on the metal oxide, electrons in the valence band are less likely to be excited to the conduction band. Therefore, by using a metal oxide having a larger band gap in the channel formation region of the transistor, it is possible to improve the resistance to the NBTIS test. In other words, by using a metal oxide having a larger band gap in the channel formation region of the transistor, the influence of stray light can be reduced without providing a light-shielding layer or the like, and degradation of the transistor characteristics can be suppressed.

[0277] Specifically, as oxide 230, a metal oxide having a composition of In:M:Zn=2:6:5 [atomic ratio] or thereabout, a metal oxide having a composition of In:M:Zn=1:3:4 [atomic ratio] or thereabout, a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or thereabout, or a metal oxide having a composition of In:M:Zn=1:4:5 [atomic ratio] or thereabout may be used.

[0278] For example, when describing a composition with an atomic ratio of In:M:Zn=2:6:5 or thereabout, this includes a case where M is 4 or more and 8 or less, and Zn is 3 or more and 7.5 or less, when In is taken as 2. Furthermore, when describing a composition with an atomic ratio of In:M:Zn=1:1:1 or thereabout, this includes a case where M is more than 0.1 and 2 or less, and Zn is more than 0.1 and 2 or less, when In is taken as 1.

[0279] The band gap of the metal oxide can be evaluated using one or more of optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy for chemical analysis (XPS or ESCA), X-ray absorption fine structure (XAFS), and the like.

[0280] The composition of the metal oxide can be evaluated using inductively coupled plasma mass spectrometry (ICP-MS), XPS, scanning electron microscopy (SEM)-energy dispersive X-ray spectroscopy (EDX), SIMS, or the like.

[0281] The oxide 230b preferably has crystallinity. In particular, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 230b.

[0282] CAAC-OS is a metal oxide having a highly crystalline and dense structure and few impurities and defects (e.g., oxygen vacancies). In particular, by performing heat treatment at a temperature (e.g., 400° C. or higher and 600° C. or lower) at which the metal oxide is not polycrystallized after formation of the metal oxide, the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0283] Furthermore, since it is difficult to identify clear crystal boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to crystal boundaries is unlikely to occur. Therefore, metal oxides having CAAC-OS have stable physical properties. Therefore, metal oxides having CAAC-OS are heat-resistant and highly reliable.

[0284] Furthermore, by using a crystalline oxide such as CAAC-OS as the oxide 230b, the conductor 242a or the conductor 242b can suppress the extraction of oxygen from the oxide 230b. Therefore, even when heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process. Furthermore, the conductivity of the conductors 242a and 242b can be suppressed from decreasing.

[0285] 6C , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as a rounded shape).

[0286] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. By using such a shape, the coverage of the insulator 252, the insulator 250, the insulator 254, and the conductor 260 with the oxide 230b can be improved.

[0287] When aluminum oxide is used as the insulator 252, aluminum may be added to the region of the oxide 230b that is in contact with the insulator 252 and its vicinity. Note that the addition of aluminum to the region of the oxide 230b that is in contact with the insulator 252 and its vicinity occurs during processes subsequent to the formation of the insulating film, such as the formation of an insulating film that becomes the insulator 252, the formation of a film on the insulating film, or heat treatment performed after the formation of the insulating film.

[0288] 10A to 10D are schematic diagrams showing the aluminum concentration profiles in the insulator 252 and the oxide 230 in the depth direction. In each of the diagrams, the vertical axis represents the aluminum (Al) concentration, and the horizontal axis represents the depth. Note that the depth can be rephrased as the film thickness.

[0289] 10A to 10D indicate the lower limit of detection of aluminum concentration when a metal oxide not containing aluminum is used as the oxide 230 before aluminum is added. Also, when a metal oxide containing aluminum is used as the oxide 230 before aluminum is added, the dotted lines in FIGS. 10A to 10D indicate the aluminum concentration of the oxide 230 near the insulator 224.

[0290] 10A to 10D, the oxide 230 has a concentration gradient in which the aluminum concentration increases from the bottom surface of the oxide 230 toward the top surface of the oxide 230. In other words, the oxide 230 has a concentration gradient in which the aluminum concentration increases toward the insulator 252 in the film thickness direction.

[0291] 10A, oxide 230 may have a region where the aluminum concentration monotonically decreases from a peak at the interface between insulator 252 and oxide 230, and a region where the aluminum concentration is constant. In this case, the region where the aluminum concentration monotonically decreases is located closer to insulator 252 than the region where the aluminum concentration is constant.

[0292] 10B , the oxide 230 may have a first region in which the aluminum concentration monotonically decreases from a peak at the interface between the insulator 252 and the oxide 230, and a second region in which the aluminum concentration monotonically decreases, where the first region is located closer to the insulator 252 than the second region.

[0293] 10C , oxide 230 may have a region where the aluminum concentration exponentially decreases from a peak at the interface between insulator 252 and oxide 230, and a region where the aluminum concentration is constant. In this case, the region where the aluminum concentration exponentially decreases is located closer to insulator 252 than the region where the aluminum concentration is constant.

[0294] Also, the oxide 230 may have an aluminum concentration that peaks at the interface between the insulator 252 and the oxide 230 and then decreases exponentially, as shown in FIG. 10D.

[0295] Adding aluminum to the region of the oxide 230b that is in contact with the insulator 252 and its vicinity can suppress the formation of oxygen vacancies in the region and its vicinity. Because a channel is likely to form in the region of the oxide 230b and its vicinity, this structure can reduce oxygen vacancies in the channel formation region. Therefore, fluctuations in the electrical characteristics of the transistor 200 can be suppressed, and variations in the electrical characteristics of the transistor 200 within the substrate surface can be suppressed. When an In-M-Zn oxide is used as the oxide 230b before aluminum is added, the oxide 230b contains at least indium (In), aluminum (Al), and zinc (Zn). The oxide 230b also contains indium (In), the element M, aluminum (Al), and zinc (Zn).

[0296] Furthermore, by providing the insulator 252 containing aluminum oxide or the like in contact with the top surface and side surface of the oxide 230, indium contained in the oxide 230 may be unevenly distributed at and near the interface between the oxide 230 and the insulator 252. As a result, the atomic ratio near the surface of the oxide 230 becomes close to that of indium oxide or In—Zn oxide. The increase in the atomic ratio of indium near the surface of the oxide 230, particularly the oxide 230b, can improve the field-effect mobility of the transistor 200.

[0297] Note that in the transistor 200, the oxide 230 has a two-layer structure of the oxide 230a and the oxide 230b, but the present invention is not limited to this. For example, a single layer of the oxide 230a, a single layer of the oxide 230b, or a stacked structure of three or more layers may be provided, or each of the oxide 230a and the oxide 230b may have a stacked structure.

[0298] Conductor 242a and conductor 242b are provided in contact with the top surface of oxide 230b.

[0299] It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductors 242a and 242b. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductors 242a and 242b. When a conductive material containing a metal element and nitrogen is used as the conductors 242a and 242b, the conductors 242a and 242b contain at least a metal element and nitrogen.

[0300] For example, it is preferable to use a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum as the conductor 242a and the conductor 242b. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when they absorb oxygen.

[0301] Note that hydrogen contained in the oxide 230b and the like may diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b and the like is likely to diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b and the like may be absorbed by the conductor 242a or the conductor 242b.

[0302] Preferably, no curved surface is formed between the side surface of the conductor 242 and the top surface of the conductor 242. The conductor 242 having no curved surface can increase the cross-sectional area of ​​the conductor 242 in the cross section in the channel width direction, as shown in Figure 6D. This can increase the conductivity of the conductor 242 and the on-state current of the transistor 200.

[0303] Furthermore, when heat treatment is performed while the conductor 242a and the oxide 230b are in contact with each other, the sheet resistance of the oxide 230b in the region overlapping with the conductor 242a may decrease. The carrier concentration may also increase. Therefore, the resistance of the oxide 230b in the region overlapping with the conductor 242a can be reduced in a self-aligned manner. Similarly, when heat treatment is performed while the conductor 242b and the oxide 230b are in contact with each other, the sheet resistance of the oxide 230b in the region overlapping with the conductor 242b may decrease. The carrier concentration may also increase. Therefore, the resistance of the oxide 230b in the region overlapping with the conductor 242b can be reduced in a self-aligned manner.

[0304] The conductors 242a and 242b are preferably formed using a conductive film having compressive stress. This allows strain (hereinafter sometimes referred to as tensile strain) that expands in the tensile direction to be formed in the regions 230ba and 230bb. The tensile strain causes V Ｏ By stably forming H, regions 230ba and 230bb can become stable n-type regions. The compressive stress of conductor 242a is a stress that attempts to relax the compressed shape of conductor 242a, and is a stress with a vector in the direction from the center to the end of conductor 242a. The same applies to the compressive stress of conductor 242b.

[0305] The magnitude of the compressive stress of the conductor 242a may be, for example, 500 MPa or more, preferably 1000 MPa or more, more preferably 1500 MPa or more, and even more preferably 2000 MPa or more. The magnitude of the stress of the conductor 242a may be determined by preparing a sample in which the conductive film used for the conductor 242a is formed on a substrate and measuring the stress of the sample. The same applies to the magnitude of the compressive stress of the conductor 242b.

[0306] Strain is formed in each of the regions 230ba and 230bb due to the action of compressive stresses of the conductors 242a and 242b. The strain is a strain (tensile strain) that is expanded in the tensile direction due to the action of compressive stresses of the conductors 242a and 242b. When the regions 230ba and 230bb have a CAAC structure, the strain corresponds to elongation in a direction perpendicular to the c-axis of the CAAC structure. When the CAAC structure elongates in a direction perpendicular to the c-axis of the CAAC structure, oxygen vacancies are likely to be formed in the strain. In addition, hydrogen is likely to be taken up in the strain, so V Ｏ Therefore, in this strain, oxygen vacancies and V Ｏ H is easily formed and these easily take a stable structure. As a result, the regions 230ba and 230bb become stable n-type regions with high carrier concentrations.

[0307] Although the above description has been made on the distortion formed in the oxide 230b, the present invention is not limited to this. Similar distortion may be formed in the oxide 230a.

[0308] In one embodiment of the present invention, it is particularly preferable to use a nitride containing tantalum or a nitride containing titanium as the conductors 242 a and 242 b. In this case, the conductors 242 a and 242 b contain tantalum or titanium and nitrogen.

[0309] Here, Fig. 11 shows a graph in which various films were provided on a substrate and stress was measured. In Fig. 11, the horizontal axis represents stress [MPa]. When the stress is positive, the film has tensile stress, and when the stress is negative, the film has compressive stress.

[0310] In FIG. 11 , PVD-W is a tungsten film formed by sputtering. CVD-TiNx\CVD-W is a stacked film of a titanium nitride film formed by CVD and a tungsten film formed thereon by CVD. PVD-TaNx is a tantalum nitride film formed by sputtering. IGZO is an In—Ga—Zn oxide film formed by sputtering using an oxide target with an In:Ga:Zn=1:1:1.2 [atomic ratio]. PVD-SiOx is a silicon oxide film formed by sputtering. PVD-AlOx is an aluminum oxide film formed by sputtering. PVD-SiNx is a silicon nitride film formed by sputtering. PEALD-SiOx is a silicon oxide film formed by PEALD. PEALD-SiNx is a silicon nitride film formed by the PEALD method, APCVD-SiOx is a silicon oxide film formed by the atmospheric pressure CVD (APCVD) method, and ALD-AlOx is an aluminum oxide film formed by the thermal ALD method.

[0311] 11, the stress of PVD-TaNx is negative and has a large absolute value, which means that PVD-TaNx has a significantly large compressive stress and is suitable for use as conductors 242a and 242b.

[0312] 6A to 6D, the conductor 242 is shown as a single layer, but the present invention is not limited to this and may have a stacked structure of two or more layers. For example, as shown in FIG. 12A, the conductor 242a may have a two-layer stacked structure of a conductor 242a1 and a conductor 242a2 on the conductor 242a1, and the conductor 242b may have a two-layer stacked structure of a conductor 242b1 and a conductor 242b2 on the conductor 242b1. In this case, the conductors 242a1 and 242b1 are arranged on the side in contact with the oxide 230b.

[0313] In the following, the conductors 242a1 and 242b1 may be collectively referred to as the lower layer of the conductor 242. The conductors 242a2 and 242b2 may be collectively referred to as the upper layer of the conductor 242.

[0314] The lower layer of the conductor 242 (conductor 242a1 and conductor 242b1) is preferably made of a conductive material that is resistant to oxidation. This prevents the lower layer of the conductor 242 from oxidizing and reducing the conductivity of the conductor 242. The lower layer of the conductor 242 may also have the property of easily absorbing (extracting) hydrogen. This allows hydrogen from the oxide 230 to diffuse into the lower layer of the conductor 242, reducing the hydrogen concentration in the oxide 230. This allows the transistor 200 to have stable electrical characteristics.

[0315] Furthermore, the upper layer of the conductor 242 (conductor 242a2 and conductor 242b2) is preferably made of a conductive material having higher conductivity than the lower layer of the conductor 242 (conductor 242a1 and conductor 242b1). In this case, the upper layer of the conductor 242 only needs to have a region with higher conductivity than the lower layer of the conductor 242 in at least a portion. Alternatively, the upper layer of the conductor 242 is preferably made of a conductive material having lower resistivity than the lower layer of the conductor 242. This makes it possible to manufacture a semiconductor device in which wiring delay is suppressed.

[0316] The upper layer of the conductor 242 may have a property of easily absorbing hydrogen. This allows hydrogen absorbed into the lower layer of the conductor 242 to diffuse into the upper layer of the conductor 242, further reducing the hydrogen concentration in the oxide 230. This allows the transistor 200 to have stable electrical characteristics.

[0317] Here, it is preferable that the lower layer and the upper layer of the conductor 242 are made of conductive materials that have the same constituent elements but different chemical compositions. In this case, the lower layer and the upper layer of the conductor 242 can be formed successively without being exposed to the atmospheric environment. By forming the layers without being exposed to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the surface of the lower layer of the conductor 242, and it is possible to keep the vicinity of the interface between the lower layer of the conductor 242 and the upper layer of the conductor 242 clean.

[0318] It is also preferable to use a tantalum-containing nitride having a high atomic ratio of nitrogen to tantalum for the lower layer of the conductor 242, and a tantalum-containing nitride having a low atomic ratio of nitrogen to tantalum for the upper layer of the conductor 242. For example, a tantalum-containing nitride having a nitrogen-to-tantalum atomic ratio of 1.0 to 2.0, preferably 1.1 to 1.8, and more preferably 1.2 to 1.5, is used for the lower layer of the conductor 242. Furthermore, for example, a tantalum-containing nitride having a nitrogen-to-tantalum atomic ratio of 0.3 to 1.5, preferably 0.5 to 1.3, and more preferably 0.6 to 1.0, is used for the upper layer of the conductor 242.

[0319] In a tantalum-containing nitride, increasing the atomic ratio of nitrogen to tantalum can suppress oxidation of the tantalum-containing nitride. Furthermore, the oxidation resistance of the tantalum-containing nitride can be improved. Furthermore, the diffusion of oxygen into the tantalum-containing nitride can be suppressed. Therefore, it is preferable to use a tantalum-containing nitride with a high atomic ratio of nitrogen to tantalum for the lower layer of the conductor 242. This can prevent the formation of an oxide layer between the lower layer of the conductor 242 and the oxide 230, or can reduce the thickness of the oxide layer.

[0320] Furthermore, in a nitride containing tantalum, the resistivity of the nitride can be reduced by lowering the atomic ratio of nitrogen to tantalum. Therefore, it is preferable to use a nitride containing tantalum with a low atomic ratio of nitrogen to tantalum as the upper layer of the conductor 242. This makes it possible to manufacture a semiconductor device with reduced wiring delay.

[0321] By forming the lower layer of the conductor 242 from a conductive material that is resistant to oxidation and forming the upper layer of the conductor 242 from a conductive material that is more conductive than the lower layer of the conductor 242, as shown in FIG. 12A , the insulators 244a and 244b each have regions with different lengths in the channel length direction. Here, the distance from the lower layer of the conductor 242 to the insulator 252 is length D2, and the distance from the upper layer of the conductor 242 to the insulator 252 is length D3. In this case, it can be said that the insulators 244a and 244b each have a first region with a length D2 in the channel length direction and a second region above the first region with a length D3 in the channel length direction. With this configuration, it is possible to reduce the parasitic capacitance between the conductor 242a and the conductor 260 and the parasitic capacitance between the conductor 242b and the conductor 260, and to prevent the channel length from increasing. Therefore, the switching speed of the transistor 200 can be improved, and the transistor 200 can have high frequency characteristics. In addition, a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200 can be suppressed.

[0322] 12A illustrates a configuration in which the lengths of the insulators 244a and 244b in the channel length direction are discontinuous at the boundary between the upper layer of the conductor 242 and the lower layer of the conductor 242. However, as shown in FIG. 12B, the lengths of the insulators 244a and 244b in the channel length direction may change continuously at the boundary between the upper layer of the conductor 242 and the lower layer of the conductor 242. In this case, in a cross-sectional view, the side surface of the insulator 244a in contact with the conductor 242a is curved. Similarly, in a cross-sectional view, the side surface of the insulator 244b in contact with the conductor 242b is curved. Even with this configuration, the parasitic capacitance between the conductor 242a and the conductor 260 and the parasitic capacitance between the conductor 242b and the conductor 260 can be reduced, and an increase in the channel length can be suppressed.

[0323] Even if the conductor 242a is a single layer, the side surface of the insulator 244a in contact with the conductor 242a may have a curved shape. Similarly, even if the conductor 242b is a single layer, the side surface of the insulator 244b in contact with the conductor 242b may have a curved shape.

[0324] It should be noted that it may be difficult to clearly detect the boundary between the upper and lower layers of the conductor 242. When a nitride containing tantalum is used for the conductor 242, the tantalum and nitrogen concentrations detected in each layer are not limited to a stepwise change in each layer, but may also change continuously (also called a gradation) in the region between the upper and lower layers. In other words, the closer to the oxide 230 in the region of the conductor 242, the higher the atomic ratio of nitrogen to tantalum should be. Therefore, it is preferable that the atomic ratio of nitrogen to tantalum in the region located below the conductor 242 be higher than the atomic ratio of nitrogen to tantalum in the region located above the conductor 242.

[0325] The film thickness of the lower layer of the conductor 242 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that at least a portion of the lower layer of the conductor 242 has a region with the above-mentioned film thickness. It is also preferable that the film thickness of the lower layer of the conductor 242 is thinner than the film thickness of the upper layer of the conductor 242. In this case, it is sufficient that at least a portion of the lower layer of the conductor 242 has a region with a film thickness thinner than the upper layer of the conductor 242.

[0326] In addition, an example has been shown in which the lower layer of conductor 242 and the upper layer of conductor 242 are made of conductive materials that are the same in constituent elements but have different chemical compositions, but this is not limited to this, and the lower layer of conductor 242 and the upper layer of conductor 242 may be made of different conductive materials.

[0327] The configurations of the lower layer and upper layer of the conductor 242 are not limited to those described above. For example, the lower layer and upper layer of the conductor 242 may differ in one or more of the constituent elements, chemical composition, and film formation conditions. For example, a nitride containing tantalum may be used as the lower layer of the conductor 242, and a nitride containing titanium may be used as the upper layer of the conductor 242.

[0328] The insulator 271a is provided in contact with the top surface of the conductor 242a, and the insulator 271b is provided in contact with the top surface of the conductor 242b. The insulator 271 preferably functions as a barrier insulating film at least against oxygen. Therefore, the insulator 271 preferably has a function of suppressing oxygen diffusion. For example, the insulator 271 preferably has a function of suppressing oxygen diffusion more than the insulator 280. As the insulator 271, for example, an insulator such as silicon nitride, aluminum oxide, or magnesium oxide may be used.

[0329] The insulator 275 is provided to cover the insulator 224, the oxide 230a, the oxide 230b, the conductor 242a, the conductor 242b, the insulator 271a, and the insulator 271b. Specifically, the insulator 275 has a region in contact with the side surface of the insulator 224, a region in contact with the side surface of the oxide 230a, a region in contact with the side surface of the oxide 230b, a region in contact with the side surface of the conductor 242a, a region in contact with the side surface of the conductor 242b, a region in contact with the side surface and top surface of the insulator 271a, and a region in contact with the side surface and top surface of the insulator 271b.

[0330] The insulator 275 preferably has the function of capturing and fixing hydrogen. In this case, the insulator 275 preferably includes an insulator such as silicon nitride or a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. Alternatively, for example, the insulator 275 may be a stacked film of aluminum oxide and silicon nitride on the aluminum oxide.

[0331] Furthermore, the insulator 275 preferably has barrier properties against oxygen. This can prevent oxygen contained in the insulator 280 from diffusing to the side surface of the conductor 242a in contact with the insulator 275 and the side surface of the conductor 242b in contact with the insulator 275. Therefore, it is possible to prevent the oxygen contained in the insulator 280 from oxidizing the side surface of the conductor 242a in contact with the insulator 275 and the side surface of the conductor 242b in contact with the insulator 275, which would increase the resistivity and reduce the on-current. Note that the insulator 275 may be made of a material that is less permeable to oxygen than the insulator 280, for example. The insulator 275 may be made of a material that is less permeable to oxygen than the insulator 280, for example.

[0332] By providing the insulators 271 and 275 as described above, the conductor 242 can be wrapped in an insulator that has a barrier property against oxygen. In other words, it is possible to prevent oxygen contained in the insulator 280 from diffusing into the conductor 242. This makes it possible to suppress the conductor 242 from being directly oxidized by the oxygen contained in the insulator 280, which would increase the resistivity and reduce the on-current.

[0333] The insulator 250 functions as part of a gate insulator. Although the insulator 250 is shown as a single layer in FIGS. 6A to 6D and the like, the present invention is not limited thereto and may have a stacked structure of two or more layers. For example, as shown in FIG. 13A , the insulator 250 may have a two-layer stacked structure of an insulator 250 a and an insulator 250 b on the insulator 250 a.

[0334] As shown in FIG. 13A , when the insulator 250 has a two-layer stacked structure, it is preferable that the insulator 250a be formed using an insulator that is easily permeable to oxygen, and the insulator 250b be formed using an insulator that has a function of suppressing oxygen diffusion. This structure can suppress the diffusion of oxygen contained in the insulator 250a into the conductor 260. That is, it can suppress a decrease in the amount of oxygen supplied to the oxide 230. It can also suppress oxidation of the conductor 260 due to the oxygen contained in the insulator 250a. For example, the insulator 250a may be formed using a material that can be used for the insulator 250 described above, and the insulator 250b may be an insulator containing oxides of one or both of aluminum and hafnium. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, hafnium oxide is used as the insulator 250b. In this case, the insulator 250b contains at least oxygen and hafnium. The thickness of the insulator 250b is 0.5 nm to 5.0 nm, preferably 1.0 nm to 5.0 nm, and more preferably 1.0 nm to 3.0 nm. In this case, the insulator 250b only needs to have a region with the above thickness in at least a portion thereof.

[0335] When silicon oxide or silicon oxynitride is used for the insulator 250a, the insulator 250b may be an insulating material that is a high-k material with a high dielectric constant. By forming the gate insulator into a layered structure of the insulators 250a and 250b, a thermally stable layered structure with a high dielectric constant can be achieved. This allows the gate potential applied during transistor operation to be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced. This allows the dielectric strength of the insulator 250 to be increased.

[0336] 13A , when the insulator 250 has a two-layer stacked structure, by using an insulator such as hafnium oxide that has a function of suppressing the permeation of impurities such as hydrogen and oxygen as the insulator 250b, the insulator 250b can also function as the insulator 254. In such a case, by not providing the insulator 254, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0337] The conductor 260 functions as the first gate electrode of the transistor 200. The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b. As shown in FIGS. 6B and 6C , the top surface of the conductor 260 is flush or approximately flush with the top surfaces of the insulators 254, 250, 252, and 280. Note that although the conductor 260 is shown as having a two-layer structure of the conductors 260a and 260b in FIGS. 6B and 6C , it may have a single-layer structure or a stacked structure of three or more layers.

[0338] The conductor 260a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0339] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress the conductor 260b from being oxidized by the oxygen contained in the insulator 250 and thereby suppress a decrease in conductivity. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. When titanium nitride or tantalum nitride is used as the conductor 260a, the conductor 260a contains titanium or tantalum and nitrogen.

[0340] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0341] Furthermore, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably disposed in the region between the conductor 242 a and the conductor 242 b without alignment.

[0342] 6C , in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in a region that does not overlap with the oxide 230b, relative to the bottom surface of the insulator 222, is preferably lower than the height of the bottom surface of the oxide 230b. When the conductor 260, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, the electric field of the conductor 260 can be easily applied to the entire channel formation region of the oxide 230b. Therefore, the on-state current of the transistor 200 can be increased, and the frequency characteristics can be improved. The difference between the height of the bottom surface of the conductor 260 in a region that does not overlap with the oxide 230b and the height of the bottom surface of the oxide 230b, relative to the bottom surface of the insulator 222, is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0343] Insulator 282 contacts at least a portion of the top surface of each of conductor 260, insulator 252, insulator 250, insulator 254, and insulator 280, as shown in FIG. 6B.

[0344] The insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 280 and preferably has a function of capturing impurities such as hydrogen. The insulator 282 also preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 282 may be an insulator such as a metal oxide having an amorphous structure, such as aluminum oxide. In this case, the insulator 282 contains at least oxygen and aluminum. By providing the insulator 282 in contact with the insulator 280 in the region sandwiched between the insulators 212 and 283 and having a function of capturing impurities such as hydrogen, the insulator 282 can capture impurities such as hydrogen contained in the insulator 280 and maintain a constant amount of hydrogen in the region. In particular, using aluminum oxide having an amorphous structure as the insulator 282 is preferable because it may be able to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 200 and semiconductor device with excellent characteristics.

[0345] Furthermore, the insulator 282 provided on the insulator 280 is preferably formed by a method capable of adding oxygen to the insulator 280. This allows the insulator 280 to contain excess oxygen. The insulator 282 is preferably formed by sputtering, and more preferably by pulsed DC sputtering using an aluminum target in an oxygen-containing atmosphere. Pulsed DC sputtering can be used to achieve a more uniform film thickness distribution and improve the sputtering rate and film quality. Here, RF (radio frequency) power may be applied to the substrate. The amount of oxygen implanted into the layer below the insulator 282 can be controlled by the magnitude of the RF power applied to the substrate. For example, the smaller the RF power, the less oxygen is implanted into the layer below the insulator 282, and the amount of oxygen is likely to saturate even if the insulator 282 is thin. Furthermore, the greater the RF power, the greater the amount of oxygen implanted into the layer below the insulator 282.

[0346] The RF power is, for example, 0 W / cm ２ Over 1.86 W / cm２ That is, the amount of oxygen suitable for the characteristics of the transistor can be changed and injected by changing the RF power when forming the insulator 282. Therefore, the amount of oxygen suitable for improving the reliability of the transistor can be injected.

[0347] The RF frequency is preferably 10 MHz or higher, typically 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate.

[0348] 6A to 6D and the like show a structure in which the insulator 282 is a single layer, the present invention is not limited to this, and the insulator 282 may have a stacked structure of two or more layers. For example, as shown in FIG. 13B , the insulator 282 may have a two-layer stacked structure of an insulator 282 a and an insulator 282 b on the insulator 282 a.

[0349] The insulators 282a and 282b may be formed using the same material but by different methods. For example, when forming the insulator 282 by pulse DC sputtering using an aluminum target in an atmosphere containing oxygen gas, it is preferable that the RF power applied to the substrate when forming the insulator 282a is different from the RF power applied to the substrate when forming the insulator 282b. It is more preferable that the RF power applied to the substrate when forming the insulator 282a is lower than the RF power applied to the substrate when forming the insulator 282b. Specifically, it is preferable that the RF power applied to the substrate when forming the insulator 282a is 0 W / cm ２ 0.62W / cm or more ２ The insulator 282b is formed as follows: ２ More specifically, the insulator 282a is formed under the following conditions: RF power applied to the substrate is 0 W / cm ２ The insulator 282b was formed as a film with an RF power of 0.31 W / cm ２ With this structure, the insulator 282 can have an amorphous structure and the amount of oxygen supplied to the insulator 280 can be adjusted.

[0350] The RF power applied to the substrate when forming the insulator 282a may be higher than the RF power applied to the substrate when forming the insulator 282b. Specifically, the RF power applied to the substrate when forming the insulator 282a may be 1.86 W / cm ２ The insulator 282b is formed as follows: ２ 0.62W / cm or more ２ More specifically, the insulator 282a is deposited under the following conditions: RF power applied to the substrate is 1.86 W / cm ２ The insulator 282b was formed as a film with an RF power of 0.62 W / cm ２ With such a structure, the amount of oxygen supplied to the insulator 280 can be increased.

[0351] The film thickness of the insulator 282a is 1 nm to 20 nm, preferably 1.5 nm to 15 nm, more preferably 2 nm to 10 nm, and even more preferably 3 nm to 8 nm. This configuration allows the insulator 282a to have an amorphous structure regardless of RF power. Furthermore, by making the insulator 282a have an amorphous structure, the insulator 282b is more likely to have an amorphous structure, and the insulator 282 can have an amorphous structure.

[0352] The insulators 282a and 282b described above have a layered structure made of the same material, but the present invention is not limited to this. The insulators 282a and 282b may have a layered structure made of different materials.

[0353] Insulator 283 contacts a portion of the top surface of insulator 214 , the side of insulator 216 , the side of insulator 222 , the side of insulator 275 , the side of insulator 280 , and the side and top surface of insulator 282 .

[0354] The insulator 283 functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 280. The insulator 283 is disposed over the insulator 282. It is preferable to use a nitride containing silicon, such as silicon nitride or silicon nitride oxide, as the insulator 283. For example, silicon nitride formed by a sputtering method may be used as the insulator 283. By forming the insulator 283 by a sputtering method, a high-density silicon nitride film can be formed. Alternatively, the insulator 283 may be formed by stacking a silicon nitride film formed by a PEALD method or a CVD method on a silicon nitride film formed by a sputtering method.

[0355] The conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 240a and 240b may have a layered structure.

[0356] Furthermore, when the conductors 240a and 240b each have a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the first conductors arranged near the insulators 285, 283, 282, 280, 275, and 271. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Furthermore, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 283 from mixing into the oxide 230 through the conductors 240a and 240b.

[0357] The insulators 241a and 241b may be a barrier insulating film that can be used for the insulator 275, for example. For example, the insulators 241a and 241b may be made of an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulators 241a and 241b are provided in contact with the insulators 283, 282, and 271, and thus can prevent impurities such as water and hydrogen contained in the insulator 280 from mixing with the oxide 230 through the conductors 240a and 240b. Silicon nitride is particularly suitable because of its high blocking properties against hydrogen. Furthermore, the oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b.

[0358] When the insulators 241a and 241b are formed into a layered structure as shown in Figure 6B, it is preferable that the first insulator in contact with the inner wall of an opening such as the insulator 280 and the second insulator inside it be made of a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0359] For example, aluminum oxide formed by ALD may be used as the first insulator, and silicon nitride formed by PEALD may be used as the second insulator. This configuration can suppress oxidation of the conductors 240 a and 240 b and further reduce hydrogen contamination of the conductors 240 a and 240 b.

[0360] Furthermore, a conductor 246a that functions as a wiring and is in contact with the upper surface of the conductor 240a, and a conductor 246b that functions as a wiring and is in contact with the upper surface of the conductor 240b may be disposed. The conductors 246a and 246b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors may also have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductors may be formed so as to be embedded in openings provided in an insulator.

[0361] <Constituent Materials of Semiconductor Device> Constituent materials that can be used in the semiconductor device will be described below.

[0362] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0363] <<Insulator>> Examples of insulators include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0364] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current can occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select materials according to the insulator's function.

[0365] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0366] Insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0367] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0368] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0369] <<Conductor>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0370] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0371] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0372] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0373] <<Metal Oxide>> A metal oxide that functions as a semiconductor (oxide semiconductor) is preferably used as the oxide 230. Hereinafter, metal oxides that can be used as the oxide 230 according to the present invention will be described.

[0374] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0375] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, an element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, the element M may be a combination of two or more of the above-mentioned elements. In particular, the element M is preferably one or more selected from gallium, aluminum, yttrium, and tin.

[0376] In particular, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) is preferably used for the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) may be used for the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (IAGZO or IGAZO) may be used for the semiconductor layer.

[0377] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0378] Hereinafter, an oxide containing indium (In), gallium (Ga), and zinc (Zn) will be described as an example of a metal oxide. Note that an oxide containing indium (In), gallium (Ga), and zinc (Zn) may be referred to as an In—Ga—Zn oxide.

[0379] <Classification of Crystal Structure> Examples of the crystal structure of an oxide semiconductor include amorphous (including completely amorphous), c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), cloud-aligned composite (CAC), single crystal, and polycrystalline.

[0380] The crystalline structure of a film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. For example, it can be evaluated using an XRD spectrum obtained by GIXD (Grazing-Incident XRD) measurement. The GIXD method is also called the thin film method or the Seemann-Bohlin method. In the following, the XRD spectrum obtained by GIXD measurement may be simply referred to as the XRD spectrum.

[0381] For example, in the case of a quartz glass substrate, the peak shape of the XRD spectrum is almost symmetrical. On the other hand, in the case of an In-Ga-Zn oxide film having a crystalline structure, the peak shape of the XRD spectrum is asymmetrical. The asymmetrical peak shape of the XRD spectrum clearly indicates the presence of crystals in the film or substrate. In other words, if the peak shape of the XRD spectrum is not symmetrical, the film or substrate cannot be said to be in an amorphous state.

[0382] The crystalline structure of a film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). For example, a halo is observed in the diffraction pattern of a quartz glass substrate, confirming that the quartz glass is in an amorphous state. Furthermore, a spot-like pattern is observed in the diffraction pattern of an In—Ga—Zn oxide film formed at room temperature, rather than a halo. For this reason, it is estimated that the In—Ga—Zn oxide formed at room temperature is neither single crystal nor polycrystalline, nor in an amorphous state, but is in an intermediate state, and it cannot be concluded that it is in an amorphous state.

[0383] <<Structure of Oxide Semiconductor>> Note that oxide semiconductors may be classified differently from the above when focusing on their structures. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0384] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0385] [CAAC-OS] A CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction refers to the thickness direction of the CAAC-OS film, the normal direction to the surface where the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region is also a region with a uniform lattice arrangement. Furthermore, a CAAC-OS has a region where multiple crystalline regions are connected in the a-b plane direction, and the region may have distortion. Note that distortion refers to a portion where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with another uniform lattice arrangement in a region where multiple crystalline regions are connected. In other words, a CAAC-OS is an oxide semiconductor whose c-axes are aligned and whose orientation is not clearly aligned in the a-b plane direction.

[0386] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the maximum diameter of the crystalline region may be several tens of nanometers.

[0387] In an In—Ga—Zn oxide, CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing gallium (Ga), zinc (Zn), and oxygen (hereinafter referred to as a (Ga, Zn) layer) are stacked. Note that indium and gallium are mutually substituted. Therefore, the (Ga, Zn) layer may contain indium. The In layer may contain gallium. The In layer may contain zinc. The layered structure is observed as a lattice image in a high-resolution transmission electron microscope (TEM) image, for example.

[0388] When a CAAC-OS film is subjected to structural analysis using an XRD apparatus, for example, a peak indicating c-axis orientation is detected at or near 2θ = 31° in out-of-plane XRD measurement using θ / 2θ scanning. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0389] For example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film, and the spots are observed at positions that are point-symmetric with respect to a spot of an incident electron beam that has passed through the sample (also referred to as a direct spot).

[0390] When a crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The distortion may also have a pentagonal, heptagonal, or other lattice arrangement. In CAAC-OS, no clear grain boundaries can be identified even near the distortion. This indicates that the distortion in the lattice arrangement suppresses the formation of grain boundaries. This is thought to be because CAAC-OS can tolerate distortion due to the lack of close-packed arrangement of oxygen atoms in the a-b plane and the change in interatomic bond distance caused by metal atom substitution.

[0391] Note that a crystal structure in which clear grain boundaries are observed is called polycrystalline. The grain boundaries act as recombination centers, and are likely to trap carriers, resulting in a decrease in the on-state current of a transistor and a decrease in field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. Note that a structure containing Zn is preferable for forming a CAAC-OS. For example, In—Zn oxide and In—Ga—Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0392] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities, the formation of defects, or the like, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, an oxide semiconductor having the CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having the CAAC-OS is heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, using the CAAC-OS in a transistor having a metal oxide in a channel formation region (sometimes referred to as an OS transistor) can increase the flexibility of the manufacturing process.

[0393] 14A and 14B show TEM images of a CAAC-OS film formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1.2, where Fig. 14A is a cross-sectional TEM image of the CAAC-OS film observed from a direction perpendicular to the c-axis, and Fig. 14B is a planar TEM image of the CAAC-OS film observed from a direction parallel to the c-axis.

[0394] 14A shows a layered structure oriented in the c-axis direction. In addition, in FIG. 14B, hexagonal lattice arrangements are predominant, but non-regular hexagonal lattice arrangements are also partially observed. Thus, the CAAC-OS is an oxide semiconductor that is c-axis aligned and does not clearly have an orientation in the a-b plane direction.

[0395] Next, the distribution of orientations of the hexagonal lattice of the CAAC-OS will be described with reference to FIGS.

[0396] Fig. 15A shows a planar TEM image of a CAAC-OS film formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1.2. Fig. 15B shows a mapping image showing the distribution of hexagonal lattice orientations of the CAAC-OS film. Fig. 15B is a mapping image obtained by image analysis of Fig. 15A.

[0397] The mapping image shown in FIG. 15B was obtained by the following procedure. First, a fast Fourier transform (FFT) was performed on the planar TEM image of FIG. 15A to obtain an FFT image. Next, a masking process was performed, leaving a specific frequency region of the FFT image. Next, an inverse fast Fourier transform (IFFT) process was performed on the masked FFT image to obtain an FFT filtered image. Next, image analysis was performed on the FFT filtered image to extract lattice points. Next, the orientation θ [deg] of the hexagon formed by the six lattice points closest to each lattice point was determined. The orientation θ of the hexagon was determined in the range of 0° to 60°, with the most frequently occurring angle set to 30°. In FIG. 15B, the color shade was set according to the angle of the orientation θ of the hexagon, and mapping was performed.

[0398] 15B, multiple domains of the same color and having a width of about several tens of nanometers are seen. That is, in the CAAC-OS, a structure having a width of about several tens of nanometers and in which the hexagonal lattice orientation is aligned is formed.

[0399] Here, regions A and B, which include the boundary between two structures whose hexagonal lattice orientations are different from each other, are shown in Figure 16. Figure 16A is a planar TEM image of region A, which is an enlarged view of region A in Figure 15A. Figure 16B is an FFT filtered image of region A. Figure 16C is an image in which hexagonal lattice points in region A are extracted from Figure 16B. Figure 16D is a mapping image of region A. Figure 16E is a planar TEM image of region B, which is an enlarged view of region B in Figure 15A. Figure 16F is an FFT filtered image of region B. Figure 16G is an image in which hexagonal lattice points in region B are extracted from Figure 16F. Figure 16H is a mapping image of region B. Note that the dashed lines in Figures 16C, 16D, 16G, and 16H correspond to the boundary between two structures whose hexagonal lattice orientations are different from each other.

[0400] 16D and 16H , the two structures with different hexagonal lattice orientations near the boundary have a small difference in color intensity and a small difference in the orientation of the hexagonal lattice. The boundary between the two structures with different hexagonal lattice orientations appears blurred, and the structures appear to be intertwined. Thus, no clear grain boundaries are observed in the CAAC-OS.

[0401] Next, the distribution of the hexagonal lattice orientation of CAAC-OS films with different film thicknesses and with or without heat treatment will be described with reference to FIGS.

[0402] 17A to 17C show planar TEM images of CAAC-OS films formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1.2. Here, FIG. 17A shows a 5-nm-thick CAAC-OS film, FIG. 17B shows a 10-nm-thick CAAC-OS film, and FIG. 17C shows a 20-nm-thick CAAC-OS film. Also, FIGS. 18A to 18C show mapping images corresponding to FIGS. 17A to 17C. The mapping images shown in FIGS. 18A to 18C, like those in FIG. 15B, show the distribution of the hexagonal lattice orientation of the CAAC-OS film.

[0403] 19A to 19C show mapping images of a CAAC-OS that was further subjected to heat treatment. The heat treatment was performed in a mixed atmosphere of 1 slm of oxygen gas and 4 slm of nitrogen gas at a substrate temperature of 450° C. for 1 hour. The film thicknesses of the CAAC-OS shown in FIGS. 19A to 19C correspond to those shown in FIGS. 17A to 17C, respectively. The mapping images shown in FIGS. 19A to 19C also show the distribution of the orientation of the hexagonal lattice of the CAAC-OS, similar to FIG. 15B.

[0404] 20A to 20C show histograms of Voronoi polygon distributions for CAAC-OS films with different thicknesses. The thicknesses of the CAAC-OS films shown in FIGS. 20A to 20C correspond to those shown in FIGS. 17A to 17C, respectively. Also, in FIGS. 20A to 20C, the histograms of the CAAC-OS films without and after heat treatment are shown side by side.

[0405] 17 to 20 show that as the film thickness of the CAAC-OS increases, the domains with a uniform hexagonal lattice orientation become larger and the angle between the domains changes continuously. Furthermore, heat treatment tends to increase the domain size. From the above, it can be seen that crystallization of the CAAC-OS begins when the film is formed to a certain thickness. It can also be seen that heat treatment promotes the crystallization of the CAAC-OS.

[0406] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. Furthermore, the nc-OS does not exhibit regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scanning. When an nc-OS film is subjected to electron diffraction (also referred to as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of a nanocrystal (e.g., 50 nm or more), a diffraction pattern resembling a halo pattern is observed. On the other hand, when an nc-OS film is subjected to electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter close to or smaller than that of a nanocrystal (e.g., 1 nm to 30 nm), an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0407] [a-Like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0408] <<Structure of Oxide Semiconductor>> Next, the above-described CAC-OS will be described in detail. Note that the CAC-OS relates to a material structure.

[0409] [CAC-OS] CAC-OS is, for example, a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0410] Furthermore, the CAC-OS has a mosaic structure in which a material is separated into a first region and a second region, and the first region is distributed throughout the film (hereinafter also referred to as a cloud structure). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0411] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In—Ga—Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In—Ga—Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0412] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be referred to as a region whose main component is In. The second region can be referred to as a region whose main component is Ga.

[0413] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0414] Furthermore, CAC-OS in In—Ga—Zn oxide refers to a structure in which a mosaic of regions containing Ga as the main component and regions containing In as the main component are randomly arranged in a material composition containing In, Ga, Zn, and O. Therefore, it is presumed that CAC-OS has a structure in which metal elements are distributed nonuniformly.

[0415] The CAC-OS can be formed by sputtering without heating the substrate. When forming the CAC-OS by sputtering, any one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. The lower the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition, the more preferable it is. For example, the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition is set to 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0416] Furthermore, for example, in the case of CAC-OS in an In—Ga—Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) can confirm that the CAC-OS has a structure in which a region containing In as a main component (first region) and a region containing Ga as a main component (second region) are unevenly distributed and mixed.

[0417] Here, the first region has higher conductivity than the second region. That is, the flow of carriers through the first region causes the metal oxide to exhibit conductivity. Therefore, the first region is distributed in a cloud-like manner in the metal oxide, thereby achieving a high field-effect mobility (μ).

[0418] On the other hand, the second region has higher insulating properties than the first region, that is, the second region is distributed in the metal oxide, thereby suppressing the off-state current.

[0419] Therefore, when a CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, thereby providing the CAC-OS with a switching function (a function of turning on / off). That is, a CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and functions as a semiconductor as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using a CAC-OS in a transistor, a high on-current (I ｏｎ ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0420] Furthermore, a transistor using the CAC-OS has high reliability, and therefore, the CAC-OS is ideal for various semiconductor devices such as display devices.

[0421] Oxide semiconductors have a variety of structures, each of which has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0422] <Transistor Having Oxide Semiconductor> Next, a case where the oxide semiconductor is used for a transistor will be described.

[0423] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0424] For the transistor, an oxide semiconductor having a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 １７ cm −３ Below 1 × 10, preferably １５ cm −３ More preferably, 1×10 １３ cm −３ or less, more preferably 1 × 10 １１ cm −３ More preferably, 1×10１０ cm −３ is less than 1×10 −９ cm −３ The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0425] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0426] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0427] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that impurities in an oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0428] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0429] When an oxide semiconductor contains silicon or carbon, which is one of Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, when the concentration of silicon or carbon in the oxide semiconductor (concentration obtained by SIMS) is set to 2×10 １８ atoms / cm ３ Below 2 × 10, preferably １７ atoms / cm３ The following applies.

[0430] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0431] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 １９ atoms / cm ３ Less than 5×10 １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ Do the following:

[0432] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor obtained by SIMS is measured to be 1×10 ２０ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ Make it less than.

[0433] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0434] <<Other Semiconductor Materials>> The oxide 230 can be rephrased as a semiconductor layer including a channel formation region of a transistor. The semiconductor material that can be used for the semiconductor layer is not limited to the metal oxides described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the semiconductor layer. For example, a semiconductor of a single element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also referred to as an atomic layer material, a two-dimensional material, or the like) is preferably used as the semiconductor material. In particular, a layered material that functions as a semiconductor is preferably used as the semiconductor material.

[0435] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0436] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0437] For example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor for the semiconductor layer. Specific examples of transition metal chalcogenides that can be used for the semiconductor layer include molybdenum sulfide (typically, MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0438] <Manufacturing Method of Semiconductor Device> Next, a manufacturing method of the semiconductor device of one embodiment of the present invention shown in FIGS. 6A to 6D will be described with reference to FIGS. 21A to 31D.

[0439] A in each figure shows a top view. B in each figure is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A1-A2 in A of each figure, and is also a cross-sectional view in the channel length direction of the transistor 200. C in each figure is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A3-A4 in A of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. D in each figure is a cross-sectional view of the portion indicated by the dashed dotted line A5-A6 in A of each figure. Note that some elements are omitted from the top view in A of each figure for clarity.

[0440] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be formed as films by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0441] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0442] CVD methods can be classified into plasma CVD, thermal CVD, photo CVD, etc. They can also be further classified into metal CVD and metal organic CVD depending on the source gas used.

[0443] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0444] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0445] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0446] Furthermore, the CVD method allows deposition of a film with any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0447] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0448] First, a substrate (not shown) is prepared, and an insulator 212 is formed on the substrate (see FIGS. 21A to 21D). The insulator 212 is preferably formed by sputtering. By using sputtering, which does not require the use of hydrogen-containing molecules in the film formation gas, the hydrogen concentration in the insulator 212 can be reduced. However, the method for forming the insulator 212 is not limited to sputtering, and CVD, MBE, PLD, ALD, or the like may also be used as appropriate.

[0449] In this embodiment, a silicon nitride film is formed as the insulator 212 by pulsed DC sputtering using a silicon target in an atmosphere containing nitrogen gas. The use of pulsed DC sputtering can suppress particle generation due to arcing on the target surface, resulting in a more uniform film thickness distribution. Furthermore, the use of pulsed voltage can make the rise and fall of discharge steeper than with high-frequency voltage. This allows for more efficient supply of power to the electrodes, improving the sputtering rate and film quality.

[0450] By using an insulator that is impermeable to impurities such as water and hydrogen, such as silicon nitride, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in layers below the insulator 212. Furthermore, by using an insulator that is impermeable to copper, such as silicon nitride, as the insulator 212, even if a metal that easily diffuses, such as copper, is used in a conductor (not shown) below the insulator 212, it is possible to suppress the upward diffusion of the metal through the insulator 212.

[0451] Next, the insulator 214 is deposited on the insulator 212 (see FIGS. 21A to 21D). The insulator 214 is preferably deposited by sputtering. By using sputtering, which does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 214 can be reduced. However, the deposition of the insulator 214 is not limited to sputtering, and CVD, MBE, PLD, ALD, or the like may also be used as appropriate.

[0452] It is preferable to use a metal oxide having an amorphous structure, such as aluminum oxide, which has a high function of capturing and fixing hydrogen, as the insulator 214. This makes it possible to capture or fix hydrogen contained in the insulator 216 or the like and prevent the hydrogen from diffusing into the oxide 230. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 214 is preferable because it may be possible to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 200 and semiconductor device with favorable characteristics.

[0453] In this embodiment, an aluminum oxide film is formed as the insulator 214 by pulsed DC sputtering using an aluminum target in an atmosphere containing oxygen gas. By using pulsed DC sputtering, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. Here, RF power may be applied to the substrate. The amount of oxygen implanted into the layer below the insulator 214 can be controlled by the magnitude of the RF power applied to the substrate. The RF power is set to 0 W / cm. ２ More than 1.86 W / cm ２ The following is true. That is, the amount of oxygen suitable for the characteristics of the transistor can be changed and injected by changing the RF power when forming the insulator 214. Therefore, an amount of oxygen suitable for improving the reliability of the transistor can be injected. The RF frequency is preferably 10 MHz or higher, typically 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate.

[0454] Next, the insulator 216 is deposited over the insulator 214. The insulator 216 is preferably deposited by sputtering. The hydrogen concentration in the insulator 216 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. However, the deposition of the insulator 216 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0455] In this embodiment, a silicon oxide film is formed as the insulator 216 by pulsed DC sputtering using a silicon target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0456] The insulators 212, 214, and 216 are preferably successively deposited without exposure to the atmosphere. For example, a multi-chamber deposition apparatus can be used. This allows the insulators 212, 214, and 216 to be deposited with reduced hydrogen content and further reduces hydrogen contamination between deposition steps.

[0457] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be, for example, a groove or a slit. The region in which the opening is formed may also be referred to as an opening. Wet etching may be used to form the opening, but dry etching is preferable for fine processing. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when etching the insulator 216 to form the groove. For example, when silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove, it is preferable to use silicon nitride, aluminum oxide, or hafnium oxide for the insulator 214.

[0458] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one of the parallel plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used.

[0459] After the opening is formed, a conductive film that becomes the conductor 205a is formed. The conductive film preferably includes a conductor that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film may be a stacked film of a conductor that has a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0460] In this embodiment, titanium nitride is formed as the conductive film that becomes the conductor 205a. By using such a metal nitride as the lower layer of the conductor 205b, it is possible to prevent the conductor 205b from being oxidized by the insulator 216 or the like. Furthermore, even if a metal that easily diffuses, such as copper, is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205a.

[0461] Next, a conductive film to be the conductor 205b is formed. For the conductive film, tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like can be used. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, tungsten is formed as the conductive film.

[0462] Next, a CMP process is performed to remove a portion of the conductive film that will become the conductor 205a and a portion of the conductive film that will become the conductor 205b, thereby exposing the insulator 216 (see FIGS. 21A to 21D). As a result, the conductor 205a and the conductor 205b remain only in the openings. Note that the CMP process may remove a portion of the insulator 216.

[0463] Next, an insulator 222 is formed over the insulator 216 and the conductor 205 (see FIGS. 22A to 22D ). The insulator 222 may contain one or both of aluminum and hafnium oxides. Note that aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator containing one or both of aluminum and hafnium oxides. Alternatively, hafnium zirconium oxide is preferably used. An insulator containing one or both of aluminum and hafnium oxides has barrier properties against oxygen, hydrogen, and water. The insulator 222 having barrier properties against hydrogen and water prevents hydrogen and water contained in structures provided around the transistor 200 from diffusing into the transistor 200 through the insulator 222, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0464] The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. In this embodiment, hafnium oxide is formed as the insulator 222 by an ALD method.

[0465] Subsequently, heat treatment is preferably performed. The heat treatment may be performed at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment may be performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas to compensate for the desorbed oxygen.

[0466] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being taken into the insulator 222 as much as possible.

[0467] In this embodiment, after the insulator 222 is formed, heat treatment is performed at 400° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas set to 4:1. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. When an oxide containing hafnium is used as the insulator 222, the heat treatment may cause part of the insulator 222 to crystallize. The heat treatment can also be performed at a timing such as after the formation of the insulating film that becomes the insulator 224.

[0468] Next, an insulating film 224A is formed on the insulator 222 (see FIGS. 22A to 22D). The insulating film 224A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is formed as the insulating film 224A by a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the film formation gas, the hydrogen concentration in the insulating film 224A can be reduced. Because the insulating film 224A will come into contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration be reduced in this manner.

[0469] Next, oxide films 230A and 230B are sequentially formed on the insulating film 224A (see FIGS. 22A to 22D). It is preferable to form the oxide films 230A and 230B consecutively without exposing them to the atmospheric environment. By forming the films without exposing them to the atmospheric environment, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide films 230A and 230B, and to keep the vicinity of the interface between the oxide films 230A and 230B clean.

[0470] The oxide film 230A and the oxide film 230B can be formed by sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, the oxide film 230A and the oxide film 230B are formed by sputtering.

[0471] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixed gas of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the formed oxide film can be increased. Furthermore, when the oxide film is formed by sputtering, the above-mentioned In-M-Zn oxide target or the like can be used.

[0472] In particular, during the formation of oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.

[0473] When the oxide film 230B is formed by a sputtering method, an oxygen-excess oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, the crystallinity of the oxide film can be improved by forming the oxide film while heating the substrate.

[0474] In this embodiment, the oxide film 230A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 1:3:4. The oxide film 230B is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 4:2:4.1, an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1, an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1.2, or an oxide target with an atomic ratio of In:Ga:Zn = 1:1:2. The oxide films 230a and 230b can be formed according to the desired characteristics by appropriately selecting the film formation conditions and atomic ratios.

[0475] Note that the insulating film 224A, the oxide film 230A, and the oxide film 230B are preferably formed by sputtering without exposure to the atmosphere. For example, a multi-chamber film formation apparatus may be used. This can reduce the incorporation of hydrogen into the insulating film 224A, the oxide film 230A, and the oxide film 230B between film formation steps.

[0476] Next, heat treatment is preferably performed. The heat treatment may be performed within a temperature range in which the oxide films 230A and 230B do not become polycrystallized, such as 250°C to 650°C, preferably 400°C to 600°C. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide films 230A and 230B, thereby reducing oxygen deficiency. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be approximately 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to replenish the desorbed oxygen. Alternatively, heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, followed by heat treatment in a nitrogen gas or inert gas atmosphere.

[0477] By performing oxygen addition treatment on the oxide 230, oxygen vacancies in the oxide 230 can be repaired by the supplied oxygen. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide 230 to convert the hydrogen into H ２ As a result, the hydrogen remaining in the oxide 230 is recombined with the oxygen vacancies to form V. Ｏ The formation of H can be suppressed.

[0478] Furthermore, it is preferable that the gas used in the heat treatment be highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed into the oxide film 230A, the oxide film 230B, and the like as much as possible.

[0479] In this embodiment, the heat treatment is performed at 400° C. for 1 hour with a nitrogen gas / oxygen gas flow ratio of 4:1. This heat treatment using oxygen gas can reduce impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B. Reducing the impurities in the film can improve the crystallinity of the oxide film 230B, resulting in a denser, more compact structure. This increases the crystalline regions in the oxide film 230A and the oxide film 230B, reducing the in-plane variation of the crystalline regions in the oxide film 230A and the oxide film 230B. This reduces the in-plane variation of the electrical characteristics of the transistor 200.

[0480] Furthermore, by performing the heat treatment, hydrogen in the insulator 216, the insulating film 224A, the oxide film 230A, and the oxide film 230B moves to the insulator 222 and is absorbed into the insulator 222. In other words, hydrogen in the insulator 216, the insulating film 224A, the oxide film 230A, and the oxide film 230B diffuses into the insulator 222. Therefore, the hydrogen concentration in the insulator 222 increases, but the hydrogen concentrations in the insulator 216, the insulating film 224A, the oxide film 230A, and the oxide film 230B decrease.

[0481] In particular, the insulating film 224A functions as a gate insulator of the transistor 200, and the oxide film 230A and the oxide film 230B function as a channel formation region of the transistor 200. Therefore, the transistor 200 including the insulating film 224A, the oxide film 230A, and the oxide film 230B in which the hydrogen concentrations are reduced is preferable because it has good reliability.

[0482] Next, a conductive film 242A is formed on the oxide film 230B (see FIGS. 22A to 22D ). The conductive film 242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a tantalum nitride film may be formed as the conductive film 242A by a sputtering method. Note that heat treatment may be performed before the formation of the conductive film 242A. The heat treatment may be performed under reduced pressure, and the conductive film 242A may be formed successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230B can be removed, and the moisture and hydrogen concentrations in the oxide film 230A and the oxide film 230B can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 200° C.

[0483] Next, an insulating film 271A is formed over the conductive film 242A (see FIGS. 22A to 22D). The insulating film 271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 271A is preferably an insulating film that has a function of suppressing oxygen permeation. For example, an aluminum oxide film or a silicon nitride film may be formed by a sputtering method as the insulating film 271A. Alternatively, for example, a silicon nitride film and a silicon oxide film on the silicon nitride film may be formed by a sputtering method as the insulating film 271A.

[0484] Note that the conductive film 242A and the insulating film 271A are preferably formed by sputtering without exposure to the atmosphere. For example, a multi-chamber film formation apparatus may be used. This allows the conductive film 242A and the insulating film 271A to be formed with reduced hydrogen content and further reduces the amount of hydrogen mixed into the films between film formation steps. Furthermore, when a hard mask is provided on the insulating film 271A, the film that becomes the hard mask may also be formed continuously without exposure to the atmosphere.

[0485] Next, the insulating film 224A, the oxide film 230A, the oxide film 230B, the conductive film 242A, and the insulating film 271A are processed into island shapes by lithography to form the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B (see FIGS. 23A to 23D). The insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B are formed so that at least a portion of each overlaps with the conductor 205. This processing can be performed by dry etching or wet etching. Dry etching is suitable for microfabrication. The insulating film 224A, the oxide film 230A, the oxide film 230B, the conductive film 242A, and the insulating film 271A may be processed under different conditions.

[0486] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left using a developer to form a resist mask. Then, etching is performed through the resist mask to process a conductor, semiconductor, or insulator into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. An electron beam or ion beam may also be used instead of the light described above. When an electron beam or ion beam is used, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0487] Furthermore, a hard mask made of an insulator or a conductor may be used under the resist mask. When using a hard mask, an insulating or conductive film serving as a hard mask material is formed on the conductive film 242A, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask with a desired shape. Etching of the conductive film 242A and the like may be performed after removing the resist mask or may be performed while the resist mask is left in place. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the conductive film 242A and the like. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask. In this embodiment, the insulating layer 271B is used as the hard mask.

[0488] Here, because the insulating layer 271B functions as a mask for the conductive layer 242B, the conductive layer 242B does not have a curved surface between its side surface and top surface, as shown in FIGS. 23B to 23D . As a result, the conductors 242a and 242b shown in FIGS. 6B and 6D have angular ends where their side surfaces and top surfaces intersect. Because the angular ends where the side surfaces and top surfaces of the conductor 242 intersect are angular, the cross-sectional area of ​​the conductor 242 is larger than when the ends have a curved surface. This reduces the resistance of the conductor 242, thereby increasing the on-state current of the transistor 200.

[0489] 23B to 23D , the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B may be tapered. In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface. For example, the angle between the inclined side surface and the substrate surface (hereinafter, sometimes referred to as the taper angle) is preferably less than 90°. The side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B may have a taper angle of, for example, 60° or more and less than 90°. Tapering the side surfaces in this manner improves the coverage of the insulator 275 and the like in subsequent processes, reducing defects such as voids.

[0490] However, the present invention is not limited to the above, and the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B may be configured to be approximately perpendicular to the top surface of the insulator 222. With such a configuration, it is possible to reduce the area and increase the density when providing multiple transistors 200.

[0491] Furthermore, by-products generated in the etching process may form layers on the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B. In this case, the layer-like by-products are formed between the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B and the insulator 275. Therefore, it is preferable to remove the layer-like by-products formed in contact with the upper surface of the insulator 222.

[0492] Next, an insulator 275 is formed to cover the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B (see FIGS. 24A to 24D ). The insulator 275 is preferably in contact with the top surface of the insulator 222 and the side surface of the insulator 224. The insulator 275 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 275 is preferably an insulating film that has a function of suppressing oxygen permeation. For example, a silicon nitride film may be formed as the insulator 275 by an ALD method. Alternatively, an aluminum oxide film may be formed as the insulator 275 by a sputtering method, and then a silicon nitride film may be formed thereon by a PEALD method. The insulator 275 having such a layered structure may have an improved function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0493] In this way, the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B can be covered with the insulator 275 and the insulating layer 271B, which have the function of suppressing oxygen diffusion, thereby reducing the direct diffusion of oxygen from the insulator 280 to the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B in a later process.

[0494] Next, an insulating film to be the insulator 280 is formed on the insulator 275. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxide film can be formed as the insulating film by a sputtering method. The insulating film can be formed by sputtering in an oxygen-containing atmosphere to form the insulator 280 containing excess oxygen. Furthermore, the hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. Note that heat treatment may be performed before the formation of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be formed successively without exposure to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 275, etc., can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, and the insulator 224 can be further reduced. The heat treatment conditions described above can be used for the heat treatment.

[0495] Next, CMP treatment is performed on the insulating film that will become the insulator 280 to form the insulator 280 with a flat upper surface (see FIGS. 24A to 24D). Note that a silicon nitride film may be formed on the insulator 280 by, for example, a sputtering method, and the CMP treatment may be performed on the silicon nitride until it reaches the insulator 280.

[0496] Next, a part of the insulator 280, a part of the insulator 275, a part of the insulating layer 271B, and a part of the conductive layer 242B are processed to form an opening that reaches the oxide 230b. The opening is preferably formed to overlap with the conductor 205. By forming the opening, the insulator 271a, the insulator 271b, the conductor 242a, and the conductor 242b are formed (see FIGS. 25A to 25D).

[0497] 25B and 25C, the side surfaces of the insulator 280, the insulator 275, the insulator 271, and the conductor 242 may have tapered shapes. The taper angle of the insulator 280 may be larger than the taper angle of the conductor 242. Although not shown in FIGS. 25A to 25C, the upper portion of the oxide 230b may be removed when the opening is formed. Removal of a portion of the oxide 230b may result in the formation of a groove in the oxide 230b.

[0498] Furthermore, a portion of the insulator 280, a portion of the insulator 275, a portion of the insulating layer 271B, and a portion of the conductive layer 242B can be processed by dry etching or wet etching. Processing by dry etching is suitable for fine processing. Furthermore, the processing may be performed under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulator 275 and a portion of the insulating layer 271B may be processed by wet etching, and a portion of the conductive layer 242B may be processed by dry etching.

[0499] When forming the openings, the side surface of the conductor 242a may be oxidized to form an insulator 244a. Also, the side surface of the conductor 242b may be oxidized to form an insulator 244b. Note that the lengths of the insulators 244a and 244b in the channel length direction vary depending on the processing conditions when forming the openings.

[0500] The dry etching apparatus used to form the conductors 242a and 242b has the function of removing static electricity accumulated on the substrate during etching. That is, after the etching process to form the conductors 242a and 242b is completed, a plasma process is performed using a lower power than that used to form the conductors 242a and 242b, thereby removing the static electricity accumulated on the substrate. This plasma process is called a static removal plasma process. For example, when nitrogen is used in the static removal plasma process, the lengths of the insulators 244a and 244b in the channel length direction tend to be smaller than when oxygen is used in the static removal plasma process.

[0501] Here, impurities may adhere to the side surfaces of the oxide 230a, the top and side surfaces of the oxide 230b, the side surfaces of the conductor 242, the side surfaces of the insulator 280, etc., or may diffuse into these surfaces. A process for removing such impurities may be performed. Furthermore, the dry etching may result in damaged regions being formed on the surface of the oxide 230b. Such damaged regions may be removed. Examples of such impurities include those originating from components contained in the insulator 280, the insulator 275, part of the insulating layer 271B, and the conductive layer 242B, components contained in the materials used in the device used to form the opening, and components contained in the gas or liquid used in etching. Examples of such impurities include hafnium, silicon, tantalum, fluorine, and chlorine.

[0502] In particular, impurities such as silicon may reduce the crystallinity of the oxide 230b. Therefore, it is preferable to remove impurities such as silicon from the surface of the oxide 230b and its vicinity. It is also preferable to reduce the concentration of the impurities. For example, the concentration of silicon atoms on the surface of the oxide 230b and its vicinity may be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %.

[0503] In addition, in the region where the crystallinity of the oxide 230b is low due to impurities such as silicon, the density of the crystal structure is reduced. Ｏ A large amount of H is formed, which makes the transistor more likely to be normally on. Therefore, it is preferable that the region of low crystallinity in the oxide 230b be reduced or removed.

[0504] In contrast, it is preferable that the oxide 230b has a layered CAAC structure. In particular, it is preferable that the oxide 230b has the CAAC structure up to the bottom end of the drain. Here, in the transistor 200, the conductor 242a or the conductor 242b and its vicinity function as the drain. In other words, it is preferable that the oxide 230b near the bottom end of the conductor 242a or the conductor 242b has a CAAC structure. In this way, even at the drain end, which significantly affects the drain breakdown voltage, the low-crystalline region of the oxide 230b is removed, and by having the CAAC structure, fluctuations in the electrical characteristics of the transistor 200 can be further suppressed. Furthermore, the reliability of the transistor 200 can be improved.

[0505] In order to remove impurities and the like that have adhered to the surface of the oxide 230b during the etching process, a cleaning process is performed. Cleaning methods include wet cleaning using a cleaning solution (also called wet etching), plasma processing using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate. Note that the cleaning process may deepen the grooves.

[0506] Cleaning treatment may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be used in combination as appropriate.

[0507] In this specification and the like, an aqueous solution obtained by diluting hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water may be referred to as diluted ammonia water. The concentration, temperature, etc. of the aqueous solution may be adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water may be set to 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid may be set to 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0508] For ultrasonic cleaning, a frequency of 200 kHz or higher is preferably used, and a frequency of 900 kHz or higher is more preferably used. By using such a frequency, damage to the oxide 230b and the like can be reduced.

[0509] The cleaning process may be repeated multiple times, and different cleaning solutions may be used for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0510] In this embodiment, the cleaning process is performed by wet cleaning using diluted ammonia water. By performing this cleaning process, impurities attached to the surfaces of the oxide 230a, the oxide 230b, etc. or diffused inside can be removed. Furthermore, by removing regions with low crystallinity, the crystallinity of the oxide 230b can be improved.

[0511] Heat treatment may be performed after the etching or cleaning. The heat treatment may be performed at a temperature of 100° C. to 450° C., preferably 350° C. to 400° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230a and the oxide 230b, thereby reducing oxygen vacancies. Furthermore, such heat treatment can improve the crystallinity of the oxide 230b. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0512] Next, the insulating film 252A is formed (see FIGS. 26A to 26D). The insulating film 252A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 252A is preferably formed using the ALD method. As described above, the insulating film 252A is preferably formed to a thin film thickness, and it is necessary to minimize film thickness variation. In contrast, the ALD method is a film formation method that alternately introduces a precursor and a reactant (e.g., an oxidizer). The film thickness can be adjusted by the number of times this cycle is repeated, allowing for precise film thickness adjustment. Furthermore, as shown in FIGS. 26B and 26C, the insulating film 252A must be formed with good coverage on the bottom and side surfaces of the opening formed by the insulator 280, etc. In particular, it is preferable that the insulating film 252A be formed with good coverage on the top and side surfaces of the oxide 230 and the side surfaces of the conductor 242. Since atomic layers can be deposited one by one on the bottom and side surfaces of the opening, the insulating film 252A can be formed with good coverage over the opening.

[0513] When the insulating film 252A is formed by the ALD method, ozone (O ３ ), oxygen (O ２ ), water (H ２ O) and the like can be used. ３ ), oxygen (O ２ By using an oxidizing agent such as HCl, hydrogen diffusing into the oxide 230b can be reduced.

[0514] In this embodiment, the insulating film 252A is formed by depositing aluminum oxide using a thermal ALD method.

[0515] Note that forming the insulating film 252A may increase the lengths of the insulators 244a and 244b in the channel length direction. Note that if the insulators 244a and 244b are not formed before the insulating film 252A is formed, the insulator 244a may be formed by oxidizing the side surface of the conductor 242a during the formation of the insulating film 252A. Also, the insulator 244b may be formed by oxidizing the side surface of the conductor 242b.

[0516] Next, the insulating film 250A is formed (see FIGS. 26A to 26D). Heat treatment may be performed before the formation of the insulating film 250A. The heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed successively without exposure to the air. The heat treatment is preferably performed in an atmosphere containing oxygen. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulating film 252A can be removed, and the moisture and hydrogen concentrations in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0517] The insulating film 250A can be formed by a sputtering method, a CVD method, a PECVD method, an MBE method, a PLD method, an ALD method, or the like. Furthermore, the insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration of the insulating film 250A to be reduced. Since the insulating film 250A will become the insulator 250 facing the oxide 230b via the thin insulator 252 in a later process, it is preferable that the hydrogen concentration be reduced in this way.

[0518] In this embodiment, the insulating film 250A is formed of silicon oxynitride by PECVD.

[0519] Note that forming the insulating film 250A may increase the lengths of the insulators 244a and 244b in the channel length direction. Note that if the insulators 244a and 244b are not formed before the insulating film 250A is formed, the insulator 244a may be formed by oxidizing the side surface of the conductor 242a during the formation of the insulating film 250A. Also, the insulator 244b may be formed by oxidizing the side surface of the conductor 242b.

[0520] Next, it is preferable to perform microwave treatment in an oxygen-containing atmosphere. Here, microwave treatment refers to treatment using, for example, a device having a power source that generates high-density plasma using microwaves. In addition, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0521] The dotted lines in Figures 26B to 26D indicate microwaves, high-frequency waves such as RF, oxygen plasma, or oxygen radicals. For microwave processing, it is preferable to use a microwave processing device having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave processing device may be 300 MHz to 300 GHz, preferably 2.4 GHz to 2.5 GHz, for example, 2.45 GHz. Using high-density plasma can generate high-density oxygen radicals. Furthermore, the power of the power supply that applies microwaves to the microwave processing device may be 1000 W to 10,000 W, preferably 2000 W to 5,000 W. The microwave processing device may also have a power supply that applies RF to the substrate side. Furthermore, applying RF to the substrate side can efficiently guide oxygen ions generated by high-density plasma into the oxide 230b.

[0522] The microwave treatment is preferably carried out under reduced pressure, with the pressure being 10 Pa to 1000 Pa, preferably 300 Pa to 700 Pa. The treatment temperature is 750°C or less, preferably 500°C or less, for example, about 250°C. After the oxygen plasma treatment, a heat treatment may be carried out without exposure to the outside air. For example, the temperature may be 100°C to 750°C, preferably 300°C to 500°C.

[0523] Furthermore, for example, the microwave treatment may be performed using oxygen gas and argon gas. ２ / (O ２ +Ar)) may be greater than 0% and less than 100%, preferably greater than 0% and less than 50%, more preferably greater than 10% and less than 40%, and even more preferably greater than 10% and less than 30%. Thus, by performing microwave treatment in an oxygen-containing atmosphere, the carrier concentration in region 230bc can be reduced. Furthermore, by preventing excessive oxygen from being introduced into the chamber during microwave treatment, an excessive reduction in the carrier concentration in regions 230ba and 230bb can be prevented.

[0524] As shown in Figures 26B to 26D, microwave processing is performed in an atmosphere containing oxygen, whereby oxygen gas is converted into plasma using microwaves or high-frequency waves such as RF, and the oxygen plasma can be applied to the region between the conductors 242a and 242b of the oxide 230b. At this time, microwaves or high-frequency waves such as RF can also be irradiated onto the region 230bc. In other words, microwaves, high-frequency waves such as RF, oxygen plasma, etc. can be applied to the region 230bc shown in Figure 8. The action of plasma, microwaves, etc. can increase the V of the region 230bc. Ｏ H to oxygen deficiency (V Ｏ ) and hydrogen (H). That is, in the region 230bc, Ｏ H → H + V Ｏ " occurs, and the V contained in the region 230bc Ｏ Furthermore, by supplying oxygen radicals generated by the oxygen plasma or oxygen contained in the insulator 250 to the oxygen vacancies in the region 230bc, the oxygen vacancies in the region 230bc can be reduced. Ｏ This can promote the reaction "+O→null". In addition, hydrogen in the region 230bc drifts (diffuses) into the strain formed in the region 230ba and the region 230bb due to the action of the compressive stress of the conductor 242a and the conductor 242b. This can reduce the hydrogen concentration in the region 230bc. Therefore, the V in the region 230bc Ｏ The concentration of H, oxygen vacancies, and hydrogen can be reduced, and the carrier concentration can be lowered. In this way, the region 230bc can be made i-type or substantially i-type.

[0525] 8, a conductor 242a and a conductor 242b are provided on the region 230ba and the region 230bb, respectively. Here, when microwave processing is performed in an oxygen-containing atmosphere, the conductor 242 preferably functions as a shielding film against the effects of microwaves, high-frequency waves such as RF, oxygen plasma, etc. Therefore, the conductor 242 preferably has a function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.

[0526] 26B to 26D, when microwave processing is performed in an atmosphere containing oxygen, the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc. are shielded by the conductors 242a and 242b and do not reach the regions 230ba and 230bb. Furthermore, the effects can be reduced by the insulators 271 and 280 that are provided to cover the oxide 230b and the conductor 242. In addition, in the regions 230ba and 230bb, hydrogen diffused from the region 230bc reacts with oxygen vacancies to form V. Ｏ H is formed. As a result, V Ｏ A decrease in carrier concentration can be prevented because H is reduced and an excessive amount of oxygen is not supplied. In this way, the regions 230ba and 230bb can be made n-type.

[0527] Furthermore, the effects of microwaves, high-frequency waves such as RF, oxygen plasma, and the like are reduced by insulators 244a and 244b, but are not as well shielded as by conductors 242a and 242b. Therefore, the effects on regions 230bd and 230be are weaker than on regions 230bc, but stronger than on regions 230ba and 230bb. Therefore, the carrier concentrations of regions 230bd and 230be due to microwave treatment decrease more than those of regions 230ba and 230bb, but not as much as those of region 230bc.

[0528] Furthermore, an insulator 252 having a barrier property against oxygen is provided in contact with the side surfaces of the conductor 242 a and the conductor 242 b, thereby making it possible to prevent an excessive amount of oxygen from being supplied to the side surfaces of the conductor 242 a and the conductor 242 b by microwave treatment.

[0529] Additionally, an insulator 275 having oxygen barrier properties is provided above the conductor 242a and the conductor 242b and in contact with the side surfaces of the conductor 242a and the conductor 242b. This prevents the upper and side surfaces of the conductor 242a and the conductor 242b from being oxidized by microwave treatment. Furthermore, as shown in FIG. 26D , the insulator 275 contacts the side surfaces of the oxide 230b in the region overlapping with the conductor 242a or the conductor 242b. Therefore, the insulator 275 prevents excessive oxygen from being supplied to the side surfaces of the oxide 230b in that region, thereby preventing a decrease in carrier concentration.

[0530] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after forming the insulating film 252A or the insulating film 250A. By performing microwave treatment in an oxygen-containing atmosphere through the insulating film 252A or the insulating film 250A in this manner, oxygen can be efficiently injected into the region 230bc. Furthermore, by arranging the insulating film 252A so that it contacts the surface of the region 230bc, it is possible to prevent more oxygen than necessary from being injected into the region 230bc. Furthermore, by arranging the insulating film 252A near the side surface of the conductor 242, it is possible to prevent excessive oxidation of the side surface of the conductor 242.

[0531] The oxygen injected into the region 230bc may take various forms, such as oxygen atoms, oxygen molecules, and oxygen radicals (atoms, molecules, or ions with an unpaired electron, also known as O radicals). The oxygen injected into the region 230bc may take one or more of the above forms, and oxygen radicals are particularly preferred.

[0532] Furthermore, the film quality of the insulator 252 and the insulator 250 can be improved, thereby improving the reliability of the transistor 200.

[0533] In this manner, oxygen vacancies and V ＯBy removing H, the region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 230ba and 230bb, which function as source and drain regions, can be suppressed, thereby maintaining the n-type state of the regions before microwave treatment. Furthermore, the regions 230bd and 230be can function as junction regions or offset regions. This suppresses fluctuations in the electrical characteristics of the transistor 200 and suppresses variations in the electrical characteristics of the transistor 200 within the substrate surface.

[0534] The microwave treatment is one of the most effective methods for making the region 230bc i-type or substantially i-type and the regions 230ba and 230bb n-type. By using the microwave treatment, it is possible to manufacture a transistor 200 with a gate length of 6 nm or even 3 nm.

[0535] In microwave processing, thermal energy may be transferred directly to the oxide 230b due to electromagnetic interactions between the microwaves and molecules in the oxide 230b. This thermal energy may heat the oxide 230b. This type of heat treatment is sometimes called microwave annealing. Performing microwave processing in an oxygen-containing atmosphere may produce an effect equivalent to that of oxygen annealing. In other words, microwave annealing can repair oxygen vacancies (null them) with oxygen. Furthermore, if the oxide 230b contains hydrogen, this thermal energy may be transferred to the hydrogen in the oxide 230b, which may activate the hydrogen and release it from the oxide 230b.

[0536] Note that the microwave treatment may increase the lengths of the insulators 244a and 244b in the channel length direction. If the insulators 244a and 244b have not been formed before the microwave treatment, the insulator 244a may be formed by oxidizing the side surface of the conductor 242a when the microwave treatment is performed. Also, the insulator 244b may be formed by oxidizing the side surface of the conductor 242b.

[0537] By appropriately adjusting the film formation conditions of the insulating film 250A, the conditions of the microwave treatment performed in an oxygen-containing atmosphere, and the addition of oxygen to the insulator 280 by forming the insulator 282, the oxygen vacancies and V Ｏ In some cases, it is possible to reduce H and suppress the supply of excess oxygen to the regions 230ba and 230bb. In such a case, the insulator 252 is not required. This can simplify the manufacturing process of the semiconductor device and improve productivity.

[0538] The microwave treatment may be performed after the formation of the insulating film 252A. Alternatively, the microwave treatment may be performed after the formation of the insulating film 252A without performing the microwave treatment after the formation of the insulating film 250A.

[0539] When the insulator 250 has the two-layer stacked structure shown in FIG. 13A , an insulating film that becomes the insulator 250b can be formed after the insulating film 250A is formed. The insulating film that becomes the insulator 250b can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The insulating film that becomes the insulator 250b is preferably formed using an insulator that has the function of suppressing oxygen diffusion. This configuration can suppress the diffusion of oxygen contained in the insulator 250a into the conductor 260. In other words, it can suppress a decrease in the amount of oxygen supplied to the oxide 230. It can also suppress oxidation of the conductor 260 due to the oxygen contained in the insulator 250a. The insulating film that becomes the insulator 250b can be formed using the same material as the insulator 222. For example, the insulating film that becomes the insulator 250b can be formed using hafnium oxide by thermal ALD.

[0540] 13A , the microwave treatment may be performed after the formation of the insulating film 250 A. Alternatively, the microwave treatment may be performed after the formation of the insulating film that will become the insulator 250 b, without performing the microwave treatment after the formation of the insulating film 250 A.

[0541] Alternatively, a heat treatment may be performed while maintaining the reduced pressure after the microwave treatment. This treatment can efficiently remove hydrogen from the oxide 230b and the oxide 230a. Furthermore, hydrogen from the insulating films that will become the insulating film 252A, the insulating film 250A, and the insulator 250b, which were formed before the microwave treatment, can be efficiently removed. Some of the hydrogen may be gettered to the conductor 242a and the conductor 242b. Alternatively, the heat treatment step may be repeated multiple times while maintaining the reduced pressure after the microwave treatment. Repeated heat treatment can more efficiently remove hydrogen from the oxide 230b and the oxide 230a. Furthermore, hydrogen from the insulating films that will become the insulating film 252A, the insulating film 250A, and the insulator 250b, which were formed before the microwave treatment, can be more efficiently removed. The heat treatment temperature is preferably 300° C. or higher and 500° C. or lower. The microwave treatment, i.e., microwave annealing, may also serve as the heat treatment. If the oxide 230b and the like are sufficiently heated by microwave annealing, the heat treatment does not need to be performed.

[0542] Furthermore, by performing microwave treatment to modify the quality of one or more of the insulating film 252A, the insulating film 250A, and the insulating film that becomes the insulator 250b, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230b, the oxide 230a, etc. via the insulator 252 in a post-process such as film formation of the conductive film that becomes the conductor 260 or a post-treatment such as heat treatment.

[0543] In the steps up to this point, insulator 244a is formed on the side surface of conductor 242a, and insulator 244b is formed on the side surface of conductor 242b. In other words, insulator 244a and insulator 244b are formed when performing one of the steps of processing a part of insulator 280 to form an opening reaching oxide 230b, forming insulating film 252A, forming insulating film 250A, and performing microwave treatment. In other words, insulator 244a and insulator 244b are formed in a self-aligned manner during the manufacturing process of the semiconductor device.

[0544] Next, the insulating film 254A is formed (see FIGS. 27A to 27D). The insulating film 254A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The insulating film 254A is preferably formed by ALD, similar to the insulating film 252A. By using the ALD method, the insulating film 254A can be formed to a thin film thickness with good coverage. In this embodiment, a silicon nitride film is formed as the insulating film 254A by PEALD.

[0545] Next, a conductive film to become the conductor 260a and a conductive film to become the conductor 260b are formed in this order. The conductive film to become the conductor 260a and the conductive film to become the conductor 260b can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, a titanium nitride film is formed by ALD as the conductive film to become the conductor 260a, and a tungsten film is formed by CVD as the conductive film to become the conductor 260b.

[0546] Next, the insulating film 252A, the insulating film 250A, the insulating film 254A, the conductive film that will become the conductor 260a, and the conductive film that will become the conductor 260b are polished by CMP until the insulator 280 is exposed, thereby forming the insulators 252, 250, 254, and the conductor 260 (the conductors 260a and 260b) (see FIGS. 28A to 28D). As a result, the insulator 252 is disposed so as to cover the opening that reaches the oxide 230b. The conductor 260 is disposed so as to fill the opening via the insulators 252, 250, and 254.

[0547] Next, heat treatment may be performed under the same conditions as the above heat treatment. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for 1 hour. This heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0548] Next, the insulator 282 is formed over the insulators 252, 250, and 254, the conductor 260, and the insulator 280 (see FIGS. 28A to 28D ). The insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 282 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0549] In this embodiment, an aluminum oxide film is formed as the insulator 282 by pulse DC sputtering using an aluminum target in an atmosphere containing oxygen gas. The RF power applied to the substrate is 1.86 W / cm. ２ Preferably, 0 W / cm ２ 0.62W / cm or more ２ The amount of oxygen injected into the insulator 280 can be suppressed by reducing the RF power. Alternatively, the insulator 282 may be formed to have a two-layer laminate structure. In this case, the lower layer of the insulator 282 is formed by applying an RF power of 0 W / cm to the substrate. ２ The upper layer of the insulator 282 was formed as follows: the RF power applied to the substrate was 0.62 W / cm ２ The film is formed as follows.

[0550] Furthermore, by depositing the insulator 282 in an oxygen-containing atmosphere by using a sputtering method, oxygen can be added to the insulator 280 during deposition. This allows the insulator 280 to contain excess oxygen. In this case, it is preferable to deposit the insulator 282 while heating the substrate.

[0551] Next, an etching mask is formed on the insulator 282 by lithography, and a part of the insulator 282, a part of the insulator 280, a part of the insulator 275, a part of the insulator 222, and a part of the insulator 216 are processed until the top surface of the insulator 214 is exposed (see FIGS. 29A to 29D ). This processing may be performed by wet etching, but dry etching is preferable for fine processing.

[0552] Next, heat treatment may be performed. The heat treatment may be performed at a temperature of 250° C. or higher and 650° C. or lower, preferably 350° C. or higher and 600° C. or lower. The temperature of this heat treatment is preferably lower than the temperature of the heat treatment performed after the formation of the oxide film 230B. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere. By performing this heat treatment, part of the oxygen added to the insulator 280 diffuses into the oxide 230 via the insulator 250 or the like.

[0553] Furthermore, by performing this heat treatment, oxygen contained in the insulator 280 and hydrogen bonded to the oxygen can be released to the outside from the side surface of the insulator 280 formed by the above processing. Note that the hydrogen bonded to oxygen is released as water. Therefore, the excess oxygen and hydrogen contained in the insulator 280 can be reduced.

[0554] Furthermore, in the region of the oxide 230 overlapping with the conductor 260, an i...

Claims

1. A semiconductor device having a circuit, the circuit has a transistor and a first region including the transistor; the transistor includes a first conductor functioning as a gate electrode and an oxide having a channel formation region; a second conductor that does not overlap with the oxide is provided in the first region; the second conductor has the same material as the first conductor; the second conductor is separate from the first conductor; the first region is divided into a square shape in a top view so as to include at least the channel formation region of the transistor; the area of ​​the first region is equal to the area occupied by one transistor calculated from the transistor density of the circuit, When viewed from above, the first region overlaps with at least a portion of the first conductor and the second conductor; the second conductor does not function as a gate electrode of a transistor; Semiconductor device.

2. In claim 1, the first conductor has a region having a width of 1 nm to 20 nm in a cross-sectional view in a channel length direction of the transistor; Semiconductor device.

3. In claim 1 or claim 2, The transistor density of the circuit is 1 / μm ２ More than 1000 pieces / μm ２ Below is the Semiconductor device.