Nitride semiconductor device

Abstract

This nitride semiconductor device comprises: a substrate; a drift layer of a first conductivity type; a first underlayer of a second conductivity type; an intermediate high-resistance layer which has a higher resistance than the first underlayer; a second underlayer of the second conductivity type; a gate opening which passes through the second underlayer, the intermediate high-resistance layer, and the first underlayer to the drift layer; a semiconductor lamination film which has a channel region of the first conductivity type, a part of which is disposed along an inner surface of the gate opening, another part of which is disposed above the second underlayer; a threshold value adjustment layer of the second conductivity type; a gate electrode; a source electrode which is disposed apart from the gate electrode; and a drain electrode which is disposed on the lower surface side of the substrate.

Description

Nitride Semiconductor Devices

[0001] The present disclosure relates to nitride semiconductor devices.

[0002] Nitride semiconductors such as GaN (gallium nitride) are wide-gap semiconductors with a large band gap, and are characterized by a high dielectric breakdown field strength and a high electron saturation drift velocity compared to GaAs (gallium arsenide) semiconductors or Si (silicon) semiconductors, etc. For this reason, research and development is being conducted on power transistors using nitride semiconductors, which are advantageous for achieving high output and high breakdown voltage.

[0003] For example, Patent Documents 1 and 2 disclose a vertical field effect transistor (FET) including a regrowth layer positioned so as to cover an opening provided in a GaN-based stacked body, and a gate electrode positioned along and on the regrowth layer. A channel is formed by two-dimensional electron gas (2DEG) generated in the regrowth layer.

[0004] International Publication No. 2020 / 137303 Patent No. 6511645

[0005] There is room for improvement in electrical characteristics compared to the above-described conventional semiconductor device.

[0006] The present disclosure provides nitride semiconductor devices with improved electrical properties.

[0007] a first semiconductor layer of a first conductivity type disposed above the substrate; a second semiconductor layer of a second conductivity type disposed above the first semiconductor layer; a third semiconductor layer disposed above the second semiconductor layer and having a higher resistance than the second semiconductor layer; a fourth semiconductor layer of the second conductivity type disposed above the third semiconductor layer; a first opening that passes through the fourth semiconductor layer, the third semiconductor layer, and the second semiconductor layer to reach the first semiconductor layer; a fifth semiconductor layer having a channel region of the first conductivity type, wherein a portion of the fifth semiconductor layer is disposed along an inner surface of the first opening and another portion of the fifth semiconductor layer is disposed above the fourth semiconductor layer; a sixth semiconductor layer of the second conductivity type disposed above the fifth semiconductor layer; a gate electrode disposed above the sixth semiconductor layer; a source electrode disposed spaced apart from the gate electrode; and a drain electrode disposed on a lower surface side of the substrate.

[0008] According to the present disclosure, it is possible to provide a nitride semiconductor device with improved electrical characteristics.

[0009] FIG. 1 is a cross-sectional view of a nitride semiconductor device according to a first embodiment. FIG. 2 is a plan view of the nitride semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view of a nitride semiconductor device according to a modification of the first embodiment. FIG. 4 is a cross-sectional view of a nitride semiconductor device according to a second embodiment. FIG. 5 is a cross-sectional view of a nitride semiconductor device according to a first modification of the second embodiment. FIG. 6 is a cross-sectional view of a nitride semiconductor device according to a second modification of the second embodiment.

[0010] (Findings that Form the Basis of the Present Disclosure) The present inventors have found that the following problems arise with the conventional nitride semiconductor devices described in the "Background Art" section.

[0011] In the nitride semiconductor devices disclosed in Patent Documents 1 and 2, a high-resistivity GaN layer is disposed between the p-type underlayer and the n-type channel (two-dimensional electron gas) to prevent a parasitic npn bipolar structure from being formed between the n-type drift layer, p-type underlayer, and n-type channel (two-dimensional electron gas), thereby improving the off-state characteristics of the transistor.

[0012] However, during switching operations, electrons in the channel may be trapped in the high-resistivity GaN layer. This is because carbon (C) or iron (Fe) doped in the high-resistivity GaN layer generates trap levels. Trapped electrons may degrade the dynamic characteristics of the transistor.

[0013] Therefore, the present disclosure provides a nitride semiconductor device including a transistor with improved off-state characteristics while suppressing degradation of dynamic characteristics.

[0014] a first semiconductor layer of a first conductivity type disposed above the substrate; a second semiconductor layer of a second conductivity type disposed above the first semiconductor layer; a third semiconductor layer disposed above the second semiconductor layer and having a higher resistance than the second semiconductor layer; a fourth semiconductor layer of the second conductivity type disposed above the third semiconductor layer; a first opening extending through the fourth semiconductor layer, the third semiconductor layer, and the second semiconductor layer to reach the first semiconductor layer; a fifth semiconductor layer having a channel region of the first conductivity type, a portion of which is disposed along an inner surface of the first opening and another portion of which is disposed above the fourth semiconductor layer; a sixth semiconductor layer of the second conductivity type disposed above the fifth semiconductor layer; a gate electrode disposed above the sixth semiconductor layer; a source electrode disposed spaced apart from the gate electrode; and a drain electrode disposed on a bottom surface side of the substrate.

[0015] As a result, since the fourth semiconductor layer is disposed above the high-resistance third semiconductor layer, electrons are less likely to be trapped in the trap levels generated in the third semiconductor layer, thereby suppressing deterioration of the dynamic characteristics of the transistor.

[0016] It is also conceivable to arrange a high-resistance third semiconductor layer at the bottom p-n junction (specifically, in contact with the top surface of the first semiconductor layer) solely for the purpose of suppressing electron trapping. However, the crystal quality of a high-resistance third semiconductor layer tends to deteriorate when doped with carbon or the like. Therefore, if a high-resistance third semiconductor layer is provided at a p-n junction to which a high electric field is applied during off-state operation, the off-state characteristics may be deteriorated. In contrast, in the nitride semiconductor device according to this embodiment, a second semiconductor layer is arranged below the third semiconductor layer, and a p-n junction is formed between the second semiconductor layer and the first semiconductor layer, thereby improving the off-state characteristics.

[0017] Furthermore, for example, the fifth semiconductor layer may include an electron transit layer and an electron supply layer disposed above the electron transit layer, and the distance between a bottom of the electron supply layer and the drain electrode may be shorter than the distance between a bottom of the third semiconductor layer and the drain electrode.

[0018] The electron transit layer and the electron supply layer can be formed continuously by crystal growth. Therefore, the pn junction at the interface between the electron transit layer and the electron supply layer (i.e., the pn junction of the gate portion) has few levels due to impurities or damage, and is the portion that can withstand the highest electric field strength in the nitride semiconductor device. By bringing the pn junction of the gate portion closer to the drain electrode, the electric field generated between the gate electrode or the source electrode and the drain electrode during the off state can be concentrated at the pn junction of the gate portion. This makes it possible to suppress the electric field from concentrating in weak portions, thereby improving the off characteristics.

[0019] Furthermore, for example, the nitride semiconductor device according to one aspect of the present disclosure may include a second opening provided apart from the gate electrode and penetrating the fifth semiconductor layer to reach the fourth semiconductor layer, and the source electrode may be provided along an inner surface of the second opening.

[0020] As a result, the channel is exposed on the inner surface of the second opening, allowing the source electrode to contact the channel at this exposed portion. This reduces the ohmic contact resistance between the source electrode and the channel. Furthermore, because the high-resistance third semiconductor layer is disposed below the fourth semiconductor layer with which the source electrode contacts at the bottom of the second opening, it is possible to suppress current flow through a parasitic pn diode formed between the source and drain. This improves the reliability of the nitride semiconductor device.

[0021] Furthermore, for example, the nitride semiconductor device according to one aspect of the present disclosure may include a third opening provided apart from the gate electrode, penetrating the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer to reach the second semiconductor layer, and the source electrode may be provided along an inner surface of the third opening.

[0022] As a result, the channel is exposed on the inner surface of the third opening, allowing the source electrode to contact the channel at this exposed portion. This reduces the ohmic contact resistance between the source electrode and the channel. Furthermore, since the source electrode contacts both the fourth semiconductor layer and the second semiconductor layer, the potentials of the respective semiconductor layers can be firmly fixed. This further improves the off-state characteristics of the nitride semiconductor device.

[0023] Furthermore, for example, the third semiconductor layer may contain C, Fe, B or Mg.

[0024] This makes it possible to easily form a high-resistance third semiconductor layer by doping during crystal growth or by ion implantation after growth.

[0025] Furthermore, for example, the first semiconductor layer may be made up of a plurality of layers having different impurity concentrations, and the uppermost layer of the plurality of layers may have the lowest impurity concentration of the plurality of layers.

[0026] This reduces the impurity concentration near the pn junction between the first and second semiconductor layers, thereby reducing electric field concentration during the off state, thereby improving the off-state characteristics of the nitride semiconductor device.

[0027] Furthermore, for example, the bottom of the first opening may be located in the nth (n is a natural number of 2 or more) layer from the top of the plurality of layers.

[0028] This makes it possible to improve the off-state characteristics while suppressing an increase in on-state resistance. Specifically, the low-impurity-concentration layer located at the top of the first semiconductor layer contributes to improving the off-state characteristics. On the other hand, the low-impurity-concentration layer has high resistance, and therefore, when included in the current path during on-state, the on-state resistance increases. In contrast, by having the bottom of the first opening penetrate the low-impurity-concentration layer located at the top of the first semiconductor layer, the low-impurity-concentration layer can be excluded from the current path during on-state. This makes it possible to reduce the on-state resistance.

[0029] In the gate region, the layer with a low impurity concentration does not contribute to improving the off-state characteristics. However, in the gate region, the pn junction at the interface between the electron transit layer and the electron supply layer can receive an electric field, so degradation of the off-state characteristics can be suppressed. This is because the pn junction at the gate region is the part that can withstand the highest electric field strength within the nitride semiconductor device.

[0030] Furthermore, for example, a trench may be provided at an end portion of the nitride semiconductor device, the trench reaching the first semiconductor layer, and a distance between a bottom of the first opening and the drain electrode may be shorter than a distance between a bottom of the trench and the drain electrode.

[0031] This makes it possible to suppress the deterioration of the off-state characteristics. The trench at the end of the device is susceptible to etching damage during formation, and the electric field strength that it can withstand may be insufficient. By bringing the pn junction of the gate closer to the drain electrode, the electric field during the off state can be received by the pn junction of the gate, thereby suppressing the deterioration of the off-state characteristics.

[0032] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0033] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0034] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0035] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, such as rectangle or trapezoid, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0036] In this specification and the drawings, the x-axis, y-axis, and z-axis represent the three axes of a three-dimensional Cartesian coordinate system. When the planar shape of the substrate is rectangular, the x-axis and y-axis are directions parallel to a first side of the rectangle and a second side perpendicular to the first side, respectively. The z-axis is the thickness direction of the substrate. In this specification, the "thickness direction" of the substrate refers to the direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layers, and is also referred to as the "vertical direction." The direction parallel to the main surface of the substrate may also be referred to as the "lateral direction."

[0037] Furthermore, the side of the substrate on which the gate electrode and source electrode are provided (positive side of the z-axis) is considered to be the "upper" or "upper side," and the side of the substrate on which the drain electrode is provided (negative side of the z-axis) is considered to be the "lower" or "lower side."

[0038] In this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are applied not only to a case where two components are arranged with a gap between them and another component exists between them, but also to a case where two components are arranged closely together and the two components are in contact with each other.

[0039] In this specification, the term "plan view" refers to a view perpendicular to the main surface of the substrate of the nitride semiconductor device, that is, a view of the main surface of the substrate from the front.

[0040] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0041] In this specification, AlGaN refers to a ternary mixed crystal Al ｘ Ga １－ｘ Hereinafter, multi-element mixed crystals are abbreviated by the arrangement of the symbols of the respective constituent elements, such as AlInN, GaInN, etc. For example, AlInN, which is an example of a nitride semiconductor, ｘ Ga １－ｘ－ｙ In ｙ N (0<x<1, 0<y<1, and 0<x+y<1) is abbreviated as AlGaInN.

[0042] First Embodiment [Outline] First, an outline of a nitride semiconductor device according to a first embodiment will be described with reference to FIGS. 1 and 2. FIG.

[0043] Fig. 1 is a cross-sectional view of a nitride semiconductor device 1 according to this embodiment. Fig. 2 is a plan view of the nitride semiconductor device 1 according to this embodiment. Fig. 1 shows a cross section taken along line II in Fig. 2. Note that Fig. 1 shows a transistor section 2 and a termination section 3 separated from each other.

[0044] 1 , the nitride semiconductor device 1 includes a transistor section 2 and a termination section 3. Specifically, the nitride semiconductor device 1 includes a substrate 10, a drift layer 12, a first underlayer 14, an intermediate high-resistance layer 16, a second underlayer 18, a third underlayer 20, a gate opening 22, a semiconductor laminated film 24, a threshold adjustment layer 32, a source opening 34, a source electrode 36, a gate electrode 38, and a drain electrode 40. The semiconductor laminated film 24 is a laminate of an electron transit layer 26 and an electron supply layer 28, and includes a two-dimensional electron gas (2DEG) 30 as a channel region. The nitride semiconductor device 1 also includes a groove 42 provided in the termination section 3.

[0045] 2, the transistor portion 2 is a region including the center of the nitride semiconductor device 1. Specifically, the transistor portion 2 is a region in which the third underlayer 20, the gate opening 22, the semiconductor stacked film 24, the threshold adjustment layer 32, and the source electrode 36 or the gate electrode 38 are arranged in a plan view.

[0046] 2 does not illustrate each component arranged in the transistor portion 2. As an example, a plurality of source electrodes 36 each elongated in one direction in a plan view are arranged in a stripe pattern, and a gate electrode 38, a threshold adjustment layer 32, and a gate opening 22 are arranged between adjacent source electrodes 36. Alternatively, a plurality of source electrodes 36 each hexagonal in a plan view may be arranged to fill a plane with gaps between them.

[0047] The termination portion 3 is a region other than the transistor portion 2, and is provided in a ring shape surrounding the transistor portion 2. The termination portion 3 does not include the third underlayer 20, the gate opening 22, the semiconductor stacked film 24, the threshold adjustment layer 32, the source electrode 36, and the gate electrode 38.

[0048] In this embodiment, the nitride semiconductor device 1 is a device having a stacked structure of semiconductor layers mainly composed of nitride semiconductors such as GaN and AlGaN. Specifically, the nitride semiconductor device 1 has a heterostructure of an AlGaN film and a GaN film.

[0049] In a heterostructure of an AlGaN film and a GaN film, spontaneous polarization or piezoelectric polarization on the (0001) plane generates a high concentration of two-dimensional electron gas 30 at the heterointerface. Therefore, even in an undoped state, a high concentration of two-dimensional electron gas 30 of 1×10 １３ cm －２ The sheet carrier concentration can be obtained as above.

[0050] The nitride semiconductor device 1 according to this embodiment is a field effect transistor (FET) that uses a two-dimensional electron gas 30 generated at an AlGaN / GaN heterointerface as a channel. Specifically, the nitride semiconductor device 1 is a so-called vertical FET.

[0051] The nitride semiconductor device 1 according to this embodiment is a normally-off FET. In the nitride semiconductor device 1, for example, the source electrode 36 is grounded (i.e., the potential is 0 V), and a positive potential is applied to the drain electrode 40. The potential applied to the drain electrode 40 is, for example, not limited to, 100 V or more and 1200 V or less. When the nitride semiconductor device 1 is in the off state, 0 V or a negative potential (e.g., −5 V) is applied to the gate electrode 38. When the nitride semiconductor device 1 is in the on state, a positive potential (e.g., +5 V) is applied to the gate electrode 38. Note that the nitride semiconductor device 1 may be a normally-on FET.

[0052] [Configuration of Transistor Portion] The configuration of the transistor portion 2 of the nitride semiconductor device 1 will be described below.

[0053] The substrate 10 is made of a nitride semiconductor and has a first major surface 10a and a second major surface 10b facing each other, as shown in FIG. 1 . The first major surface 10a is the major surface (upper surface) on which the drift layer 12 is formed. Specifically, the first major surface 10a substantially coincides with the c-plane. The second major surface 10b is the major surface (lower surface) on which the drain electrode 40 is formed. The shape of the substrate 10 in a plan view is, for example, rectangular, but is not limited to this.

[0054] The substrate 10 has a thickness of, for example, 300 μm and a carrier concentration of 1×10 １８ cm－３ n ＋ The substrate is made of n-type GaN. Note that n-type and p-type indicate the conductivity type of the semiconductor. ＋ The n-type indicates a state in which a semiconductor is doped with a high concentration of n-type dopants, i.e., a heavily doped semiconductor. － The term "type" refers to a state in which a semiconductor is doped with a low concentration of n-type dopant, i.e., a so-called lightly doped state. ＋ Type and p － The same applies to types. n-type, n ＋ Type and n － The p-type is an example of the first conductivity type. ＋ Type and p － The second conductivity type is an example of a second conductivity type, which is a conductivity type of opposite polarity to the first conductivity type.

[0055] The substrate 10 does not have to be a nitride semiconductor substrate, but may be, for example, a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a zinc oxide (ZnO) substrate.

[0056] The drift layer 12 is an example of a first semiconductor layer of a first conductivity type disposed above the substrate 10. The drift layer 12 is, for example, an n-type semiconductor layer having a thickness of 8 μm. － The drift layer 12 is a film made of GaN of the type. The donor concentration of the drift layer 12 is, for example, 1×10 １５ cm －３ 1x10 or more １７ cm －３ The range is as follows: 1 × 10 １６ cm －３ The carbon concentration (C concentration) of the drift layer 12 is 1×10 １５ cm －３ 2 x 10 or more １７ cm －３ The range is as follows:

[0057] The drift layer 12 is provided, for example, in contact with the first main surface 10a of the substrate 10. The drift layer 12 is formed on the first main surface 10a of the substrate 10 by crystal growth such as metalorganic vapor phase epitaxial growth (MOVPE).

[0058] The first underlayer 14 is an example of a second semiconductor layer of a second conductivity type disposed above the drift layer 12. The first underlayer 14 has a thickness of 400 nm and a carrier concentration of 1×10 １７ cm －３ The first underlayer 14 is a film made of p-type GaN, where p is a p-type GaN film. The first underlayer 14 is provided in contact with the upper surface of the drift layer 12. The first underlayer 14 is formed on the drift layer 12 by crystal growth, for example, by MOVPE or other methods. The first underlayer 14 may be formed by ion implanting magnesium (Mg) into a deposited undoped GaN film. Here, "undoped" means that the GaN film is not doped with a dopant such as Si or Mg that changes the polarity of the GaN to n-type or p-type.

[0059] The intermediate high-resistance layer 16 is an example of a third semiconductor layer disposed above the first underlayer 14. The intermediate high-resistance layer 16 is a high-resistance layer having a higher resistance than the first underlayer 14. The intermediate high-resistance layer 16 is formed of an insulating or semi-insulating nitride semiconductor. The intermediate high-resistance layer 16 is, for example, a 200 nm-thick film made of GaN. The intermediate high-resistance layer 16 is provided in contact with the first underlayer 14.

[0060] The intermediate high-resistivity layer 16 contains carbon (C). The carbon concentration of the intermediate high-resistivity layer 16 is higher than the carbon concentration of each of the first underlayer 14 and the second underlayer 18. For example, the carbon concentration of the intermediate high-resistivity layer 16 is, for example, 3×10 １７ cm －３ That's all, but 1 x 10 １８ cm －３ More than that is fine.

[0061] The intermediate high-resistance layer 16 may contain silicon (Si) or oxygen (O) that is mixed in during film formation. In this case, the carbon concentration of the intermediate high-resistance layer 16 is higher than the silicon concentration (Si concentration) or oxygen concentration (O concentration). The silicon concentration or oxygen concentration of the intermediate high-resistance layer 16 is, for example, 5×10 １６ cm －３ The following is 2 x 10 １６ cm －３ The following is also acceptable.

[0062] The intermediate high-resistivity layer 16 may contain magnesium (Mg), iron (Fe), boron (B), or the like instead of or in addition to carbon. The intermediate high-resistivity layer 16 may also contain other impurities as long as the impurities can increase the resistance of GaN.

[0063] The intermediate high-resistance layer 16 is formed on the first underlayer 14 by crystal growth such as MOVPE. Alternatively, the intermediate high-resistance layer 16 may be formed by ion implanting impurities into a deposited undoped GaN film.

[0064] The second underlayer 18 is an example of a fourth semiconductor layer of the second conductivity type disposed above the intermediate high-resistance layer 16. The second underlayer 18 has a thickness of 200 nm and a carrier concentration of 1×10 １７ cm －３ The second underlayer 18 is a film made of p-type GaN, where p is a p-type GaN film. The second underlayer 18 is provided in contact with the upper surface of the intermediate high-resistivity layer 16. The second underlayer 18 is formed on the intermediate high-resistivity layer 16 by crystal growth such as MOVPE. The second underlayer 18 may be formed by ion implanting magnesium (Mg) into a deposited undoped GaN film.

[0065] The third underlayer 20 is an undoped semiconductor layer disposed above the second underlayer 18. The third underlayer 20 is, for example, a 150 nm-thick film made of undoped AlGaN. The third underlayer 20 may be a film made of GaN, InAlN, or InAlGaN. The third underlayer 20 is provided in contact with the upper surface of the second underlayer 18. The third underlayer 20 is formed on the second underlayer 18 by crystal growth such as MOVPE. The provision of the third underlayer 20 can suppress diffusion of p-type impurities such as Mg from the second underlayer 18 into the electron transit layer 26.

[0066] The drift layer 12, the first underlayer 14, the intermediate high-resistance layer 16, the second underlayer 18, and the third underlayer 20 can be formed successively in the same chamber.

[0067] The gate opening 22 is an example of a first opening that penetrates the third underlayer 20, the second underlayer 18, the intermediate high-resistance layer 16, and the first underlayer 14 to reach the drift layer 12. A bottom 22a of the gate opening 22 is part of the upper surface of the drift layer 12. As shown in FIG. 1 , the bottom 22a is located below the lower surface of the first underlayer 14. The lower surface of the first underlayer 14 corresponds to the interface between the first underlayer 14 and the drift layer 12. The bottom 22a is, for example, parallel to the first main surface 10a of the substrate 10.

[0068] In this embodiment, the gate opening 22 is formed so that the opening area increases with increasing distance from the substrate 10. Specifically, the sidewall 22b of the gate opening 22 is inclined obliquely. As shown in FIG. 1 , the cross-sectional shape of the gate opening 22 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid.

[0069] The inclination angle of the sidewall 22b with respect to the bottom 22a is, for example, in the range of 30° to 45°. The smaller the inclination angle, the closer the sidewall 22b is to the c-plane, which improves the quality of the electron transit layer 26 and other films formed along the sidewall 22b by crystal regrowth. On the other hand, the larger the inclination angle, the more the gate opening 22 is prevented from becoming too large, which enables the nitride semiconductor device 1 to be miniaturized.

[0070] The gate opening 22 is formed by successively depositing the drift layer 12, the first underlayer 14, the intermediate high-resistance layer 16, the second underlayer 18, and the third underlayer 20 in this order on the first main surface 10a of the substrate 10, and then removing a portion of each of the third underlayer 20, the second underlayer 18, the intermediate high-resistance layer 16, and the first underlayer 14 so as to partially expose the drift layer 12. At this time, by removing a surface portion of the drift layer 12 by a predetermined thickness, a bottom 22a of the gate opening 22 is formed below the lower surface of the first underlayer 14.

[0071] The third underlayer 20, the second underlayer 18, the intermediate high-resistance layer 16, and the first underlayer 14 are removed by applying and patterning a resist, followed by dry etching. Specifically, the resist is patterned and then baked, so that the edges of the resist are inclined. Dry etching is then performed to form a gate opening 22 with inclined sidewalls 22b, with the resist shape being transferred.

[0072] The semiconductor laminated film 24 is an example of a fifth semiconductor layer, a part of which is disposed along the inner surface of the gate opening 22, and another part of which is disposed above the second underlayer 18. That is, a part of the semiconductor laminated film 24 is disposed along the inner surface of the gate opening 22, and another part of the semiconductor laminated film 24 is disposed above the second underlayer 18. The semiconductor laminated film 24 is a laminated film of an electron transit layer 26 and an electron supply layer 28.

[0073] The electron transit layer 26 is an example of a first regrown layer provided along the inner surface of the gate opening 22. Specifically, a portion of the electron transit layer 26 is provided along the bottom 22a and sidewall 22b of the gate opening 22, and another portion of the electron transit layer 26 is provided on the upper surface of the third underlayer 20. The electron transit layer 26 is, for example, a film made of undoped GaN with a thickness of 150 nm. Note that the electron transit layer 26 does not have to be undoped, and may be made n-type by, for example, doping with Si.

[0074] The electron transit layer 26 is in contact with the drift layer 12 at the bottom 22 a and the sidewall 22 b of the gate opening 22. The electron transit layer 26 is in contact with the end faces of the first underlayer 14, the intermediate high-resistance layer 16, the second underlayer 18, and the third underlayer 20 at the sidewall 22 b of the gate opening 22. Furthermore, the electron transit layer 26 is in contact with the top surface of the third underlayer 20. The electron transit layer 26 is formed by crystal regrowth after the gate opening 22 is formed.

[0075] The electron transit layer 26 has a channel region of the first conductivity type. Specifically, a two-dimensional electron gas 30 is generated near the interface between the electron transit layer 26 and the electron supply layer 28. The two-dimensional electron gas 30 functions as a channel of the electron transit layer 26. In FIG. 1 , the two-dimensional electron gas 30 is schematically illustrated by a dashed line. The two-dimensional electron gas 30 bends along the interface between the electron transit layer 26 and the electron supply layer 28, i.e., along the inner surface of the gate opening 22.

[0076] 1, an AlN film having a thickness of about 1 nm may be provided as a second regrown layer between the electron transit layer 26 and the electron supply layer 28. The AlN film can suppress alloy scattering and improve the mobility of the channel.

[0077] The electron supply layer 28 is an example of a third regrown layer provided along the inner surface of the gate opening 22. The electron supply layer 28 is disposed above the electron transit layer 26. The electron supply layer 28 is formed to a shape that conforms to the upper surface of the electron transit layer 26 and to a substantially uniform thickness. The electron supply layer 28 is, for example, a film made of undoped AlGaN with a thickness of 50 nm. The electron supply layer 28 is formed by crystal regrowth following the step of forming the electron transit layer 26.

[0078] The electron supply layer 28 forms an AlGaN / GaN heterointerface with the electron transit layer 26. This generates a two-dimensional electron gas 30 in the electron transit layer 26. The electron supply layer 28 supplies electrons to a channel region (i.e., the two-dimensional electron gas 30) formed in the electron transit layer 26.

[0079] The threshold adjustment layer 32 is an example of a sixth semiconductor layer of the second conductivity type arranged above the semiconductor laminated film 24. Specifically, the threshold adjustment layer 32 is provided between the gate electrode 38 and the electron supply layer 28. The threshold adjustment layer 32 is formed to a shape that follows the upper surface of the electron supply layer 28 and to a substantially uniform thickness.

[0080] The threshold adjustment layer 32 has, for example, a thickness of 100 nm and a carrier concentration of 1×10 １７ cm －３The threshold adjustment layer 32 is a nitride semiconductor layer made of p-type GaN or AlGaN. The threshold adjustment layer 32 is formed by regrowth using MOVPE following the step of forming the electron supply layer 28, and then patterning the film. The electron transit layer 26, the electron supply layer 28, and the threshold adjustment layer 32 can be formed consecutively in this order in the same chamber.

[0081] The provision of the threshold adjustment layer 32 raises the potential of the conduction band edge in the channel portion. This increases the threshold voltage of the nitride semiconductor device 1. This allows the nitride semiconductor device 1 to be realized as a normally-off FET. In other words, when a potential of 0 V is applied to the gate electrode 38, the nitride semiconductor device 1 can be turned off.

[0082] The source opening 34 is an example of a second opening that penetrates the semiconductor stacked film 24 and the third underlayer 20 and reaches the second underlayer 18 at a position away from the gate opening 22. The source opening 34 is located at a position away from the gate electrode 38 in a plan view.

[0083] The bottom 34a of the source opening 34 is part of the upper surface of the second underlayer 18. As shown in Fig. 1, the bottom 34a is located lower than the lower surface of the third underlayer 20. The lower surface of the third underlayer 20 corresponds to the interface between the third underlayer 20 and the second underlayer 18. The bottom 34a is parallel to the first main surface 10a of the substrate 10, for example.

[0084] 1, the source opening 34 is formed so that the opening area is constant regardless of the distance from the substrate 10. Specifically, the sidewall 34b of the source opening 34 is perpendicular to the bottom 34a. In other words, the cross-sectional shape of the source opening 34 is rectangular.

[0085] Like the gate opening 22, the source opening 34 may be formed so that its opening area increases with increasing distance from the substrate 10. Specifically, the sidewalls 34b of the source opening 34 may be obliquely inclined. For example, the cross-sectional shape of the source opening 34 may be an inverted trapezoid, more specifically, an inverted isosceles trapezoid. In this case, the inclination angle of the sidewalls 34b relative to the bottom 34a may be, for example, between 30° and 60°. For example, the inclination angle of the sidewalls 34b of the source opening 34 may be larger than the inclination angle of the sidewalls 22b of the gate opening 22. The oblique inclination of the sidewalls 34b increases the contact area between the source electrode 36 and the electron transit layer 26 (two-dimensional electron gas 30), thereby facilitating ohmic contact. The two-dimensional electron gas 30 is exposed at the sidewalls 34b of the source opening 34 and connected to the source electrode 36 at the exposed portion.

[0086] The source opening 34 is formed, for example, following the step of forming the threshold adjustment layer 32 (i.e., a crystal regrowth step), by etching the threshold adjustment layer 32, the electron supply layer 28, the electron transit layer 26, and the third underlayer 20 so as to expose the second underlayer 18 in a region different from the gate opening 22. At this time, a surface portion of the second underlayer 18 is also removed, so that a bottom 34a of the source opening 34 is formed below the lower surface of the third underlayer 20. The source opening 34 is formed into a predetermined shape by, for example, patterning using photolithography and dry etching.

[0087] The source electrode 36 is disposed at a distance from the gate electrode 38. In this embodiment, the source electrode 36 is provided along the inner surface of the source opening 34. Specifically, the source electrode 36 is connected to each of the electron supply layer 28, the electron transit layer 26, and the second underlayer 18. The source electrode 36 is in ohmic contact with each of the electron transit layer 26 and the electron supply layer 28. The source electrode 36 is in direct contact with the two-dimensional electron gas 30 at the sidewall 34b. This reduces the contact resistance between the source electrode 36 and the two-dimensional electron gas 30 (channel).

[0088] The source electrode 36 is formed using a conductive material such as a metal. For example, a material such as Ti / Al that can be ohmically connected to the n-type GaN layer by heat treatment can be used as the material for the source electrode 36. The source electrode 36 is formed by patterning a conductive film formed by, for example, sputtering or vapor deposition.

[0089] The gate electrode 38 is disposed above the threshold adjustment layer 32. Specifically, the gate electrode 38 is provided in contact with the upper surface of the threshold adjustment layer 32 so as to cover the gate opening 22. The gate electrode 38 is formed, for example, with a shape that conforms to the upper surface of the threshold adjustment layer 32 and a substantially uniform film thickness. Alternatively, the gate electrode 38 may be formed so as to fill a recess in the upper surface of the threshold adjustment layer 32.

[0090] The gate electrode 38 is formed using a conductive material such as a metal. For example, the gate electrode 38 is formed using palladium (Pd). The gate electrode 38 may be formed using a material that is Schottky-connected to the p-type GaN layer, such as a nickel (Ni)-based material, tungsten silicide (WSi), or gold (Au). The gate electrode 38 is formed by patterning a conductive film formed by sputtering or vapor deposition after the threshold adjustment layer 32 is formed, the source opening 34 is formed, or the source electrode 36 is formed.

[0091] The drain electrode 40 is provided on the lower surface side of the substrate 10, i.e., the side opposite the drift layer 12. Specifically, the drain electrode 40 is provided in contact with the second main surface 10b of the substrate 10. The drain electrode 40 is formed using a conductive material such as a metal. As with the material of the source electrode 36, the drain electrode 40 can be made of a material that forms an ohmic contact with the n-type GaN layer, such as Ti / Al. The drain electrode 40 is formed by patterning a conductive film formed by, for example, sputtering or vapor deposition.

[0092] [Configuration of Termination Portion] Next, the configuration of the termination portion 3 of the nitride semiconductor device 1 according to this embodiment will be described.

[0093] 1 , the third underlayer 20, the semiconductor laminated film 24, and the threshold adjustment layer 32 are not provided in the termination portion 3. For example, the third underlayer 20, the semiconductor laminated film 24, and the threshold adjustment layer 32 in the termination portion 3 are removed simultaneously with the formation of the source opening 34. In the termination portion 3, the top surface of the second underlayer 18 is located at the same height as the bottom 34a of the source opening 34. Note that "at the same height" means that the distance from the first main surface 10a of the substrate 10 is the same.

[0094] A groove 42 is provided in the termination portion 3. The groove 42 is an isolation trench for partitioning and isolating the transistor portion 2. The groove 42 penetrates the second underlayer 18, the intermediate high-resistance layer 16, and the first underlayer 14 to reach the drift layer 12.

[0095] The groove 42 has a bottom 42a and a sidewall 42b. In this embodiment, the groove 42 is a stepped portion having the sidewall 42b only on the transistor portion 2 side. In other words, the bottom 42a of the groove 42 is connected to the end face of the nitride semiconductor device 1. As shown in FIG. 2 , the groove 42 is provided in a ring shape surrounding the transistor portion 2.

[0096] A bottom 42a of the groove 42 is part of the upper surface of the drift layer 12. As shown in Fig. 1 , the bottom 42a is located lower than the lower surface of the first underlayer 14. The bottom 42a is parallel to the first main surface 10a of the substrate 10, for example.

[0097] 1, groove 42 is formed so that the opening area is constant regardless of the distance from substrate 10. Specifically, sidewall 42b of groove 42 is perpendicular to bottom 42a. In other words, the cross-sectional shape of groove 42 is rectangular.

[0098] The groove 42 is formed, for example, by performing dry etching with a different etching mask following the dry etching step for forming the source opening 34. Alternatively, the groove 42 may be formed by dry etching after the source electrode 36 or the gate electrode 38 is formed.

[0099] [Major Characteristic Configuration] Next, a description will be given of a major characteristic configuration of the nitride semiconductor device 1 according to this embodiment.

[0100] 1, in the nitride semiconductor device 1, a stacked structure of a p-type first underlayer 14, an intermediate high-resistance layer 16, and a p-type second underlayer 18 is provided between the source electrode 36 and the drain electrode 40. In other words, the intermediate high-resistance layer 16, which has high resistance, is sandwiched between two p-type semiconductor layers.

[0101] As described above, the intermediate high-resistance layer 16 is a nitride semiconductor layer such as GaN that is doped with impurities such as carbon to increase its resistance. The doped impurities can generate trap levels in the intermediate high-resistance layer 16.

[0102] In this embodiment, the second underlayer 18 is disposed above the intermediate high-resistance layer 16, so that electrons in the channel are less likely to be trapped in the trap level of the intermediate high-resistance layer 16. This makes it possible to suppress deterioration of the dynamic characteristics of the transistor section 2.

[0103] In addition, a first underlayer 14 is disposed below the intermediate high-resistance layer 16. The provision of the first underlayer 14 can suppress leakage current between the source electrode 36 and the drain electrode 40. For example, when a reverse voltage is applied to the pn junction formed between the first underlayer 14 and the drift layer 12, specifically when the drain electrode 40 has a higher potential than the source electrode 36, a depletion layer extends to the drift layer 12. This enables the nitride semiconductor device 1 to have a high breakdown voltage. As described above, in this embodiment, the drain electrode 40 has a higher potential than the source electrode 36 in both the off state and the on state. This allows the nitride semiconductor device 1 to have a high breakdown voltage.

[0104] Note that, if the sole purpose is to suppress electron trapping by the intermediate high-resistance layer 16, it is conceivable to dispose the intermediate high-resistance layer 16 between the first underlayer 14 and the drift layer 12. However, the crystal quality of the intermediate high-resistance layer 16 tends to deteriorate when doped with carbon or the like. Therefore, if the intermediate high-resistance layer 16 is disposed in a pn junction portion to which a high electric field is applied during off-state operation, there is a risk of deterioration in off-state characteristics. In this embodiment, by disposing the intermediate high-resistance layer 16 above the first underlayer 14, it is possible to suppress deterioration in off-state characteristics.

[0105] Furthermore, if the nitride semiconductor device 1 did not include the intermediate high-resistance layer 16, a parasitic npn structure, i.e., a parasitic bipolar transistor, would exist between the source electrode 36 and the drain electrode 40, consisting of the electron transit layer 26, the p-type first underlayer 14, the second underlayer 18, and the n-type drift layer 12. Therefore, when the nitride semiconductor device 1 is in the off state, if a current flows through the p-type first underlayer 14 or the second underlayer 18, the parasitic bipolar transistor may be turned on, potentially reducing the breakdown voltage of the nitride semiconductor device 1. In this case, the nitride semiconductor device 1 is likely to malfunction. In the present embodiment, the intermediate high-resistance layer 16 is provided to prevent the formation of the parasitic npn structure, thereby preventing malfunction of the nitride semiconductor device 1.

[0106] In this embodiment, a source opening 34 is provided that reaches the second underlayer 18. The channel (two-dimensional electron gas 30) is exposed at the sidewall 34b of the source opening 34, so that the source electrode 36 can come into contact with the channel at this exposed portion. This reduces the ohmic contact resistance between the source electrode 36 and the channel.

[0107] Furthermore, since the intermediate high-resistivity layer 16 is disposed below the second underlayer 18 with which the source electrode 36 contacts at the bottom 34a of the source opening 34, it is possible to suppress current flow through a parasitic pn diode formed between the source and drain, thereby improving the reliability of the nitride semiconductor device 1.

[0108] 1 is shorter than the distance D2. The distance D1 is the distance between the bottom 28a of the electron supply layer 28 and the drain electrode 40. The distance D2 is the distance between the bottom 16a of the intermediate high-resistance layer 16 and the drain electrode 40.

[0109] The bottom 28a of the electron supply layer 28 is the portion of the lower surface of the electron supply layer 28 that is closest to the drain electrode 40. Specifically, it is the portion of the lower surface of the electron supply layer 28 that is located within the gate opening 22 and is parallel to the bottom 22a of the gate opening 22. The bottom 16a of the intermediate high resistance layer 16 is the portion of the lower surface of the intermediate high resistance layer 16 that is closest to the drain electrode 40. In this embodiment, the lower surface of the intermediate high resistance layer 16 is parallel to the upper surface of the drain electrode 40 (the second main surface 10b of the substrate 10), so the bottom 16a is any portion of the lower surface of the intermediate high resistance layer 16.

[0110] The electron transit layer 26 and the electron supply layer 28 can be formed continuously by crystal growth. Therefore, the pn junction portion at the interface between the electron transit layer 26 and the electron supply layer 28, i.e., the bottom portion 28a of the electron supply layer 28, has few levels due to impurities or damage, and is the portion that can withstand the highest electric field strength in the nitride semiconductor device 1. By placing the bottom portion 28a of the electron supply layer 28 close to the drain electrode 40, the electric field generated between the gate electrode 38 or the source electrode 36 and the drain electrode 40 during the off state can be concentrated at the bottom portion 28a of the electron supply layer 28. This makes it possible to prevent the electric field from concentrating in weak portions, thereby improving the off characteristics.

[0111] [Modification] Next, a modification of the first embodiment will be described with reference to Fig. 3. Fig. 3 is a cross-sectional view of a nitride semiconductor device 101 according to a modification of the present embodiment.

[0112] 3, nitride semiconductor device 101 differs from nitride semiconductor device 1 shown in Fig. 1 in that it includes a source opening 134 and a source electrode 136 instead of source opening 34 and source electrode 36. The following description will focus on the differences from the embodiment, and description of commonalities may be omitted or simplified.

[0113] The source opening 134 is an example of a third opening that penetrates the semiconductor stack 24, the third underlayer 20, the second underlayer 18, and the intermediate high-resistance layer 16 at a position away from the gate opening 22 and reaches the first underlayer 14. The source opening 134 is located at a position away from the gate electrode 38 in a plan view.

[0114] A bottom 134a of the source opening 134 is part of the upper surface of the first underlayer 14. As shown in Fig. 3, the bottom 134a is located below the lower surface (bottom 16a) of the intermediate high-resistance layer 16. The lower surface of the intermediate high-resistance layer 16 corresponds to the interface between the intermediate high-resistance layer 16 and the first underlayer 14.

[0115] As described above, in this modification, the source opening 134 reaches the first underlayer 14. The source electrode 136 is provided along the inner surface of the source opening 134 and is therefore in contact with the first underlayer 14. Specifically, the source electrode 136 is connected to each of the electron supply layer 28, the electron transit layer 26, the second underlayer 18, and the first underlayer 14.

[0116] Therefore, as in the embodiment, the channel (two-dimensional electron gas 30) is exposed on the sidewall 34b of the source opening 134, and the source electrode 136 can come into contact with the channel at this exposed portion, thereby reducing the ohmic contact resistance between the source electrode 136 and the channel.

[0117] Furthermore, since the source electrode 136 is in contact with both the second underlayer 18 and the first underlayer 14, the potential of each layer can be firmly fixed, thereby further improving the off-state characteristics of the nitride semiconductor device 1.

[0118] The second underlayer 18 and the intermediate high-resistance layer 16 may be provided in the termination section 3. That is, in the termination section 3, the second underlayer 18 and the intermediate high-resistance layer 16 may be removed simultaneously with the formation of the source opening 134, so that the upper surface of the first underlayer 14 is exposed.

[0119] Second Embodiment Next, a second embodiment will be described.

[0120] The nitride semiconductor device according to the second embodiment differs from the first embodiment in that the drift layer includes a plurality of layers with different impurity concentrations. The following description will focus on the differences from the first embodiment and its modifications, and the description of the commonalities may be omitted or simplified.

[0121] [Configuration] First, the configuration of the nitride semiconductor device according to this embodiment will be described with reference to Fig. 4. Fig. 4 is a cross-sectional view of a nitride semiconductor device 201 according to this embodiment.

[0122] As shown in FIG. 4 , the nitride semiconductor device 201 differs from the nitride semiconductor device 1 according to the first embodiment in that it includes a drift layer 212 instead of the drift layer 12 .

[0123] The drift layer 212 is composed of multiple layers having different impurity concentrations. In this embodiment, the multiple layers are composed of two layers. Specifically, as shown in FIG. 3 , the drift layer 212 has a high-concentration layer 212 a and a low-concentration layer 212 b. The high-concentration layer 212 a and the low-concentration layer 212 b are formed continuously on the substrate 10 by crystal growth such as MOVPE.

[0124] The high-concentration layer 212a is an example of the n-th layer from the top among the multiple layers, where n is a natural number equal to or greater than 2. In the present embodiment, n is 2. The high-concentration layer 212a is provided in contact with the first main surface 10a of the substrate 10.

[0125] The high concentration layer 212a is, for example, a 7 μm thick n ＋ The impurity concentration (donor concentration) of the high concentration layer 212a is, for example, 3×10 １５ cm －３ That's it, 5 x 10 １６ cm －３ The range is as follows: 1.5 × 10 １６ cm －３ is.

[0126] The low-concentration layer 212b is an example of a layer located above the n-th layer. In this embodiment, the low-concentration layer 212b is the uppermost layer in the drift layer 212, and is provided between and in contact with the high-concentration layer 212a and the first underlayer 14. The impurity concentration of the low-concentration layer 212b is the lowest among the multiple layers constituting the drift layer 212. In other words, the impurity concentration of the low-concentration layer 212b is lower than the impurity concentration of the high-concentration layer 212a.

[0127] The low concentration layer 212b is, for example, a 1 μm thick n － The low concentration layer 212b is a film made of GaN of the type. The impurity concentration (donor concentration) of the low concentration layer 212b is, for example, 1×10 １５ cm －３ That's it, 3 x 10 １６ cm －３ The range is as follows: 9 × 10 １５ cm －３ is.

[0128] In this way, by making the impurity concentration of the low-concentration layer 212b on the first underlayer 14 side (upper side) lower than the donor concentration of the high-concentration layer 212a on the side closer to the substrate 10 (lower side), when a high voltage is applied to the drain electrode 40 in the off state, the extension of the depletion layer into the drift layer 212 is promoted. This makes it possible to increase the breakdown voltage of the nitride semiconductor device 201.

[0129] [Modification 1] Next, Modification 1 of the second embodiment will be described with reference to Fig. 5. Fig. 5 is a cross-sectional view of a nitride semiconductor device 202 according to this modification.

[0130] 5, the nitride semiconductor device 202 differs from the nitride semiconductor device 201 shown in Fig. 4 in that it includes a source opening 134 and a source electrode 136 instead of the source opening 34 and the source electrode 36. The source opening 134 and the source electrode 136 are the same as the source opening 134 and the source electrode 136 according to the modification of the first embodiment.

[0131] Therefore, the nitride semiconductor device 202 according to this modification can obtain the effects of both the nitride semiconductor devices 101 and 201. Specifically, the nitride semiconductor device 202 can further improve the off-state characteristics and increase the breakdown voltage.

[0132] [Modification 2] Next, Modification 2 of the second embodiment will be described with reference to Fig. 6. Fig. 6 is a cross-sectional view of a nitride semiconductor device 203 according to this modification.

[0133] As shown in FIG. 6, the nitride semiconductor device 203 differs from the nitride semiconductor device 202 shown in FIG. 5 in that it includes a gate opening 222 instead of the gate opening 22 .

[0134] The gate opening 222 penetrates the third underlayer 20, the second underlayer 18, the intermediate high-resistance layer 16, the first underlayer 14, and the low-concentration layer 212b to reach the high-concentration layer 212a. The bottom 222a of the gate opening 222 is part of the upper surface of the high-concentration layer 212a. As shown in FIG. 1, the bottom 222a is located below the lower surface of the low-concentration layer 212b. The lower surface of the low-concentration layer 212b corresponds to the interface between the low-concentration layer 212b and the high-concentration layer 212a.

[0135] As a result, in the on-state, the drain current flows from the drain electrode 40 through the substrate 10, the high-concentration layer 212a, and the two-dimensional electron gas 30 to the source electrode 36. Since the low-concentration layer 212b, which has high resistance, does not exist on the path of the drain current, the on-resistance can be reduced.

[0136] 6 is shorter than distance D4. Distance D3 is the distance between the bottom 222a of the gate opening 222 and the drain electrode 40. Distance D4 is the distance between the bottom 42a of the groove 42 and the drain electrode 40. This can improve the off-state characteristics of the nitride semiconductor device 203. Specifically, this is as follows.

[0137] When the transistor portion 2 is in the off state, a high voltage is applied between the drain electrode 40 and the source electrode 136, causing the drain electrode 40 side to have a higher potential than the source electrode 136 side. Therefore, in the off state, a high electric field is generated in the vertical direction of the nitride semiconductor device 203.

[0138] Because the distance D3 is shorter than the distance D4, the electric field is more likely to concentrate at the gate opening 222 of the transistor section 2 than at the termination section 3. The concentrated electric field can be received by the pn junction between the electron supply layer 28 and the electron transit layer 26. This pn junction is of higher quality and has a higher electric field strength than the pn junction between the first underlayer 14 and the drift layer 212 near the trench 42, which is subject to etching damage. Because the electric field concentration can be received at the pn junction with a higher electric field strength, the electric field concentration at the pn junction near the trench 42 can be alleviated.

[0139] In this way, it is possible to improve the off-state characteristics of the nitride semiconductor device 203. Specifically, it is possible to reduce the leakage current near the groove 42 and to suppress a decrease in the breakdown voltage. The greater the difference between the distance D3 and the distance D4, the more the electric field concentration near the groove 42 can be alleviated.

[0140] In this embodiment, the distance D1 may be shorter than the distance D4, which can reduce the concentration of the electric field near the groove 42.

[0141] Although the drift layer 212 has been described as having two stacked layers, the number of stacked layers may be three or more. When the drift layer 212 includes three or more semiconductor layers, the bottom 222 a of the gate opening 222 is located in a layer other than the uppermost layer, which has the lowest impurity concentration. In other words, the bottom 222 a is located in the nth layer (n is a natural number greater than or equal to 2) from the top of the multiple layers that make up the drift layer 212.

[0142] While nitride semiconductor devices according to one or more aspects have been described above based on embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0143] For example, the source opening 34 or 134 may not be provided. In this case, the source electrode 36 or 136 is provided on the upper surface of the semiconductor laminated film 24 at a position away from the threshold adjustment layer 32.

[0144] Furthermore, for example, the drift layer 12 may have a graded structure in which the impurity concentration (donor concentration) is gradually reduced from the substrate 10 side to the first underlayer 14 side. The donor concentration may be controlled by Si, which acts as a donor, or by carbon, which acts as an acceptor that compensates for Si.

[0145] Furthermore, for example, the termination portion 3 does not have to include an end face of the nitride semiconductor device. The termination portion 3 is a portion for separating the transistor portion 2 from other devices. Another element may be disposed in an adjacent region of the transistor portion 2, sandwiching the termination portion 3 therebetween. For example, the other element is a pn diode that utilizes a pn junction between the drift layer 12 and the first underlayer 14. In this case, the nitride semiconductor device includes the transistor portion 2, the termination portion 3, and the pn diode.

[0146] Alternatively, the first conductivity type may be p-type, p+ type, or p- type, and the second conductivity type may be n-type, n+ type, or n- type.

[0147] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to each of the above-described embodiments within the scope of the claims or their equivalents.

[0148] The present disclosure can be used as a nitride semiconductor device with improved electrical characteristics, and can be used in power devices such as power transistors used in power supply circuits of consumer appliances such as televisions.

[0149] 1, 101, 201, 202, 203 Nitride semiconductor device 2 Transistor section 3 Termination section 10 Substrate 10a First main surface 10b Second main surface 12, 212 Drift layer 14 First underlayer 16 Intermediate high-resistance layer 16a, 22a, 28a, 34a, 42a, 134a, 222a Bottom 18 Second underlayer 20 Third underlayer 22, 222 Gate opening 22b, 34b, 42b Sidewall 24 Semiconductor laminated film 26 Electron transit layer 28 Electron supply layer 30 Two-dimensional electron gas 32 Threshold adjustment layer 34, 134 Source opening 36, 136 Source electrode 38 Gate electrode 40 Drain electrode 42 Groove 212a Highly-doped layer 212b Low-doped layer

Claims

1. A substrate, A first semiconductor layer of a first conductivity type disposed above the substrate, A second semiconductor layer of a second conductivity type disposed above the first semiconductor layer, A third semiconductor layer disposed above the second semiconductor layer and having a higher resistance than the second semiconductor layer, A fourth semiconductor layer of the second conductivity type disposed above the third semiconductor layer, A fifth semiconductor layer having a channel region of the first conductivity type, wherein a part of the fifth semiconductor layer is disposed along an inner surface of a first opening that penetrates the fourth semiconductor layer, the third semiconductor layer, and the second semiconductor layer and reaches the first semiconductor layer, and another part of the fifth semiconductor layer is disposed above the fourth semiconductor layer. A fifth semiconductor layer, A nitride semiconductor device.

2. Comprising a drain electrode disposed on the lower surface side of the substrate, The fifth semiconductor layer includes an electron traveling layer and an electron supply layer disposed above the electron traveling layer, The distance between the bottom of the electron supply layer and the drain electrode is shorter than the distance between the bottom of the third semiconductor layer and the drain electrode, The nitride semiconductor device according to claim 1.

3. A sixth semiconductor layer of the second conductivity type disposed above the fifth semiconductor layer, A gate electrode disposed above the sixth semiconductor layer, A source electrode disposed spaced apart from the gate electrode, The source electrode is a second opening provided spaced apart from the gate electrode, and is provided along an inner surface of the second opening that penetrates the fifth semiconductor layer and reaches the fourth semiconductor layer. The nitride semiconductor device according to claim 1 or 2.

4. The source electrode is a third opening provided spaced apart from the gate electrode, and is provided along an inner surface of the third opening that penetrates the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer and reaches the second semiconductor layer. The nitride semiconductor device according to claim 3.

5. The third semiconductor layer contains C, Fe, B, or Mg. The nitride semiconductor device according to claim 1 or 2.

6. The first semiconductor layer is composed of a plurality of layers having different impurity concentrations, The impurity concentration of the uppermost layer among the plurality of layers is the lowest among the plurality of layers. The nitride semiconductor device according to claim 1 or 2.

7. ​ ​ ​ ​ The bottom of the first opening is located in the n-th (n is a natural number of 2 or more) layer from the top among the plurality of layers. The nitride semiconductor device according to claim 6.

8. A groove reaching the first semiconductor layer is provided at the end portion of the nitride semiconductor device. The nitride semiconductor device according to claim 1 or 2.

9. It includes a drain electrode provided on the lower surface side of the substrate. A groove reaching the first semiconductor layer is provided at the end portion of the nitride semiconductor device. The distance between the bottom of the first opening and the drain electrode is shorter than the distance between the bottom of the groove and the drain electrode. The nitride semiconductor device according to claim 1.