Semiconductor device, motor system, and vehicle

Abstract

This semiconductor device (1) comprises: upper-side control input terminals (T1p, T2p, T3p); lower-side control input terminals (T1n, T2n, T3n); a power source terminal (Tvb); a control logic unit (16); a reference power source circuit (2) that is configured to be supplied with the power source voltage and to be able to generate a reference power source voltage (VDD) that is to be supplied to the control logic unit; and a switch circuit (3) having switches (SW1p, SW2p, SW3p, SW1n, SW2n, SW3n) that are provided with respect to the respective ones of upper-side control input signals and lower-side control input signals and the ON and OFF of which are switched according to the logic levels of the upper-side control input signals and of the lower-side control input signals. The reference power source circuit is activated on the basis of a combination of the logic levels of the upper-side control input signals and of the lower-side control input signals.

Description

Semiconductor device, motor system, and vehicle

[0001] The present disclosure relates to semiconductor devices.

[0002] Conventionally, semiconductor devices capable of driving a half-bridge formed by connecting an upper transistor (high-side transistor) and a lower transistor (low-side transistor) are known, including, for example, a motor drive device that drives a three-phase brushless direct current (DC) motor using a three-phase (U-phase, V-phase, W-phase) half-bridge (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2021-40404

[0004] In the semiconductor device described above, it is desired to reduce the size by reducing the number of external terminals (number of pins) while maintaining the same functionality.

[0005] An object of the present disclosure is to provide a semiconductor device that can be downsized by reducing the number of external terminals in a configuration capable of driving a half bridge.

[0006] For example, a semiconductor device according to the present disclosure is a semiconductor device configured to be capable of driving at least one half bridge including an upper transistor and a lower transistor, and comprising: an upper control input terminal configured to be able to input an upper control input signal for driving and controlling the upper transistor; a lower control input terminal configured to be able to input a lower control input signal for driving and controlling the lower transistor; a power supply terminal configured to be able to input a power supply voltage; a control logic unit; a reference power supply circuit configured to receive the power supply voltage and generate a reference power supply voltage to be supplied to the control logic unit; and switch circuits provided for the upper control input signal and the lower control input signal, respectively, having switches that are switched on and off according to the logic levels of the upper control input signal and the lower control input signal, wherein the reference power supply circuit is configured to be activated based on a combination of the logic levels of the upper control input signal and the lower control input signal.

[0007] According to the semiconductor device according to the present disclosure, in a configuration capable of driving a half bridge, it is possible to reduce the size by reducing the number of external terminals.

[0008] FIG. 1 is a diagram showing the configuration of a motor system according to a comparative example. FIG. 2 is a timing chart relating to the start-up of a semiconductor device according to a comparative example. FIG. 3 is a diagram showing the configuration of a motor system according to an embodiment of the present disclosure. FIG. 4 is a diagram showing a specific example configuration of a reference power supply circuit and a switch circuit. FIG. 5 is a timing chart relating to the start-up of a semiconductor device according to an embodiment of the present disclosure. FIG. 6 is a diagram showing the configuration of a switch circuit according to a modified example. FIG. 7 is an external view showing an example configuration of a vehicle equipped with a motor system.

[0009] Exemplary embodiments of the present disclosure will now be described with reference to the drawings.

[0010] <1. Comparative Example> Before describing the embodiments of the present disclosure, a comparative example will be described for comparison, which will clarify the problems of the present disclosure.

[0011] <1.1 Overall Configuration> Figure 1 is a diagram showing the configuration of a motor system 50 according to a comparative example. The motor system 50 according to the comparative example shown in Figure 1 includes a semiconductor device 10, a brushless DC motor (hereinafter simply referred to as a motor) 35, and a microcomputer 30. The semiconductor device 10 is configured as a gate driver that drives transistors in a three-phase half bridge UH, VH, and WH that is provided to drive the three-phase (U-phase, V-phase, and W-phase) motor 35. The motor 35 is for use in a vehicle.

[0012] The semiconductor device 10 has a regulator 11, a reference power supply circuit 12, a Schmitt buffer 13, Schmitt buffers 14A to 14F, a charge pump 15, a control logic unit 16, pre-drivers 17H and 17L, pre-drivers 18H and 18L, and pre-drivers 19H and 19L integrated on a single chip, and is packaged by sealing the chip with a sealing material (resin or the like).

[0013] Furthermore, semiconductor device 10 includes, as external terminals (pins) for establishing electrical connection with the outside, a power supply terminal Tvb, a regulator output terminal Tvcc, an enable terminal Teb, a U-phase upper control input terminal T1p, a U-phase lower control input terminal T1n, a V-phase upper control input terminal T2p, a V-phase lower control input terminal T2n, a W-phase upper control input terminal T3p, a W-phase lower control input terminal T3n, a U-phase upper drive output terminal DUH, a U-phase upper source terminal VSUH, a U-phase lower drive output terminal DUL, a U-phase lower source terminal VSUL, a V-phase upper drive output terminal DVH, a V-phase upper source terminal VSVH, a V-phase lower drive output terminal DVL, a V-phase lower source terminal VSVL, a W-phase upper drive output terminal DWH, a W-phase upper source terminal VSWH, a W-phase lower drive output terminal DWL, and a W-phase lower source terminal VSWL.

[0014] In addition to the external terminals shown in FIG. 1 , the semiconductor device 10 also includes a terminal for connecting a charge pump capacitor, a terminal used for both charge pump output and for controlling a power supply relay (not shown) provided between the application terminal of the power supply voltage VB and the half bridges UH, VH, and WH, a terminal for controlling a motor relay transistor (not shown) provided between the half bridges UH, VH, and WH and the motor 35, a terminal for connecting shunt resistors of each phase (the shunt resistors are not shown in FIG. 1 ), a terminal for outputting a voltage obtained by amplifying the voltage across the shunt resistor of each phase to the microcomputer 30, and a terminal for SPI (Serial Peripheral Interface) communication with the microcomputer 30.

[0015] 1.2 Motor Driving Configuration The motor system 50 includes, outside the semiconductor device 10, a U-phase half-bridge UH, a V-phase half-bridge VH, a W-phase half-bridge WH, capacitors C1H, C1L, C2H, C2L, C3H, C3L, and capacitors R1H, R1L, R2H, R2L, R3H, R3L.

[0016] The U-phase half bridge UH has a U-phase upper transistor Q1H and a U-phase lower transistor Q1L. The U-phase upper transistor Q1H and the U-phase lower transistor Q1L are configured by N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). The drain of the U-phase upper transistor Q1H is connected to the application terminal of the power supply voltage VB. The power supply voltage VB is the battery voltage.

[0017] The source of the U-phase upper transistor Q1H is connected to the drain of the U-phase lower transistor Q1L, the source of which is connected to a terminal to which the ground potential is applied via a U-phase shunt resistor (not shown).

[0018] A pull-down resistor R1H is connected to the gate of the U-phase upper transistor Q1H. A capacitor C1H is connected between the gate and source of the U-phase upper transistor Q1H. A pull-down resistor R1L is connected to the gate of the U-phase lower transistor Q1L. A capacitor C1L is connected between the gate and source of the U-phase lower transistor Q1L.

[0019] In the semiconductor device 10, the power supply terminal Tvb is connected to an application terminal of the power supply voltage VB. The charge pump 15 boosts the power supply voltage VB input to the power supply terminal Tvb and outputs a lower boosted voltage VCPL and an upper boosted voltage VCPH. The lower boosted voltage VCPL is the output of the first stage of the charge pump 15, and the upper boosted voltage VCPH is the output of the second stage of the charge pump 15. VCPH>VCPL.

[0020] The gate of the U-phase upper transistor Q1H is connected to the U-phase upper drive output terminal DUH. The output terminal of the pre-driver 17H is connected to the U-phase upper drive output terminal DUH. The source of the U-phase upper transistor Q1H is connected to the U-phase upper source terminal VSUH. The pre-driver 17H is connected to the application terminal of the high-side boosted voltage VCPH and the U-phase upper source terminal VSUH.

[0021] The gate of the U-phase low-side transistor Q1L is connected to the U-phase low-side drive output terminal DUL. The output terminal of the pre-driver 17L is connected to the U-phase low-side drive output terminal DUL. The source of the U-phase low-side transistor Q1L is connected to the U-phase low-side source terminal VSUL. The pre-driver 17L is connected to the application terminal of the low-side boosted voltage VCPL and the U-phase low-side source terminal VSUL.

[0022] The V-phase half bridge VH includes a V-phase upper transistor Q2H and a V-phase lower transistor Q2L. The V-phase upper transistor Q2H and the V-phase lower transistor Q2L are each configured using an N-channel MOSFET. The drain of the V-phase upper transistor Q2H is connected to the application terminal of the power supply voltage VB.

[0023] The source of the V-phase upper transistor Q2H is connected to the drain of the V-phase lower transistor Q2L, the source of which is connected to a terminal to which the ground potential is applied via a V-phase shunt resistor (not shown).

[0024] A pull-down resistor R2H is connected to the gate of the V-phase upper transistor Q2H. A capacitor C2H is connected between the gate and source of the V-phase upper transistor Q2H. A pull-down resistor R2L is connected to the gate of the V-phase lower transistor Q2L. A capacitor C2L is connected between the gate and source of the V-phase lower transistor Q2L.

[0025] The gate of the V-phase upper transistor Q2H is connected to the V-phase upper drive output terminal DVH. The output terminal of the pre-driver 18H is connected to the V-phase upper drive output terminal DVH. The source of the V-phase upper transistor Q2H is connected to the V-phase upper source terminal VSVH. The pre-driver 18H is connected to the application terminal of the high-side boosted voltage VCPH and the V-phase upper source terminal VSVH.

[0026] The gate of the V-phase low-side transistor Q2L is connected to the V-phase low-side drive output terminal DVL. The output terminal of the pre-driver 18L is connected to the V-phase low-side drive output terminal DVL. The source of the V-phase low-side transistor Q2L is connected to the V-phase low-side source terminal VSVL. The pre-driver 18L is connected to the application terminal of the low-side boosted voltage VCPL and the V-phase low-side source terminal VSVL.

[0027] The W-phase half bridge WH includes a W-phase upper transistor Q3H and a W-phase lower transistor Q3L. The W-phase upper transistor Q3H and the W-phase lower transistor Q3L are each configured by an N-channel MOSFET. The drain of the W-phase upper transistor Q3H is connected to the application terminal of the power supply voltage VB.

[0028] The source of the W-phase upper transistor Q3H is connected to the drain of the W-phase lower transistor Q3L, the source of which is connected to a terminal to which the ground potential is applied via a W-phase shunt resistor (not shown).

[0029] A pull-down resistor R3H is connected to the gate of the W-phase upper transistor Q3H. A capacitor C3H is connected between the gate and source of the W-phase upper transistor Q3H. A pull-down resistor R3L is connected to the gate of the W-phase lower transistor Q3L. A capacitor C3L is connected between the gate and source of the W-phase lower transistor Q3L.

[0030] The gate of the W-phase upper transistor Q3H is connected to the W-phase upper drive output terminal DWH. The output terminal of the pre-driver 19H is connected to the W-phase upper drive output terminal DWH. The source of the W-phase upper transistor Q3H is connected to the W-phase upper source terminal VSWH. The pre-driver 19H is connected to the application terminal of the high-side boosted voltage VCPH and the W-phase upper source terminal VSWH.

[0031] The gate of the W-phase low-side transistor Q3L is connected to the W-phase low-side drive output terminal DWL. The output terminal of the pre-driver 19L is connected to the W-phase low-side drive output terminal DWL. The source of the W-phase low-side transistor Q3L is connected to the W-phase low-side source terminal VSWL. The pre-driver 19L is connected to the application terminal of the low-side boosted voltage VCPL and the W-phase low-side source terminal VSWL.

[0032] A node NU connecting the U-phase upper transistor Q1H and the U-phase lower transistor Q1L is connected to a U-phase coil (not shown) included in the motor 35. A node NV connecting the V-phase upper transistor Q2H and the V-phase lower transistor Q2L is connected to a V-phase coil (not shown) included in the motor 35. A node NW connecting the W-phase upper transistor Q3H and the W-phase lower transistor Q3L is connected to a W-phase coil (not shown) included in the motor 35. The coils of each phase are so-called star-connected. However, the coils of each phase may also be delta-connected.

[0033] In the semiconductor device 10, the regulator 11 generates a power supply voltage VCC by stepping down the power supply voltage VB input to the power supply terminal Tvb, and outputs the generated power supply voltage VCC to the microcomputer 30 from the regulator output terminal Tvcc.

[0034] Furthermore, a U-phase upper control input signal IN1P is input from the microcomputer 30 to the U-phase upper control input terminal T1p. The input U-phase upper control input signal IN1P is input to the control logic unit 16 via a Schmitt buffer 14A. A U-phase lower control input signal IN1N is input from the microcomputer 30 to the U-phase lower control input terminal T1n. The input U-phase lower control input signal IN1N is input to the control logic unit 16 via a Schmitt buffer 14B.

[0035] A V-phase upper control input signal IN2P is input from the microcomputer 30 to the V-phase upper control input terminal T2p. The input V-phase upper control input signal IN2P is input to the control logic unit 16 via a Schmitt buffer 14C. A V-phase lower control input signal IN2N is input from the microcomputer 30 to the V-phase lower control input terminal T2n. The input V-phase lower control input signal IN2N is input to the control logic unit 16 via a Schmitt buffer 14D.

[0036] A W-phase upper control input signal IN3P is input from the microcomputer 30 to the W-phase upper control input terminal T3p. The input W-phase upper control input signal IN3P is input to the control logic unit 16 via a Schmitt buffer 14E. A W-phase lower control input signal IN3N is input from the microcomputer 30 to the W-phase lower control input terminal T3n. The input W-phase lower control input signal IN3N is input to the control logic unit 16 via a Schmitt buffer 14F.

[0037] Each of the control input signals IN1P to IN3N is a pulse signal having a high level and a low level. The Schmitt buffers 14A to 14F binarize the input control input signals IN1P to IN3N into a high level and a low level and output the binarized signals.

[0038] The control logic unit 16 drives the pre-driver 17H based on the output of the Schmitt buffer 14A, so that the pre-driver 17H outputs the high-side boosted voltage VCPH or the potential of the U-phase high-side source terminal VSUH to the gate of the U-phase high-side transistor Q1H, thereby driving the U-phase high-side transistor Q1H for switching.

[0039] The control logic unit 16 drives the pre-driver 17L based on the output of the Schmitt buffer 14B, whereby the pre-driver 17L outputs the low-side boosted voltage VCPL or the potential of the U-phase low-side source terminal VSUL to the gate of the U-phase low-side transistor Q1L, thereby driving the U-phase low-side transistor Q1L for switching.

[0040] The control logic unit 16 drives the pre-driver 18H based on the output of the Schmitt buffer 14C, whereby the pre-driver 18H outputs the high-side boosted voltage VCPH or the potential of the V-phase high-side source terminal VSVH to the gate of the V-phase high-side transistor Q2H, thereby driving the V-phase high-side transistor Q2H for switching.

[0041] The control logic unit 16 drives the pre-driver 18L based on the output of the Schmitt buffer 14D, so that the pre-driver 18L outputs the low-side boosted voltage VCPL or the potential of the V-phase low-side source terminal VSVL to the gate of the V-phase low-side transistor Q2L, thereby driving the V-phase low-side transistor Q2L for switching.

[0042] The control logic unit 16 drives the pre-driver 19H based on the output of the Schmitt buffer 14E, whereby the pre-driver 19H outputs the high-side boosted voltage VCPH or the potential of the W-phase high-side source terminal VSWH to the gate of the W-phase high-side transistor Q3H, thereby driving the W-phase high-side transistor Q3H for switching.

[0043] The control logic unit 16 drives the pre-driver 19L based on the output of the Schmitt buffer 14F, whereby the pre-driver 19L outputs the low-side boosted voltage VCPL or the potential of the W-phase low-side source terminal VSWL to the gate of the W-phase low-side transistor Q3L, thereby driving the W-phase low-side transistor Q3L for switching.

[0044] In this way, the transistors in the half bridges UH, VH, and WH of each phase are driven and controlled based on the control input signals IN1P to IN3N, thereby enabling the motor 35 to be driven and controlled.

[0045] For each of the U-phase control input signals IN1P and IN1N, the V-phase control input signals IN2P and IN2N, and the W-phase control input signals IN3P and IN3N, the upper and lower control input signals have complementary levels. That is, when one is high, the other is low, and when one is low, the other is high. As a result, the upper and lower transistors in each half bridge UH, VH, and WH of each phase are driven complementarily. That is, when one is on, the other is off, and when one is off, the other is on. A dead time (simultaneous off period) during which the upper and lower transistors are simultaneously off may be provided. In this case, the upper and lower control input signals are simultaneously low.

[0046] The transistors in the half-bridges UH, VH, and WH of each phase are driven in accordance with the duty cycle of the control input signal, thereby performing PWM (pulse width modulation) control, which generates drive voltages with phase-shifted AC waveforms at the nodes NU, NV, and NW, thereby driving the motor 35.

[0047] 1.3 Reference Power Supply Circuit In the semiconductor device 10, an enable signal EB can be applied to an enable terminal Teb from the outside. The enable signal EB is generated by a power supply voltage VB. The enable signal EB input to the enable terminal Teb is converted by a Schmitt buffer 13 into a binary enable signal ENA consisting of high and low levels. The enable signal ENA is input to a reference power supply circuit 12.

[0048] The reference power supply circuit 12 includes an LDO (Low Drop Out) that is a series regulator (not shown). The LDO reduces the power supply voltage VB and converts it into a reference power supply voltage VDD. The reference power supply voltage VDD is supplied to the control logic unit 16 as a power supply.

[0049] The start-up of the semiconductor device 10 will now be described with reference to the timing chart of Fig. 2. Fig. 2 shows, from the top to the bottom, the power supply voltages VB and VCC, the enable signal EB, and the state of the semiconductor device 10.

[0050] When the ignition of the vehicle equipped with the motor system 50 is turned on, the power supply voltage (battery voltage) VB is turned on. As a result, the power supply voltage VB starts to rise from 0 V, as shown in Figure 2. Accordingly, the power supply voltage VCC that serves as the power supply for the microcomputer 30 also rises.

[0051] At this time, the enable signal EB also rises, and when it exceeds the threshold voltage of the Schmitt buffer 13, the enable signal ENA output from the Schmitt buffer 13 switches from low to high. This activates the reference power supply circuit 12 (LDO) and turns on the reference power supply voltage VDD. Therefore, the semiconductor device 10 transitions from the sleep state to the standby state in which the control logic unit 16 is operable by the supply of the reference power supply voltage VDD.

[0052] As described above, in the comparative example, the semiconductor device 10 can be activated using the enable signal EB, but the need for the enable terminal Teb poses a problem of increasing the number of external terminals (number of pins) of the semiconductor device 10. Specifically, for example, if there are 48-pin packages and 64-pin packages for semiconductor devices, the need for the enable terminal Teb makes it impossible to keep the number of pins below 48, resulting in a pin count of, for example, 49 pins, and the semiconductor device 10 may have no choice but to use a 64-pin package. Increasing the number of pins leads to an increase in the size of the semiconductor device 10.

[0053] 2. Embodiments of the Present Disclosure In order to solve the above-described problems, the following embodiments of the present disclosure are implemented. That is, the embodiments of the present disclosure aim to reduce the number of pins while maintaining the function of starting up a semiconductor device.

[0054] 2.1 Configuration of Semiconductor Device Figure 3 is a diagram showing the configuration of a motor system 5 according to an embodiment of the present disclosure. The motor system 5 shown in Figure 3 differs from the comparative example (Figure 1) described above in that it includes a semiconductor device 1. Note that the external configuration of the semiconductor device 1 in the motor system 5 (motor 35, microcomputer 30, half bridges for each phase, etc.) is the same as that in the comparative example, and therefore will not be described here.

[0055] 3, the semiconductor device 1 differs from the semiconductor device 10 (FIG. 1) according to the comparative example in that it includes a reference power supply circuit 2 and a switch circuit 3. Note that the configuration of the semiconductor device 1 other than the reference power supply circuit 2 and the switch circuit 3 is the same as that of the semiconductor device 10 according to the comparative example, and therefore description thereof will be omitted here.

[0056] Furthermore, unlike the semiconductor device 10 according to the comparative example, the semiconductor device 1 according to the embodiment of the present disclosure does not include an enable terminal EB, which is an external terminal. The reason why the enable terminal EB is unnecessary will be described later. Note that the other external terminals of the semiconductor device 1 are similar to those of the semiconductor device 10 according to the comparative example, and therefore will not be described here.

[0057] 4 is a diagram showing a specific example of the configuration of the reference power supply circuit 2 and the switch circuit 3. The reference power supply circuit 2 has a Zener diode 21, a resistor 22, a PDMOS transistor (P-channel double-diffused MOSFET) 23, a resistor 24, a Zener diode 25, an NDMOS transistor (N-channel double-diffused MOSFET) 26, a resistor 27, a bandgap reference 28, and an LDO 29.

[0058] The cathode of the Zener diode 21 is connected to the terminal to which the power supply voltage VB is applied. The anode of the Zener diode 21 is connected to one end of a resistor 22. The other end of the resistor 22 is connected to the switch circuit 3. A node N1, at which the Zener diode 21 and the resistor 22 are connected, is connected to the gate of a PDMOS transistor 23. The source of the PDMOS transistor 23 is connected to the terminal to which the power supply voltage VB is applied. The drain of the PDMOS transistor 23 is connected to one end of a resistor 24. The other end of the resistor 24 is connected to the cathode of a Zener diode 25. The anode of the Zener diode 25 is connected to the terminal to which the ground potential is applied. A node N2, at which the resistor 24 and the Zener diode 25 are connected, is connected to the gate of an NDMOS transistor 26. The drain of the NDMOS transistor 26 is connected to one end of a resistor 27. The other end of the resistor 27 is connected to the terminal to which the power supply voltage VB is applied.

[0059] The switch circuit 3 also has a U-phase upper switch SW1p, a U-phase lower switch SW1n, a V-phase upper switch SW2p, a V-phase lower switch SW2n, a W-phase upper switch SW3p, and a W-phase lower switch SW3n, and each of these switches is configured by an N-channel MOSFET.

[0060] The drain of the U-phase upper switch SW1p is connected to the other end of the resistor 22. The source of the U-phase upper switch SW1p is connected to the drain of the U-phase lower switch SW1n. The source of the U-phase lower switch SW1n is connected to the drain of the V-phase upper switch SW2p. The source of the V-phase upper switch SW2p is connected to the drain of the V-phase lower switch SW2n. The source of the V-phase lower switch SW2n is connected to the drain of the W-phase upper switch SW3p. The source of the W-phase upper switch SW3p is connected to the drain of the W-phase lower switch SW3n. The source of the W-phase lower switch SW3n is connected to the terminal to which the ground potential is applied. In other words, the switches SW1p to SW3n are connected in series. The order in which the switches are connected is not limited to the configuration of FIG. 4 and can be any order.

[0061] A U-phase upper control input signal IN1P is input to the gate of the U-phase upper switch SW1p. A U-phase lower control input signal IN1N is input to the gate of the U-phase lower switch SW1n. A V-phase upper control input signal IN2P is input to the gate of the V-phase upper switch SW2p. A V-phase lower control input signal IN2N is input to the gate of the V-phase lower switch SW2n. A W-phase upper control input signal IN3P is input to the gate of the W-phase upper switch SW3p. A W-phase lower control input signal IN3N is input to the gate of the W-phase lower switch SW3n.

[0062] The startup of the semiconductor device 1 using the configuration shown in Fig. 4 will now be described with reference to the timing chart of Fig. 5. In Fig. 5, from the top to bottom, the power supply voltages VB and VCC, the control input signals IN1P, IN1N, IN2P, IN2N, IN3P, and IN3N, and the states of the semiconductor device 1 are shown.

[0063] When the ignition of the vehicle equipped with the motor system 5 is turned on, the power supply voltage (battery voltage) VB is turned on. As a result, the power supply voltage VB starts to rise from 0 V (timing t1), as shown in Fig. 5. Accordingly, the power supply voltage VCC that serves as the power supply for the microcomputer 30 also rises.

[0064] After the power supply voltages VB and VCC reach a steady state (high level) at time t2, the microcomputer 30 switches each of the control input signals IN1P, IN1N, IN2P, IN2N, IN3P, and IN3N from low level to high level (time t3), which turns on all of the switches SW1p to SW3n and causes current to flow through the Zener diode 21.

[0065] The voltage V1 generated at node N1 is clamped to a voltage lower than the power supply voltage VB by the breakdown voltage of Zener diode 21. Therefore, PDMOS transistor 23 is turned on, and current flows through Zener diode 25. As a result, voltage V2 applied to the gate of NDMOS transistor 26 (the voltage at node N2) is clamped to the breakdown voltage of Zener diode 25. Therefore, the source voltage of NDMOS transistor 26, which is approximately voltage V2, is applied to bandgap reference 28. Bandgap reference 28 generates a reference voltage Vref based on the source voltage of NDMOS transistor 26.

[0066] Since the reference voltage Vref is turned ON, the LDO regulator 29 is activated and steps down the power supply voltage VB to generate the reference power supply voltage VDD. The generated reference power supply voltage VDD is supplied to the control logic unit 16. As a result, the semiconductor device 1 transitions from the sleep state to the standby state in which the control logic unit 16 is operable due to the supply of the reference power supply voltage VDD.

[0067] 4, the control logic unit 16 has a flip-flop 16A. The semiconductor device 1 also has a power-on reset unit 4. A reset release signal RST output from the power-on reset unit 4 is input to a D terminal of the flip-flop 16A. A clock signal CLK is input to a clock terminal of the flip-flop 16A.

[0068] The switch circuit 3 has a latching switch 3A. The latching switch 3A is configured by an N-channel MOSFET. The drain of the latching switch 3A is connected to the drain of the U-phase upper switch SW1p. The source of the latching switch 3A is connected to the terminal to which the ground potential is applied. In other words, the latching switch 3A is connected in parallel with the series-connected configuration of each of the switches SW1p to SW3n. The Q output terminal of the flip-flop 16A is connected to the gate of the latching switch 3A.

[0069] A pull-down resistor Rp is connected to the gate of the latching switch 3A. This allows the gate of the latching switch 3A to be fixed at a low level by the pull-down resistor Rp, even if the flip-flop 16A is not activated and the Q output terminal is open. In this case, the latching switch 3A is in an OFF state.

[0070] When the power-on reset unit 4 detects that the reference power supply voltage VDD has been turned ON as described above, the power-on reset unit 4 outputs a reset release signal RST indicating reset release. At this time, the reset release signal RST goes high, causing a high-level signal to be output from the Q output terminal of the flip-flop 16A. This causes the latch switch 3A to go into the ON state. Thereafter, regardless of the logic levels of the control input signals IN1P to IN3N, a current flows through the Zener diode 21, latching the state in which the reference power supply voltage VDD is ON.

[0071] In this manner, in this embodiment, by sharing the control input signals IN1P to IN3N for driving the transistors in the half-bridges UH, VH, and WH of each phase, it is possible to start up the reference power supply circuit 2 and start up the semiconductor device 1. Furthermore, after starting up the semiconductor device 1, the started state can be latched regardless of the logic levels of the control input signals IN1P to IN3N (for example, when driving the motor 35).

[0072] In particular, in this embodiment, the switch circuit 3 is provided with switches SW1p to SW3n corresponding to all of the control input signals IN1P to IN3N for driving the three-phase motor 35. As a result, even if the control input signals IN1P to IN3N output from the microcomputer 30 become unstable when the power supply voltage VCC supplied to the microcomputer 30 rises, the reference power supply circuit 2 will not be started unless all of the control input signals IN1P to IN3N go high. This prevents the reference power supply circuit 2 from being started at an unintended timing. In other words, the reference power supply circuit 2 can be started at the intended timing when the control input signals IN1P to IN3N go high according to the control sequence in the microcomputer 30.

[0073] 2.3 Modifications Figure 6 is a diagram showing the configuration of a switch circuit 3 according to a modification. Unlike the configuration described above (Figure 4), the switch circuit 3 shown in Figure 6 includes switches SW1p, Sw2n, and Sw3p configured as P-channel MOSFETs rather than N-channel MOSFETs. As a result, after the power supply voltages VB and VCC rise, when the microcomputer 30 sets the control input signals IN1P=low level, IN1N=high level, IN2P=high level, IN2N=low level, IN3P=low level, and IN3N=high level, all of the switches SW1p to SW3n are turned on, and the reference power supply circuit 2 is started up.

[0074] Furthermore, the switch circuit 3 may be configured so that the reference power supply circuit 2 is activated when a different combination of logic levels of the control input signals is present.

[0075] 7 is an external view showing an example of the configuration of a vehicle equipped with the aforementioned motor system 5. In Fig. 7, various motors X11 to X17 mounted on a vehicle X are shown as application examples of the motor 35.

[0076] X11 is an electric power steering motor. X12 is an electric oil pump motor. X13 is a headlight drive motor. X14 is an electric parking brake motor. X15 is a seat cooling fan motor. X16 is a door opening / closing motor. X17 is a door lock motor.

[0077] <3. Others> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0078] The semiconductor device is not limited to being configured as a gate driver for driving a motor, but may also be configured as a gate driver for a DC / DC converter provided with one half bridge, for example.

[0079] <4. Supplementary Note> As described above, for example, a semiconductor device (1) according to one aspect of the present disclosure is a semiconductor device configured to be capable of driving at least one half bridge (UH, VH, WH) including upper transistors (Q1H, Q2H, Q3H) and lower transistors (Q1L, Q2L, Q3L), and includes upper control input terminals (T1p, T2p, T3p) configured to be able to input upper control input signals (IN1P, IN2P, IN3P) for driving and controlling the upper transistors, lower control input terminals (T1n, T2n, T3n) configured to be able to input lower control input signals (IN1N, IN2N, IN3N) for driving and controlling the lower transistors, a power supply terminal (Tvb) configured to be able to input a power supply voltage (VB), a control logic unit (16), and a reference power supply circuit (2) to which the power supply voltage is supplied and configured to be able to generate a reference power supply voltage (VDD) to be supplied to the control logic unit. a switch circuit (3) having switches (SW1p, SW2p, SW3p, SW1n, SW2n, SW3n) provided for the upper control input signal and the lower control input signal, respectively, and switched on and off according to the logic levels of the upper control input signal and the lower control input signal, wherein the reference power supply circuit is configured to be activated based on a combination of the logic levels of the upper control input signal and the lower control input signal (first configuration).

[0080] In addition, in the first configuration, the reference power supply circuit (2) may be configured to start up when all of the upper control input signals (IN1P, IN2P, IN3P) and the lower control input signals (IN1N, IN2N, IN3N) are at a high level (second configuration).

[0081] In addition, in the second configuration, all of the switches (SW1p, SW2p, SW3p, SW1n, SW2n, SW3n) may be configured as N-channel MOSFETs and connected in series between the reference power supply circuit (2) and ground potential (third configuration).

[0082] Furthermore, in any one of the first to third configurations, the reference power supply circuit (2) includes: a first diode (21) including a cathode connected to an application terminal of the power supply voltage (VB); a first resistor (22) including a first terminal connected to an anode of the first diode and a second terminal connected to the switch circuit (3); a PMOS transistor (23) including a gate connected to a first node (N1) at which the first diode and the first resistor are connected and a source connected to the application terminal of the power supply voltage; a second resistor (24) including a first terminal connected to the drain of the PMOS transistor; a second diode (25) including a cathode connected to the second terminal of the second resistor and an anode connected to an application terminal of a ground potential; an NMOS transistor (26) including a gate connected to a second node (N2) at which the second resistor and the second diode are connected; and a third resistor (27) connected between the application terminal of the power supply voltage and the drain of the NMOS transistor. A fourth configuration may also be provided, which includes a bandgap reference (28) connected to the source of the NMOS transistor, and an LDO (29) configured to be activated based on a reference voltage (Vref) output from the bandgap reference and to generate the reference power supply voltage (VDD) from the power supply voltage.

[0083] Furthermore, in any of the first to fourth configurations, a fifth configuration may be configured, further comprising a detection unit (4) configured to detect activation of the reference power supply voltage (VDD), wherein the switch circuit (3) has a latching switch (3A) connected in parallel to the series-connected configuration of the switches (SW1p, SW2p, SW3p, SW1n, SW2n, SW3n), and the control logic unit (16) is configured to maintain the latching switch in an on state based on detection by the detection unit.

[0084] Furthermore, in any one of the first to fifth configurations, the at least one half bridge is a U-phase, V-phase, and W-phase half bridge (UH, VH, WH) connected to a three-phase brushless DC motor (35), the upper control input signal includes a U-phase upper control input signal (IN1P), a V-phase upper control input signal (IN2P), and a W-phase upper control input signal (IN3P), the lower control input signal includes a U-phase lower control input signal (IN1N), a V-phase lower control input signal (IN2N), and a W-phase lower control input signal (IN3N), The switches may be configured to include a U-phase upper switch (SW1p) to which a U-phase upper control input signal can be input, a V-phase upper switch (SW2p) to which a V-phase upper control input signal can be input, a W-phase upper switch (SW3p) to which a W-phase upper control input signal can be input, a U-phase lower switch (SW1n) to which a U-phase lower control input signal can be input, a V-phase lower switch (SW2n) to which a V-phase lower control input signal can be input, and a W-phase lower switch (SW3n) to which a W-phase lower control input signal can be input (sixth configuration).

[0085] In addition, in the sixth configuration, the U-phase upper switch (SW1p), the V-phase upper switch (SW2p), the W-phase upper switch (SW3p), the U-phase lower switch (SW1n), the V-phase lower switch (SW2n), and the W-phase lower switch (SW3n) may all be configured with N-channel MOSFETs and connected in series between the reference power supply circuit (2) and ground potential (seventh configuration).

[0086] Furthermore, a motor system (5) according to one aspect of the present disclosure includes a semiconductor device (1) of the sixth or seventh configuration described above, the U-phase, V-phase, and W-phase half bridges (UH, VH, WH) configured to be drivable by the semiconductor device, and the three-phase brushless DC motor (35) connected to the U-phase, V-phase, and W-phase half bridges (eighth configuration).

[0087] Furthermore, a vehicle (X) according to one aspect of the present disclosure includes a motor system having the eighth configuration described above.

[0088] The present disclosure can be used, for example, in an in-vehicle motor system.

[0089] REFERENCE SIGNS LIST 1 semiconductor device 2 reference power supply circuit 3 switch circuit 3A latch switch 4 power-on reset unit 5 motor system 10 semiconductor device 11 regulator 12 reference power supply circuit 13 Schmitt buffer 14A to 14F Schmitt buffer 15 charge pump 16 control logic unit 16A flip-flop 17H, 17L pre-driver 18H, 18L pre-driver 19H, 19L pre-driver 21 Zener diode 22 resistor 23 PDMOS transistor 24 resistor 25 Zener diode 26 NDMOS transistor 27 resistor 28 bandgap reference 30 microcomputer 35 motor 50 motor system C1H, C1L, C2H, C2L, C3H, C3L capacitor Q1H U-phase upper transistor Q1L U-phase lower transistor Q2H V-phase upper transistor Q2L V-phase lower transistor Q3H W-phase upper transistor Q3L W-phase lower transistor R1H Pull-down resistor R1L Pull-down resistor R2H Pull-down resistor R2L Pull-down resistor R3H Pull-down resistor R3L Pull-down resistor Rp Pull-down resistor SW1n U-phase lower switch SW1p U-phase upper switch SW2n V-phase lower switch SW2p V-phase upper switch SW3n W-phase lower switch SW3p W-phase upper switch UH U-phase half-bridge VH V-phase half-bridge WH W-phase half-bridge X Vehicle

Claims

1. A semiconductor device configured to be capable of driving at least one half bridge including an upper transistor and a lower transistor, an upper control input terminal configured to be able to receive an upper control input signal for driving and controlling the upper transistor; a lower-side control input terminal configured to be able to receive a lower-side control input signal for driving and controlling the lower-side transistor; a power supply terminal configured to be able to input a power supply voltage; A control logic unit; a reference power supply circuit configured to receive the power supply voltage and generate a reference power supply voltage to be supplied to the control logic unit; a switch circuit including a switch provided for each of the upper control input signals and the lower control input signals, the switch being switched on and off in response to logic levels of the upper control input signals and the lower control input signals; Equipped with The semiconductor device is configured such that the reference power supply circuit is activated based on a combination of logic levels of the upper control input signal and the lower control input signal.

2. 2. The semiconductor device according to claim 1, wherein the reference power supply circuit is configured to start up when both the upper control input signal and the lower control input signal are at a high level.

3. 3. The semiconductor device according to claim 2, wherein all of said switches are constituted by N-channel MOSFETs and are connected in series between said reference power supply circuit and a ground potential.

4. The reference power supply circuit includes: a first diode including a cathode connected to the power supply voltage application terminal; a first resistor having a first end connected to the anode of the first diode and a second end connected to the switch circuit; a gate connected to a first node to which the first diode and the first resistor are connected; a source connected to the power supply voltage application terminal; a second resistor having a first terminal connected to the drain of the PMOS transistor; a second diode including a cathode connected to the second end of the second resistor and an anode connected to an application terminal of a ground potential; an NMOS transistor including a gate connected to a second node to which the second resistor and the second diode are connected; a third resistor connected between the power supply voltage application terminal and the drain of the NMOS transistor; a bandgap reference connected to the source of the NMOS transistor; an LDO configured to start up based on a reference voltage output from the bandgap reference and generate the reference power supply voltage from the power supply voltage; The semiconductor device according to claim 1 ,

5. a detection unit configured to detect the start-up of the reference power supply voltage; the switch circuit includes a latching switch connected in parallel to the series-connected configuration of the switches; The semiconductor device according to claim 1 , wherein the control logic unit is configured to maintain the latching switch in an on state based on detection by the detection unit.

6. The at least one half bridge is a U-phase, V-phase, and W-phase half bridge connected to a three-phase brushless DC motor, the high-side control input signals include a U-phase high-side control input signal, a V-phase high-side control input signal, and a W-phase high-side control input signal; the low-side control input signals include a U-phase low-side control input signal, a V-phase low-side control input signal, and a W-phase low-side control input signal; 2. The semiconductor device according to claim 1, wherein the switches include a U-phase upper switch to which a U-phase upper control input signal can be input, a V-phase upper switch to which a V-phase upper control input signal can be input, a W-phase upper switch to which a W-phase upper control input signal can be input, a U-phase lower switch to which a U-phase lower control input signal can be input, a V-phase lower switch to which a V-phase lower control input signal can be input, and a W-phase lower switch to which a W-phase lower control input signal can be input.

7. 7. The semiconductor device according to claim 6, wherein the U-phase upper switch, the V-phase upper switch, the W-phase upper switch, the U-phase lower switch, the V-phase lower switch, and the W-phase lower switch are all configured with N-channel MOSFETs, and are connected in series between the reference power supply circuit and a ground potential.

8. A semiconductor device according to claim 6 or 7, the U-phase, V-phase, and W-phase half bridges configured to be drivable by the semiconductor device; the three-phase brushless DC motor connected to the U-phase, V-phase, and W-phase half bridges; A motor system comprising:

9. A vehicle comprising the motor system according to claim 8.