Thin-film transistor and electronic device

Abstract

This thin-film transistor comprises: a substrate; a metal oxide layer provided on the substrate; an oxide semiconductor layer provided in contact with the metal oxide layer and having crystallinity; a gate electrode provided so as to overlap the oxide semiconductor layer; and an insulating layer provided between the oxide semiconductor layer and the gate electrode. The oxide semiconductor layer contains a plurality of crystal grains, each including at least one of crystal orientation <001>, crystal orientation <101>, and crystal orientation <111> obtained by a electron backscatter diffraction (EBSD) method.

Description

Thin-film transistors and electronic devices

[0001] An embodiment of the present invention relates to a thin film transistor including an oxide semiconductor film, and an electronic device including the thin film transistor.

[0002] In recent years, development of thin film transistors using oxide semiconductor films as channels has been progressing, instead of silicon semiconductor films such as amorphous silicon, low-temperature polysilicon, and single-crystal silicon (see, for example, Patent Documents 1 to 6). Thin film transistors including such oxide semiconductor films can be formed using a simple structure and a low-temperature process, similar to thin film transistors including amorphous silicon films. Furthermore, thin film transistors including oxide semiconductor films are known to have higher mobility than thin film transistors including amorphous silicon films.

[0003] JP 2021-141338 A JP 2014-099601 A JP 2021-153196 A JP 2018-006730 A JP 2016-184771 A JP 2021-108405 A

[0004] However, the field-effect mobility of a thin film transistor including a conventional oxide semiconductor film is not so high even when a crystalline oxide semiconductor film is used. Therefore, it has been desired to improve the crystalline structure of the oxide semiconductor film used in the thin film transistor and thereby increase the field-effect mobility of the thin film transistor.

[0005] In view of the above problems, an object of one embodiment of the present invention is to provide a thin film transistor including an oxide semiconductor film having a novel crystal structure. Another embodiment of the present invention relates to an electronic device including the thin film transistor.

[0006] A thin film transistor according to one embodiment of the present invention includes a substrate, a metal oxide layer provided on the substrate, a crystalline oxide semiconductor layer provided in contact with the metal oxide layer, a gate electrode provided to overlap the oxide semiconductor layer, and an insulating layer provided between the oxide semiconductor layer and the gate electrode, and the oxide semiconductor layer includes a plurality of crystal grains each having at least one of a crystal orientation <001>, a crystal orientation <101>, and a crystal orientation <111>, which are obtained by EBSD (electron backscatter diffraction) method.

[0007] An electronic device according to one embodiment of the present invention includes the thin film transistor.

[0008] 1 is an IPF map of an oxide semiconductor film (Example 1) according to one embodiment of the present invention. FIG. 2 is an IPF map of an oxide semiconductor film (Example 1) according to one embodiment of the present invention. FIG. 3 is an IPF map of an oxide semiconductor film (Example 2) according to one embodiment of the present invention. FIG. 4 is an IPF map of an oxide semiconductor film (Example 2) according to one embodiment of the present invention. FIG. 5 is an IPF map of an oxide semiconductor film (Example 2) according to one embodiment of the present invention. FIG. 6 is a map showing the distribution of GOS in an oxide semiconductor film (Example 2) according to one embodiment of the present invention. FIG. 7 is a cross-sectional view showing an outline of a thin film transistor according to one embodiment of the present invention. FIG. 8 is a plan view showing an outline of a thin film transistor according to one embodiment of the present invention. FIG. 9 is a flowchart showing a manufacturing method of a thin film transistor according to one embodiment of the present invention. FIG. 10 is a cross-sectional view showing a manufacturing method of a thin film transistor according to one embodiment of the present invention. FIG. 11 is a cross-sectional view showing a manufacturing method of a thin film transistor according to one embodiment of the present invention. FIG. 12 is a cross-sectional view showing a manufacturing method of a thin film transistor according to one embodiment of the present invention. FIG. 13 is a cross-sectional view showing a manufacturing method of a thin film transistor according to one embodiment of the present invention. FIG. 14 is a cross-sectional view showing a manufacturing method of a thin film transistor according to one embodiment of the present invention. FIG. 15 is a cross-sectional view showing a manufacturing method of a thin film transistor according to one embodiment of the present invention. 1 is an IPF map of a conventional oxide semiconductor film (comparative example), FIG. 2 is an IPF map of a conventional oxide semiconductor film (comparative example), FIG. 3 is a map showing the distribution of GOS in a conventional oxide semiconductor film (comparative example).

[0009] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art can easily come up with by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention are naturally included within the scope of the present invention. For clarity of explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0010] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downper." For convenience of explanation, the terms "up" and "downper" are used in the description. However, for example, the hierarchical relationship between the substrate and the oxide semiconductor layer may be reversed from that illustrated. In the following description, for example, the expression "oxide semiconductor layer on a substrate" merely describes the hierarchical relationship between the substrate and the oxide semiconductor layer as described above, and other components may be disposed between the substrate and the oxide semiconductor layer. "Above" or "below" refers to the stacking order in a structure in which multiple layers are stacked. When a pixel electrode is referred to as being above a transistor, the transistor and the pixel electrode may not overlap in a planar view. On the other hand, when a pixel electrode is referred to as being vertically above a transistor, the transistor and the pixel electrode may overlap in a planar view.

[0011] In this specification, the terms "film" and "layer" may be used interchangeably in some cases.

[0012] The term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical components (e.g., a polarizing component, a backlight, a touch panel, etc.) are attached to a display cell. The term "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, the embodiments described below will be described using a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer as examples of display devices, but the structure of this embodiment can be applied to display devices including the other electro-optical layers described above.

[0013] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0014] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0015] First Embodiment An oxide semiconductor film according to one embodiment of the present invention will be described with reference to FIGS.

[0016] [1. Composition of Oxide Semiconductor Film] The oxide semiconductor film according to this embodiment contains indium (In) and a metal element other than indium (M). In the composition of the oxide semiconductor film, the atomic ratio of indium and the metal element other than indium preferably satisfies formula (1). In other words, the ratio of indium to all metal elements including indium in the oxide semiconductor film is preferably 50% or more. By increasing the ratio of indium, an oxide semiconductor film having crystallinity can be formed. Furthermore, the crystal structure of the oxide semiconductor film preferably has a bixbyite structure. By increasing the ratio of indium, an oxide semiconductor film having a bixbyite structure can be formed.

[0017]

[0018] The metal element other than the indium element is not limited to one type of metal element, and may include a plurality of types of metal elements.

[0019] Although a detailed manufacturing method of the oxide semiconductor film will be described later, the oxide semiconductor film can be formed by a sputtering method. The composition of the oxide semiconductor film formed by sputtering depends on the composition of the sputtering target. With a sputtering target having the above-described composition, an oxide semiconductor film without compositional deviation of metal elements can be formed by sputtering. Therefore, the composition of metal elements (e.g., indium and other metal elements) of the oxide semiconductor film may be equivalent to the composition of metal elements of the sputtering target. For example, the composition of metal elements of the oxide semiconductor film can be specified based on the composition of metal elements of the sputtering target. Note that the oxygen element contained in the oxide semiconductor film is not limited to this because it varies depending on the sputtering process conditions, etc.

[0020] Alternatively, the composition of metal elements in the oxide semiconductor film can be determined by X-ray fluorescence analysis, electron probe microanalyzer (EPMA) analysis, etc. Furthermore, since the oxide semiconductor film has crystallinity, the composition of metal elements in the oxide semiconductor film can also be determined from the crystal structure and lattice constant by X-ray diffraction (XRD).

[0021] [2. Crystal Structure of Oxide Semiconductor Film] The oxide semiconductor film according to this embodiment has crystallinity. The crystal structure of the oxide semiconductor film is not particularly limited, but is preferably a bixbyite structure. The crystal structure of the oxide semiconductor film can be identified by XRD or electron beam diffraction.

[0022] Moreover, the oxide semiconductor film according to this embodiment includes a plurality of crystal grains. The inventors have found that the crystal grains of the oxide semiconductor film according to this embodiment have characteristics different from those of crystal grains of conventional oxide semiconductor films. Specifically, the inventors have found an oxide semiconductor film having a novel crystal structure including crystal grains different from conventional crystal grains. An oxide semiconductor film having such a novel crystal structure can be measured using electron backscatter diffraction (EBSD). Therefore, measurement of an oxide semiconductor film by EBSD will be described below.

[0023] [2-1. EBSD Method] The EBSD method is an analytical method for measuring the crystal structure of a measurement region of an object by irradiating an electron beam onto the object and analyzing electron backscatter diffraction generated on each crystal plane of the crystal structure of the object. The EBSD method can obtain information such as the crystal grains or crystal orientation of an oxide semiconductor film in the measurement region by analyzing data obtained from an EBSD detector attached to a scanning electron microscope (SEM) or a transmission electron microscope (TEM).

[0024] [2-2. IPF Map] An IPF (Inverse Pole Figure) map is an image in which crystal orientations are color-coded according to a predetermined color key. Measurements using the EBSD method can acquire information on crystal orientations, and an IPF map can be created based on the acquired information on crystal orientations. In an IPF map, the area of ​​each color-coded region for multiple crystal orientations is acquired, and the ratio of that area to the area of ​​the entire measurement region (hereinafter referred to as "occupancy rate") can be calculated, allowing for quantitative comparison.

[0025] The IPF map may be an image obtained by extracting data from measurement points whose crystal orientation difference with respect to the normal direction of the substrate surface (or the surface of the oxide semiconductor film) is within a predetermined range. For example, the predetermined range is 0° or more and 15° or less. In an IPF map from which data from specific measurement points is extracted, measurement points having crystal orientations that are significantly tilted from the normal direction of the substrate surface are excluded, thereby making it possible to identify crystal orientations that are likely to be oriented among multiple crystal orientations. Therefore, in an IPF map from which data from specific measurement points is extracted, the occupancy rates of multiple crystal orientations can be compared, making it possible to more clearly identify crystal orientations that are likely to be oriented.

[0026] When the oxide semiconductor film according to this embodiment has a bixbyite structure, the occupancy rates of the <101> and <111> crystal orientations are greater than that of the <001> crystal orientation when the crystal orientation difference with respect to the normal direction of the substrate surface is in the range of 0° to 15°. In other words, in the oxide semiconductor film according to this embodiment, the occupancy rate of the <001> crystal orientation is significantly smaller, at 5% or less, which is a feature not seen in conventional oxide semiconductor films. In the oxide semiconductor film according to this embodiment, the occupancy rates of the <101> and <111> crystal orientations are each at least four times, preferably at least ten times, and more preferably at least 15 times, the occupancy rate of the <001> crystal orientation. In contrast, in conventional oxide semiconductor films, the occupancy rates of the <101> and <111> crystal orientations are each no more than four times the occupancy rate of the <001> crystal orientation. In the oxide semiconductor film according to this embodiment, the total occupancy rate of the <101> and <111> crystal orientations is 10 times or more, preferably 20 times or more, and more preferably 30 times or more than the occupancy rate of the <001> crystal orientation. On the other hand, in a conventional oxide semiconductor film, the total occupancy rate of the <101> and <111> crystal orientations is less than 10 times the occupancy rate of the <001> crystal orientation.

[0027] The ratio of the occupancy rate of the crystal orientation <101> to the occupancy rate of the crystal orientation <111> is 0.7 or more and 1.5 or less.

[0028] Here, the crystal orientation <001> represents

[001] and its equivalents

[100] and

[010] . The crystal orientation <101> represents

[101] and its equivalents

[110] and

[011] . The crystal orientation <111> represents

[111] . Furthermore, in each orientation, "1" may be "-1" and is considered to be an axis equivalent to each orientation.

[0029] In addition to <001>, <101>, and <111>, other crystal orientations include <hk0> (h≠k, h and k are natural numbers), <hhl> (h≠l, h and l are natural numbers), and <hkl> (h≠k≠l, h, k, and l are natural numbers).

[0030] [2-3. Crystal Grains] A crystal grain is a crystalline region surrounded by a crystal grain boundary. Since the EBSD method can obtain information about the crystal orientation, a crystal grain boundary can be defined based on the crystal orientation. Generally, when the difference in crystal orientation between two adjacent measurement points exceeds 5°, it is defined that a crystal grain boundary exists between them. Therefore, the above definition also applies to the oxide semiconductor film according to this embodiment.

[0031] The oxide semiconductor film according to this embodiment includes multiple regions with different crystal orientations within each crystal grain. For example, when the oxide semiconductor film according to this embodiment has a bixbyite structure, crystal grains containing at least two of the crystal orientations <001>, <101>, and <111> exist. This is considered to be a significant change in crystal orientation within the crystal grain, and is a feature not seen in conventional oxide semiconductor films.

[0032] [2-4. Grain size] The grain size is a value indicating the size of a grain. Since the EBSD method can calculate the area S of a grain, the diameter of a circle corresponding to the area S is defined as the grain size d.

[0033] [2-5. Average Crystal Grain Size] The average crystal grain size is the average value of the crystal grain sizes of a plurality of crystal grains. Since the oxide semiconductor film according to this embodiment includes a plurality of crystal grains, the oxide semiconductor film can be evaluated using the average crystal grain size. Average crystal grain size d ＡＶＥ is calculated by the formula (2). ｊis the area ratio of the jth grain (the ratio of the area of ​​the grain to the area of ​​the entire EBSD measurement area (measurement area)), and d ｊ is the grain size of the jth grain, and N is the number of grains. As shown in equation (2), the average grain size d ＡＶＥ is the area average within the measurement area weighted by the area of ​​the grains. ＡＶＥ When the crystal grain size is large, it can be said that many crystal grains with large grain sizes are present in the oxide semiconductor film.

[0034]

[0035] The crystal grains in the oxide semiconductor film according to this embodiment have a larger average crystal grain size than the crystal grains in conventional oxide semiconductor films. The average crystal grain size of the crystal grains included in the oxide semiconductor film according to this embodiment is, for example, 1 μm or more, preferably 1.3 μm or more, and more preferably 1.5 μm or more.

[0036] [2-6. Maximum Crystal Grain Size] The maximum crystal grain size is the maximum value of the crystal grain size of a plurality of crystal grains. The crystal grains in the oxide semiconductor film according to this embodiment have a larger maximum crystal grain size than the crystal grains in conventional oxide semiconductor films. The maximum crystal grain size of the crystal grains included in the oxide semiconductor film according to this embodiment is, for example, 1 μm or more, preferably 2 μm or more, and more preferably 3 μm or more.

[0037] [2-7. GOS] GOS (Grain Orientation Spread) is a value indicating the difference in crystal orientation within a crystal grain. GOS is calculated by the formula (3). That is, GOS is the crystal orientation θ ｉ and the average crystal orientation θ of n measurement points within the grain. ＡＶＥ The GOS is the difference between the GOS and the n measurement points in the crystal grain, divided by n measurement points in the crystal grain. In other words, the GOS is the average value of the crystal orientation in the crystal grain. The GOS represents the magnitude of strain in the crystal grain, and it can be said that a large GOS means a large strain in the crystal grain.

[0038]

[0039] [2-7. GOS Average Value] The GOS average value is the average value of GOS of a plurality of crystal grains. Since the oxide semiconductor film according to this embodiment includes a plurality of crystal grains, the oxide semiconductor film can be evaluated using the GOS average value. GOS average value ＡＶＥ is calculated by the formula (4). ｊ is the area ratio of the jth grain, and GOS ｊ is the GOS of the jth grain, and N is the number of grains. As shown in equation (4), the average GOS GOS ＡＶＥ is the area average within the measurement area weighted by the area of ​​the crystal grain. ＡＶＥ When the σ is large, it can be said that the oxide semiconductor film contains many crystal grains whose crystal orientation changes greatly.

[0040]

[0041] As described above, the oxide semiconductor film according to this embodiment contains crystal grains whose crystal orientations change significantly, and the number of such crystal grains is reflected in the GOS average value. In the oxide semiconductor film according to this embodiment, the GOS average value is 5° or more. The GOS average value of conventional oxide semiconductor films is 1° or less, and the large GOS average value is also one of the characteristics of the oxide semiconductor film according to this embodiment.

[0042] In conventional oxide semiconductor films, when the crystal orientation within a crystal grain changes significantly, the crystal grains become distorted, inhibiting their crystal growth. Therefore, in conventional oxide semiconductor films, the change in crystal orientation within the crystal grains is small, and the average crystal grain size or maximum crystal grain size is also small. In contrast, in the oxide semiconductor film according to this embodiment, large crystal grains are formed despite the large change in crystal orientation within the crystal grains, and the oxide semiconductor film according to this embodiment has a larger average crystal grain size or maximum crystal grain size than conventional oxide semiconductor films. Furthermore, generally, when the crystal orientation within a crystal grain changes significantly, lattice defects are likely to be generated, resulting in a deterioration in the insulating properties (or semiconductor properties) of the oxide semiconductor film. However, in the oxide semiconductor film according to this embodiment, the sputtering film formation conditions are optimized to generate crystal nuclei with a specific crystal orientation, thereby suppressing the amount of oxygen vacancies in the film after heat treatment. This prevents a deterioration in the insulating properties, and for example, a thin film transistor using the oxide semiconductor film as a channel has excellent electrical properties, such as high mobility.

[0043] Note that the measurement of the crystal structure of the oxide semiconductor film according to this embodiment is not limited to the EBSD method, and a measurement method other than the EBSD method may be used to measure the crystal orientation or a change in the crystal orientation within a crystal grain.

[0044] 3. Method for Producing Oxide Semiconductor Film The oxide semiconductor film according to this embodiment is produced by a sputtering process and an annealing process.

[0045] In the sputtering process, an oxide semiconductor film is formed in contact with a metal oxide film. The oxide semiconductor film according to this embodiment can improve crystallinity by being formed in contact with a metal oxide film. Therefore, for example, an oxide semiconductor film is formed in contact with the metal oxide film on a substrate on which a metal oxide film has already been formed. Details of the metal oxide film will be described later, but for example, aluminum oxide can be used as the metal oxide film.

[0046] The oxide semiconductor film after the sputtering process is preferably a film with a small amount of crystalline components, and is particularly preferably amorphous. In sputtering film formation, ions generated in the plasma and atoms recoiled from the sputtering target collide with the substrate, causing the substrate temperature to rise during film formation even if the substrate temperature is room temperature at the start of sputtering. If the substrate temperature rises during film formation, the oxide semiconductor film immediately after film formation contains microcrystals, which makes it easier for crystal grains with a <001> crystal orientation to be generated by the subsequent annealing process. Therefore, it is preferable to form the oxide semiconductor film while controlling the substrate temperature. The substrate temperature is, for example, 100°C or less, preferably 70°C or less, and more preferably 50°C or less. The substrate temperature may be 30°C or less. The substrate temperature can be controlled, for example, by cooling the substrate. Alternatively, the oxide semiconductor film may be formed at a film formation rate that does not cause the substrate temperature to exceed a predetermined temperature. Alternatively, the substrate temperature may be controlled by increasing the distance between the target and the substrate to prevent the substrate from being affected by the sputtering target.

[0047] The substrate on which the oxide semiconductor film is formed may be a rigid substrate such as a glass substrate, a quartz substrate, or a sapphire substrate, or a flexible substrate such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate. ｘ ) film, silicon oxynitride (SiO ｘ N ｙ ) film, silicon nitride (SiN ｘ ) film, silicon oxynitride (SiN ｘ O ｙ ) film, aluminum oxide (AlO ｘ ) film, aluminum oxynitride (AlO ｘ N ｙ ), aluminum oxide nitride (AlN ｘ O ｙ ), or aluminum nitride (AlN ｘ ) may be formed on the substrate.

[0048] In addition, in the sputtering process, the oxide semiconductor film is formed under conditions of an oxygen partial pressure of 10% or less. If the oxygen partial pressure is high, the oxide semiconductor film immediately after deposition contains microcrystals due to excess oxygen, and crystal grains with a <001> crystal orientation are likely to be generated by the subsequent annealing process. Therefore, it is preferable to form the oxide semiconductor film under conditions of a low oxygen partial pressure. The oxygen partial pressure is, for example, 2% or more and 10% or less, preferably 3% or more and 8% or less, and more preferably 3% or more and 6% or less.

[0049] In the annealing process, the oxide semiconductor film is crystallized. The annealing is performed by holding the oxide semiconductor film at a predetermined temperature for a predetermined time. The predetermined temperature is 300° C. or higher and 500° C. or lower, and preferably 350° C. or higher and 450° C. or lower. The holding time at the temperature is 15 minutes or higher and 120 minutes or lower, and preferably 30 minutes or higher and 60 minutes or lower.

[0050] [4. Examples] The oxide semiconductor film according to this embodiment will be described in more detail based on specific examples. Note that the examples described below are examples of the oxide semiconductor film according to this embodiment, and the configuration of the oxide semiconductor according to this embodiment is not limited to the configuration of the examples described below.

[0051] [4-1. Fabrication Method] Example 1 In Example 1, an oxide semiconductor film according to this embodiment was fabricated on a substrate on which an aluminum oxide film had been formed, using the sputtering process and annealing process described above. In the sputtering process, an oxide semiconductor film was formed on a glass substrate using a sputtering target in which the atomic ratio of indium to all metal elements contained in the sintered body was 70% or more. The oxygen partial pressure during film formation was 5.1% and the substrate temperature during film formation was controlled to be 100°C or less. The oxide semiconductor film was then subjected to an annealing process in an air atmosphere. In the annealing process, the ultimate temperature was controlled to 400°C and held at that temperature for 30 minutes. The chemical composition of the oxide semiconductor film was similar to that of the sputtering target.

[0052] Example 2 In Example 2, only the conditions of the annealing process were changed, and an oxide semiconductor film according to this embodiment was fabricated in the same manner as in Example 1. In the annealing process, the ultimate temperature was controlled to be 450° C., and the ultimate temperature was maintained for 60 minutes.

[0053] Comparative Example: As a comparative example, a conventional oxide semiconductor film was fabricated on a substrate without an aluminum oxide film using conventional sputtering and annealing processes. In the sputtering process, a sputtering target containing 70% or more indium atoms relative to all metal elements contained in the sintered body was used to form the oxide semiconductor film on a quartz substrate. The oxygen partial pressure during film formation was 10.0%, and the substrate temperature was not controlled during film formation. The oxide semiconductor film was then subjected to an annealing process in an air atmosphere. In the annealing process, the ultimate temperature was controlled to 450°C and held at that temperature for 60 minutes. The chemical composition of the oxide semiconductor film was similar to that of the sputtering target.

[0054] The fabrication conditions (film formation conditions and annealing conditions) for Example 1, Example 2, and Comparative Example are shown in Table 1. Although there are differences in the film thickness of the oxide semiconductor film between Example 1 and Example 2 and Comparative Example, the major differences are whether an aluminum oxide (AlOx) film is formed on the substrate, whether the substrate temperature is controlled during film formation, and the oxygen partial pressure.

[0055]

[0056] [4-2. Crystal Structure Analysis by XRD Method] The crystal structures of the oxide semiconductor films of Examples 1 and 2 and the oxide semiconductor film of the Comparative Example were analyzed by XRD method. The oxide semiconductor films of Examples 1 and 2 and the oxide semiconductor film of the Comparative Example all had crystallinity and had a bixbyite-type crystal structure.

[0057] [4-3. Crystal Orientation Analysis by EBSD Method] Crystal orientation analysis was performed on the oxide semiconductor films of Examples 1 and 2 and the oxide semiconductor film of the Comparative Example using EBSD. The measurement conditions for EBSD are as shown in Table 2. The crystal orientation analysis was performed using OIM-Analysis (ver. 7.1) manufactured by TSL Solutions, Inc. The crystal structure file of bixbyite-type structure 14388 from the Inorganic Crystal Structure Database (ICSD: Chemical Information Association) was used to orient the crystal structure. As a result of the measurement and analysis, when the CI value was 0.6 or more, it was determined that the obtained pattern was sufficiently clear and the crystal orientation was identified as a bixbyite-type structure.

[0058]

[0059] IPF maps of the oxide semiconductor film of Example 1 are shown in FIGS. 1 and 2 . IPF maps of the oxide semiconductor film of Example 2 are shown in FIGS. 4 and 5 . IPF maps of the oxide semiconductor film of the Comparative Example are shown in FIGS. 21 and 22 . In FIGS. 1 , 2 , 4 , 5 , 21 , and 22 , black lines represent crystal grain boundaries. That is, multiple crystal grains surrounded by black lines can be seen in both the oxide semiconductor films of Examples 1 and 2 and the oxide semiconductor film of the Comparative Example. The IPF maps shown in FIGS. 1 , 2 , 4 , 5 , 21 , and 22 are color-coded according to the color key shown in each figure. The crystal orientation <001> is primarily color-coded by red, the crystal orientation <101> by green, and the crystal orientation <111> by blue. 2, 5, and 22, measurement points where the crystal orientation misorientation of the <001>, <101>, or <111> with respect to the normal direction to the surface of the substrate (or the surface of the oxide semiconductor film) is in the range of 0° to 15° are extracted and color-coded. In other words, Figures 2, 5, and 22 are images obtained by excluding measurement points where the crystal orientation misorientation of the <001>, <101>, or <111> with respect to the normal direction to the surface of the substrate is more than 15° from Figures 1, 4, and 21, respectively.

[0060] The average crystal grain sizes of the oxide semiconductor films of Examples 1 and 2 were calculated to be 1.94 (μm) and 1.96 (μm), respectively. On the other hand, the average crystal grain size of the oxide semiconductor film of the Comparative Example was calculated to be 0.65 (μm). The average crystal grain sizes of the oxide semiconductor films of Examples 1 and 2 were more than 2.5 times that of the oxide semiconductor film of the Comparative Example.

[0061] 2 and 5 with the IPF map shown in Fig. 22, the IPF map shown in Fig. 22 has many regions colored green, whereas the IPF maps shown in Fig. 2 and 5 have many regions colored blue as well as green. Based on Fig. 2 (i.e., measurement points having crystal orientations with a crystal orientation difference of 0° or more and 15° or less with respect to the normal direction of the substrate surface), the occupancies of the crystal orientation <001>, the crystal orientation <101>, and the crystal orientation <111> of the oxide semiconductor film of Example 1 within the measurement region were calculated to be 1.1(%), 29.1(%), and 29.3(%), respectively. 5 (i.e., measurement points having crystal orientations with a crystal orientation misorientation of 0° to 15° from the normal direction to the substrate surface), the occupancies of the crystal orientation <001>, the crystal orientation <101>, and the crystal orientation <111> in the measurement region of the oxide semiconductor film of Example 2 were calculated to be 1.4(%), 28.5(%), and 27.5(%), respectively. On the other hand, the occupancies of the crystal orientation <001>, the crystal orientation <101>, and the crystal orientation <111> in the measurement region of the oxide semiconductor film of Comparative Example were calculated to be 5.6(%), 23.3(%), and 19.8(%), respectively, based on FIG. 22 (i.e., measurement points having crystal orientations with a crystal orientation misorientation of 0° to 15° from the normal direction to the substrate surface).

[0062] The maximum crystal grain sizes of the oxide semiconductor films of Examples 1 and 2 were 3.1 (μm) and 3.3 (μm), respectively. On the other hand, the maximum crystal grain size of the oxide semiconductor film of the Comparative Example was 1.1 (μm). The maximum crystal grain sizes of the oxide semiconductor films of Examples 1 and 2 were about three times larger than the maximum crystal grain size of the oxide semiconductor film of the Comparative Example.

[0063] In the oxide semiconductor films of Examples 1 and 2, the occupancy rates of the crystal orientation <001> are lower than those of the crystal orientation <101> and the crystal orientation <111>. In other words, the occupancy rates of the crystal orientation <101> and the crystal orientation <111> are higher than those of the crystal orientation <001>. In the oxide semiconductor film of Example 1, the occupancy rates of the crystal orientation <101> and the crystal orientation <111> are 26.5 times and 26.6 times, respectively, the occupancy rates of the crystal orientation <001>. In addition, in the oxide semiconductor film of Example 2, the occupancy rates of the crystal orientation <101> and the crystal orientation <111> are 20.4 times and 19.6 times, respectively, the occupancy rates of the crystal orientation <001>. On the other hand, in the oxide semiconductor film of the comparative example, the occupancy rates of the crystal orientation <101> and the crystal orientation <111> are 4.2 times and 3.5 times the occupancy rates of the crystal orientation <001>, respectively.

[0064] FIG. 3 shows a GOS distribution map in which a plurality of crystal grains are color-coded based on the GOS of each of the plurality of crystal grains contained in the oxide semiconductor film of Example 1. FIG. 6 shows a GOS distribution map in which a plurality of crystal grains are color-coded based on the GOS of each of the plurality of crystal grains contained in the oxide semiconductor film of Example 2. FIG. 23 shows a GOS distribution map in which a plurality of crystal grains are color-coded based on the GOS of each of the plurality of crystal grains contained in the oxide semiconductor film of the comparative example. In other words, FIGS. 3, 6, and 23 are distribution maps showing the magnitude of crystal misorientation within crystal grains. In FIGS. 3, 6, and 23, the GOS of each of the plurality of crystal grains is color-coded based on the color bar shown in the figures, and the color of the crystal grains changes from blue to red, i.e., the crystal misorientation within the crystal grains increases as the visible light wavelength increases.

[0065] Comparing the GOS distribution maps shown in FIGS. 3 and 6 with the GOS distribution map shown in FIG. 23 , in the GOS distribution map shown in FIG. 23 , all of the multiple crystal grains are colored blue, whereas in the GOS distribution maps shown in FIGS. 3 and 6 , many crystal grains are colored green, yellow, and red, and almost no crystal grains are colored blue. Therefore, it was found that the oxide semiconductor films of Examples 1 and 2 contain more crystal grains with larger changes in crystal orientation than the oxide semiconductor film of the comparative example. The IPF maps shown in FIGS. 2 and 5 also confirm color gradations within the crystal grains, indicating that many crystal grains with large changes in crystal orientation are contained. Furthermore, the IPF maps shown in FIGS. 2 and 5 confirm the presence of crystal grains with two crystal orientations.

[0066] When the average GOS value within the measurement region was calculated, the average GOS values ​​of the oxide semiconductor films of Examples 1 and 2 were 20.26° and 19.28°, respectively. On the other hand, the average GOS value of the oxide semiconductor film of the Comparative Example was 0.71°. It can also be seen from the average GOS values ​​that the oxide semiconductor films of Examples 1 and 2 had significantly larger changes in crystal orientation within crystal grains than the oxide semiconductor film of the Comparative Example.

[0067] Information about the crystal structures of the oxide semiconductor films of Examples 1 and 2 and the oxide semiconductor film of the Comparative Example is shown in Table 3. As shown in Table 3, the oxide semiconductor films of Examples 1 and 2 and the oxide semiconductor film of the Comparative Example have the same crystal structure, a bixbyite structure, but the crystal orientation characteristics of the crystal grains contained therein are significantly different.

[0068]

[0069] As described above, the oxide semiconductor film according to this embodiment has a distinctive feature in the crystal orientation of the crystal grains and has a novel crystal structure different from that of conventional oxide semiconductors. As will be described in detail later, a thin film transistor using the oxide semiconductor film according to this embodiment has a higher field-effect mobility than a thin film transistor using a conventional oxide semiconductor film. Therefore, it is presumed that the oxide semiconductor film according to this embodiment itself also has a high mobility.

[0070] Second Embodiment A thin film transistor according to one embodiment of the present invention will be described with reference to Figures 7 to 17. The thin film transistor according to this embodiment can be used in, for example, a display device, an integrated circuit (IC) such as a microprocessor (MPU), or a memory circuit.

[0071] 7 is a cross-sectional view showing an outline of a thin film transistor 10 according to one embodiment of the present invention. FIG. 8 is a plan view showing an outline of a thin film transistor 10 according to one embodiment of the present invention.

[0072] 7 , the thin film transistor 10 is provided on a substrate 100. The thin film transistor 10 includes a gate electrode 105, gate insulating layers 110 and 120, a metal oxide layer 130, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, insulating layers 170 and 180, a source electrode 201, and a drain electrode 203. When the source electrode 201 and the drain electrode 203 are not particularly distinguished from each other, they may be collectively referred to as the source-drain electrodes 200.

[0073] The gate electrode 105 is provided on the substrate 100. The gate insulating layer 110 and the gate insulating layer 120 are provided on the substrate 100 and the gate electrode 105. The metal oxide layer 130 is provided on the gate insulating layer 120. The metal oxide layer 130 is in contact with the gate insulating layer 120. The oxide semiconductor layer 140 is provided on the metal oxide layer 130. The oxide semiconductor layer 140 is in contact with the metal oxide layer 130. Of the main surfaces of the oxide semiconductor layer 140, the surface in contact with the metal oxide layer 130 is referred to as the lower surface 142. The edge of the metal oxide layer 130 and the edge of the oxide semiconductor layer 140 are approximately aligned.

[0074] In the thin film transistor 10 according to this embodiment, no semiconductor layer or oxide semiconductor layer is provided between the metal oxide layer 130 and the substrate 100 .

[0075] In the thin film transistor 10 according to this embodiment, a configuration in which the metal oxide layer 130 is in contact with the gate insulating layer 120 is illustrated, but the present invention is not limited to this configuration. Another layer may be provided between the gate insulating layer 120 and the metal oxide layer 130.

[0076] 7, the sidewall of the metal oxide layer 130 and the sidewall of the oxide semiconductor layer 140 are aligned in a straight line, but the present invention is not limited to this configuration. The angle of the sidewall of the metal oxide layer 130 with respect to the main surface of the substrate 100 may be different from the angle of the sidewall of the oxide semiconductor layer 140. The cross-sectional shape of the sidewall of at least one of the metal oxide layer 130 and the oxide semiconductor layer 140 may be curved.

[0077] The gate electrode 160 faces the oxide semiconductor layer 140. The gate insulating layer 150 is provided between the oxide semiconductor layer 140 and the gate electrode 160. The gate insulating layer 150 is in contact with the oxide semiconductor layer 140. Of the major surfaces of the oxide semiconductor layer 140, the surface in contact with the gate insulating layer 150 is referred to as an upper surface 141. The surface between the upper surface 141 and the lower surface 142 is referred to as a side surface 143. The insulating layers 170 and 180 are provided on the gate insulating layer 150 and the gate electrode 160. The insulating layers 170 and 180 have openings 171 and 173 through which the oxide semiconductor layer 140 is exposed. The source electrode 201 is provided to fill the opening 171. The source electrode 201 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 171. The drain electrode 203 is provided to fill the opening 173. The drain electrode 203 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 173 .

[0078] The gate electrode 105 functions as a bottom gate of the thin film transistor 10 and as a light-shielding film for the oxide semiconductor layer 140. The gate insulating layer 110 functions as a barrier film that blocks impurities diffusing from the substrate 100 toward the oxide semiconductor layer 140. The gate insulating layers 110 and 120 function as gate insulating layers for the bottom gate. The metal oxide layer 130 is a layer containing a metal oxide containing aluminum as a main component, and not only improves the crystallinity of the oxide semiconductor layer 140 but also functions as a gas barrier film that blocks gases such as oxygen and hydrogen.

[0079] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH. The channel region CH is a region of the oxide semiconductor layer 140 vertically below the gate electrode 160. The source region S is a region of the oxide semiconductor layer 140 that does not overlap with the gate electrode 160 and is closer to the source electrode 201 than the channel region CH. The drain region D is a region of the oxide semiconductor layer 140 that does not overlap with the gate electrode 160 and is closer to the drain electrode 203 than the channel region CH. The oxide semiconductor layer 140 in the channel region CH has the physical properties of a semiconductor. The oxide semiconductor layer 140 in the source region S and the drain region D has the physical properties of a conductor.

[0080] The gate electrode 160 functions as a light-shielding film for the top gate of the thin-film transistor 10 and the oxide semiconductor layer 140. The gate insulating layer 150 functions as a gate insulating layer for the top gate and releases oxygen by heat treatment in the manufacturing process. The insulating layers 170 and 180 insulate the gate electrode 160 from the source / drain electrodes 200 and reduce parasitic capacitance between them. The operation of the thin-film transistor 10 is controlled mainly by the voltage supplied to the gate electrode 160. An auxiliary voltage is supplied to the gate electrode 105. However, when the gate electrode 105 is used simply as a light-shielding film, the gate electrode 105 may be floating without being supplied with a specific voltage. In other words, the gate electrode 105 may simply be called a "light-shielding film."

[0081] In this embodiment, a configuration in which a dual-gate transistor in which gate electrodes are provided both above and below the oxide semiconductor layer is used as the thin-film transistor 10 is exemplified, but the present invention is not limited to this configuration. For example, the thin-film transistor 10 may be a bottom-gate transistor in which the gate electrode is provided only below the oxide semiconductor layer 140, or a top-gate transistor in which the gate electrode is provided only above the oxide semiconductor layer 140. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0082] As shown in FIG. 8 , in a plan view, the planar pattern of the metal oxide layer 130 is substantially the same as the planar pattern of the oxide semiconductor layer 140. Referring to FIGS. 7 and 8 , the lower surface 142 of the oxide semiconductor layer 140 is covered with the metal oxide layer 130. In particular, in the thin film transistor 10 according to this embodiment, the entire lower surface 142 of the oxide semiconductor layer 140 is covered with the metal oxide layer 130. In the D1 direction, the width of the gate electrode 105 is greater than the width of the gate electrode 160. The D1 direction is a direction connecting the source electrode 201 and the drain electrode 203, and is the direction indicating the channel length L of the thin film transistor 10. Specifically, the length in the D1 direction of a region (channel region CH) where the oxide semiconductor layer 140 and the gate electrode 160 overlap is the channel length L, and the width of the channel region CH in the D2 direction is the channel width W.

[0083] In the present embodiment, a configuration in which the entire lower surface 142 of the oxide semiconductor layer 140 is covered with the metal oxide layer 130 has been exemplified, but this configuration is not limiting. For example, a portion of the lower surface 142 of the oxide semiconductor layer 140 may not be in contact with the metal oxide layer 130. For example, the entire lower surface 142 of the oxide semiconductor layer 140 in the channel region CH may be covered with the metal oxide layer 130, and all or part of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and the drain region D may not be covered with the metal oxide layer 130. In other words, all or part of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and the drain region D may not be in contact with the metal oxide layer 130. However, in the above configuration, a portion of the lower surface 142 of the oxide semiconductor layer 140 in the channel region CH may not be covered with the metal oxide layer 130, and the other portion of the lower surface 142 may be in contact with the metal oxide layer 130.

[0084] In this embodiment, the configuration in which the gate insulating layer 150 is formed on the entire surface and the openings 171 and 173 are provided in the gate insulating layer 150 has been exemplified, but the configuration is not limited to this. The gate insulating layer 150 may be patterned. For example, the gate insulating layer 150 may be patterned so that not only the top surface of the oxide semiconductor layer 140 but also the side surface of the oxide semiconductor layer 140 is exposed.

[0085] 8 illustrates a configuration in which the source / drain electrode 200 does not overlap the gate electrodes 105 and 160 in a plan view, but the present invention is not limited to this configuration. For example, the source / drain electrode 200 may overlap at least one of the gate electrodes 105 and 160 in a plan view. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0086] [2. Materials of Each Component of the Thin Film Transistor 10] The substrate 100 is a rigid substrate having optical transparency, such as a glass substrate, a quartz substrate, or a sapphire substrate. When the substrate 100 needs to be flexible, a substrate containing a resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, is used. When a substrate containing a resin is used as the substrate 100, impurities may be introduced into the resin to improve the heat resistance of the substrate 100. When the thin film transistor 10 is a pixel transistor included in a display device such as a top-emission OLED, the substrate 100 does not need to be transparent, and therefore impurities that reduce the transparency of the substrate 100 may be used. When the thin film transistor 10 is used in an integrated circuit other than a display device, a non-optically transparent substrate, such as a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, or a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate, is used as the substrate 100.

[0087] Common metal materials are used for the gate electrode 105, the gate electrode 160, and the source / drain electrodes 200. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof are used as these materials. The above materials may be used as a single layer or a stacked layer for the gate electrode 105, the gate electrode 160, and the source / drain electrodes 200.

[0088] A general insulating material is used for the gate insulating layers 110 and 120 and the insulating layers 170 and 180. For example, silicon oxide (SiO ｘ ), silicon oxynitride (SiO ｘ N ｙ ), silicon nitride (SiN ｘ ), silicon oxynitride (SiN ｘ O ｙ ), aluminum oxide (AlO ｘ ), aluminum oxynitride (AlO ｘ N ｙ), aluminum oxide nitride (AlN ｘ O ｙ ), aluminum nitride (AlN ｘ ) or other inorganic insulating layers are used.

[0089] The gate insulating layer 150 is an insulating layer containing oxygen among the above insulating layers. For example, the gate insulating layer 150 is made of silicon oxide (SiO ｘ ), silicon oxynitride (SiO ｘ N ｙ ), aluminum oxide (AlO ｘ ), aluminum oxynitride (AlO ｘ N ｙ ) or other inorganic insulating layers are used.

[0090] An insulating layer having a function of releasing oxygen by heat treatment is used as the gate insulating layer 120. The temperature of the heat treatment at which the gate insulating layer 120 releases oxygen is, for example, 600° C. or less, 500° C. or less, 450° C. or less, or 400° C. or less. That is, the gate insulating layer 120 releases oxygen at the heat treatment temperature performed in the manufacturing process of the thin film transistor 10 when a glass substrate is used as the substrate 100, for example.

[0091] An insulating layer with few defects is used as the gate insulating layer 150. For example, when the oxygen composition ratio in the gate insulating layer 150 is compared with the oxygen composition ratio in an insulating layer having the same composition as the gate insulating layer 150 (hereinafter referred to as "another insulating layer"), the oxygen composition ratio in the gate insulating layer 150 is closer to the stoichiometric ratio for the insulating layer than the oxygen composition ratio in the other insulating layer. Specifically, when silicon oxide (SiO ｘ ) is used, the oxygen composition ratio in the silicon oxide used as the gate insulating layer 150 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio in the silicon oxide used as the insulating layer 180. For example, the gate insulating layer 150 may be a layer in which no defects are observed when evaluated by electron spin resonance (ESR).

[0092] The above SiO ｘ N ｙ and AlOｘ N ｙ is a silicon and aluminum compound containing a smaller ratio (x>y) of nitrogen (N) than oxygen (O). ｘ O ｙ and AlN ｘ O ｙ are silicon and aluminum compounds containing a smaller proportion of oxygen than nitrogen (x>y).

[0093] The metal oxide layer 130 is made of a metal oxide containing aluminum as a main component. For example, the metal oxide layer 130 may be made of aluminum oxide (AlO ｘ ), aluminum oxynitride (AlO ｘ N ｙ ), aluminum oxide nitride (AlN ｘ O ｙ ), aluminum nitride (AlN ｘ ) or other inorganic insulating layer is used. The term "metal oxide layer containing aluminum as a main component" means that the ratio of aluminum contained in the metal oxide layer 130 is 1% or more of the entire metal oxide layer 130. The ratio of aluminum contained in the metal oxide layer 130 may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide layer 130. The above ratio may be a mass ratio or a weight ratio.

[0094] The oxide semiconductor film according to the first embodiment can be used as the oxide semiconductor layer 140. The oxide semiconductor layer 140 has crystallinity. Oxygen vacancies are less likely to form in a crystalline oxide semiconductor than in an amorphous oxide semiconductor. However, the crystal grain boundaries of the oxide semiconductor layer 140 may contain amorphous regions.

[0095] Note that the metal oxide layer 130 and the oxide semiconductor layer 140 may contain a metal element common to each other. That is, the metal oxide layer 130 may contain a metal element other than the indium element contained in the oxide semiconductor layer 140.

[0096] 9 is a flowchart showing a method for manufacturing the thin film transistor 10 according to one embodiment of the present invention. FIGS. 10 to 17 are cross-sectional views showing a method for manufacturing the thin film transistor 10 according to one embodiment of the present invention.

[0097] 9 and 10 , a gate electrode 105 is formed on a substrate 100 as a bottom gate, and gate insulating layers 110 and 120 are formed on the gate electrode 105 (step S3001 "Bottom GI / GE formation" in FIG. 9 ). For example, silicon nitride is formed as the gate insulating layer 110. For example, silicon oxide is formed as the gate insulating layer 120. The gate insulating layers 110 and 120 are formed by a CVD (Chemical Vapor Deposition) method.

[0098] By using silicon nitride as the gate insulating layer 110, the gate insulating layer 110 can block impurities diffusing from, for example, the substrate 100 side toward the oxide semiconductor layer 140. The silicon oxide used as the gate insulating layer 120 is silicon oxide that has the physical property of releasing oxygen by heat treatment.

[0099] 9 and 11 , a metal oxide layer 130 and an oxide semiconductor layer 140 are formed on the gate insulating layer 120 (step S3002 "OS / AlOx deposition" in FIG. 9 ). The metal oxide layer 130 is deposited by sputtering or atomic layer deposition (ALD). The oxide semiconductor layer 140 is deposited by sputtering.

[0100] The thickness of the metal oxide layer 130 is, for example, 1 nm to 100 nm, 1 nm to 50 nm, 1 nm to 30 nm, or 1 nm to 10 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 130. Aluminum oxide has high barrier properties against gases. In this embodiment, the aluminum oxide used as the metal oxide layer 130 blocks hydrogen and oxygen released from the gate insulating layer 120 and prevents the released hydrogen and oxygen from reaching the oxide semiconductor layer 140. In addition, the metal oxide layer 130 improves the crystallinity of the oxide semiconductor layer 140.

[0101] The thickness of the oxide semiconductor layer 140 is, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 20 nm to 40 nm. The oxide semiconductor layer 140 is amorphous before heat treatment (OS annealing) described later.

[0102] When the oxide semiconductor layer 140 is crystallized by OS annealing, which will be described later, the oxide semiconductor layer 140 is preferably amorphous (having a small amount of crystalline components in the oxide semiconductor) after deposition and before OS annealing. That is, the oxide semiconductor layer 140 is preferably formed under conditions that prevent the oxide semiconductor layer 140 from crystallizing immediately after deposition as much as possible. For example, when the oxide semiconductor layer 140 is formed by sputtering, the oxide semiconductor layer 140 is formed while controlling the temperature of the deposition target (the substrate 100 and a structure formed thereon) to 100° C. or less. Furthermore, the oxide semiconductor layer 140 is formed under conditions where the oxygen partial pressure is 10% or less.

[0103] 9 and 12 , a pattern of the oxide semiconductor layer 140 is formed ("OS pattern formation" in step S3003 in FIG. 9 ). Although not shown, a resist mask is formed over the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is etched using the resist mask. Wet etching or dry etching may be used to etch the oxide semiconductor layer 140. Wet etching can be performed using an acidic etchant. For example, oxalic acid or hydrofluoric acid can be used as the etchant.

[0104] After the oxide semiconductor layer 140 is patterned, heat treatment (OS annealing) is performed on the oxide semiconductor layer 140 ("OS annealing" in step S3004 in FIG. 9). In this embodiment, the oxide semiconductor layer 140 is crystallized by this OS annealing.

[0105] As shown in FIGS. 9 and 13 , a pattern of the metal oxide layer 130 is formed (step S3005 “AlOx pattern formation” in FIG. 9 ). The metal oxide layer 130 is etched using the oxide semiconductor layer 140 patterned in the above process as a mask. The metal oxide layer 130 may be etched by wet etching or dry etching. For example, diluted hydrofluoric acid (DHF) is used for wet etching. As described above, by etching the metal oxide layer 130 using the oxide semiconductor layer 140 as a mask, the photolithography process can be omitted.

[0106] As shown in FIGS. 9 and 14 , a gate insulating layer 150 is formed ("GI formation" in step S3006 in FIG. 9 ). The gate insulating layer 150 is formed, for example, of silicon oxide. The gate insulating layer 150 is formed by a CVD method. For example, in order to form an insulating layer with few defects as the gate insulating layer 150 as described above, the gate insulating layer 150 may be formed at a film formation temperature of 350° C. or higher. The thickness of the gate insulating layer 150 is, for example, 50 nm to 300 nm, 60 nm to 200 nm, or 70 nm to 150 nm. After the gate insulating layer 150 is formed, a process of implanting oxygen into a portion of the gate insulating layer 150 may be performed.

[0107] With the gate insulating layer 150 formed on the oxide semiconductor layer 140, heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 140 ("oxidation annealing" in step S3007 in FIG. 9). During the process from when the oxide semiconductor layer 140 is formed until when the gate insulating layer 150 is formed on the oxide semiconductor layer 140, many oxygen vacancies are generated on the top surface 141 and side surface 143 of the oxide semiconductor layer 140. By the above-mentioned oxidation annealing, oxygen released from the gate insulating layers 120 and 150 is supplied to the oxide semiconductor layer 140, and the oxygen vacancies are repaired.

[0108] 9 and 15, the gate electrode 160 is formed ("GE formation" in step S3008 in FIG. 9). The gate electrode 160 is formed by sputtering or atomic layer deposition, and is patterned through a photolithography process.

[0109] With the gate electrode 160 patterned, the resistance of the source region S and the drain region D of the oxide semiconductor layer 140 is reduced ("SD resistance reduction" in step S3009 in FIG. 9). Specifically, impurities are implanted into the oxide semiconductor layer 140 from the gate electrode 160 side through the gate insulating layer 150 by ion implantation. For example, argon (Ar), phosphorus (P), or boron (B) is implanted into the oxide semiconductor layer 140 by ion implantation. Oxygen vacancies are formed in the oxide semiconductor layer 140 by ion implantation, thereby reducing the resistance of the oxide semiconductor layer 140. Because the gate electrode 160 is provided above the oxide semiconductor layer 140, which functions as the channel region CH of the thin-film transistor 10, impurities are not implanted into the oxide semiconductor layer 140 in the channel region CH.

[0110] 9 and 16, insulating layers 170 and 180 are formed as interlayer films on the gate insulating layer 150 and the gate electrode 160 ("Interlayer film formation" in step S3010 in FIG. 9). The insulating layers 170 and 180 are formed by a CVD method. For example, silicon nitride is formed as the insulating layer 170, and silicon oxide is formed as the insulating layer 180. The materials used for the insulating layers 170 and 180 are not limited to those mentioned above. The thickness of the insulating layer 170 is 50 nm or more and 500 nm or less. The thickness of the insulating layer 180 is 50 nm or more and 500 nm or less.

[0111] 9 and 17 , openings 171 and 173 are formed in the gate insulating layer 150 and the insulating layers 170 and 180 ("contact hole" in step S3011 in FIG. 9 ). The opening 171 exposes the oxide semiconductor layer 140 in the source region S. The opening 173 exposes the oxide semiconductor layer 140 in the drain region D. By forming source / drain electrodes 200 on the oxide semiconductor layer 140 exposed by the openings 171 and 173 and on the insulating layer 180 ("SD formation" in step S3012 in FIG. 9 ), the thin-film transistor 10 shown in FIG. 7 is completed.

[0112] In the thin film transistor 10 manufactured by the above manufacturing method, when the channel length L of the channel region CH is in the range of 2 μm to 4 μm and the channel width of the channel region CH is in the range of 2 μm to 25 μm, the mobility is 30 cm ２ / Vs] or more, 35[cm ２ / Vs] or more, or 40 [cm ２ / Vs] or more can be obtained. Note that the mobility in this embodiment refers to the field-effect mobility in the saturated region of the thin-film transistor 10, and refers to the maximum value of the field-effect mobility in a region where the potential difference (Vd) between the source electrode and the drain electrode is greater than the value (Vg-Vth) obtained by subtracting the threshold voltage (Vth) of the thin-film transistor 10 from the voltage (Vg) supplied to the gate electrode.

[0113] Furthermore, cross-sectional scanning transmission electron microscopy (STEM) observation was performed on the thin film transistor 10 fabricated by the above manufacturing method. Figures 18 and 19 are cross-sectional STEM images of the thin film transistor 10 according to one embodiment of the present invention. Regions (a) and (b) enclosed by rectangles in Figure 18 are regions including the oxide semiconductor layer OS, and Figure 19 is an enlarged cross-sectional STEM image of the regions (a) and (b).

[0114] 19 , in both regions (a) and (b), crystal grain boundaries can be seen in the oxide semiconductor layer OS in the in-plane direction, but crystal grain boundaries cannot be seen in the film thickness direction. That is, in at least a part of the oxide semiconductor layer OS, one crystal grain forms part of the top surface and part of the bottom surface of the oxide semiconductor layer OS. In other words, the oxide semiconductor layer OS has a continuous crystal structure in the film thickness direction.

[0115] Third Embodiment An electronic device according to a third embodiment of the present invention will be described with reference to FIG.

[0116] FIG. 20 is a schematic diagram showing an electronic device 1000 according to an embodiment of the present invention. Specifically, FIG. 20 shows a smartphone, which is an example of the electronic device 1000. The electronic device 1000 includes a display device 1100 with curved sides. The display device 1100 includes a plurality of pixels for displaying an image, and the plurality of pixels are controlled by a pixel circuit, a drive circuit, and the like. The pixel circuit and the drive circuit include the thin-film transistor 10 described in the second embodiment. The thin-film transistor 10 has high field-effect mobility, which improves the responsiveness of the pixel circuit and the drive circuit, and as a result, can improve the performance of the electronic device 1000.

[0117] The electronic device 1000 according to this embodiment is not limited to a smartphone. The electronic device 1000 also includes electronic devices having a display device, such as a watch, a tablet, a laptop computer, a car navigation system, or a television. The oxide semiconductor film described in the first embodiment or the thin film transistor 10 described in the second embodiment can be applied to any electronic device, regardless of whether or not it has a display device.

[0118] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, even if a person skilled in the art appropriately adds or deletes components or modifies designs, or adds or omits processes or modifies conditions based on the embodiments, such combinations are included within the scope of the present invention as long as they include the gist of the present invention.

[0119] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention.

[0120] 10: Thin film transistor, 100: Substrate, 105, 160: Gate electrode, 110, 120, 150: Gate insulating layer, 130: Metal oxide layer, 140: Oxide semiconductor layer, 141: Upper surface, 142: Lower surface, 143: Side surface, 170, 180: Insulating layer, 171, 173: Opening, 200: Source / drain electrode, 201: Source electrode, 203: Drain electrode, 1000: Electronic device, 1100: Display device

Claims

1. A metal oxide layer provided on a substrate; a crystalline oxide semiconductor layer provided in contact with the metal oxide layer; a gate electrode provided so as to overlap with the oxide semiconductor layer; an insulating layer provided between the oxide semiconductor layer and the gate electrode; the oxide semiconductor layer includes a plurality of crystal grains each including at least one of a crystal orientation <001>, a crystal orientation <101>, and a crystal orientation <111>, as obtained by an electron backscatter diffraction (EBSD) method; A thin film transistor, wherein the occupancy rate of the crystal orientation <001> is 5% or less, in the occupancy rate of the crystal orientation calculated based on measurement points having a crystal orientation with a crystal orientation difference of 0° or more and 15° or less with respect to the normal direction of the surface of the substrate.

2. 2. The thin film transistor of claim 1, wherein the occupancy rate of the crystal orientation calculated based on measurement points having a crystal orientation with a crystal orientation difference of 0° or more and 15° or less with respect to the normal direction of the surface of the substrate is such that the occupancy rate of the crystal orientation <101> is four times or more than the occupancy rate of the crystal orientation <001>.

3. A thin film transistor as described in claim 1, wherein the occupancy rate of the crystal orientation <111> is four times or more than the occupancy rate of the crystal orientation <001>.

4. A thin film transistor as described in claim 1, wherein the ratio of the occupancy rate of the crystal orientation <101> to the occupancy rate of the crystal orientation <111> is 0.7 or more and 1.5 or less.

5. 2. The thin film transistor of claim 1, wherein at least one of the plurality of crystal grains includes at least two of the <001> crystal orientation, the <101> crystal orientation, and the <111> crystal orientation.

6. The thin film transistor of claim 1 , wherein the average GOS of the plurality of crystal grains is 5° or more.

7. The thin film transistor according to claim 1 , wherein the average crystal grain size of the plurality of crystal grains is 1 μm or more.

8. The thin film transistor according to claim 1 , wherein the maximum crystal grain size of the plurality of crystal grains is 2 μm or more.

9. the oxide semiconductor layer contains indium and at least one metal element; The thin film transistor according to claim 1 , wherein a ratio of the indium element to all metal elements including the indium element in the oxide semiconductor layer is 50% or more.

10. The thin film transistor of claim 9 , wherein the metal oxide layer comprises one of the at least one or more metal elements.

11. The thin film transistor of claim 1 , wherein the metal oxide layer comprises aluminum oxide.

12. The thin film transistor according to claim 1 , wherein the oxide semiconductor layer is formed while controlling the substrate temperature to be 50° C. or lower during film formation.

13. The thin film transistor according to claim 12 , wherein the oxide semiconductor layer is formed under conditions where the partial pressure of oxygen is 10% or less.

14. The thin film transistor of claim 13 , wherein the oxide semiconductor layer is crystallized by annealing after deposition.

15. The thin film transistor according to claim 14 , wherein the oxide semiconductor layer is annealed at an ultimate temperature of 350° C. or more and 450° C. or less.

16. 16. An electronic device comprising the thin film transistor according to claim 1.