Semiconductor device

Abstract

This semiconductor device comprises: a chip having a main surface; a trench that demarks a first region on one side and a second region on the other side in the chip in a cross-sectional view; a plurality of trench insulating structures that cover side and bottom walls of the trench and that are integrated with each other; and a first conductivity-type drift region formed along the side and bottom walls of the trench in the chip and that provide an electric current path connecting the first region and the second region.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Patent Application No. 2022-053290 filed with the Japan Patent Office on March 29, 2022, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] Patent Document 1 discloses a semiconductor device including a p-type region, a first p-epitaxial region, an n-type buried region, a second p-epitaxial region, and a deep trench isolation (DTI) structure. The first p-type epitaxial layer is formed on the p-type region. The n-type buried region is formed on the first p-epitaxial region. The second p-epitaxial region is formed on the n-type buried region. The DTI structure surrounds a region where a high-voltage lateral MOS transistor is formed in a plan view. The DTI structure penetrates the second p-epitaxial region, the n-type buried region, and the first p-epitaxial region to reach the p-type region.

[0004] JP 2015-122543 A

[0005] An embodiment of the present disclosure provides a semiconductor device that can reduce the element area while suppressing a decrease in breakdown voltage.

[0006] A semiconductor device according to one embodiment of the present disclosure includes a chip having a main surface, a trench that partitions the chip into a first region on one side and a second region on the other side in a cross-sectional view, a plurality of trench isolation structures that cover side walls and a bottom wall of the trench and are integrated with one another, and a drift region of a first conductivity type that is formed inside the chip along the side walls and the bottom wall of the trench and provides a current path connecting the first region and the second region.

[0007] FIG. 1 is a schematic plan view of a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is an enlarged view of a region surrounded by a two-dot chain line II in FIG. 1. FIG. 3 is a view showing a cross section taken along line III-III in FIG. 2. FIG. 4 is an enlarged view of a portion surrounded by a two-dot chain line IV in FIG. 3. FIG. 5 is an enlarged view of a main portion of FIG. 4. FIG. 6 is a view showing a flow of a manufacturing process of the semiconductor device. FIG. 7A is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device. FIG. 7B is a view showing a process subsequent to FIG. 7A. FIG. 7C is a view showing a process subsequent to FIG. 7B. FIG. 7D is a view showing a process subsequent to FIG. 7C. FIG. 8 is a view showing a modified example of the semiconductor device.

[0008] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The components in the accompanying drawings are not necessarily precisely illustrated, but are shown schematically, and the scales of the drawings do not necessarily match.

[0009] Fig. 1 is a schematic plan view of a semiconductor device 1 according to an embodiment of the present disclosure. Fig. 2 is an enlarged view of a region surrounded by a two-dot chain line II in Fig. 1. Fig. 3 is a view showing a cross section taken along line III-III in Fig. 2. Fig. 4 is an enlarged view of a portion surrounded by a two-dot chain line IV in Fig. 3. Fig. 5 is an enlarged view of a main portion of Fig. 4.

[0010] The semiconductor device 1 includes a rectangular parallelepiped semiconductor chip 2. In this embodiment, the semiconductor chip 2 is made of a silicon (Si) chip. The semiconductor chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.

[0011] The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view"). The normal direction Z is also the thickness direction of the semiconductor chip 2. The first side surface 5A and the second side surface 5B extend in a first direction X (horizontal direction) along the first main surface 3 and face a second direction Y (horizontal direction) that intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0012] The semiconductor device 1 includes a p-type first layer 6, a p-type or n-type second layer 7, and an n-type third layer 8 formed within a semiconductor chip 2. The first layer 6 may be referred to as a "base layer." The second layer 7 may be referred to as a "device-forming layer." The third layer 8 may be referred to as a "buried layer." The first layer 6, the second layer 7, and the third layer 8 may be considered components of the semiconductor chip 2.

[0013] The first layer 6 is formed in a region on the second main surface 4 side within the semiconductor chip 2, and forms part of the second main surface 4 and the first to fourth side surfaces 5A to 5D. The first layer 6 may have a concentration gradient in which the p-type impurity concentration on the first main surface 3 side is lower than the p-type impurity concentration on the second main surface 4 side. Specifically, the first layer 6 may have a layered structure including a high-concentration layer and a low-concentration layer stacked in this order from the second main surface 4 side. The first layer 6 may have a thickness of, for example, 100 μm or more and 600 μm or less. In this embodiment, the first layer 6 may be made of a p-type semiconductor substrate (Si substrate).

[0014] The second layer 7 is formed in a region on the first main surface 3 side of the semiconductor chip 2 and forms part of the first main surface 3 and the first to fourth side surfaces 5A to 5D. The conductivity type (n-type or p-type) of the second layer 7 is arbitrary and is selected according to the specifications of the semiconductor device 1. In this embodiment, an example in which the second layer 7 has n-type conductivity is described, but the conductivity type of the second layer 7 is not intended to be limited to n-type. The second layer 7 may have a uniform n-type impurity concentration in the thickness direction, or may have an n-type impurity concentration gradient that increases toward the first main surface 3. In this embodiment, the second layer 7 may be composed of an n-type epitaxial layer (Si epitaxial layer).

[0015] The third layer 8 is interposed in the region between the first layer 6 and the second layer 7 within the semiconductor chip 2, and forms part of the first to fourth side surfaces 5A to 5D of the semiconductor chip 2. The third layer 8 forms a pn junction J at the boundary with the first layer 6. That is, within the semiconductor chip 2, a pn junction J (a pn-junction portion) is formed midway in the thickness direction between the first main surface 3 and the second main surface 4, extending horizontally along the first main surface 3 (orthogonal to the thickness direction). The pn junction J may also be referred to as a "pn-connection portion" or a "pn-boundary portion."

[0016] The third layer 8 has a higher n-type impurity concentration than the second layer 7. Specifically, the third layer 8 may have a concentration gradient in which the n-type impurity concentration on the first main surface 3 side is higher than the n-type impurity concentration on the second main surface 4 side. The third layer 8 may have a thickness of, for example, 0.1 μm or more and 10 μm or less. In this embodiment, the third layer 8 may be made of an n-type epitaxial layer (Si epitaxial layer).

[0017] The semiconductor device 1 includes a plurality of element regions 9 provided on the first main surface 3 (second layer 7). The plurality of element regions 9 are regions in which various functional elements are respectively formed. The plurality of element regions 9 are respectively partitioned inwardly of the first main surface 3 at intervals from the first to fourth side surfaces 5A to 5D in a plan view. The number, arrangement, and shape of the element regions 9 are arbitrary and are not limited to a specific number, arrangement, or shape.

[0018] The plurality of functional elements may each include at least one of a semiconductor switching element, a semiconductor rectifying element, and a passive element. The semiconductor switching element may include at least one of a JFET (Junction Field Effect Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), a BJT (Bipolar Junction Transistor), and an IGBT (Insulated Gate Bipolar Junction Transistor).

[0019] The semiconductor rectifying element may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive element may include at least one of a resistor, a capacitor, an inductor, and a fuse. In this embodiment, the multiple element regions 9 include at least one transistor region 9A. The structure of the transistor region 9A side will be specifically described below.

[0020] The semiconductor device 1 includes an element isolation structure 10 that defines a transistor region 9A on the first main surface 3. The element isolation structure 10 defines the transistor region 9A having a predetermined shape in a plan view. The element isolation structure 10 may also be referred to as a "trench electrode structure."

[0021] Referring to FIG. 2 , the element isolation structure 10 is formed in a strip shape extending along the transistor region 9A in a plan view. In this embodiment, the element isolation structure 10 is formed in a ring shape (a square ring shape in this embodiment) in a plan view, and defines a transistor region 9A of a predetermined shape (a square shape in this embodiment). In this embodiment, the four corners of the element isolation structure 10 have rounded shapes that curve in a direction away from the transistor region 9A in a plan view. The planar shape of the element isolation structure 10 (the planar shape of the transistor region 9A) is arbitrary. The element isolation structure 10 may be formed in a polygonal ring shape, a circular ring shape, or an elliptical ring shape in a plan view, and define a transistor region 9A that is polygonal, circular, or elliptical in a plan view.

[0022] 2, the element isolation structure 10 has a trench width W1. The trench width W1 is the width in a direction perpendicular to the direction in which the element isolation structure 10 extends in a plan view. The trench width W1 may be 0.5 μm or more and 10 μm or less.

[0023] 3 , the element isolation structure 10 is formed on the first main surface 3 so as to penetrate the pn junction J, and defines a transistor region 9A on the first main surface 3. Specifically, the element isolation structure 10 penetrates the second layer 7 and the third layer 8 to reach the first layer 6, and defines the transistor region 9A in the second layer 7. In this embodiment, the element isolation structure 10 extends from the first main surface 3 toward the second main surface 4 so as to reach the first layer 6, and penetrates the second layer 7 and the third layer 8.

[0024] The element isolation structure 10 includes an inner wall on the transistor region 9A side, an outer wall on the opposite side of the inner wall (the peripheral edge side of the semiconductor chip 2), and a bottom wall connecting the inner and outer walls. The element isolation structure 10 is electrically connected to the semiconductor chip 2 at the bottom wall and electrically insulated from the semiconductor chip 2 at the side walls (inner and outer walls). That is, the element isolation structure 10 has a lower end electrically connected to the semiconductor chip 2. Specifically, the element isolation structure 10 is electrically connected to the first layer 6 and electrically insulated from the second layer 7 and the third layer 8. That is, the element isolation structure 10 is fixed at the same potential as the first layer 6.

[0025] The element isolation structure 10 includes an element isolation trench 13 , an element isolation insulating film 14 , and an element isolation electrode 15 .

[0026] 2, the element isolation trench 13 is formed in a ring shape in a plan view. The width of the element isolation trench 13 may be the trench width W1 described above. Referring to FIG. 3, the element isolation trench 13 is formed on the first main surface 3 side of the semiconductor chip 2 so as to penetrate the pn junction J. Specifically, the element isolation trench 13 penetrates the second layer 7 and the third layer 8 so as to reach the first layer 6. The element isolation trench 13 includes an inner wall 16 on the transistor region 9A side, an outer wall 17 on the opposite side of the inner wall 16 (the peripheral edge side of the semiconductor chip 2), and a bottom wall 18 connecting the inner wall 16 and the outer wall 17. The inner wall 16 and the outer wall 17 may be referred to as an "inner wall" and an "outer wall," or as a "first side wall" and a "second side wall," respectively.

[0027] The element isolation insulating film 14 covers the inner wall 16 and the outer wall 17 of the element isolation trench 13 so as to expose the semiconductor chip 2 from the bottom wall 18 of the element isolation trench 13. Specifically, the element isolation insulating film 14 exposes the first layer 6 from the bottom wall 18 of the element isolation trench 13. The element isolation insulating film 14 preferably covers the entire inner wall 16 and the entire outer wall 17 of the element isolation trench 13. The region where the bottom wall 18 of the element isolation trench 13 is exposed may be a contact hole 11 in the element isolation insulating film 14. The element isolation insulating film 14 may include a silicon oxide film. The element isolation insulating film 14 preferably includes a silicon oxide film made of an oxide of the semiconductor chip 2.

[0028] The element isolation electrode 15 is embedded in the element isolation trench 13 with the element isolation insulating film 14 sandwiched therebetween and is electrically connected to the semiconductor chip 2 at the bottom wall 18 of the element isolation trench 13. Specifically, the element isolation electrode 15 is electrically connected to the first layer 6 via the contact hole 11 and is electrically insulated from the second layer 7 and the third layer 8 by the element isolation insulating film 14. The element isolation electrode 15 preferably contains conductive polysilicon. The element isolation electrode 15 preferably contains conductive polysilicon of the same conductivity type (p-type in this embodiment) as the first layer 6. The p-type impurity of the element isolation electrode 15 is preferably boron. Referring to FIG. 2 , an element isolation contact 79 may be connected to the element isolation electrode 15. This allows the potential of the element isolation electrode 15 to be controlled via wiring (not shown).

[0029] The semiconductor device 1 further includes a sinker layer 12 formed in the second layer 7. The sinker layer 12 extends in the depth direction of the isolation trench 13 and is in contact with the third layer 8 and the isolation insulating film 14. More specifically, the sinker layer 12 is formed in an annular shape along the inner and outer peripheral walls 16 and 17 of the isolation trench 13 and is in contact with the isolation insulating film 14 over the entire depth direction of the isolation trench 13 as shown in FIG. 3 . The sinker layer 12 may have a thickness of 0.5 μm to 5 μm in a direction perpendicular to the depth direction of the isolation trench 13.

[0030] A contact region 19 is formed at the end of the sinker layer 12 on the first main surface 3 side along the inner peripheral wall 16. The contact region 19 is exposed from the first main surface 3. As shown in FIG. 2, the contact region 19 is formed linearly along a part of the element isolation trench 13 and is in contact with the element isolation insulating film 14. The sinker layer 12 has the same conductivity type as the third layer 8, which is n-type in this embodiment. The contact region 19 also has the same conductivity type as the third layer 8, which is n-type in this embodiment. ＋ The impurity concentration of the contact region 19 may be higher than that of the sinker layer 12.

[0031] 2 to 4, the semiconductor device 1 includes a planar gate MISFET 30 as an example of a functional element formed in the transistor region 9 A. Depending on the magnitude of the drain-source voltage applied between the drain and the source, the MISFET 30 can take any one of the following forms: an HV (high voltage)-MISFET (for example, 100 V or more and 1000 V or less), an MV (middle voltage)-MISFET (for example, 30 V or more and 100 V or less), and an LV (low voltage)-MISFET (for example, 1 V or more and 30 V or less).

[0032] The MISFET 30 includes a first trench isolation structure 20 and a second trench isolation structure 21 formed in the transistor region 9A.

[0033] 3 , the first trench isolation structure 20 may also be referred to as a shallow trench structure or an STI (shallow trench isolation) structure. The first trench isolation structure 20 is formed in the second layer 7 at a distance from the third layer 8 in the thickness direction of the second layer 7. The first trench isolation structure 20 is formed along the periphery of the sinker layer 12 and is in contact with the sinker layer 12. The first trench isolation structure 20 surrounds the second trench isolation structure 21 in the second layer 7. The first trench isolation structure 20 includes a shallow trench 22 and a buried insulator 23. The shallow trench 22 is formed in the first main surface 3. The buried insulator 23 is buried in the shallow trench 22.

[0034] 3 and 4 , the second trench isolation structure 21 divides the transistor region 9A into an outer first region 24 and an inner second region 25. In this embodiment, as shown in Fig. 2 , the second trench isolation structure 21 is formed in a ring shape in a plan view. The inner region surrounded by the annular second trench isolation structure 21 is the second region 25, and the outer region surrounding the annular second trench isolation structure 21 is the first region 24.

[0035] 4 and 5, the second trench isolation structure 21 includes a trench 26 and a trench isolation structure 27.

[0036] The trench 26 is formed in a ring shape in a plan view. The width W2 of the trench 26 is the width in a direction perpendicular to the extension direction of the second trench isolation structure 21 in a plan view (see FIG. 2 ). The width W2 of the trench 26 is greater than the trench width W1 and the width of the shallow trench 22. The trench width W2 may be 20 μm or more and 100 μm or less. The trench 26 is formed in the second layer 7 at a distance from the third layer 8 in the thickness direction of the second layer 7. The trench 26 has a greater depth than the shallow trench 22. The trench 26 includes an inner wall 28 on the second region 25 side, an outer wall 29 on the opposite side of the inner wall 28 (the peripheral edge side of the semiconductor chip 2), and a bottom wall 31 connecting the inner wall 28 and the outer wall 29. The inner wall 28 and the outer wall 29 may be referred to as the "inner wall" and the "outer wall," or as the "first side wall" and the "second side wall," respectively.

[0037] The trench insulation structure 27 includes a plurality of trench insulation structures 27 that integrally cover the peripheral walls 28, 29 and bottom wall 31 of the trench 26. The plurality of trench insulation structures 27 may be distinguished into individual trench insulation structures 27 by protrusions 34 formed on the bottom wall 31 of the trench 26. The protrusions 34 protrude from the lower ends of the trench insulation structures 27 toward the interior and upper portions of the trench insulation structures 27 in the depth direction of the trench 26. The protrusions 34 are embedded in the trench insulation structures 27. As a result, recesses 35 corresponding to the shape of the protrusions 34 are formed at the lower ends of the trench insulation structures 27 (see FIG. 5). The protrusions 34 are formed in an annular shape along the circumferential direction of the annular trench 26 so as to overlap the trench insulation structures 27 in a plan view. Because the protrusions 34 are continuous around the entire circumference of the trench 26 in a plan view, they may also be referred to as "annular ridges." Therefore, the recess 35 corresponding to the shape of the protrusion 34 may be called an "annular groove."

[0038] In this embodiment, a plurality of protrusions 34 are formed. The plurality of protrusions 34 are formed concentrically in order from the inner peripheral wall 28 toward the outer peripheral wall 29 of the trench 26. That is, a plurality of protrusions 34 are formed surrounding the second region 25 in a plan view. In this embodiment, portions of the trench insulation structure 27 on the regions between adjacent protrusions 34 may each be an individual unit 36 ​​of the trench insulation structure 27. Each individual unit 36 ​​is formed vertically in the depth direction of the trench 26, extending from the bottom wall 31 of the trench 26 to the first main surface 3.

[0039] The multiple individual units 36 of the trench isolation structure 27 are not physically separated from one another, but are integrated in the horizontal direction along the first main surface 3. In other words, in this embodiment, the multiple trench isolation structures 27 are not physically separated, but are conceptually distinguished by the multiple protrusions 34. Each individual unit 36 ​​of the trench isolation structure 27 is formed along a fill line 37 that extends upward in the depth direction of the trench 26 from the region between adjacent protrusions 34. The fill line 37 is an imaginary line that extends upward from the center between adjacent protrusions 34, and is shown by a dashed line in FIGS. 2 to 5 .

[0040] The trench isolation structure 27 includes a first structure 38 and a second structure 39 as a plurality of individual units 36. The first structure 38 is located closer to the second region 25 than to the central portion between the first region 24 and the second region 25. In this embodiment, of the plurality of trench isolation structures 27 (six in FIG. 4 ), only the trench isolation structure 27 at the farthest end closer to the second region 25 is the first structure 38, and the rest are second structures 39. In other words, the second structures 39 are formed more on the first region 24 side than on the second region 25 side relative to the central portion between the first region 24 and the second region 25. Also, referring to FIG. 5 , in the horizontal direction along the first main surface 3, the first width W3 of the first structure 38 is larger than the second width W4 of the second structure 39. The first width W3 and the second width W4 may be defined by the pitch between adjacent protrusions 34. The width of the outermost trench insulating structure 27 may be the width between the peripheral walls 28, 29 of the trench 26 and the protruding portion 34 closest to the peripheral walls 28, 29. The number of first structures 38 and second structures 39 may be adjusted appropriately according to the breakdown voltage required for the semiconductor device 1. For example, if the semiconductor device 1 is required to have a high breakdown voltage, the number of first structures 38 and second structures 39 may be increased as much as possible.

[0041] 4 and 5, the trench isolation structure 27 includes a buried insulator 40 and a buried conductor 41.

[0042] The buried insulator 40 is an insulator portion of the trench isolation structure 27 and is integrated between the first structure 38 and the second structure 39. Referring to Fig. 5, the buried insulator 40 may include a first film portion 42 having a relatively high density and a second film portion 43 having a lower density than the first film portion 42. A clearly defined film interface may exist between the first film portion 42 and the second film portion 43 as shown in Fig. 5, or may not exist as shown in Fig. 4.

[0043] The density of the film can be compared, for example, by etching the first film portion 42 and the second film portion 43 with a common etching gas or etching solution, based on the difference in etching rate. For example, when the first film portion 42 and the second film portion 43 are etched with a common etching gas or etching solution, the etching rate of the first film portion 42, which has a relatively high density, may be slower than the etching rate of the second film portion 43. Note that when the buried insulator 40 is made of silicon oxide, hydrofluoric acid (HF) can be used as the common etching gas.

[0044] In the first structure 38, the first film portion 42 has a recess 44 extending in the depth direction of the trench 26, and a second film portion 43 is formed along the inner wall of the recess 44. An embedded conductor 41 is embedded in the recess 44. The embedded conductor 41 is exposed at the first main surface 3. In this embodiment, the embedded conductor 41 is made of conductive polysilicon. As shown in FIG. 4 , the embedded conductor 41 may have a tapered shape at an upper portion closer to the first main surface 3. On the other hand, in the second structure 39, the first film portion 42 has a recess 45 extending in the depth direction of the trench 26, and a second film portion 43 is embedded in the recess 45.

[0045] 4 , when the boundary between the first film portion 42 and the second film portion 43 cannot be defined, the embedded insulator 40 may include a first portion 46 on the first region 24 side of the embedded conductor 41 and a second portion 47 on the second region 25 side of the embedded conductor 41. In the horizontal direction along the first main surface 3, a thickness T1 of the first portion 46 may be larger than a thickness T2 of the second portion 47.

[0046] In the transistor region 9A, an n-type drift region 48 is formed in the second layer 7. The drift region 48 is formed along the peripheral walls 28, 29 and bottom wall 31 of the trench 26 so as to form a current path connecting the first region 24 and the second region 25. As shown in FIG. 4 , the drift region 48 is in contact with the buried insulator 40 throughout the entire depth direction of the trench 26. The drift region 48 may have a thickness of 0.5 μm to 5 μm in a direction perpendicular to the depth direction of the trench 26. The impurity concentration of the drift region 48 may be the same as the impurity concentration of the sinker layer 12.

[0047] 2 , drift region 48 is formed in an annular shape in plan view and is exposed from first main surface 3 in both first region 24 and second region 25. Referring to FIG. 4 , drift region 48 in second region 25 may branch out from first main surface 3 toward the depth direction of trench 26. As a result, in second region 25, a portion of second layer 7 may be sandwiched between the pair of drift regions 48 in cross-sectional view. This portion of second layer 7 may be a protruding portion 49 that protrudes into second region 25 from a position below trench 26 toward first main surface 3.

[0048] 4 , a drain region 50 is formed in the first region 24 at the end of the drift region 48 on the first main surface 3 side. The drain region 50 is electrically connected to the drift region 48. The drain region 50 is sandwiched between the first trench isolation structure 20 and the second trench isolation structure 21. The drain region 50 is in contact with the buried insulator 40 and the buried insulator 23. A drain contact region 51 is formed in a surface layer portion of the drain region 50. The drain contact region 51 is exposed from the first main surface 3. The drain contact region 51 is formed linearly along a portion of the trench 26 as shown in FIG. 2 . The drain region 50 has the same conductivity type as the drift region 48, which is n-type in this embodiment. The drain contact region 51 also has the same conductivity type as the drift region 48, which is n-type in this embodiment. ＋ The impurity concentration of the drain contact region 51 may be higher than that of the drain region 50.

[0049] 4 , a body region 52 is formed in the second region 25 at an end of the drift region 48 on the first main surface 3 side. The body region 52 is electrically connected to the drift region 48. The body region 52 is formed in an inner region of the second region 25 spaced apart from the second trench isolation structure 21. The body region 52 may be formed to cross the protrusion 49 between the pair of drift regions 48 in a cross-sectional view. When the second layer 7 is of n-type, the body region 52 may form a pn junction with the protrusion 49.

[0050] A source region 53 and a body contact region 54 are formed in a surface layer portion of the body region 52. The source region 53 is formed with a gap between the outer periphery of the body region 52 and the inside. Referring to FIG. 2 , the source region 53 may be rectangular in shape, extending along the longitudinal direction of the rectangular body region 52 in a plan view and crossing the body region 52 from one end to the other end in the longitudinal direction. A channel region 55 is formed in the surface layer portion of the body region 52, between the outer periphery of the body region 52 and the outer periphery of the source region 53. In this embodiment, the body region 52 is p-type, and the source region 53 is n-type. ＋ It is a type.

[0051] The body contact region 54 is formed in the center of the source region 53 and is connected to the body region 52. Referring to Fig. 2, the body contact region 54 may have a rectangular shape that extends along the longitudinal direction of the source region 53 and is formed in an inner region of the source region 53. In this embodiment, the body contact region 54 is surrounded by the source region 53 in a plan view.

[0052] A planar gate structure 56 is further formed in the second region 25. Referring to Fig. 4, the planar gate structure 56 is formed on the first main surface 3 so as to cover the channel region 55 and controls the on / off of the channel region 55. In this embodiment, the planar gate structure 56 is formed so as to straddle the source region 53 and the second trench isolation structure 21. The planar gate structure 56 may cover a portion of the trench insulation structure 27 of the second trench isolation structure 21.

[0053] The planar gate structure 56 includes a gate insulating film 57 and a gate electrode 58 stacked in this order from the first main surface 3 side. The gate insulating film 57 may include a silicon oxide film. The gate insulating film 57 preferably includes a silicon oxide film made of an oxide of the semiconductor chip 2.

[0054] 2, the gate electrode 58 may be formed in a ring shape in a plan view. The gate electrode 58 preferably includes conductive polysilicon. The gate electrode 58 preferably includes n-type conductive polysilicon. The n-type impurity of the gate electrode 58 is preferably phosphorus or arsenic. Of course, the gate electrode 58 may have p-type conductivity. In this case, the p-type impurity of the gate electrode 58 is preferably boron.

[0055] 4, an interlayer insulating film 59 is formed on first main surface 3 so as to cover planar gate structure 56. Interlayer insulating film 59 is made of, for example, silicon oxide. A plurality of interconnections 60-62 are formed on interlayer insulating film 59. Each of the plurality of interconnections 60-62 may include a drain interconnection 60, a source interconnection 61, and a field plate interconnection 62.

[0056] The drain wiring 60 is connected to the drain contact region 51 via a drain contact 63 buried in the interlayer insulating film 59. The source wiring 61 is connected to the source region 53 and the body contact region 54 via a source contact 64 buried in the interlayer insulating film 59. The field plate wiring 62 is connected to the buried conductor 41 via a field plate contact 65 buried in the interlayer insulating film 59. Therefore, the buried conductor 41 may be referred to as a field plate.

[0057] In this embodiment, the potential of the buried conductor 41 may be equal to or higher than the potential of the source region 53 and equal to or lower than the potential of the drain region 50. Furthermore, by omitting the field plate wiring 62 and the field plate contact 65, the buried conductor 41 may be in an electrically floating state.

[0058] 6 is a diagram showing a flow of the manufacturing process of the semiconductor device 1. Figures 7A to 7D are schematic cross-sectional views showing some of the manufacturing processes of the semiconductor device 1 in the order of steps.

[0059] To manufacture the semiconductor device 1, referring to FIG. 6, a p-type semiconductor wafer (first layer 6) that will become the semiconductor chip 2 is prepared. Then, a buried layer (third layer 8) and a second layer 7 are formed on a semiconductor wafer 66 (see FIGS. 7A to 7D) (step S1). For example, n-type impurities (e.g., phosphorus) are implanted into the surface of the first layer 6. Next, the second layer 7 is formed on the first layer 6 by epitaxially growing silicon while introducing the n-type impurities. Then, an annealing process is performed, causing the n-type impurities implanted into the surface of the first layer 6 to diffuse to both sides of the semiconductor wafer 66 in the thickness direction. This results in the formation of a third layer 8 (buried layer) between the first layer 6 and the second layer 7. The resulting semiconductor wafer 66 has the first main surface 3 and the second main surface 4 described above.

[0060] 6 , a hard mask (e.g., silicon oxide) is formed on the first main surface 3 of the first layer 6, and the second layer 7 and the third layer 8 are selectively etched through the hard mask. This forms an isolation trench 13, and a transistor region 9A is defined in the first layer 6 (step S2). At this stage, the bottom of the isolation trench 13 is located midway through the third layer 8 in the thickness direction.

[0061] 6, n-type impurities are selectively implanted into the inner walls (inner peripheral wall 16, outer peripheral wall 17, and bottom wall 18) of the element isolation trench 13 and the first main surface 3 of the transistor region 9A (step S3). In this embodiment, the n-type impurities are implanted at a tilt angle θ of 3° to 7° with respect to the direction n normal to the first main surface 3. This allows the n-type impurities to be efficiently implanted into the inner peripheral wall 16 and outer peripheral wall 17 of the element isolation trench 13. Phosphorus (P) or the like can be used as the n-type impurity.

[0062] 6, additional etching is performed on the isolation trench 13 (step S4). As a result, the isolation trench 13 is further dug down, and the bottom wall 18 of the isolation trench 13 reaches the first layer 6. This additional etching step can be omitted. In that case, the isolation trench 13 may be formed by the etching step of step S2 so that the bottom wall 18 reaches the first layer 6.

[0063] 6, the element isolation insulating film 14 is formed on the inner walls (inner peripheral wall 16, outer peripheral wall 17, and bottom wall 18) of the element isolation trench 13 (step S5). The element isolation insulating film 14 is formed by, for example, thermal oxidation. Heat generated during the formation of the element isolation insulating film 14 diffuses the n-type impurities on the inner peripheral wall 16 and outer peripheral wall 17 of the element isolation trench 13 and the n-type impurities in the transistor region 9A, forming the sinker layer 12 and the drift region 48.

[0064] 6, the portion of the isolation insulating film 14 on the bottom wall 18 of the isolation trench 13 is removed by etching, thereby forming the contact hole 11. Next, the isolation electrode 15 is buried in the isolation trench 13 (step S6).

[0065] 6 and 7A, a hard mask 67 is formed on the first main surface 3 of the semiconductor wafer 66 (step S7). The hard mask 67 has a first opening 68 and a second opening 69 corresponding to the shapes of a main trench 71 and a sub-trench 72, respectively, which will be described later. Next, the semiconductor wafer 66 is etched through the hard mask 67 to form a deep trench 70 in the semiconductor wafer 66 (step S8). The deep trench 70 is formed in the drift region 48 and has a bottom within the drift region 48. The deep trench 70 divides the first main surface 3 side of the semiconductor wafer 66 into a first region 24 and a second region 25.

[0066] In this embodiment, the deep trench 70 includes a plurality of annular deep trenches 70 that are concentrically arranged and physically separated from one another. Specifically, the deep trench 70 may be a trench group 73 that includes a main trench 71 at the outermost end on the second region 25 side and a plurality of sub-trenches 72 that are arranged outside the main trench 71 and have a narrower width than the main trench 71. In FIG. 7A , three sub-trenches 72 are formed outside the main trench 71. The number of sub-trenches 72 may be adjusted according to the number of second structures 39 described above. The width of the main trench 71 may be, for example, 2.5 μm or more and 3 μm or less, and the width of the sub-trenches 72 may be, for example, 1 μm or more and 1.5 μm or less.

[0067] In the trench group 73, the deep trenches 70 are annular and physically separated from one another, and therefore, semiconductor wall portions 74 formed using a portion of the semiconductor wafer 66 are formed between adjacent deep trenches 70. Each semiconductor wall portion 74 is formed in a strip shape along the circumferential direction of the trench group 73 in a plan view, and forms a boundary between adjacent deep trenches 70. The thickness of the semiconductor wall portion 74 is preferably, for example, 1 μm or less. This allows the semiconductor wall portions 74 to be easily transformed into insulator wall portions 76 in the subsequent thermal oxidation step.

[0068] 6 and 7B , the semiconductor wafer 66 is subjected to a thermal oxidation process. This forms a first insulating film 75 (first film portion 42) on the bottom wall and sidewall of the deep trench 70 (step S9). The first insulating film 75 may also be referred to as a "thermal oxide film" or a "liner oxide film." This thermal oxidation transforms the semiconductor wall portion 74 into an insulator by oxidizing it from both sides of adjacent deep trenches 70, forming the insulator wall portion 76. The insulator wall portion 76 may also be referred to as a boundary insulating film that forms the boundary between adjacent deep trenches 70. Because the insulator wall portion 76 is formed by the transformation of the semiconductor wall portion 74, it may have the same thickness as the semiconductor wall portion 74. Meanwhile, in this process, the lower portion of the semiconductor wall portion 74 is not partially transformed into an insulator in the depth direction of the deep trench 70, forming a protrusion 34 that protrudes upward from the lower end of the insulator wall portion 76.

[0069] 6 and 7C , an insulating material is deposited on the semiconductor wafer 66 by, for example, CVD. The gas used for the CVD may be, for example, tetra ethyl orthosilicate (TEOS) gas. The insulating material backfills the sub-trench 72 and is deposited along the inner surface of the main trench 71. This forms a buried insulating film 77 buried in the recess 45 of the sub-trench 72, and a second insulating film 78 along the inner surface of the recess 44 of the main trench 71 (step S10). The buried insulating film 77 and the second insulating film 78 correspond to the second film portion 43 described above.

[0070] 6 and 7D, a conductive material is deposited on the semiconductor wafer 66 by, for example, CVD. In this embodiment, the conductive material is polysilicon. The conductive material backfills the recess 44 of the main trench 71. This forms a buried conductor 41 in the main trench 71 (step S11).

[0071] The next step is to form the MISFET 30 in the transistor region 9A. For example, a first trench isolation structure 20 (STI) is formed in the first main surface 3 (step S12). After that, element structures such as a body region 52, a drain region 50, and a source region 53 are formed (step S13), and a planar gate structure 56 is formed. The semiconductor wafer 66 is then divided into pieces each having the size of a semiconductor chip 2. Thereafter, if necessary, the semiconductor chip 2 is bonded to a lead frame and sealed with a sealing resin, thereby obtaining the semiconductor device 1.

[0072] As described above, according to the semiconductor device 1, the drift region 48 is formed along the peripheral walls 28, 29 and bottom wall 31 of the trench 26, and the depth direction of the trench 26 can be used as the drift region 48. This allows the source-drain distance in the horizontal direction along the first main surface 3 to be shortened by the depth of the trench 26. As a result, the device area can be reduced, thereby achieving a low on-resistance. Furthermore, by forming the drift region 48 along the peripheral walls 28, 29 of the trench 26, the total length of the drift region 48 can be prevented from becoming shorter, thereby suppressing a decrease in breakdown voltage.

[0073] Furthermore, the buried conductor 41 can be maintained at an appropriate potential and used as a field plate to reduce the electric field between the source and drain.

[0074] The embodiments of the present disclosure are to be considered as illustrative in all respects and not restrictive, and are intended to include modifications in all respects.

[0075] 8 , all trench isolation structures 27 may be first structures 38 including embedded conductors 41. In this case, the potentials of the multiple embedded conductors 41 may form a potential gradient that decreases stepwise from the first region 24 to the second region 25 in the range of the potential difference between the drain region 50 and the source region 53. For example, the potential may be first potential V1 > second potential V2 > third potential V3.

[0076] For example, in the above-described embodiments, an example was described in which the first conductivity type was n-type and the second conductivity type was p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. A specific configuration in this case can be obtained by replacing n-type regions with p-type regions and p-type regions with n-type regions in the above description and accompanying drawings. In the above-described embodiments, examples were described in which the n-type was expressed as the "first conductivity type" and the p-type was expressed as the "second conductivity type," but these terms are used to clarify the order of the description, and the n-type may be expressed as the "second conductivity type" and the p-type as the "first conductivity type."

[0077] The following characteristics can be extracted from the description of this specification and the drawings.

[0078] [Supplementary Note 1-1] A semiconductor device comprising: a chip having a main surface; a trench that partitions the chip into a first region on one side and a second region on the other side in a cross-sectional view; a plurality of trench isolation structures that cover side walls and a bottom wall of the trench, the plurality of trench isolation structures being integrated with one another; and a drift region of a first conductivity type that is formed inside the chip along the side walls and the bottom wall of the trench and provides a current path connecting the first region and the second region.

[0079] [Supplementary Note 1-2] The semiconductor device according to Supplementary Note 1-1, comprising: a drain region of a first conductivity type formed in a surface layer portion of the main surface so as to be electrically connected to the drift region on the first region side; a body region of a second conductivity type formed in a surface layer portion of the main surface so as to be electrically connected to the drift region on the second region side; a source region of the first conductivity type formed in a surface layer portion of the body region so as to form a channel region between the source region of the first conductivity type and the drift region; and a gate structure arranged on the main surface so as to overlap the channel region on the second region side.

[0080] [Supplementary Note 1-3] The semiconductor device according to Supplementary Note 1-1 or Supplementary Note 1-2, further comprising a plurality of protrusions formed on the bottom wall of the trench and protruding from a lower end of the integrated trench insulation structure toward an interior upward portion of the trench insulation structure in a depth direction of the trench, and each of the trench insulation structures is formed to extend from a region between adjacent protrusions toward an interior upward portion of the trench in the depth direction.

[0081] [Supplementary Note 1-4] The semiconductor device according to Supplementary Note 1-3, wherein at least one of the trench isolation structures includes a first structure including conductive polysilicon embedded in the trench in a depth direction.

[0082] [Supplementary Note 1-5] The semiconductor device according to Supplementary Note 1-4, wherein the first structure is unevenly distributed toward the second region with respect to a central portion between the first region and the second region.

[0083] [Supplementary Note 1-6] The semiconductor device according to Supplementary Note 1-4 or Supplementary Note 1-5, wherein, of the plurality of trench insulation structures, only the trench insulation structure at the outermost end on the second region side is the first structure.

[0084] [Supplementary Note 1-7] The semiconductor device according to any one of Supplementary Note 1-4 to Supplementary Note 1-6, wherein at least one of the trench insulation structures includes a second structure including a buried insulating film buried in the depth direction of the trench, and the second structure is formed in a proportion that is greater on the first region side than on the second region side with respect to a central portion between the first region and the second region.

[0085] [Supplementary Note 1-8] The semiconductor device according to any one of Supplementary Note 1-3 to Supplementary Note 1-7 relating to Supplementary Note 1-2, wherein the potential of the conductive polysilicon is equal to or higher than the potential of the source region and equal to or lower than the potential of the drain region.

[0086] [Supplementary Note 1-9] The semiconductor device according to any one of Supplementary Note 1-3 to Supplementary Note 1-7 relating to Supplementary Note 1-2, wherein the conductive polysilicon is in an electrically floating state.

[0087] [Supplementary Note 1-10] The semiconductor device according to any one of Supplementary Note 1-1 to Supplementary Note 1-3, wherein the plurality of trench isolation structures include a first structure having a first width and a second structure having a second width smaller than the first width.

[0088] [Supplementary Note 1-11] The semiconductor device according to Supplementary Note 1-10, wherein the first structure is formed so as to be biased toward the second region, and the second structure is formed so as to be biased toward the first region.

[0089] [Supplementary Note 1-12] The semiconductor device according to Supplementary Note 1-10 or Supplementary Note 1-11, wherein the first structure includes conductive polysilicon embedded in an insulator.

[0090] [Supplementary Note 1-13] The semiconductor device according to Supplementary Note 1-12 relating to Supplementary Note 1-2, wherein the potential of the conductive polysilicon is equal to or higher than the potential of the source region and equal to or lower than the potential of the drain region.

[0091] [Supplementary Note 1-14] The semiconductor device according to Supplementary Note 1-12 relating to Supplementary Note 1-2, wherein the conductive polysilicon is in an electrically floating state.

[0092] [Supplementary Note 1-15] The semiconductor device according to Supplementary Note 1-2, wherein all of the trench isolation structures include conductive polysilicon embedded in an insulator.

[0093] [Supplementary Note 1-16] The semiconductor device according to Supplementary Note 1-15, wherein the plurality of trench isolation structures form a potential gradient that decreases stepwise from the drain region side toward the source region side within a range of a potential difference between the drain region and the source region.

[0094] 1: Semiconductor device 2: Semiconductor chip 3: First main surface 4: Second main surface 5A: First side surface 5B: Second side surface 5C: Third side surface 5D: Fourth side surface 6: First layer 7: Second layer 8: Third layer 9: Element region 9A: Transistor region 10: Element isolation structure 11: Contact hole 12: Sinker layer 13: Element isolation trench 14: Element isolation insulating film 15: Element isolation electrode 16: Inner peripheral wall 17: Outer peripheral wall 18: Bottom wall 19: Contact region 20: First trench isolation structure 21: Second trench isolation structure 22: Shallow trench 23: Buried insulator 24: First region 25: Second region 26: Trench 27: Trench isolation structure 28 : Inner peripheral wall 29 : Outer peripheral wall 31 : Bottom wall 34 : Protrusion 35 : Recess 36 : Individual unit 37 : Buried line 38 : First structure 39 : Second structure 40 : Buried insulator 41 : Buried conductor 42 : First film portion 43 : Second film portion 44 : Recess 45 : Recess 46 : First portion 47 : Second portion 48 : Drift region 49 : Protrusion 50 : Drain region 51 : Drain contact region 52 : Body region 53 : Source region 54 : Body contact region 55 : Channel region 56 : Planar gate structure 57 : Gate insulating film 58 : Gate electrode 59 : Interlayer insulating film 60 : Drain wiring 61 : Source wiring 62 : Field plate wiring 63 : Drain contact 64: Source contact 65: Field plate contact 66: Semiconductor wafer 67: Hard mask 68: First opening 69: Second opening 70: Deep trench 71: Main trench 72: Sub-trench 73: Trench group 74: Semiconductor wall portion 75: First insulating film 76: Insulator wall portion 77: Buried insulating film 78: Second insulating film 79: Element isolation contact

Claims

1. a chip having a major surface; a trench that partitions the chip into a first region on one side and a second region on the other side in a cross-sectional view; a plurality of trench isolation structures covering sidewalls and a bottom wall of the trench, the plurality of trench isolation structures being integral with one another; a drift region of a first conductivity type formed along the sidewalls and the bottom wall of the trench inside the chip, the drift region providing a current path connecting the first region and the second region.

2. a drain region of a first conductivity type formed in a surface layer portion of the main surface so as to be electrically connected to the drift region on the first region side; a body region of a second conductivity type formed in a surface layer portion of the main surface so as to be electrically connected to the drift region on the second region side; a first conductivity type source region formed in a surface layer portion of the body region such that a channel region is formed between the source region and the drift region; 2. The semiconductor device according to claim 1, further comprising: a gate structure disposed on said main surface so as to overlap said channel region on said second region side.

3. a plurality of protrusions formed on the bottom wall of the trench and protruding from a lower end of the integrated trench insulation structure toward an interior upper portion of the trench insulation structure in a depth direction of the trench; 3. The semiconductor device according to claim 2, wherein each of said trench insulation structures is formed so as to extend upward in a depth direction of said trench from a region between adjacent said protrusions.

4. 4. The semiconductor device of claim 3, wherein at least one of said trench isolation structures includes a first structure including conductive polysilicon embedded into the depth of said trench.

5. The semiconductor device according to claim 4 , wherein the first structure is located closer to the second region than to a central portion between the first region and the second region.

6. 5. The semiconductor device according to claim 4, wherein, of said plurality of trench insulation structures, only said trench insulation structure at the outermost end on said second region side is said first structure.

7. At least one of the trench isolation structures includes a second structure including a buried insulating film buried in the depth direction of the trench; 5 . The semiconductor device according to claim 4 , wherein the second structure is formed in a larger proportion on the first region side than on the second region side with respect to a central portion between the first region and the second region.

8. 8. The semiconductor device according to claim 3, wherein the potential of said conductive polysilicon is equal to or higher than the potential of said source region and equal to or lower than the potential of said drain region.

9. 8. The semiconductor device according to claim 3, wherein the conductive polysilicon is in an electrically floating state.

10. 3. The semiconductor device of claim 2, wherein the plurality of trench isolation structures includes a first structure having a first width and a second structure having a second width less than the first width.

11. The semiconductor device according to claim 10 , wherein the first structure is formed biased toward the second region, and the second structure is formed biased toward the first region.

12. 12. The semiconductor device of claim 10 or 11, wherein the first structure comprises conductive polysilicon embedded in an insulator.

13. 13. The semiconductor device according to claim 12, wherein the potential of said conductive polysilicon is equal to or higher than the potential of said source region and equal to or lower than the potential of said drain region.

14. The semiconductor device according to claim 12 , wherein the conductive polysilicon is in an electrically floating state.

15. 3. The semiconductor device of claim 2, wherein all of said trench isolation structures comprise conductive polysilicon embedded in an insulator.

16. 16. The semiconductor device according to claim 15, wherein the plurality of trench isolation structures form a potential gradient that decreases stepwise from the drain region side toward the source region side within a range of a potential difference between the drain region and the source region.