Audio amplifier circuit and vehicle-mounted electronic device

Abstract

An audio amplifier circuit 200 receives power supply voltage VCC at a power supply terminal VCC. A voltage source 250 generates internal power supply voltage VREGA obtained by multiplying the power supply voltage VCC by a first gain, and bias voltage VFIL obtained by multiplying the power supply voltage VCC by a second gain. An input gain circuit 210 amplifies an analog audio signal with the bias voltage VFIL as a reference. The input gain circuit 210 has an input stage 214 and a gain stage 216. A phase compensation capacitor C21 is connected to the gain stage 216. A withstand voltage protection circuit 212 clamps output voltage VM of the gain stage 216 at a predetermined clamp voltage VCL.

Description

Audio amplifier circuits, automotive electronic devices

[0001] The present disclosure relates to audio circuits.

[0002] In-vehicle audio systems and car navigation systems include audio circuits, which often use class D amplifiers, which are capable of highly efficient operation, in their amplification stages.

[0003] 1 is a simplified block diagram of a class-D audio amplifier circuit 1. The class-D audio amplifier circuit 1 has a two-stage configuration: a first stage including an input gain circuit 10, and a second stage including a PWM circuit 20, a driver circuit 30, and an output stage 40. The output stage 40 is connected to a speaker 3 via a filter 2. The PWM circuit 20 includes an integrator 22, an oscillator 24, and a PWM comparator 26.

[0004] Assume that the input gain circuit 10 in the preceding stage is configured with 5V-based elements. This means that the amplitude of the output signal from the input gain circuit 10 is a maximum of 5V, meaning that the gain of the input gain circuit 10 is low. The integrator 22 of the PWM circuit 20 includes an operational amplifier OA1, resistors Ri and Rfb, and a capacitor Cfb. Because the capacitance value that can be built into an LSI cannot be large, the resistance values ​​of the resistors Ri and Rfb must be large. As a result, the thermal noise of resistors with large resistance values ​​becomes dominant, making it difficult to reduce noise.

[0005] The gain of the integrator 22 needs to be determined according to the withstand voltage (5 V) of the preceding block and the power supply voltage Vcc. If the gain of the input gain circuit 10 is small, the gain of the integrator 22 needs to be increased. In other words, the thermal noise of the resistors Ri and Rfb is amplified by the integrator 22. Patent Document 1 proposes a method of improving characteristics by increasing the withstand voltage of the preceding stage of the integrator.

[0006] Japanese Patent Application Laid-Open No. 2021-072551

[0007] The present disclosure has been made in this context, and one of its exemplary purposes is to improve the characteristics of an audio amplifier circuit.

[0008] An aspect of the present disclosure relates to an audio amplifier circuit, the audio amplifier circuit including a power supply terminal for receiving a power supply voltage, a power supply node to which the power supply voltage is supplied, an internal power supply voltage obtained by multiplying the power supply voltage by a first gain, and a bias voltage V 1 obtained by multiplying the power supply voltage by a second gain. ＦＩＬ and a voltage source that generates a bias voltage V ＦＩＬ The input gain circuit includes an input gain circuit that amplifies an analog audio signal based on a reference voltage V, a pulse modulator that receives an internal power supply voltage at a power supply node and generates a pulse signal having a pulse width corresponding to the output signal of the input gain circuit, and a driver that amplifies the pulse signal. The input gain circuit includes an operational amplifier having an input stage and a gain stage, a phase compensation capacitor connected to the gain stage, and a driver that amplifies the pulse signal. ＣＬ and a voltage protection circuit that clamps the voltage at

[0009] Any combination of the above elements, or mutual substitution of elements or expressions between methods, devices, systems, etc., are also valid aspects of the present invention or the present disclosure. Furthermore, the description in this section (Means for Solving the Problems) does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention.

[0010] According to certain aspects of the present disclosure, the characteristics of an audio amplifier circuit can be improved.

[0011] FIG. 1 is a simplified block diagram of a Class D audio amplifier circuit. FIG. 2 is a circuit diagram of an in-car audio system including an audio amplifier circuit according to a first embodiment. FIG. 3 is a diagram showing input / output characteristics of a voltage source. FIG. 4 is a diagram showing a level diagram of the in-car audio system of FIG. 2. FIG. 5 is a diagram showing a level diagram of an input gain circuit according to the first embodiment. FIG. 6 is a circuit diagram showing a first configuration example of an operational amplifier and a voltage protection circuit. FIG. 7 is a circuit diagram showing a second configuration example of an operational amplifier and a voltage protection circuit. FIG. 8 is a diagram showing a level diagram of an input gain circuit according to a second embodiment. FIG. 9 is a circuit diagram showing a third configuration example of an operational amplifier and a voltage protection circuit. FIG. 10 is a circuit diagram showing a fourth configuration example of an operational amplifier and a voltage protection circuit. FIG. 11 is a circuit diagram showing a configuration example of a voltage source. FIG. 12 is a circuit diagram of an audio amplifier circuit according to a modified example.

[0012] (Summary of the Embodiments) A summary of some exemplary embodiments of the present disclosure will be provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows, and is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0013] The audio amplifier circuit according to one embodiment includes a power supply terminal for receiving a power supply voltage, a power supply node to which the power supply voltage is supplied, an internal power supply voltage obtained by multiplying the power supply voltage by a first gain, and a bias voltage V ＦＩＬ and a voltage source that generates a bias voltage V ＦＩＬThe input gain circuit includes an input gain circuit that amplifies an analog audio signal based on a reference voltage V, a pulse modulator that receives an internal power supply voltage at a power supply node and generates a pulse signal having a pulse width corresponding to the output signal of the input gain circuit, and a driver that amplifies the pulse signal. The input gain circuit includes an operational amplifier having an input stage and a gain stage, a phase compensation capacitor connected to the gain stage, and a driver that amplifies the pulse signal. ＣＬ and a voltage protection circuit that clamps the voltage at

[0014] In this embodiment, the input gain circuit is configured with elements having a breakdown voltage higher than 5V, and the amplitude of the output signal of the input gain circuit is configured to be sufficiently large. This allows the gain of the integrator to be reduced, and thermal noise to be reduced. On the other hand, if the amplitude of the output signal of the input gain circuit becomes large, the breakdown voltage of the phase compensation capacitor becomes an issue. Therefore, a clamp voltage V according to the breakdown voltage of the phase compensation capacitor is set. ＣＬ By adding a voltage protection circuit having a bias voltage V ＦＩＬ By appropriately setting the value of the voltage, the amplitude of the output signal of the input gain circuit can be increased within the range of the withstand voltage of the phase compensation capacitor.

[0015] In one embodiment, the input stage may have a P-type input. The voltage protection circuit may clamp the output voltage of the gain stage to a clamp voltage V ＣＬ It may be clamped so as not to exceed

[0016] In one embodiment, when α is a constant satisfying 0.9≦α≦1.1, V ＦＩＬ = α × V ＣＬ may be satisfied.

[0017] In one embodiment, the clamp voltage V ＣＬ is the bias voltage V ＦＩＬ The voltage protection circuit may be configured to prevent the output voltage of the gain stage from being clamped to a clamp voltage V ＣＬ may sink current from the output node of the gain stage.

[0018] In one embodiment, the voltage protection circuit includes a current source and a bias voltage VＦＩＬ and a first electrode of the first transistor that receives the signal and has a first electrode that is grounded; a resistor connected to a second electrode of the first transistor; and a current mirror circuit that includes an input transistor and an output transistor, the input transistor being inserted between the resistor and the current source and the output transistor being connected to an output node of the gain stage.

[0019] The voltage protection circuit may include a Zener diode connected between the ground line and the output node of the gain stage.

[0020] In one embodiment, the input stage may have an N-type input. The voltage protection circuit may clamp the output voltage of the gain stage so that it does not fall below a clamp voltage.

[0021] In one embodiment, when β is a constant satisfying 0.9≦β≦1.1, V ＦＩＬ =V ＲＥＧＡ -β×V ＣＬ may be satisfied.

[0022] In one embodiment, the clamp voltage V ＣＬ is the bias voltage V ＦＩＬ The voltage protection circuit may be configured to level-shift the output voltage of the gain stage to a clamp voltage V ＣＬ below which current may be sourced into the output node of the gain stage.

[0023] In one embodiment, the voltage protection circuit includes a power supply node receiving an internal power supply voltage, a current source, and a control electrode that supplies the bias voltage V ＦＩＬ and a first transistor receiving the signal and having a first electrode connected to a power supply node, a resistor connected to a second electrode of the first transistor, and a current mirror circuit including an input transistor and an output transistor, the input transistor being inserted between the resistor and the current source, and the output transistor being connected to an output node of the gain stage.

[0024] In one embodiment, the voltage protection circuit may include a power supply node that receives the internal power supply voltage, and a Zener diode connected between the power supply node and the output node of the gain stage.

[0025] In one embodiment, the first gain may be greater than 0.9.

[0026] In one embodiment, the voltage source includes a voltage divider circuit that divides the power supply voltage at a second voltage division ratio corresponding to the second gain, a linear regulator that receives the output voltage of the voltage divider circuit as a reference voltage and generates an internal power supply voltage, and a bias voltage V ＦＩＬ and a clamp circuit that clamps the voltage at the output node of the voltage divider circuit so that it does not exceed a predetermined voltage.

[0027] In one embodiment, the audio amplifier circuit may be monolithically integrated on a single semiconductor substrate. "Monolithically integrated" includes cases where all of the circuit components are formed on the semiconductor substrate, or where the main circuit components are monolithically integrated, and some resistors, capacitors, etc., may be provided outside the semiconductor substrate for adjusting circuit constants. By integrating the circuit on a single chip, the circuit area can be reduced and the characteristics of the circuit elements can be maintained uniformly.

[0028] (Embodiments) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0029] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their connection.

[0030] Similarly, "a state in which component C is connected (provided) between component A and component B" includes not only a case in which component A and component C, or component B and component C, are directly connected, but also a case in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0031] 2 is a circuit diagram of an in-vehicle audio system 100 including an audio amplifier circuit 200 according to embodiment 1. The in-vehicle audio system 100 includes an in-vehicle battery (hereinafter simply referred to as the battery) 102, a filter 104, a speaker 106, and the audio amplifier circuit 200.

[0032] The battery 102 has a rated battery voltage V ＢＡＴ The audio amplifier circuit 200 is a functional IC (Integrated Circuit) integrated on a single semiconductor substrate. ＣＣ as the battery voltage V ＢＡＴ The audio amplifier circuit 200 receives an input audio signal V from a sound source (not shown). ＡＵＤ receives the input audio signal V ＡＵＤ and drives a load, that is, a speaker 106. In this embodiment, the in-vehicle audio system 100 is configured as a single-ended circuit.

[0033] The audio amplifier circuit 200 receives an audio signal V from a sound source (not shown) via a coupling capacitor C22 at an input terminal IN. ＡＵＤ Furthermore, a speaker 106 is connected to an output terminal OUT of the audio amplifier circuit 200 via a filter 104.

[0034] The audio amplifier circuit 200 is a class D amplifier (switching amplifier) ​​that receives an input audio signal V ＡＵＤ The pulse drive signal V ＤＲＶ is an analog audio signal V in the audio band, with high frequency components removed by the filter 104. ＯＵＴis supplied to the speaker 106.

[0035] The power supply terminal VCC of the audio amplifier circuit 200 is connected to the battery 102 and supplies a power supply voltage V ＣＣ An external capacitor C31 is connected to the capacitor connection terminal FILA. ＤＲＶ is the power supply voltage V ＣＣ has an amplitude equal to

[0036] The audio amplifier circuit 200 includes an input gain circuit 210 , a PWM (Pulse Width Modulation) circuit 220 , a driver circuit 230 , an output stage 240 , and a voltage source 250 .

[0037] The power supply node VCC of the voltage source 250 is connected to the power supply voltage V ＣＣ The voltage source 250 supplies a power supply voltage V ＣＣ First gain K １ Internal power supply voltage V multiplied by ＲＥＧＡ and the power supply voltage V ＣＣ Second gain K ２ Bias voltage V multiplied by ＦＩＬ Furthermore, the voltage source 250 generates a power supply voltage V ＣＣ Third gain K ３ Bias voltage V multiplied by ＦＩＬＰ For example, the first gain K １ is 0.9 or more, and specifically, V ＣＣ When V = 14V, ＲＥＧＡ = 13V １ = 13 / 14.

[0038] The power supply node VCC of the input gain circuit 210 is connected to the internal power supply voltage V ＲＥＧＡ is supplied, and a bias voltage V ＦＩＬ The input gain circuit 210 receives the bias voltage V ＦＩＬ With the analog audio signal V ＡＵＤ The analog audio signal V ＡＵＤ The AC component of V ＳＩＧ When written as above, the input signal V ＩＮ is expressed by the following formula: ＩＮ =VＦＩＬ +V ＳＩＧ The gain of the input gain circuit 210 is g １ Then, the output signal V of the input gain circuit 210 Ｎ is expressed by the following formula: Ｎ = g １ ×V ＳＩＧ +V ＦＩＬ

[0039] The input gain circuit 210 includes resistors R21 to R23, an operational amplifier OA21, and a voltage protection circuit 212. The gain g １ is g １ = (R21 + R22) / R21.

[0040] The operational amplifier OA21 includes an input stage 214, a gain stage 216, an output stage 218, and a phase compensation capacitor C21. The phase compensation capacitor C21 is connected between the input and output of the gain stage 216. The configurations of the input stage 214, the gain stage 216, and the output stage 218 may each use known technology and are not particularly limited. The output stage 218 may be omitted.

[0041] The phase compensation capacitor C21 has a breakdown voltage Vbd determined by the device structure and the semiconductor manufacturing process. The breakdown voltage protection circuit 212 is connected to the output node of the gain stage 216, and is configured to protect the voltage across the phase compensation capacitor C21 from a predetermined threshold voltage V ＴＨ The output voltage V of the gain stage 216 is set to 0 so as not to exceed Ｍ at a predetermined clamp level V ＣＬ The voltage is clamped at a predetermined threshold voltage V ＴＨ is determined according to the breakdown voltage Vbd of the phase compensation capacitor C21.

[0042] The PWM circuit 220 is a feedback pulse modulator. The power supply node of the PWM circuit 220 receives an internal power supply voltage V ＲＥＧＡ The PWM circuit 220 is also supplied with a reference voltage V ＦＩＬＰ is entered.

[0043] The PWM circuit 220 receives the output signal V Ｎ A pulse signal S having a pulse width according to ＰＷＭThe PWM circuit 220 includes an integrator 222, a comparator 224, and an oscillator 226.

[0044] The integrator 222 receives the output signal V Ｎ and the driving pulse V ＤＲＶ The integrator 222 includes an operational amplifier 223, resistors Ri and Rfb, and a capacitor Cfb. The non-inverting input node of the integrator 222 receives a reference voltage V ＦＩＬＰ The integrator 222 functions as an error amplifier and converts the two voltages V Ｎ and V ＤＲＶ is the integral value (smoothed voltage) of the voltage obtained by dividing the voltage by the resistors Ri and Rf, and the reference voltage V ＦＩＬＰ This amplifies the error.

[0045] The comparator 224 detects the output voltage V ＥＲＲ is compared with the triangular wave periodic signal generated by the oscillator 226, and a pulse signal S ＰＷＭ The power supply voltage of the comparator 224 is the internal power supply voltage V ＲＥＧＤ Therefore, the pulse signal S ＰＷＭ The high level of ＲＥＧＤ and the pulse signal S ＰＷＭＰ The low level of V is 0V. ＲＥＧＤ = 5V.

[0046] The output stage 240 includes a high-side transistor M1 and a low-side transistor M2. The high-side transistor M1 is connected between a power supply terminal VCC and an output terminal OUT, and the low-side transistor M2 is connected between the output terminal OUT and a ground terminal GND.

[0047] The driver circuit 230 generates a pulse signal S ＰＷＭ In response to this, the output stage 240 is driven so that the high-side transistor M1 and the low-side transistor M2 are turned on in a complementary manner.

[0048] The above is the configuration of the audio amplifier circuit 200.

[0049] 3 is a diagram showing the input / output characteristics of the voltage source 250. The audio amplifier circuit 200 ＣＣ<V Ｒ The internal power supply voltage V ＲＥＧＡ and bias voltage V ＦＩＬ is V ＣＣ <V Ｒ Within the range of the power supply voltage V ＣＣ is proportional to V ＣＣ >V Ｒ In the range of the internal power supply voltage V ＲＥＧＡ and bias voltage V ＦＩＬ is clamped.

[0050] 4 is a level diagram of the in-vehicle audio system 100 of FIG. 2. In FIG. 4, the voltage V ＩＮ , the output signal V of the input gain circuit 210 Ｎ , PWM signal S ＰＷＭ , drive signal V ＤＲＶ , output voltage V ＯＵＴ is shown.

[0051] The input voltage V of the input gain circuit 210 ＩＮ is the bias level V ＦＩＬ to the audio signal V ＡＵＤ AC component V ＳＩＧ The input signal V of the input gain circuit 210 is a signal on which ＩＮ and the output signal V Ｎ The bias level of ＦＩＬ and the amplitude of the audio signal is １ Generally, the bias level V ＦＩＬ is the internal power supply voltage V ＲＥＧＡ Midpoint voltage V ＲＥＧＡ / 2, but in this embodiment, V ＦＩＬ ≠V ＲＥＧＡ / 2. Bias level V ＦＩＬ More on this later.

[0052] PWM signal S ＰＷＭ is the internal power supply voltage V ＲＥＧＤ is a pulse signal with a high level and a ground voltage GND (0 V) as a low level, and its duty cycle is Ｎ Specifically, V Ｎ =V ＦＩＬ When the PWM signal SＰＷＭＰ The duty cycle of V is 50%. Ｎ V ＦＩＬ When it becomes lower, the PWM signal S ＰＷＭＰ The duty cycle of V becomes higher than 50% and Ｎ V ＦＩＬ If it is higher, the duty cycle will be lower than 50%.

[0053] Drive signal V ＤＲＶ is the power supply voltage V ＣＣ is a pulse signal with a high level and a ground voltage GND (0 V) is a low level. ＤＲＶＰ The duty cycle of the PWM signal S ＰＷＭＰ is equal to the duty cycle of

[0054] Next, the bias voltage V ＦＩＬ 1, the relationship between the withstand voltage of the phase compensation capacitor C21 and the clamp voltage of the withstand voltage protection circuit 212 will be described. FIG. 5 is a diagram showing a level diagram of the input gain circuit 210 in the first embodiment.

[0055] 5 shows the output voltage V of the gain stage 216 of the input gain circuit 210. Ｍ Since the voltage gain of the output stage 218 of the input gain circuit 210 is substantially unity, the output voltage V Ｍ is the output voltage V of the input gain circuit 210 Ｎ It is considered to be equal to the voltage V Ｎ is the bias voltage V ＦＩＬ Since it is an AC signal centered on , the output voltage V of the gain stage 216 Ｍ The bias voltage V ＦＩＬ In FIG. 5, Vsig is assumed to be the maximum value that can be assumed.

[0056] As described above, the phase compensation capacitor C21 is connected between the input and output terminals of the gain stage 216. The input voltage of the gain stage 216, i.e., one end of the phase compensation capacitor C21, can be considered to be at a substantially constant level. When the input stage 214 is a P-type input, the input voltage of the gain stage 216 is a voltage near 0 V (actually 0.5 to 1 V), and when the input stage 214 is an N-type input, the input voltage of the gain stage 216 is a voltage near the internal power supply voltage V ＲＥＧＡ Nearby (actually V ＲＥＧＡ -0.5V to V ＲＥＧＡ In the first embodiment, the input voltage of the gain stage 216 is a voltage V close to 0 V. Ｌ Assume that the input voltage of the gain stage 216 is V ＲＥＧＡ The case where it is close to will be described later in the second embodiment.

[0057] On the other hand, the voltage at the other end of the phase compensation capacitor C21 is V Ｍ Therefore, the voltage V across the phase compensation capacitor C21 Ｃ２１ is V Ｍ -V Ｌ Considering the breakdown voltage Vbd of the phase compensation capacitor C21, the voltage V Ｍ The peak of V Ｌ +Vbd, the reliability of the phase compensation capacitor C21 is guaranteed. ＣＬ is V ＣＬ ≦V Ｌ +Vbd.

[0058] 0V to V ＣＬ In order to obtain the maximum amplitude in the range of V ＦＩＬ ≒V ＣＬ / 2. ＦＩＬ is V ＣＬ For example, by using a parameter α ranging from 0.9 to 1.1, V ＦＩＬ = α × V ＣＬ In other words, V ＣＬ / 2×0.9≦V ＦＩＬ ≦V ＣＬ / 2×1.1, the bias voltage V ＦＩＬ may be determined.

[0059] When α=1, that is, V ＦＩＬ =V ＣＬ When it is set to / 2, the voltage V Ｎ The maximum amplitude of V ＣＬ Therefore, V ＳＩＧ ×g １ ≦V ＣＬ The gain g of the input gain circuit 210 is set to １ It is sufficient to determine the following.

[0060] When α<1, that is, V ＦＩＬ <V ＣＬ When it is set to / 2, the voltage V Ｎ Maximum amplitude α×V ＣＬ Therefore, V ＳＩＧ ×g １ ≦α×V ＣＬ The gain g of the input gain circuit 210 is set to １ It is sufficient to determine the following.

[0061] When α>1, that is, V ＦＩＬ >V ＣＬ When it is set to / 2, the voltage V Ｎ Maximum amplitude of (2-α) × V ＣＬ Therefore, V ＳＩＧ ×g １ ≦(2−α)×V ＣＬ The gain g of the input gain circuit 210 is set to １ It is sufficient to determine the following.

[0062] The above is the configuration of the audio amplifier circuit 200.

[0063] According to this audio amplifier circuit 200, a large amplitude input audio signal V ＡＵＤ When this occurs, the voltage V between both ends of the phase compensation capacitor C21 Ｃ２１ This can protect the device from exceeding its withstand voltage.

[0064] Also, the gain g of the input gain circuit 210 １ Since the gain g of the PWM circuit 220 can be set to a large value, ２This allows the amplification factor of the thermal noise generated in the resistors Ri and Rfb of the PWM circuit 220 to be reduced, and the noise characteristics of the audio amplifier circuit 200 as a whole to be improved.

[0065] The present disclosure covers various devices and methods that can be understood as the block diagram or circuit diagram of Figure 2 or derived from the above description, and is not limited to a specific configuration. Below, more specific configuration examples and examples will be described not to narrow the scope of the present disclosure, but to aid in understanding and clarify the essence and operation of the present disclosure and the present invention.

[0066] 6 is a circuit diagram showing a first configuration example of the operational amplifier OA21 and the voltage protection circuit 212. The input stage 214 of the operational amplifier OA21 can be configured as a P-type input differential amplifier. PNP bipolar transistors Qp1 and Qp2 form a differential pair. NPN bipolar transistors Qn1 and Qn2 are current mirror circuit loads. A tail current source CS41 generates a tail current It.

[0067] The gain stage 216 includes transistors Q21 and Q22, a current source CS21, and a resistor R24. The transistor Q21 and the resistor R24 ​​form a source follower circuit. The current source CS21 generates a constant current Ic1.

[0068] The output stage 218 includes a current source CS51 and transistors Q51 to Q55.

[0069] The voltage protection circuit 212 protects the output voltage V Ｍ is the bias voltage V ＦＩＬ is shifted to a clamp level V by a predetermined voltage step ΔV to the high potential side. ＣＬ exceeds V, sinking current Is from the output node of gain stage 216. ＣＬ =V ＦＩＬ +ΔV

[0070] The voltage protection circuit 212 is connected to the output node of the gain stage 216. The voltage protection circuit 212 includes a current source CS31, a resistor R31, a transistor Q31, and a current mirror circuit CM31. The current source CS31 generates a constant current Ic2. The transistor Q31 is a PNP bipolar transistor, and has a control electrode (base) connected to a bias voltage V ＦＩＬ The resistor R31 is connected to the second electrode (emitter) of the transistor Q31.

[0071] The current mirror circuit CM31 includes transistors Q32 and Q33. The transistor Q32 on the input side of the current mirror circuit CM31 is inserted between the resistor R31 and the current source CS31. The output transistor Q33 of the current mirror circuit CM31 is connected to the output node of the gain stage 216.

[0072] In this voltage-resistance protection circuit 212, ΔV=2×Vbe+R31×Ic2, and the clamp level V ＣＬ is V ＣＬ =V ＦＩＬ +2×Vbe+R31×Ic2, where Vbe is the base-emitter voltage of the transistors Q31 and Q33, and R31×Ic2 is the voltage drop across the resistor R31.

[0073] The output voltage V of the gain stage 216 Ｍ is the clamp level V ＣＬ =V ＦＩＬ +2 × Vbe + R31 × Ic2, the current flowing through transistor Q22 decreases, and the voltage V Ｍ is clamped.

[0074] 7 is a circuit diagram showing a second example configuration of the operational amplifier OA21 and the voltage protection circuit 212. In the operational amplifier OA21, the output stage 218 is omitted, and the gain stage 216 also performs the function of the output stage 218. The input stage 214 has a configuration in which the bipolar transistors in FIG. 6 are replaced with MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and includes transistors Mp1, Mp2, Mn1, and Mn2, and a tail current source CS41.

[0075] The gain stage 216 includes a transistor M31 and a current source CS31. The transistor M31 is an N-channel MOSFET, and its source is grounded. The current source CS31 supplies a constant current to the transistor M31. A phase compensation capacitor C21 is connected between the input and output of the gain stage 216, i.e., between the gate and drain of the transistor M31.

[0076] The voltage protection circuit 212 includes a plurality of Zener diodes ZD1 and ZD2 connected in series. When the Zener diode voltage is Vz and the number of stages is n (2 in this example), the clamp level V ＣＬ is V ＣＬ = n × Vz.

[0077] In the configuration of Fig. 6, the bipolar transistors may be replaced with FETs, and in the configuration of Fig. 7, the FETs may be replaced with bipolar transistors.

[0078] In the second embodiment, the input stage 214 of the operational amplifier OA21 is an N-type input. When the input stage 214 is an N-type input, the input voltage of the gain stage 216 is an internal power supply voltage V ＲＥＧＡ Nearby (actually V ＲＥＧＡ -0.5V to V ＲＥＧＡ -1V) voltage V Ｈ This becomes:

[0079] 8 is a diagram showing a level diagram of the input gain circuit 210 in the second embodiment. In FIG. 8, the input voltage of the gain stage 216, i.e., the voltage at one end of the phase compensation capacitor C21, is ＲＥＧＡ High voltage V close to Ｈ The output voltage V of the gain stage 216 is Ｍ is the bias voltage V ＦＩＬ It is assumed that the signal is an AC signal centered on

[0080] The voltage V across the phase compensation capacitor C21 Ｃ２１ is V Ｈ -V Ｎ Considering the breakdown voltage Vbd of the phase compensation capacitor C21, the voltage V Ｎ The bottom is a V ＨIf the voltage V is higher than −Vbd, the reliability of the phase compensation capacitor C21 is guaranteed. ＣＬ is V ＣＬ ≧V Ｈ It is defined to be −Vbd.

[0081] 0V to V ＣＬ In order to obtain the maximum amplitude in the range of V ＦＩＬ ≒V ＲＥＧＡ -V ＣＬ / 2. ＦＩＬ is V ＲＥＧＡ -V ＣＬ It is not necessary for the voltage V to be exactly equal to / 2, but it may be shifted to the higher or lower potential side. For example, by using a parameter β ranging from 0.9 to 1.1, ＦＩＬ =V ＲＥＧＡ -β×V ＣＬ In other words, V ＲＥＧＡ -V ＣＬ / 2×1.1≦V ＦＩＬ ≦V ＲＥＧＡ -V ＣＬ / 2×0.9, the bias voltage V ＦＩＬ may be determined.

[0082] When β=1, that is, V ＦＩＬ =V ＲＥＧＡ -V ＣＬ When it is set to / 2, the voltage V Ｎ The maximum amplitude of V ＲＥＧＡ -V ＣＬ Therefore, V ＳＩＧ ×g １ ≦V ＲＥＧＡ -V ＣＬ The gain g of the input gain circuit 210 is set to １ It is sufficient to determine the following.

[0083] When β<1, that is, V ＦＩＬ >V ＲＥＧＡ -V ＣＬ When it is set to / 2, the voltage V Ｎ The maximum amplitude of (V ＲＥＧＡ -V ＦＩＬ ) x 2 = 2α・V ＣＬ Therefore, V ＳＩＧ ×g１ ≦2α・V ＣＬ The gain g of the input gain circuit 210 is set to １ It is sufficient to determine the following.

[0084] When β>1, that is, V ＦＩＬ <V ＲＥＧＡ -V ＣＬ When it is set to / 2, the voltage V Ｎ The maximum amplitude of V ＦＩＬ × 2 = 2 × (V ＲＥＧＡ -α×V ＣＬ ) V ＳＩＧ ×g １ ≦2×(V ＲＥＧＡ -α×V ＣＬ ) so that the gain g of the input gain circuit 210 is １ It is sufficient to determine the following.

[0085] 9 is a circuit diagram showing a third example of the configuration of the operational amplifier OA21 and the voltage protection circuit 212. The operational amplifier OA21 has an N-type input. This is the same as the configuration in FIG. 6, but with the polarity of the transistors reversed.

[0086] The voltage protection circuit 212 has a configuration in which the voltage protection circuit 212 in FIG. Ｍ is the bias voltage V ＦＩＬ is shifted to a clamp level V by a predetermined voltage width ΔV to the low potential side. ＣＬ , it sources current to the output node of gain stage 216. ＣＬ =V ＦＩＬ -ΔV ΔV=2×Vbe+R31×Ic2

[0087] 10 is a circuit diagram showing a fourth example of the configuration of the operational amplifier OA21 and the withstand voltage protection circuit 212. Fig. 10 is an inverted version of the configuration of Fig. 7. The withstand voltage protection circuit 212 Ｍ is the internal power supply voltage V ＲＥＧＡ The clamp level V is shifted by a predetermined width ΔV in the lower voltage direction. ＣＬ The output voltage V Ｍ Clamp V ＣＬ =V ＲＥＧＡ −n×Vz

[0088] Next, an example of the configuration of the voltage source 250 will be described.

[0089] 11 is a circuit diagram showing an example of the configuration of the voltage source 250. The voltage source 250 includes a voltage dividing circuit 252, a linear regulator 254, a buffer 256, and a clamping circuit 260. The voltage dividing circuit 252 divides the power supply voltage V ＣＣ The output node of the voltage dividing circuit 252 is connected to the capacitor connection terminal FILA. The voltage dividing circuit 252 includes resistors R11 and R12. The voltage V at the output node of the voltage dividing circuit 252 is ＦＩＬＡ is V ＦＩＬＡ =V ＣＣ ×R12 / (R11+R12) The buffer 256 outputs the voltage V ＦＩＬＡ , the bias voltage V ＦＩＬ That is, the gain g ２ is the voltage division ratio R12 / (R11+R12) of the voltage divider circuit 252. ＦＩＬ =V ＦＩＬＡ = g ２ ×V ＣＣ g ２ =R12 / (R11+R12)

[0090] The linear regulator 254 converts the output voltage V ＦＩＬＡ is received as a reference voltage, and the internal power supply voltage V ＲＥＧＡ The linear regulator 254 includes an operational amplifier OA11, resistors R13 and R14, and a transistor M13. The input / output characteristics of the linear regulator 254 are as follows: ＲＥＧＡ = (R13 x R14) / R14 x V ＦＩＬＡ = (R13 x R14) / R14 x g ２ ×V ＣＣ Therefore, g １ = (R13 x R14) / R14 x g ２ It is sufficient to satisfy the above.

[0091] The clamp circuit 260 clamps the voltage V ＦＩＬＡ at a predetermined level g ２ ×V Ｒ This clamps the input / output characteristics shown in Figure 3.

[0092] (Modifications) The above-described embodiment is merely an example, and it will be understood by those skilled in the art that various modifications are possible in the combination of the components and the processing steps. These modifications will be described below.

[0093] In the embodiment, the audio amplifier circuit 200 is configured as a single-ended circuit, but it may also be configured as a differential circuit.

[0094] 12 is a circuit diagram of an audio amplifier circuit 200A according to a modified example. The audio amplifier circuit 200A receives a differential audio signal V ＩＮＮ , V ＩＮＰ is input. In-vehicle audio system 100A is of a fully differential type, and input gain circuit 210, PWM circuit 220, driver circuit 230, and output stage 240 are provided on the P side and N side. Note that the polarity of the signal is inverted in PWM circuit 220, so that an N polarity signal is input to the block corresponding to P side output OUTP, and a P polarity signal is input to the block corresponding to N side output OUTN.

[0095] (Additional Note) The following techniques are disclosed in this specification.

[0096] (Item 1) An audio amplifier circuit, comprising: a power supply terminal for receiving a power supply voltage; a power supply node to which the power supply voltage is supplied; an internal power supply voltage obtained by multiplying the power supply voltage by a first gain; and a bias voltage V obtained by multiplying the power supply voltage by a second gain. ＦＩＬ a voltage source that generates the internal power supply voltage V; ＦＩＬ an input gain circuit for amplifying an analog audio signal based on a reference voltage V; a pulse modulator for receiving the internal power supply voltage at a power supply node and generating a pulse signal having a pulse width according to an output signal of the input gain circuit; and a driver for amplifying the pulse signal, wherein the input gain circuit comprises an operational amplifier having an input stage and a gain stage; a phase compensation capacitor connected to the gain stage; and a driver for amplifying the output voltage of the gain stage by adjusting the output voltage of the gain stage to a predetermined clamp voltage V. ＣＬ and a voltage protection circuit that clamps the output voltage at a voltage above 100 V.

[0097] (Item 2) The input stage has a P-type input, and the voltage protection circuit controls the output voltage of the gain stage to the clamp voltage V ＣＬ 2. The audio amplifier circuit of claim 1, wherein the amplifier clamps the input signal so as not to exceed

[0098] (Item 3) When α is a constant that satisfies 0.9≦α≦1.1, V ＦＩＬ = α × V ＣＬ 3. The audio amplifier circuit according to item 2, which satisfies the above.

[0099] (Item 4) The clamp voltage V ＣＬ is the bias voltage V ＦＩＬ is a voltage obtained by level-shifting the output voltage of the gain stage to the high potential side, and the voltage protection circuit ＣＬ 4. The audio amplifier circuit of claim 2, wherein the amplifier sinks current from the output node of the gain stage when

[0100] (Item 5) The withstand voltage protection circuit includes a current source and a control electrode that supplies the bias voltage V ＦＩＬ and a first electrode of the first transistor connected to ground; a resistor connected to a second electrode of the first transistor; and a current mirror circuit including an input transistor and an output transistor, the input transistor being inserted between the resistor and the current source, and the output transistor being connected to an output node of the gain stage.

[0101] (Item 6) The audio amplifier circuit according to item 2 or 3, wherein the voltage protection circuit includes a Zener diode connected between a ground line and an output node of the gain stage.

[0102] (Item 7) The audio amplifier circuit according to item 1, wherein the input stage has an N-type input, and the voltage protection circuit clamps the output voltage of the gain stage so that it does not fall below a clamp voltage.

[0103] (Item 8) When β is a constant that satisfies 0.9≦β≦1.1, V ＦＩＬ =V ＲＥＧＡ -β×V ＣＬ8. The audio amplifier circuit according to item 7, which satisfies the above.

[0104] (Item 9) The clamp voltage V ＣＬ is the bias voltage V ＦＩＬ is a voltage obtained by level-shifting the output voltage of the gain stage to a low potential side, and the voltage protection circuit ＣＬ 9. The audio amplifier circuit of claim 7, wherein the circuit sources current to the output node of the gain stage when the input voltage Vout falls below .

[0105] (Item 10) The voltage protection circuit includes a power supply node that receives the internal power supply voltage, a current source, and a control electrode that supplies the bias voltage V ＦＩＬ and a first transistor receiving the signal and having a first electrode connected to the power supply node; a resistor connected to a second electrode of the first transistor; and a current mirror circuit including an input transistor and an output transistor, the input transistor being inserted between the resistor and the current source, and the output transistor being connected to an output node of the gain stage.

[0106] (Item 11) The audio amplifier circuit according to item 7 or 8, wherein the voltage protection circuit includes: a power supply node that receives the internal power supply voltage; and a Zener diode connected between the power supply node and an output node of the gain stage.

[0107] (Item 12) The audio amplifier circuit according to any one of Items 1 to 5, wherein the first gain is greater than 0.9.

[0108] (Item 13) The voltage source includes: a voltage divider circuit that divides the power supply voltage at a second voltage division ratio corresponding to the second gain; a linear regulator that receives an output voltage of the voltage divider circuit as a reference voltage and generates the internal power supply voltage; and a linear regulator that receives an output voltage of the voltage divider circuit as a reference voltage and generates the bias voltage V ＦＩＬ and a clamp circuit that clamps the voltage at the output node of the voltage divider circuit so that it does not exceed a predetermined voltage.

[0109] (Item 14) The audio amplifier circuit according to any one of items 1 to 13, which is monolithically integrated on a single semiconductor substrate.

[0110] (Item 15) An in-vehicle electronic device comprising the audio amplifier circuit according to any one of items 1 to 14.

[0111] The present disclosure relates to audio circuits.

[0112] 100 In-vehicle audio system 102 Battery 104 Filter 106 Speaker 200 Audio amplifier circuit 210 Input gain circuit 212 Withstand voltage protection circuit 214 Input stage 216 Gain stage 218 Output stage C21 Phase compensation capacitor CS31 Current source R31 Resistor Q31, Q32, Q33 Transistor CM31 Current mirror circuit 220 PWM circuit 222 Integrator 224 Comparator 226 Oscillator 230 Driver circuit 240 Output stage M1 High-side transistor M2 Low-side transistor 250 Voltage source 252 Voltage divider circuit 254 Linear regulator 256 Buffer 260 Clamp circuit

Claims

1. 1. An audio amplifier circuit, comprising: a power supply terminal for receiving a power supply voltage; The power supply voltage is supplied to a power supply node, and an internal power supply voltage obtained by multiplying the power supply voltage by a first gain and a bias voltage V ＦＩＬ A voltage source generating The internal power supply voltage is supplied to a power supply node, and the bias voltage V ＦＩＬ an input gain circuit for amplifying an analog audio signal based on a pulse modulator that receives the internal power supply voltage at a power supply node and generates a pulse signal having a pulse width corresponding to an output signal of the input gain circuit; A driver that amplifies the pulse signal; Equipped with The input gain circuit includes: an operational amplifier having an input stage and a gain stage; a phase compensation capacitor connected to the gain stage; The output voltage of the gain stage is clamped to a predetermined voltage V ＣＬ A voltage protection circuit that clamps the 2. An audio amplifier circuit comprising:

2. the input stage having a P-type input; The voltage protection circuit controls the output voltage of the gain stage to the clamp voltage V ＣＬ 2. The audio amplifier circuit of claim 1, wherein the amplifier is configured to clamp the input signal so as not to exceed

3. When α is a constant satisfying 0.9≦α≦1.1, V ＦＩＬ =α×V ＣＬ 3. The audio amplifier circuit according to claim 2, wherein

4. The clamp voltage V ＣＬ is the bias voltage V ＦＩＬ is a voltage level-shifted to the high potential side, The voltage protection circuit is configured to protect the output voltage of the gain stage from the clamp voltage V ＣＬ 4. An audio amplifier circuit as claimed in claim 2 or 3, which sinks current from the output node of the gain stage when

5. The voltage protection circuit includes: A current source; The bias voltage V ＦＩＬ a first transistor receiving the signal and having a first electrode grounded; a resistor connected to the second electrode of the first transistor; a current mirror circuit including an input transistor and an output transistor, the input transistor being inserted between the resistor and the current source, and the output transistor being connected to an output node of the gain stage; 4. An audio amplifier circuit as claimed in claim 2 or 3, comprising:

6. 4. The audio amplifier circuit according to claim 2, wherein the voltage protection circuit includes a Zener diode connected between a ground line and an output node of the gain stage.

7. the input stage having an N-type input; 2. The audio amplifier circuit according to claim 1, wherein the voltage protection circuit clamps the output voltage of the gain stage so that it does not fall below a clamp voltage.

8. When β is a constant satisfying 0.9≦β≦1.1, V ＦＩＬ =V ＲＥＧＡ -β×V ＣＬ 8. The audio amplifier circuit according to claim 7, wherein

9. The clamp voltage V ＣＬ is the bias voltage V ＦＩＬ is a voltage level-shifted to the low potential side, The voltage protection circuit includes: The output voltage of the gain stage is the clamp voltage V ＣＬ 9. An audio amplifier circuit as claimed in claim 7 or 8, further comprising: a gain stage that sources current into an output node of the gain stage when

10. The voltage protection circuit includes: a power supply node for receiving the internal power supply voltage; A current source; The bias voltage V ＦＩＬ a first transistor receiving the first input and having a first electrode connected to the power supply node; a resistor connected to the second electrode of the first transistor; a current mirror circuit including an input transistor and an output transistor, the input transistor being inserted between the resistor and the current source, and the output transistor being connected to an output node of the gain stage; 9. An audio amplifier circuit as claimed in claim 7 or 8, comprising:

11. The voltage protection circuit includes: a power supply node for receiving the internal power supply voltage; a Zener diode connected between the power supply node and an output node of the gain stage; 9. An audio amplifier circuit as claimed in claim 7 or 8, comprising:

12. 4. The audio amplifier circuit according to claim 1, wherein the first gain is greater than 0.

9.

13. The voltage source is a voltage divider circuit that divides the power supply voltage by a second voltage division ratio corresponding to the second gain; a linear regulator that receives the output voltage of the voltage divider circuit as a reference voltage and generates the internal power supply voltage; The output voltage of the voltage divider circuit is received as a reference voltage, and the bias voltage V ＦＩＬ and a buffer that outputs a clamp circuit that clamps the voltage at the output node of the voltage divider circuit so that it does not exceed a predetermined voltage; 4. An audio amplifier circuit as claimed in claim 1, comprising:

14. 4. The audio amplifier circuit according to claim 1, which is monolithically integrated on a single semiconductor substrate.

15. An in-vehicle electronic device comprising the audio amplifier circuit according to any one of claims 1 to 3.