Semiconductor device

Abstract

A semiconductor device according to the present invention comprises a first semiconductor element, a second semiconductor element, first to third power terminals, first and second signal terminals, and a sealing resin. The first power terminal and the first signal terminal are electrically connected to the first semiconductor element. The second power terminal and the second signal terminal are electrically connected to the second semiconductor element. The third power terminal is electrically connected to the first semiconductor element and the second semiconductor element. The sealing resin has a first lateral surface and a second lateral surface, which face opposite directions in a second direction. The first power terminal and the second power terminal protrude from the first lateral surface. The third power terminal protrudes from the second lateral surface. The first power terminal and the second power terminal are separated from each other in a third direction.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Patent Document 1 discloses an example of a semiconductor device equipped with two power semiconductor elements (e.g., IGBTs). The semiconductor device is used in a power conversion device such as an inverter. The semiconductor device is surface-mounted on a wiring board.

[0003] The semiconductor device disclosed in Patent Document 1 includes multiple power supply terminals and multiple control terminals. The multiple power supply terminals and multiple control terminals protrude from a housing that encases two power semiconductor elements. The portion of each of these terminals that protrudes from the housing is bent into a gull-wing shape to enable surface mounting. However, attempts to miniaturize the semiconductor device require further reduction in the spacing between the multiple power supply terminals. Meanwhile, the semiconductor device has parasitic inductance. Therefore, there is concern that mutual induction between a terminal through which AC current flows and an adjacent terminal through which DC current flows may increase power loss in the terminal through which DC current flows.

[0004] Japanese Patent Application Laid-Open No. 2012-244176

[0005] An object of the present disclosure is to provide a semiconductor device that is improved over conventional semiconductor devices. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that can reduce the parasitic inductance of the device while also achieving miniaturization of the device.

[0006] A first aspect of the present disclosure provides a semiconductor device comprising: a first semiconductor element; a second semiconductor element; a first power terminal and a first signal terminal electrically connected to the first semiconductor element; a second power terminal and a second signal terminal electrically connected to the second semiconductor element; a third power terminal electrically connected to the first semiconductor element and the second semiconductor element; and a sealing resin covering the first semiconductor element and the second semiconductor element. The sealing resin has a bottom surface facing a first direction and a first side surface and a second side surface facing opposite each other in a second direction perpendicular to the first direction. Each of the first power terminal, the second power terminal, and the third power terminal has a first mounting surface facing the same side as the bottom surface in the first direction. Each of the first signal terminal and the second signal terminal has a second mounting surface facing the same side as the bottom surface in the first direction. The first mounting surface and the second mounting surface are positioned closer to the bottom surface than to the first semiconductor element and the second semiconductor element in the first direction. The first power terminal and the second power terminal protrude from the first side surface, the third power terminal protrudes from the second side surface, the first signal terminal and the second signal terminal each protrude from either the first side surface or the second side surface, and the first power terminal and the second power terminal are spaced apart from each other in a third direction perpendicular to the first direction and the second direction.

[0007] According to the above configuration, it is possible to reduce the parasitic inductance in the semiconductor device while also miniaturizing the semiconductor device.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1. FIG. 3 is a bottom view corresponding to FIG. 2, seen through the sealing resin. FIG. 4 is a front view of the semiconductor device shown in FIG. 1. FIG. 5 is a rear view of the semiconductor device shown in FIG. 1. FIG. 6 is a right side view of the semiconductor device shown in FIG. 1. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 2. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 2. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 2. FIG. 10 is a partially enlarged view of FIG. 7. FIG. 11 is a plan view of a semiconductor device according to a second embodiment of the present disclosure. FIG. 12 is a bottom view of the semiconductor device shown in FIG. 11. FIG. 13 is a bottom view corresponding to FIG. 12, seen through the sealing resin. FIG. 14 is a front view of the semiconductor device shown in FIG. 11. FIG. 15 is a rear view of the semiconductor device shown in FIG. 11. FIG. 16 is a plan view of a semiconductor device according to a third embodiment of the present disclosure. 17 is a bottom view of the semiconductor device shown in FIG. 16 . FIG. 18 is a bottom view corresponding to FIG. 17 , seen through the sealing resin. FIG. 19 is a front view of the semiconductor device shown in FIG. 16 . FIG. 20 is a rear view of the semiconductor device shown in FIG. 16 . FIG. 21 is a plan view of a semiconductor device according to a fourth embodiment of the present disclosure. FIG. 22 is a bottom view of the semiconductor device shown in FIG. 21 . FIG. 23 is a front view of the semiconductor device shown in FIG. 21 . FIG. 24 is a rear view of the semiconductor device shown in FIG. 21 . FIG. 25 is a right side view of the semiconductor device shown in FIG. 21 . FIG. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. 22 . FIG. 27 is a plan view of a semiconductor device according to a fifth embodiment of the present disclosure. FIG. 28 is a bottom view of the semiconductor device shown in FIG. 27 . FIG. 29 is a plan view of a semiconductor device according to a sixth embodiment of the present disclosure. FIG. 30 is a bottom view of the semiconductor device shown in FIG. 29 .

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0011] First Embodiment: A semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 10 . The semiconductor device A10 is used in electronic devices equipped with a power conversion circuit such as an inverter. The semiconductor device A10 includes a support member 10, two semiconductor elements 20, a plurality of power terminals 30, a plurality of first signal terminals 31, a plurality of second signal terminals 32, two conductive members 40, two gate wires 41, two detection wires 42, and a sealing resin 50. For ease of understanding, FIG. 3 shows the sealing resin 50 in a see-through view. In FIG. 3 , the outline of the sealing resin 50 is indicated by an imaginary line (a two-dot chain line).

[0012] In the description of the semiconductor device A10, for convenience, the normal direction to the bottom surface 52 of the sealing resin 50 (described later) will be referred to as the "first direction z." One direction perpendicular to the first direction z will be referred to as the "second direction x." A direction perpendicular to both the first direction z and the second direction x will be referred to as the "third direction y."

[0013] The semiconductor device A10 converts a DC power supply voltage applied to a first power terminal 30A and a second power terminal 30B (see FIGS. 1 and 2) of the plurality of power terminals 30 into AC power using two semiconductor elements 20. The converted AC power is input to a power supply target such as a motor from a third power terminal 30C (see FIGS. 1 and 2) of the plurality of power terminals 30. The semiconductor device A10 is surface-mounted on a wiring board.

[0014] As shown in FIGS. 2 , 7 , and 8 , the sealing resin 50 covers the two semiconductor elements 20. Furthermore, the sealing resin 50 covers the support member 10, the two conductive members 40, the two gate wires 41, and the two detection wires 42, excluding the heat dissipation layer 16. The sealing resin 50 has electrical insulation properties. The sealing resin 50 is made of a material containing, for example, black epoxy resin. As shown in FIGS. 1 and 2 , the sealing resin 50 has a top surface 51, a bottom surface 52, a first side surface 53, a second side surface 54, and two third side surfaces 55. The outer edge 501 shown in FIG. 1 corresponds to the outline of the sealing resin 50 when viewed in the first direction z.

[0015] As shown in FIGS. 4 to 9, the top surface 51 and the bottom surface 52 face in opposite directions in the first direction z.

[0016] 1, 2, and 6, the first side surface 53 and the second side surface 54 face opposite each other in the second direction x. The first side surface 53 and the second side surface 54 are connected to the top surface 51 and the bottom surface 52. Each of the first side surface 53 and the second side surface 54 includes a region that is connected to the bottom surface 52 and faces the second direction x, and a region that is connected to the top surface 51 and is inclined with respect to the top surface 51.

[0017] 1 , 2 , 4 , and 5 , the two third side surfaces 55 face opposite each other in the third direction y. The two third side surfaces 55 are connected to the top surface 51 and the bottom surface 52. Each of the two third side surfaces 55 includes a region that is connected to the bottom surface 52 and faces the third direction y, and a region that is connected to the top surface 51 and is inclined with respect to the top surface 51.

[0018] 3 and 9, the support member 10 has two semiconductor elements 20 mounted thereon. As shown in FIGS. 1 and 3, the support member 10 has an insulating layer 11, a first conductive layer 12, a second conductive layer 13, a third conductive layer 14, a plurality of pad layers 15, and a heat dissipation layer 16.

[0019] 1 and 3, the insulating layer 11 is located between the first conductive layer 12 and the second conductive layer 13 and the heat dissipation layer 16 in the first direction z. The material of the insulating layer 11 preferably has a relatively high thermal conductivity. Therefore, the insulating layer 11 is made of a material containing aluminum nitride (AlN), for example. As shown in FIGS. 7 to 9, the end of the insulating layer 11 in a direction perpendicular to the first direction z is sandwiched between the sealing resin 50 in the first direction z.

[0020] As shown in FIGS. 1 and 3 , the first conductive layer 12, the second conductive layer 13, the third conductive layer 14, and the multiple pad layers 15 are located on the opposite side of the insulating layer 11 from the heat dissipation layer 16 in the first direction z. The first conductive layer 12 and the second conductive layer 13 are located between the two semiconductor elements 20 and the insulating layer 11 in the first direction z. Each of the first conductive layer 12, the second conductive layer 13, the third conductive layer 14, and the multiple pad layers 15 is electrically connected to at least one of the two semiconductor elements 20. The first conductive layer 12, the second conductive layer 13, the third conductive layer 14, and the multiple pad layers 15 contain copper (Cu). The first conductive layer 12 is located on one side in the third direction y. The second conductive layer 13 is located adjacent to the first conductive layer 12 in the third direction y. The third conductive layer 14 is sandwiched between the first conductive layer 12 and the second conductive layer 13 in the third direction y. The pad layers 15 are located on the opposite side of the third conductive layer 14 in the second direction x with respect to the first conductive layer 12 and the second conductive layer 13. The pad layers 15 are arranged along the third direction y.

[0021] 9, the heat dissipation layer 16 is located on the opposite side of the insulating layer 11 from the first conductive layer 12 and the second conductive layer 13 in the first direction z. The heat dissipation layer 16 is exposed from a top surface 51 of the sealing resin 50. The heat dissipation layer 16 contains copper. As shown in FIG. 1, the heat dissipation layer 16 overlaps the entirety of each of the two semiconductor elements 20.

[0022] As shown in FIG. 9 , the two semiconductor elements 20 are positioned between the bottom surface 52 of the sealing resin 50 and the support member 10 in the first direction z. As shown in FIGS. 3 and 9 , the two semiconductor elements 20 are individually conductively bonded to the first conductive layer 12 and the second conductive layer 13 of the support member 10 via bonding layers 29. The bonding layers 29 are, for example, solder. Alternatively, the bonding layers 29 may be sintered metal containing silver (Ag). In the semiconductor device A10, the two semiconductor elements 20 are n-channel, vertical-structure metal-oxide-semiconductor field-effect transistors (MOSFETs). The two semiconductor elements 20 include compound semiconductor substrates. The main material of the compound semiconductor substrate is silicon carbide (SiC). Alternatively, silicon (Si) may be used as the main material of the compound semiconductor substrate. Alternatively, the two semiconductor elements 20 may be other switching elements such as IGBTs (Insulated Gate Bipolar Transistors). Furthermore, the number of semiconductor elements 20 in the semiconductor device A10 is an example, and the number can be set freely.

[0023] 10 , each of the two semiconductor elements 20 has a first electrode 21, a second electrode 22, and a gate electrode 23. The first electrode 21 is provided opposite either the first conductive layer 12 or the second conductive layer 13 of the support member 10. A current corresponding to the power before being converted by the semiconductor element 20 flows through the first electrode 21. In other words, the first electrode 21 corresponds to a drain electrode.

[0024] 10 , the second electrode 22 is provided on the opposite side of the first electrode 21 in the first direction z. A current corresponding to the power converted by the semiconductor element 20 flows through the second electrode 22. In other words, the second electrode 22 corresponds to a source electrode.

[0025] 10 , the gate electrode 23 is provided on the opposite side of the first electrode 21 in the first direction z and is located away from the second electrode 22. A gate voltage for driving the semiconductor element 20 is applied to the gate electrode 23. As shown in FIG. 3 , the area of ​​the gate electrode 23 is smaller than the area of ​​the second electrode 22 when viewed in the first direction z.

[0026] 3 and 9 , the two semiconductor elements 20 include a first semiconductor element 20A and a second semiconductor element 20B. The first electrode 21 of the first semiconductor element 20A is conductively bonded to the first conductive layer 12 of the support member 10 via a bonding layer 29. This provides electrical continuity between the first semiconductor element 20A and the first conductive layer 12. The first electrode 21 of the second semiconductor element 20B is conductively bonded to the second conductive layer 13 via the bonding layer 29. This provides electrical continuity between the second semiconductor element 20B and the second conductive layer 13.

[0027] 7 and 8 , the power terminals 30, the first signal terminals 31, and the second signal terminals 32 are located between the bottom surface 52 of the sealing resin 50 and the support member 10 in the first direction z. As shown in FIG. 2 , the power terminals 30, the first signal terminals 31, and the second signal terminals 32 are exposed from the bottom surface 52.

[0028] 1 , when viewed in the first direction z, each of the multiple power terminals 30, each of the multiple first signal terminals 31, and each of the multiple second signal terminals 32 intersects with an outer edge 501 of the sealing resin 50. When viewed in the first direction z, each of the multiple power terminals 30, each of the multiple first signal terminals 31, and each of the multiple second signal terminals 32 protrudes from the support member 10. The multiple power terminals 30, the multiple first signal terminals 31, and the multiple second signal terminals 32 contain copper. In the semiconductor device A10, the multiple power terminals 30, the multiple first signal terminals 31, and the multiple second signal terminals 32 are metal leads.

[0029] As shown in FIGS. 1 to 3 , the multiple power terminals 30 include a first power terminal 30A, a second power terminal 30B, and a third power terminal 30C. As shown in FIGS. 2 , 7 , and 8 , the first power terminal 30A and the second power terminal 30B protrude from a first side surface 53 of the sealing resin 50. As shown in FIG. 2 , the third power terminal 30C protrudes from a second side surface 54 of the sealing resin 50. The first power terminal 30A and the second power terminal 30B are located on opposite sides of the third power terminal 30C relative to the two semiconductor elements 20 in the second direction x. The first power terminal 30A and the second power terminal 30B are spaced apart from each other in the third direction y. In the semiconductor device A10, the second power terminal 30B is located next to the first power terminal 30A in the third direction y.

[0030] As shown in Figures 3 and 7, the first power terminal 30A is conductively bonded to the first conductive layer 12 of the support member 10. This provides electrical continuity between the first power terminal 30A and the first semiconductor element 20A. As shown in Figures 3 and 8, the second power terminal 30B is conductively bonded to the third conductive layer 14 of the support member 10. As shown in Figure 3, the third power terminal 30C is conductively bonded to the second conductive layer 13 of the support member 10. This provides electrical continuity between the third power terminal 30C and the second semiconductor element 20B.

[0031] As shown in FIGS. 1 to 3 , the multiple first signal terminals 31 are located on the opposite side of the multiple second signal terminals 32 from the third power terminal 30C in the third direction y. As shown in FIGS. 2 and 7 , the multiple first signal terminals 31 protrude from the second side surface 54 of the sealing resin 50. The multiple first signal terminals 31 include a first gate terminal 31A, a first detection terminal 31B, and a second detection terminal 31C. Each of the multiple first signal terminals 31 is electrically connected to the first semiconductor element 20A. Of the multiple first signal terminals 31, the first gate terminal 31A is located closest to the third power terminal 30C. The first detection terminal 31B is located between the first gate terminal 31A and the second detection terminal 31C in the third direction y.

[0032] 3 , the first gate terminal 31A and the first detection terminal 31B are individually conductively bonded to any two of the multiple pad layers 15 of the support member 10. The second detection terminal 31C is conductively bonded to the first conductive layer 12 of the support member 10. A gate voltage for driving the first semiconductor element 20A is applied to the first gate terminal 31A. A voltage equivalent to the potential applied to the second electrode 22 of the first semiconductor element 20A is applied to the first detection terminal 31B. A voltage equivalent to the potential applied to the first electrode 21 of the first semiconductor element 20A is applied to the second detection terminal 31C.

[0033] 2 and 8, the multiple second signal terminals 32 protrude from the second side surface 54 of the sealing resin 50. As shown in FIGS. 1 to 3, the multiple second signal terminals 32 include a second gate terminal 32A, a third detection terminal 32B, and a fourth detection terminal 32C. Each of the multiple second signal terminals 32 is electrically connected to the second semiconductor element 20B. Of the multiple second signal terminals 32, the second gate terminal 32A is located closest to the third power terminal 30C. The third detection terminal 32B is located between the second gate terminal 32A and the fourth detection terminal 32C in the third direction y.

[0034] 3 , the second gate terminal 32A and the third detection terminal 32B are individually conductively bonded to any two of the multiple pad layers 15 of the support member 10. The fourth detection terminal 32C is conductively bonded to the first conductive layer 12 of the support member 10. A gate voltage for driving the second semiconductor element 20B is applied to the second gate terminal 32A. A voltage equivalent to the potential applied to the second electrode 22 of the second semiconductor element 20B is applied to the third detection terminal 32B. A voltage equivalent to the potential applied to the first electrode 21 of the second semiconductor element 20B is applied to the fourth detection terminal 32C.

[0035] 2 , 7 , and 8 , each of the multiple power terminals 30 has a first mounting surface 33. The position of the first mounting surface 33 in the first direction z is closer to the bottom surface 52 of the sealing resin 50 than to the first semiconductor element 20A and the second semiconductor element 20B. The first mounting surface 33 is exposed from the bottom surface 52. The first mounting surface 33 extends in the second direction x. The first mounting surface 33 includes an area that protrudes from either the first side surface 53 or the second side surface 54 of the sealing resin 50.

[0036] 2 , 7 , and 8 , each of the plurality of first signal terminals 31 and the plurality of second signal terminals 32 has a second mounting surface 34. The position of the second mounting surface 34 in the first direction z is closer to the bottom surface 52 of the sealing resin 50 than to the first semiconductor element 20A and the second semiconductor element 20B. The second mounting surface 34 is exposed from the bottom surface 52. The second mounting surface 34 extends in the second direction x. The second mounting surface 34 includes a region that protrudes from the second side surface 54 of the sealing resin 50.

[0037] As shown in Figures 3, 7 and 8, each of the multiple power terminals 30, the multiple first signal terminals 31, and the multiple second signal terminals 32 has a first mounting surface 33, a joint portion 35, a mounting portion 36, and an intermediate portion 37.

[0038] 3 , 7 , and 8 , the joint portion 35 is conductively bonded to any of the first conductive layer 12, the second conductive layer 13, the third conductive layer 14, and the plurality of pad layers 15 of the support member 10. The joint portion 35 is sandwiched between the sealing resin 50 and the support member 10. The mounting portion 36 is spaced apart from the joint portion 35 in the first direction z. The mounting portion 36 is exposed from the bottom surface 52 of the sealing resin 50. The intermediate portion 37 connects the joint portion 35 and the mounting portion 36.

[0039] 3 , 7 , and 8 , the mounting portion 36 is located on the opposite side of the intermediate portion 37 from the joint portion 35 in the second direction x. The mounting portion 36 of each of the multiple power terminals 30 includes a first mounting surface 33. The mounting portion 36 of each of the multiple first signal terminals 31 and the multiple second signal terminals 32 includes a second mounting surface 34. The intermediate portion 37 is inclined with respect to the mounting portion 36 such that the farther the intermediate portion 37 is from the mounting portion 36 in the first direction z, the closer it is to the joint portion 35 in the second direction x.

[0040] As shown in FIG. 3 , the two conductive members 40 are individually conductively bonded to the two semiconductor elements 20 and the second conductive layer 13 and third conductive layer 14 of the support member 10. The two conductive members 40 include a first member 40A and a second member 40B. Each of the first member 40A and the second member 40B is made of a plurality of wires. The composition of the plurality of wires includes aluminum (Al). Alternatively, the composition of the plurality of wires may include copper. Furthermore, each of the first member 40A and the second member 40B may be a metal clip instead of a plurality of wires.

[0041] As shown in Fig. 3 , the first member 40A is conductively bonded to the second electrode 22 of the first semiconductor element 20A and the second conductive layer 13 of the support member 10. As a result, the first semiconductor element 20A is electrically connected to the second semiconductor element 20B and the third power terminal 30C of the multiple power terminals 30. As shown in Fig. 3 , the second member 40B is conductively bonded to the second electrode 22 of the second semiconductor element 20B and the third conductive layer 14 of the support member 10. As a result, the second power terminal 30B of the multiple power terminals 30 is electrically connected to the second semiconductor element 20B.

[0042] Furthermore, as described above, of the multiple power terminals 30, the first power terminal 30A is electrically connected to the first semiconductor element 20A. The third power terminal 30C is electrically connected to the second semiconductor element 20B. Therefore, the third power terminal 30C is electrically connected to the first semiconductor element 20A and the second semiconductor element 20B. From the above, it can be said that in the semiconductor device A10, the two semiconductor elements 20 and the multiple power terminals 30 form a half-bridge circuit. In this case, the first power terminal 30A corresponds to the positive electrode (P terminal). Therefore, a direct current flows from the outside to the first semiconductor element 20A through the first power terminal 30A. Furthermore, the second power terminal 30B corresponds to the negative electrode (N terminal). Therefore, a direct current flows from the second semiconductor element 20B to the outside through the second power terminal 30B.

[0043] 3 , one of the two gate wires 41 is conductively bonded to the gate electrode 23 of the first semiconductor element 20A and to one of the pad layers 15 of the support member 10, to which the first gate terminal 31A is conductively bonded. As a result, the first gate terminal 31A is electrically connected to the gate electrode 23 of the first semiconductor element 20A. The other of the two gate wires 41 is conductively bonded to the gate electrode 23 of the second semiconductor element 20B and to one of the pad layers 15 of the support member 10, to which the second gate terminal 32A is conductively bonded. As a result, the second gate terminal 32A is electrically connected to the gate electrode 23 of the second semiconductor element 20B. The composition of the two gate wires 41 includes gold (Au).

[0044] 3 , one of the two detection wires 42 is conductively bonded to the second electrode 22 of the first semiconductor element 20A and to one of the pad layers 15 of the support member 10, to which the first detection terminal 31B is conductively bonded. As a result, the first detection terminal 31B is electrically connected to the second electrode 22 of the first semiconductor element 20A. The other of the two detection wires 42 is conductively bonded to the second electrode 22 of the second semiconductor element 20B and to one of the pad layers 15 of the support member 10, to which the third detection terminal 32B is conductively bonded. As a result, the third detection terminal 32B is electrically connected to the second electrode 22 of the second semiconductor element 20B. The composition of the two detection wires 42 includes aluminum.

[0045] Next, the effects of the semiconductor device A10 will be described.

[0046] The semiconductor device A10 includes a first power terminal 30A and a first signal terminal 31 electrically connected to the first semiconductor element 20A, a second power terminal 30B and a second signal terminal 32 electrically connected to the second semiconductor element 20B, and a third power terminal 30C electrically connected to the first semiconductor element 20A and the second semiconductor element 20B. The semiconductor device A10 further includes a sealing resin 50 covering the first semiconductor element 20A and the second semiconductor element 20B. The positions of the first mounting surfaces 33 of the first power terminal 30A, the second power terminal 30B, and the second power terminal 30B in the first direction z and the positions of the second mounting surfaces 34 of the first signal terminal 31 and the second signal terminal 32 in the first direction z are closer to a bottom surface 52 of the sealing resin 50 than to the first semiconductor element 20A and the second semiconductor element 20B. This configuration enables the semiconductor device A10 to be surface-mounted on a wiring board.

[0047] The first power terminal 30A and the second power terminal 30B protrude from the first side surface 53. The third power terminal 30C protrudes from the second side surface 54. The first power terminal 30A and the second power terminal 30B are spaced apart from each other in the third direction y. This configuration can improve the effect of mutual induction acting on the first power terminal 30A and the second power terminal 30B while suppressing the influence of AC current flowing through the third power terminal 30C. Therefore, this configuration makes it possible to reduce the parasitic inductance in the semiconductor device A10 while miniaturizing the semiconductor device A10.

[0048] The first signal terminal 31 of each of the first power terminal 30A, the second power terminal 30B, and the third power terminal 30C is exposed from the bottom surface 52 of the sealing resin 50. The first mounting surface 33 extends in the second direction x and includes an area that protrudes from either the first side surface 53 or the second side surface 54 of the sealing resin 50. With this configuration, even if the semiconductor device A10 is miniaturized, the first mounting surface 33 is more exposed to solder when the semiconductor device A10 is mounted on a wiring board. This makes it possible to increase the bonding strength of the semiconductor device A10 to the wiring board.

[0049] The semiconductor device A10 further includes a support member 10 on which the first semiconductor element 20A and the second semiconductor element 20B are mounted. The support member 10 is exposed from a top surface 51 of the sealing resin 50. The first semiconductor element 20A, the second semiconductor element 20B, the first power terminal 30A, the second power terminal 30B, the third power terminal 30C, the first signal terminal 31, and the second signal terminal 32 are located between a bottom surface 52 of the sealing resin 50 and the support member 10 in the first direction z. This configuration enables the semiconductor device A10 to dissipate heat from the side opposite to the side on which the wiring board on which the semiconductor device A10 is mounted is located in the first direction z.

[0050] In the above case, the support member 10 has the heat dissipation layer 16 exposed from the top surface 51. By adopting this configuration, the heat dissipation efficiency of the semiconductor device A10 can be further improved.

[0051] Each of the first power terminal 30A, the second power terminal 30B, and the third power terminal 30C has a joint portion 35, a mounting portion 36, and an intermediate portion 37. The joint portion 35 is joined to the support member 10. The mounting portion 36 is spaced apart from the joint portion 35 in the first direction z and is exposed from the bottom surface 52 of the sealing resin 50. The intermediate portion 37 connects the joint portion 35 and the mounting portion 36. The joint portion 35 is sandwiched between the sealing resin 50 and the support member 10. This configuration prevents the multiple power terminals 30 from falling off the bottom surface 52.

[0052] Second Embodiment: A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to Figures 11 to 15. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated explanations will be omitted. Here, for ease of understanding, Figure 13 shows a perspective view of the sealing resin 50. In Figure 13, the outline of the transparent sealing resin 50 is shown by an imaginary line.

[0053] In the semiconductor device A20, the configuration of the plurality of second signal terminals 32 is different from that of the semiconductor device A10.

[0054] 11 to 13 , the second gate terminal 32A of the multiple second signal terminals 32 protrudes from the first side surface 53 of the sealing resin 50. As shown in FIG. 14 , the second gate terminal 32A is located next to the second power terminal 30B of the multiple power terminals 30 in the third direction y. The third detection terminal 32B and the fourth detection terminal 32C of the multiple second signal terminals 32 are located on the opposite side of the second gate terminal 32A from the two semiconductor elements 20 in the second direction x. As shown in FIG. 15 , of the third detection terminal 32B and the fourth detection terminal 32C, the fourth detection terminal 32C is located closest to the third power terminal 30C of the multiple power terminals 30.

[0055] As described above, a gate voltage for driving the second semiconductor element 20B of the two semiconductor elements 20 is applied to the second gate terminal 32A. Therefore, a current flows from the outside toward the gate electrode 23 of the second semiconductor element 20B in the second gate terminal 32A. Therefore, the direction of the current flowing in the second gate terminal 32A is opposite to the direction of the current flowing in the second power terminal 30B.

[0056] As shown in FIGS. 11 and 14, the dimension of the second power terminal 30B in the third direction y is greater than the dimension of each of the plurality of second signal terminals 32, including the second gate terminal 32A, in the third direction y.

[0057] Next, the effects of the semiconductor device A20 will be described.

[0058] The semiconductor device A20 includes a first power terminal 30A and a first signal terminal 31 electrically connected to the first semiconductor element 20A, a second power terminal 30B and a second signal terminal 32 electrically connected to the second semiconductor element 20B, and a third power terminal 30C electrically connected to the first semiconductor element 20A and the second semiconductor element 20B. The semiconductor device A20 further includes a sealing resin 50 covering the first semiconductor element 20A and the second semiconductor element 20B. The positions of the first mounting surfaces 33 of the first power terminal 30A, the second power terminal 30B, and the second power terminal 30B in the first direction z and the positions of the second mounting surfaces 34 of the first signal terminal 31 and the second signal terminal 32 in the first direction z are closer to a bottom surface 52 of the sealing resin 50 than to the first semiconductor element 20A and the second semiconductor element 20B. The first power terminal 30A and the second power terminal 30B protrude from a first side surface 53. The third power terminal 30C protrudes from the second side surface 54. The first power terminal 30A and the second power terminal 30B are spaced apart in the third direction y. Therefore, with this configuration, the semiconductor device A20 can also be miniaturized and the parasitic inductance of the semiconductor device A20 can be reduced. Furthermore, by sharing the same configuration as the semiconductor device A10, the semiconductor device A20 achieves the same effects as the semiconductor device A10.

[0059] In the semiconductor device A20, the second gate terminal 32A serving as the second signal terminal 32 protrudes from the first side surface 53 of the sealing resin 50. The current flowing through the second signal terminal 32 is opposite to that flowing through the second power terminal 30B. The second signal terminal 32 is located adjacent to the second power terminal 30B in the third direction y. This configuration causes mutual induction between the second signal terminal 32 and the second power terminal 30B. This reduces the parasitic inductance of the second signal terminal 32. When the second signal terminal 32 is the second gate terminal 32A, it is possible to reduce switching loss associated with driving the second semiconductor element 20B.

[0060] Third Embodiment: A semiconductor device A30 according to a third embodiment of the present disclosure will be described with reference to Figures 16 to 20. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, Figure 18 shows a perspective view of the sealing resin 50. In Figure 18, the outline of the transparent sealing resin 50 is shown by imaginary lines.

[0061] In the semiconductor device A30, the configuration of the plurality of first signal terminals 31 is different from that of the semiconductor device A20 described above.

[0062] As shown in FIGS. 16 to 18 , the first gate terminal 31A of the multiple first signal terminals 31 protrudes from the first side surface 53 of the sealing resin 50. As shown in FIG. 19 , the first gate terminal 31A is located next to the second power terminal 30B of the multiple power terminals 30 in the third direction y. In the semiconductor device A30, the first power terminal 30A of the multiple power terminals 30 is located on the opposite side of the second power terminal 30B from the first gate terminal 31A in the third direction y. The first detection terminal 31B and the second detection terminal 31C of the multiple first signal terminals 31 are located on the opposite side of the first gate terminal 31A from the two semiconductor elements 20 in the second direction x. As shown in FIG. 20 , of the first detection terminal 31B and the second detection terminal 31C, the first detection terminal 31B is located closest to the third power terminal 30C of the multiple power terminals 30.

[0063] As described above, a gate voltage for driving the first semiconductor element 20A of the two semiconductor elements 20 is applied to the first gate terminal 31A. Therefore, a current flows from the outside toward the gate electrode 23 of the first semiconductor element 20A in the first gate terminal 31A. Therefore, the direction of the current flowing in the first gate terminal 31A is opposite to the direction of the current flowing in the second power terminal 30B.

[0064] As shown in FIGS. 16 and 19, the dimension of the second power terminal 30B in the third direction y is greater than the dimension of each of the plurality of first signal terminals 31 including the first gate terminal 31A in the third direction y.

[0065] As shown in Figure 19, among the multiple second signal terminals 32, the second gate terminal 32A is located on the opposite side of the first power terminal 30A in the third direction y with the second power terminal 30B as the reference, and is located next to the second power terminal 30B in the third direction y.

[0066] Next, the effects of the semiconductor device A30 will be described.

[0067] The semiconductor device A30 includes a first power terminal 30A and a first signal terminal 31 electrically connected to the first semiconductor element 20A, a second power terminal 30B and a second signal terminal 32 electrically connected to the second semiconductor element 20B, and a third power terminal 30C electrically connected to the first semiconductor element 20A and the second semiconductor element 20B. The semiconductor device A30 further includes a sealing resin 50 covering the first semiconductor element 20A and the second semiconductor element 20B. The positions of the first mounting surfaces 33 of the first power terminal 30A, the second power terminal 30B, and the second power terminal 30B in the first direction z and the positions of the second mounting surfaces 34 of the first signal terminal 31 and the second signal terminal 32 in the first direction z are closer to a bottom surface 52 of the sealing resin 50 than to the first semiconductor element 20A and the second semiconductor element 20B. The first power terminal 30A and the second power terminal 30B protrude from a first side surface 53. The third power terminal 30C protrudes from the second side surface 54. The first power terminal 30A and the second power terminal 30B are spaced apart in the third direction y. Therefore, with this configuration, the semiconductor device A30 can also be miniaturized and the parasitic inductance of the semiconductor device A30 can be reduced. Furthermore, by sharing the same configuration as the semiconductor device A10, the semiconductor device A30 achieves the same effects as the semiconductor device A10.

[0068] In the semiconductor device A30, the first gate terminal 31A serving as the first signal terminal 31 protrudes from the first side surface 53 of the sealing resin 50. The current flowing through the first signal terminal 31 is opposite to that flowing through the second power terminal 30B. The first signal terminal 31 is located adjacent to the second power terminal 30B in the third direction y. This configuration causes mutual induction between the first signal terminal 31 and the second power terminal 30B. This reduces the parasitic inductance of the first signal terminal 31. When the first signal terminal 31 is the first gate terminal 31A, it is possible to reduce switching loss associated with driving the first semiconductor element 20A.

[0069] Furthermore, in the semiconductor device A30, the second gate terminal 32A serving as the second signal terminal 32 protrudes from the first side surface 53 of the sealing resin 50. The current flowing through the second signal terminal 32 is opposite to that flowing through the second power terminal 30B. The second signal terminal 32 is located on the opposite side of the first signal terminal 31 in the third direction y with respect to the second power terminal 30B, and is located next to the second power terminal 30B in the third direction y. With this configuration, the second signal terminal 32 achieves the same effects as those of the semiconductor device A20.

[0070] 21 to 26, a semiconductor device A40 according to a fourth embodiment of the present disclosure will be described. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted.

[0071] In the semiconductor device A40, the configurations of the power terminals 30, the first signal terminals 31, and the second signal terminals 32 are different from those of the semiconductor device A10.

[0072] 21 and 22 , each of the multiple power terminals 30 is exposed only from either a first side surface 53 or a second side surface 54 of the sealing resin 50. As shown in FIGS. 23 to 26 , in each of the multiple power terminals 30, the portion of the mounting portion 36 exposed from the sealing resin 50 is bent in a gull-wing shape toward the bottom surface 52 of the sealing resin 50 when viewed in the third direction y. As shown in FIG. 22 , the first mounting surface 33 of each of the multiple power terminals 30 is spaced outward from the bottom surface 52 when viewed in the first direction z.

[0073] 21 and 22 , each of the plurality of first signal terminals 31 and the plurality of second signal terminals 32 is exposed only from the second side surface 54 of the sealing resin 50. As shown in FIGS. 24 to 26 , in each of the plurality of first signal terminals 31 and the plurality of second signal terminals 32, the portion of the mounting portion 36 exposed from the sealing resin 50 is bent in a gull-wing shape toward the bottom surface 52 of the sealing resin 50 as viewed in the third direction y. As shown in FIG. 22 , the second mounting surface 34 of each of the plurality of first signal terminals 31 and the plurality of second signal terminals 32 is spaced outward from the bottom surface 52 as viewed in the first direction z.

[0074] Next, the effects of the semiconductor device A40 will be described.

[0075] The semiconductor device A40 includes a first power terminal 30A and a first signal terminal 31 electrically connected to the first semiconductor element 20A, a second power terminal 30B and a second signal terminal 32 electrically connected to the second semiconductor element 20B, and a third power terminal 30C electrically connected to the first semiconductor element 20A and the second semiconductor element 20B. The semiconductor device A40 further includes a sealing resin 50 covering the first semiconductor element 20A and the second semiconductor element 20B. The positions of the first mounting surfaces 33 of the first power terminal 30A, the second power terminal 30B, and the second power terminal 30B in the first direction z and the positions of the second mounting surfaces 34 of the first signal terminal 31 and the second signal terminal 32 in the first direction z are closer to a bottom surface 52 of the sealing resin 50 than to the first semiconductor element 20A and the second semiconductor element 20B. The first power terminal 30A and the second power terminal 30B protrude from a first side surface 53. The third power terminal 30C protrudes from the second side surface 54. The first power terminal 30A and the second power terminal 30B are spaced apart in the third direction y. Therefore, with this configuration, the semiconductor device A40 can also be miniaturized and the parasitic inductance of the semiconductor device A40 can be reduced. Furthermore, by sharing the same configuration as the semiconductor device A10, the semiconductor device A40 achieves the same effects as the semiconductor device A10.

[0076] 27 and 28, a semiconductor device A50 according to a fifth embodiment of the present disclosure will be described. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0077] In the semiconductor device A50, the configurations of the power terminals 30, the first signal terminals 31, and the second signal terminals 32 are different from those of the semiconductor device A20.

[0078] 27 and 28 , each of the multiple power terminals 30 is exposed only from either a first side surface 53 or a second side surface 54 of the sealing resin 50. As in the case of the semiconductor device A40, in each of the multiple power terminals 30, the portion of the mounting portion 36 exposed from the sealing resin 50 is bent in a gull-wing shape toward the bottom surface 52 of the sealing resin 50 when viewed in the third direction y. As shown in FIG. 28 , the first mounting surface 33 of each of the multiple power terminals 30 is spaced outward from the bottom surface 52 when viewed in the first direction z.

[0079] 27 and 28 , each of the plurality of first signal terminals 31 and the plurality of second signal terminals 32 is exposed only from either a first side surface 53 or a second side surface 54 of the sealing resin 50. As in the case of the semiconductor device A40, in each of the plurality of first signal terminals 31 and the plurality of second signal terminals 32, the portion of the mounting portion 36 exposed from the sealing resin 50 is bent in a gull-wing shape toward the bottom surface 52 of the sealing resin 50 as viewed in the third direction y. As shown in FIG. 28 , the second mounting surface 34 of each of the plurality of first signal terminals 31 and the plurality of second signal terminals 32 is spaced outward from the bottom surface 52 as viewed in the first direction z.

[0080] Next, the effects of the semiconductor device A50 will be described.

[0081] The semiconductor device A50 includes a first power terminal 30A and a first signal terminal 31 electrically connected to the first semiconductor element 20A, a second power terminal 30B and a second signal terminal 32 electrically connected to the second semiconductor element 20B, and a third power terminal 30C electrically connected to the first semiconductor element 20A and the second semiconductor element 20B. The semiconductor device A50 further includes a sealing resin 50 covering the first semiconductor element 20A and the second semiconductor element 20B. The positions of the first mounting surfaces 33 of the first power terminal 30A, the second power terminal 30B, and the second power terminal 30B in the first direction z and the positions of the second mounting surfaces 34 of the first signal terminal 31 and the second signal terminal 32 in the first direction z are closer to a bottom surface 52 of the sealing resin 50 than to the first semiconductor element 20A and the second semiconductor element 20B. The first power terminal 30A and the second power terminal 30B protrude from a first side surface 53. The third power terminal 30C protrudes from the second side surface 54. The first power terminal 30A and the second power terminal 30B are spaced apart in the third direction y. Therefore, with this configuration, the semiconductor device A50 can also be miniaturized and the parasitic inductance of the semiconductor device A50 can be reduced. Furthermore, by sharing the same configuration as the semiconductor device A20, the semiconductor device A50 achieves the same effects as the semiconductor device A20.

[0082] 29 and 30, a semiconductor device A60 according to a sixth embodiment of the present disclosure will be described. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are designated by the same reference numerals, and duplicated descriptions will be omitted.

[0083] In the semiconductor device A60, the configurations of the power terminals 30, the first signal terminals 31, and the second signal terminals 32 are different from those of the semiconductor device A30.

[0084] 29 and 30 , each of the multiple power terminals 30 is exposed only from either a first side surface 53 or a second side surface 54 of the sealing resin 50. As in the case of the semiconductor device A40, in each of the multiple power terminals 30, the portion of the mounting portion 36 exposed from the sealing resin 50 is bent in a gull-wing shape toward the bottom surface 52 of the sealing resin 50 when viewed in the third direction y. As shown in FIG. 30 , the first mounting surface 33 of each of the multiple power terminals 30 is spaced outward from the bottom surface 52 when viewed in the first direction z.

[0085] 29 and 30 , each of the plurality of first signal terminals 31 and the plurality of second signal terminals 32 is exposed only from either a first side surface 53 or a second side surface 54 of the sealing resin 50. As in the case of the semiconductor device A40, in each of the plurality of first signal terminals 31 and the plurality of second signal terminals 32, the portion of the mounting portion 36 exposed from the sealing resin 50 is bent in a gull-wing shape toward the bottom surface 52 of the sealing resin 50 as viewed in the third direction y. As shown in FIG. 30 , the second mounting surface 34 of each of the plurality of first signal terminals 31 and the plurality of second signal terminals 32 is spaced outward from the bottom surface 52 as viewed in the first direction z.

[0086] Next, the effects of the semiconductor device A60 will be described.

[0087] The semiconductor device A60 includes a first power terminal 30A and a first signal terminal 31 electrically connected to the first semiconductor element 20A, a second power terminal 30B and a second signal terminal 32 electrically connected to the second semiconductor element 20B, and a third power terminal 30C electrically connected to the first semiconductor element 20A and the second semiconductor element 20B. The semiconductor device A60 further includes a sealing resin 50 covering the first semiconductor element 20A and the second semiconductor element 20B. The positions of the first mounting surfaces 33 of the first power terminal 30A, the second power terminal 30B, and the second power terminal 30B in the first direction z and the positions of the second mounting surfaces 34 of the first signal terminal 31 and the second signal terminal 32 in the first direction z are closer to a bottom surface 52 of the sealing resin 50 than to the first semiconductor element 20A and the second semiconductor element 20B. The first power terminal 30A and the second power terminal 30B protrude from a first side surface 53. The third power terminal 30C protrudes from the second side surface 54. The first power terminal 30A and the second power terminal 30B are spaced apart in the third direction y. Therefore, with this configuration, the semiconductor device A60 can also be miniaturized and the parasitic inductance of the semiconductor device A60 can be reduced. Furthermore, by sharing the same configuration as the semiconductor device A30, the semiconductor device A60 achieves the same effects as the semiconductor device A30.

[0088] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0089] The present disclosure includes the embodiments described in the following appendices.

[0090] Supplementary Note 1. A semiconductor device comprising: a first semiconductor element; a second semiconductor element; a first power terminal and a first signal terminal electrically connected to the first semiconductor element; a second power terminal and a second signal terminal electrically connected to the second semiconductor element; a third power terminal electrically connected to the first semiconductor element and the second semiconductor element; and a sealing resin covering the first semiconductor element and the second semiconductor element, wherein the sealing resin has a bottom surface facing a first direction and a first side surface and a second side surface facing opposite each other in a second direction perpendicular to the first direction, each of the first power terminal, the second power terminal, and the third power terminal has a first mounting surface facing the same side as the bottom surface in the first direction, each of the first signal terminal and the second signal terminal has a second mounting surface facing the same side as the bottom surface in the first direction, and the positions of the first mounting surface and the second mounting surface in the first direction are closer to the bottom surface than to the first semiconductor element and the second semiconductor element, A semiconductor device wherein the first power terminal and the second power terminal protrude from the first side surface, the third power terminal protrudes from the second side surface, the first signal terminal and the second signal terminal each protrude from either the first side surface or the second side surface, and the first power terminal and the second power terminal are spaced apart in a third direction orthogonal to the first and second directions. Appendix 2. The semiconductor device according to Appendix 1, wherein the first mounting surface is exposed from the bottom surface, and the first mounting surface extends in the second direction and includes a region protruding from either the first side surface or the second side surface. Appendix 3. The semiconductor device according to Appendix 2, wherein the second mounting surface is exposed from the bottom surface, and the second mounting surface extends in the second direction and includes a region protruding from either the first side surface or the second side surface. Appendix 4. The semiconductor device according to Appendix 2 or 3, wherein the second power terminal is located next to the first power terminal in the third direction.Appendix 5. The semiconductor device according to Appendix 4, wherein the second signal terminal protrudes from the first side surface, a direction of current flowing through the second signal terminal is opposite to a direction of current flowing through the second power terminal, and the second signal terminal is located adjacent to the second power terminal in the third direction. Appendix 6. The semiconductor device according to Appendix 5, wherein a dimension of the second power terminal in the third direction is larger than a dimension of the second signal terminal in the third direction. Appendix 7. The semiconductor device according to Appendix 2 or 3, wherein the first signal terminal protrudes from the first side surface, a direction of current flowing through the first signal terminal is opposite to a direction of current flowing through the second power terminal, and the first signal terminal is located adjacent to the second power terminal in the third direction. Appendix 8. The semiconductor device according to Appendix 7, wherein a dimension of the second power terminal in the third direction is larger than a dimension of the first signal terminal in the third direction. Appendix 9. The semiconductor device according to Appendix 8, wherein the second signal terminal protrudes from the first side surface, a direction of current flowing through the second signal terminal is opposite to a direction of current flowing through the second power terminal, and the second signal terminal is located on the opposite side of the first signal terminal with the second power terminal as a reference in the third direction and adjacent to the second power terminal in the third direction. Appendix 10. The semiconductor device according to any one of Appendixes 1 to 9, further comprising a support member on which the first semiconductor element and the second semiconductor element are mounted, and the first semiconductor element and the second semiconductor element are located between the bottom surface and the support member in the first direction. Appendix 11. The semiconductor device according to Appendix 10, wherein the first power terminal, the second power terminal, the third power terminal, the first signal terminal, and the second signal terminal are located between the bottom surface and the support member in the first direction. Appendix 12. The semiconductor device according to Appendix 11, wherein the sealing resin has a top surface facing opposite to the bottom surface in the first direction, and the support member is exposed from the top surface. Appendix 13. The semiconductor device according to Appendix 12, wherein the first power terminal, the second power terminal, and the third power terminal are joined to the support member.Appendix 14. The semiconductor device of Appendix 13, wherein the first signal terminal and the second signal terminal are bonded to the support member. Appendix 15. The semiconductor device of Appendix 13 or 14, wherein the support member has an insulating layer and a first conductive layer and a second conductive layer located between the first semiconductor element and the second semiconductor element and the insulating layer in the first direction, the first semiconductor element being conductively bonded to the first conductive layer, and the second semiconductor element being conductively bonded to the second conductive layer. Appendix 16. The semiconductor device of Appendix 15, wherein the first power terminal is conductively bonded to the first conductive layer, and the third power terminal is conductively bonded to the second conductive layer. Appendix 17. The semiconductor device of Appendix 15 or 16, wherein the support member has a heat dissipation layer located on the opposite side of the insulating layer from the first conductive layer and the second conductive layer, and the heat dissipation layer is exposed from the top surface.

[0091] A10, A20, A30, A40, A50, A60: semiconductor device 10: support member 11: insulating layer 12: first conductive layer 13: second conductive layer 14: third conductive layer 15: pad layer 16: heat dissipation layer 20: semiconductor element 20A: first semiconductor element 20B: second semiconductor element 21: first electrode 22: second electrode 23: gate electrode 29: bonding layer 30: power terminal 30A: first power terminal 30B: second power terminal 30C: third power terminal 31: first signal terminal 31A: first gate terminal 31B: first detection terminal 31C: second detection terminal 32: second signal terminal 32A: second gate terminal 32B: third detection terminal 32C: fourth detection terminal 33: first mounting surface 34: second mounting surface 35: Joint portion 36: Mounting portion 37: Intermediate portion 40: Conductive member 40A: First member 40B: Second member 41: Gate wire 42: Detection wire 50: Sealing resin 501: Outer edge 51: Top surface 511: Periphery 52: Bottom surface 53: First side surface 54: Second side surface 55: Third side surface z: First direction x: Second direction y: Third direction

Claims

1. A first semiconductor element; A second semiconductor element; a first power terminal and a first signal terminal electrically connected to the first semiconductor element; a second power terminal and a second signal terminal electrically connected to the second semiconductor element; a third power terminal electrically connected to the first semiconductor element and the second semiconductor element; a sealing resin that covers the first semiconductor element and the second semiconductor element, the sealing resin has a bottom surface facing a first direction, and a first side surface and a second side surface facing opposite sides in a second direction perpendicular to the first direction; each of the first power terminal, the second power terminal, and the third power terminal has a first mounting surface facing the same side as the bottom surface in the first direction; each of the first signal terminal and the second signal terminal has a second mounting surface facing the same side as the bottom surface in the first direction; a position of each of the first mounting surface and the second mounting surface in the first direction is closer to the bottom surface than to the first semiconductor element and the second semiconductor element; the first power terminal and the second power terminal protrude from the first side surface, the third power terminal protruding from the second side; each of the first signal terminal and the second signal terminal protrudes from either the first side surface or the second side surface; The first power terminal and the second power terminal are spaced apart from each other in a third direction perpendicular to the first direction and the second direction.

2. the first mounting surface is exposed from the bottom surface, The semiconductor device according to claim 1 , wherein the first mounting surface extends in the second direction and includes a region that protrudes from either the first side surface or the second side surface.

3. the second mounting surface is exposed from the bottom surface, The semiconductor device according to claim 2 , wherein the second mounting surface extends in the second direction and includes a region that protrudes from either the first side surface or the second side surface.

4. The semiconductor device according to claim 2 , wherein the second power terminal is located adjacent to the first power terminal in the third direction.

5. the second signal terminal protrudes from the first side surface, a direction of a current flowing through the second signal terminal is opposite to a direction of a current flowing through the second power terminal; The semiconductor device according to claim 4 , wherein the second signal terminal is located adjacent to the second power terminal in the third direction.

6. The semiconductor device according to claim 5 , wherein a dimension of said second power terminal in said third direction is larger than a dimension of said second signal terminal in said third direction.

7. the first signal terminal protrudes from the first side surface, a direction of a current flowing through the first signal terminal is opposite to a direction of a current flowing through the second power terminal; The semiconductor device according to claim 2 , wherein the first signal terminal is located adjacent to the second power terminal in the third direction.

8. The semiconductor device according to claim 7 , wherein a dimension of said second power terminal in said third direction is larger than a dimension of said first signal terminal in said third direction.

9. the second signal terminal protrudes from the first side surface, a direction of a current flowing through the second signal terminal is opposite to a direction of a current flowing through the second power terminal; 9. The semiconductor device according to claim 8, wherein the second signal terminal is located on an opposite side to the first signal terminal with respect to the second power terminal in the third direction, and is located adjacent to the second power terminal in the third direction.

10. a support member on which the first semiconductor element and the second semiconductor element are mounted, 10. The semiconductor device according to claim 1, wherein the first semiconductor element and the second semiconductor element are located between the bottom surface and the support member in the first direction.

11. The semiconductor device according to claim 10 , wherein the first power terminal, the second power terminal, the third power terminal, the first signal terminal, and the second signal terminal are located between the bottom surface and the support member in the first direction.

12. the sealing resin has a top surface facing a side opposite to the bottom surface in the first direction, The semiconductor device according to claim 11 , wherein the support member is exposed from the top surface.

13. The semiconductor device according to claim 12 , wherein the first power terminal, the second power terminal and the third power terminal are joined to the support member.

14. The semiconductor device according to claim 13 , wherein the first signal terminal and the second signal terminal are joined to the support member.

15. the support member has an insulating layer, and a first conductive layer and a second conductive layer located between the first semiconductor element and the insulating layer in the first direction, the first semiconductor element is conductively bonded to the first conductive layer; The semiconductor device according to claim 13 , wherein the second semiconductor element is conductively joined to the second conductive layer.

16. the first power terminal is conductively connected to the first conductive layer; The semiconductor device according to claim 15 , wherein the third power terminal is conductively joined to the second conductive layer.

17. the support member has a heat dissipation layer located on an opposite side of the insulating layer from the first conductive layer and the second conductive layer, The semiconductor device according to claim 15 , wherein the heat dissipation layer is exposed from the top surface.