Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device comprises a semiconductor element, a sealing resin that covers the semiconductor element, a terminal that conducts electricity to the semiconductor element and protrudes from the sealing resin in a first direction that is orthogonal to the thickness direction, and a plating layer that is disposed on the terminal. The terminal is provided with: a distal-end surface, which is an end surface located on the side protruding from the sealing resin; a first surface that faces a first thickness-direction side; and a recess that is recessed from both the distal-end surface and the first surface. The plating layer includes a recess plating section disposed on at least part of the recess.

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] Various configurations have been proposed for semiconductor devices including semiconductor elements. Patent Document 1 discloses an example of an SOP (Small Outline Package) type semiconductor device. The semiconductor device disclosed in this document includes a semiconductor element, a die pad, terminals, and a sealing resin. The semiconductor element is mounted on the die pad and is electrically connected to the terminals via bonding wires. The semiconductor element, the die pad, and a portion of the terminals are covered with a sealing resin. An exterior plating layer made of an alloy containing Sn is formed on the portion of the terminal exposed from the sealing resin to improve solder adhesion when the terminal is joined to a wiring board by solder.

[0003] Japanese Patent Application Laid-Open No. 2016-207714

[0004] Because the outer plating layer is formed before the terminal is separated from the lead frame, no outer plating layer is formed on the tip surface of the terminal. Therefore, when the terminal is joined to the wiring board by soldering, the solder does not adhere well to the tip surface of the terminal, and a solder fillet may not be formed. In this case, a visual inspection will determine that the solder adhesion is poor.

[0005] An object of the present disclosure is to provide a semiconductor device that is improved over conventional semiconductor devices. In particular, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device that can suppress solder adhesion defects when mounted on a wiring board.

[0006] A semiconductor device provided by a first aspect of the present disclosure includes a semiconductor element, an encapsulation resin covering the semiconductor element, a terminal electrically connected to the semiconductor element and protruding from the encapsulation resin in a first direction perpendicular to a thickness direction, and a plating layer disposed on the terminal. The terminal includes a tip surface that is an end surface on the side protruding from the encapsulation resin, a first surface facing the first side in the thickness direction, and a recess recessed from both the tip surface and the first surface. The plating layer includes a recess plating portion disposed in at least a portion of the recess.

[0007] A method for manufacturing a semiconductor device provided by a second aspect of the present disclosure includes the steps of preparing a lead frame including a terminal portion having a first surface facing a first side in a thickness direction and a recess recessed from the first surface in the thickness direction, forming a plating layer on the terminal portion, and cutting the terminal portion along a cutting line intersecting the recess using a cutting die.

[0008] According to the above configuration, it is possible to provide a semiconductor device that can suppress poor solder adhesion when mounted on a wiring board.

[0009] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0010] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view showing the semiconductor device of FIG. 1, seen through the sealing resin. FIG. 3 is a front view showing the semiconductor device of FIG. 1. FIG. 4 is a left side view showing the semiconductor device of FIG. 1. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 2. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 2. FIG. 7 is a partially enlarged view of FIG. 5. FIG. 8 is a partially enlarged view of FIG. 4. FIG. 9 is a partially enlarged view of FIG. 5. FIG. 10 is a plan view showing a step in a method for manufacturing the semiconductor device of FIG. 1. FIG. 11 is a bottom view showing a step in a method for manufacturing the semiconductor device of FIG. 1. FIG. 12 is a cross-sectional view showing a step in a method for manufacturing the semiconductor device of FIG. 1. FIG. 13 is a plan view showing a step in a method for manufacturing the semiconductor device of FIG. 1. FIG. 14 is a plan view showing a step in a method for manufacturing the semiconductor device of FIG. 1. FIG. 15 is a cross-sectional view showing a step in a method for manufacturing the semiconductor device of FIG. 1. FIG. 16 is a cross-sectional view showing a step in a method for manufacturing the semiconductor device of FIG. 1. FIG. 17 is a partially enlarged view of FIG. 16. FIG. 18 is a cross-sectional view showing a step in a method for manufacturing the semiconductor device of FIG. 1 . FIG. 19 is a cross-sectional view showing a step in a method for manufacturing the semiconductor device of FIG. 1 . FIG. 20 is a partially enlarged view of FIG. 19 . FIG. 21 is a partially enlarged cross-sectional view showing the semiconductor device of FIG. 1 mounted on a wiring substrate. FIG. 22 is a partially enlarged left side view showing a semiconductor device according to a first modified example of the first embodiment of the present disclosure. FIG. 23 is a partially enlarged bottom view showing the semiconductor device of FIG. 22 . FIG. 24 is a partially enlarged left side view showing a semiconductor device according to a second modified example of the first embodiment of the present disclosure. FIG. 25 is a partially enlarged bottom view showing the semiconductor device of FIG. 24 . FIG. 26 is a partially enlarged left side view showing a semiconductor device according to a third modified example of the first embodiment of the present disclosure. FIG. 27 is a partially enlarged bottom view showing the semiconductor device of FIG. 26 . FIG. 28 is a partially enlarged cross-sectional view showing a semiconductor device according to a second embodiment of the present disclosure. FIG. 29 is a partially enlarged left side view showing the semiconductor device of FIG. 28 . FIG. 30 is a partially enlarged cross-sectional view showing a step in a method for manufacturing the semiconductor device of FIG. 28 . Fig. 31 is a partially enlarged cross-sectional view showing a semiconductor device according to a third embodiment of the present disclosure, Fig. 32 is a partially enlarged left side view showing the semiconductor device of Fig. 31, and Fig. 33 is a partially enlarged cross-sectional view showing a semiconductor device according to a fourth embodiment of the present disclosure.

[0011] Preferred embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0012] First Embodiment: FIGS. 1 to 9 show an example of a semiconductor device according to the present disclosure. A semiconductor device A10 of this embodiment includes a first semiconductor element 11, a second semiconductor element 12, an insulating element 13, a conductive member 2, multiple wires 61 to 64, and a sealing resin 7. The conductive member 2 includes a first die pad 3, a second die pad 4, multiple first terminals 51, multiple second terminals 52, multiple pad portions 53 and 55, a pair of connecting portions 54, and a pair of connecting portions 56. The semiconductor device A10 is surface-mounted on a wiring board of an inverter device, for example, in an electric vehicle or a hybrid vehicle. The application and function of the semiconductor device A10 are not limited. The package format of the semiconductor device A10 is a small outline package (SOP). However, the package format of the semiconductor device A10 is not limited to SOP.

[0013] FIG. 1 is a plan view showing the semiconductor device A10. FIG. 2 is a plan view showing the semiconductor device A10. In FIG. 2, for ease of understanding, the outline of the sealing resin 7 is shown by an imaginary line (two-dot chain line) through the sealing resin 7. FIG. 3 is a front view showing the semiconductor device A10. FIG. 4 is a left side view showing the semiconductor device A10. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 2. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 2. FIG. 7 is a partial enlarged view of FIG. 5. FIG. 8 is a partial enlarged view of FIG. 4. FIG. 9 is a partial enlarged view of FIG. 5.

[0014] The semiconductor device A10 has a rectangular shape when viewed in the thickness direction (plan view). For convenience of explanation, the thickness direction of the semiconductor device A10 is defined as the z direction, the direction along one side of the semiconductor device A10 perpendicular to the z direction (the left-right direction in FIGS. 1 and 2) is defined as the x direction, and the direction perpendicular to the z direction and the x direction (the up-down direction in FIGS. 1 and 2) is defined as the y direction. Note that the shape and dimensions of the semiconductor device A10 are not limited.

[0015] The first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 are elements that are the core of the function of the semiconductor device A10.

[0016] As shown in FIG. 2 , the first semiconductor element 11 is mounted on a portion of the conductive member 2 (a first die pad 3 described later) and is disposed in the center of the semiconductor device A10 in the y direction, toward the x1 side in the x direction. When viewed in the z direction, the first semiconductor element 11 has a rectangular shape elongated in the y direction. The first semiconductor element 11 is a control element. The first semiconductor element 11 includes a circuit that converts a control signal input from an ECU or the like into a PWM control signal, a transmission circuit that transmits the PWM control signal to the second semiconductor element 12, and a reception circuit that receives an electrical signal from the second semiconductor element 12. The first semiconductor element 11 has an element main surface 111 and an element back surface 112 that face opposite each other in the z direction. The element main surface 111 faces the z1 side in the z direction. The element back surface 112 faces the z2 side in the z direction. A plurality of electrodes 11A are provided on the element main surface 111. The plurality of electrodes 11A are electrically connected to circuits configured in the first semiconductor element 11.

[0017] As shown in FIG. 2 , the second semiconductor element 12 is mounted on a portion of the conductive member 2 (the second die pad 4 described below) and is positioned in the center of the semiconductor device A10 in the y direction, toward the x2 side in the x direction. When viewed in the z direction, the second semiconductor element 12 has a rectangular shape elongated in the y direction. The second semiconductor element 12 is a driving element. The second semiconductor element 12 includes a receiving circuit that receives a PWM control signal transmitted from the first semiconductor element 11, a circuit (gate driver) that generates and outputs a driving signal for a switching element (e.g., an IGBT or MOSFET) based on the received PWM control signal, and a transmitting circuit that transmits an electrical signal to the first semiconductor element 11. The second semiconductor element 12 has an element main surface 121 and an element back surface 122 that face opposite each other in the z direction. The element main surface 121 faces the z1 side in the z direction. The element back surface 122 faces the z2 side in the z direction. A plurality of electrodes 12A are provided on the element main surface 121. The plurality of electrodes 12A are electrically connected to a circuit formed in the second semiconductor element 12 .

[0018] As shown in FIG. 2 , the insulating element 13 is mounted on a portion of the conductive member 2 (first die pad 3) and is disposed at the center of the semiconductor device A10 in the y direction. The insulating element 13 is located on the x2 side of the first semiconductor element 11 in the x direction and on the x1 side of the second semiconductor element 12 in the x direction. That is, the insulating element 13 is located between the first semiconductor element 11 and the second semiconductor element 12 in the x direction. When viewed in the z direction, the insulating element 13 has a rectangular shape that is elongated in the y direction. The insulating element 13 is an element for transmitting PWM control signals and other electrical signals in an insulated state. The insulating element 13 receives a PWM control signal from the first semiconductor element 11 via wire 63 and transmits the received PWM control signal to the second semiconductor element 12 via wire 64 in an insulated state. The insulating element 13 also receives an electrical signal from the second semiconductor element 12 via wire 64 and transmits the received electrical signal to the first semiconductor element 11 via wire 63 in an insulated state. In other words, the insulating element 13 relays signals between the first semiconductor element 11 and the second semiconductor element 12 while insulating the first semiconductor element 11 and the second semiconductor element 12 from each other.

[0019] In this embodiment, the insulating element 13 is an inductive insulating element. An inductive insulating element transmits electrical signals in an isolated state by inductively coupling two inductors (coils). The insulating element 13 has a substrate made of Si, on which an inductor made of Cu is formed. The inductors include a transmitting inductor and a receiving inductor, which are stacked on top of each other in the thickness direction (z direction) of the insulating element 13. A dielectric layer made of SiO or the like is interposed between the transmitting inductor and the receiving inductor. The dielectric layer electrically insulates the transmitting inductor from the receiving inductor. Although this embodiment illustrates a case in which the insulating element 13 is an inductive type, the insulating element 13 may also be a capacitive type. An example of a capacitive insulating element is a capacitor.

[0020] The insulating element 13 has an element main surface 131 and an element back surface 132 facing opposite to each other in the z direction. The element main surface 131 faces the z1 side in the z direction. The element back surface 132 faces the z2 side in the z direction. A plurality of first electrodes 13A and a plurality of second electrodes 13B are provided on the element main surface 131. Each of the plurality of first electrodes 13A and the plurality of second electrodes 13B is electrically connected to either the transmitting inductor or the receiving inductor. In the insulating element 13, the plurality of first electrodes 13A are arranged along the y direction near the x1 side in the x direction. The plurality of second electrodes 13B are arranged along the y direction near the center in the x direction.

[0021] The first semiconductor element 11 transmits a PWM control signal to the second semiconductor element 12 via the insulating element 13. The first semiconductor element 11 may transmit a signal other than the PWM control signal to the second semiconductor element 12. The second semiconductor element 12 transmits an electrical signal to the first semiconductor element 11 via the insulating element 13. The information indicated by the electrical signal transmitted from the second semiconductor element 12 to the first semiconductor element 11 is not limited.

[0022] Motor driver circuits in inverter devices, such as those used in hybrid vehicles, typically use half-bridge circuits, in which low-side and high-side switching elements are connected in a totem-pole configuration. In an isolated gate driver, only one of the low-side or high-side switching elements is turned on at any given time. In the high-voltage region, the source of the low-side switching element and the reference potential of the isolated gate driver that drives that switching element are connected to ground, so the gate-source voltage operates based on ground. Meanwhile, the source of the high-side switching element and the reference potential of the isolated gate driver that drives that switching element are connected to the output node of the half-bridge circuit. The potential of the output node of the half-bridge circuit changes depending on whether the low-side or high-side switching element is on, so the reference potential of the isolated gate driver that drives the high-side switching element also changes. When the high-side switching element is on, the reference potential becomes a voltage equivalent to the voltage applied to the drain of the high-side switching element (e.g., 600 V or higher). The first semiconductor element 11 and the second semiconductor element 12 are isolated from each other by ground to ensure insulation. When the semiconductor device A10 is used as an isolated gate driver that drives a high-side switching element, a voltage of 600 V or more is transiently applied to the second semiconductor element 12 compared to the ground of the first semiconductor element 11. Because a significant potential difference occurs between the first semiconductor element 11 and the second semiconductor element 12, in the semiconductor device A10, the input side circuit including the second semiconductor element 12 and the output side circuit including the first semiconductor element 11 are insulated by the insulating element 13. In other words, the insulating element 13 insulates the input side circuit, which has a relatively low potential, from the output side circuit, which has a relatively high potential.

[0023] In the semiconductor device A10, the conductive member 2 is a member that forms a conductive path between the first semiconductor element 11 and the second semiconductor element 12 and the wiring board of the inverter device. The conductive member 2 is made of, for example, an alloy containing Cu. The conductive member 2 is formed from a lead frame 81, which will be described later. The first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 are mounted on the conductive member 2. As shown in FIG. 2 , the conductive member 2 includes a first die pad 3, a second die pad 4, a plurality of first terminals 51, a plurality of second terminals 52, a plurality of pad portions 53 and 55, a pair of connecting portions 54, and a pair of connecting portions 56.

[0024] The first die pad 3 is disposed in the center of the semiconductor device A10 in the y direction, closer to the x1 side in the x direction. The second die pad 4 is disposed on the x2 side of the first die pad 3 in the x direction, spaced apart from the first die pad 3.

[0025] As shown in FIGS. 2 and 5 , the first die pad 3 has the first semiconductor element 11 and the insulating element 13 mounted thereon. The first die pad 3 is electrically connected to the first semiconductor element 11 and is one element of the input circuit described above. The first die pad 3 has, for example, a rectangular (or substantially rectangular) shape when viewed in the z direction. The first die pad 3 has a main surface 31 and a back surface 32. The main surface 31 and the back surface 32 are spaced apart from each other in the z direction as shown in FIGS. 5 and 6 . The main surface 31 faces the z1 side, and the back surface 32 faces the z2 side. The first semiconductor element 11 and the insulating element 13 are mounted on the main surface 31.

[0026] 6 and 8 , the first semiconductor element 11 and the insulating element 13 are bonded to the main surface 31 of the first die pad 3 by a conductive bonding material 19. In this embodiment, the conductive bonding material 19 is, for example, solder. However, the conductive bonding material 19 is not limited to this and may be a metal paste, a sintered metal, or the like.

[0027] As shown in FIGS. 2 and 5 , the second die pad 4 has the second semiconductor element 12 mounted thereon. The second die pad 4 is electrically connected to the second semiconductor element 12 and is one element of the output circuit described above. The second die pad 4 has, for example, a rectangular (or substantially rectangular) shape when viewed in the z direction. The second die pad 4 has a main surface 41 and a back surface 42. The main surface 41 and the back surface 42 are spaced apart from each other in the z direction as shown in FIG. 5 . The main surface 41 faces the z1 side, and the back surface 42 faces the z2 side. The second semiconductor element 12 is mounted on the main surface 41.

[0028] The multiple first terminals 51 are bonded to a wiring board of an inverter device to form a conductive path between the semiconductor device A10 and the wiring board. Each first terminal 51 is appropriately electrically connected to the first semiconductor element 11 and is an element of the aforementioned input circuit. As shown in FIGS. 1, 2, and 4, the multiple first terminals 51 are spaced apart from one another and arranged at equal intervals along the y direction. Each of the multiple first terminals 51 is located on the x1 side of the x direction relative to the first die pad 3 and protrudes from the sealing resin 7 (the resin side surface 73 described below) toward the x1 side in the x direction. The multiple first terminals 51 include a power supply terminal to which a voltage is supplied, a ground terminal, an input terminal to which a control signal is input, an input terminal to which other electrical signals are input, and an output terminal to which other electrical signals are output. In this embodiment, the semiconductor device A10 includes ten first terminals 51. The number of first terminals 51 is not limited. Furthermore, the signals input and output by each first terminal 51 are not limited.

[0029] Each first terminal 51 has an elongated rectangular shape extending along the x direction, and includes a portion exposed from the sealing resin 7 and a portion covered by the sealing resin 7. As shown in Figures 3 and 5 , the portion of each first terminal 51 exposed from the sealing resin 7 is bent into a gull-wing shape bent toward the z-direction z2.

[0030] As shown in FIGS. 7 and 8 , each first terminal 51 has a tip surface 511, a bottom surface 512, and a recess 513. The tip surface 511 is the end surface of the first terminal 51 that protrudes from the sealing resin 7. The tip surface 511 is a cross section formed by cutting the lead frame in a cutting process described below. The bottom surface 512 is the surface that faces and is bonded to a wiring board of an inverter device when the semiconductor device A10 is surface-mounted on the wiring board, and faces the z-direction z2. The recess 513 is recessed from the tip surface 511 toward the x-direction x2 and from the bottom surface 512 toward the z-direction z1. The z-direction dimension T1 of the recess 513 is between ¼ and ¾ of the z-direction dimension T2 of the total thickness portion 514, which is the portion of the first terminal 51 where the bottom surface 512 is located. The x-direction dimension of the recess 513 is not particularly limited, but is approximately the same as dimension T1. In this embodiment, the recess 513 extends over the entire first terminal 51 in the y direction.

[0031] A plating layer 25 is disposed on the entire portion of the first terminal 51 exposed from the sealing resin 7, except for the tip surface 511. In FIG. 8 , the plating layer 25 is indicated by dotted lines. The region where the plating layer 25 is disposed is not limited. The plating layer 25 may contain, for example, Sn. The constituent material of the plating layer 25 is not limited. The plating layer 25 improves solder adhesion to the exposed portion while preventing erosion of the exposed portion due to solder bonding when the semiconductor device A10 is surface-mounted on a wiring board of an inverter device by solder bonding. The plating layer 25 includes a recess plating portion 25a. The recess plating portion 25a is disposed in the recess 513. In this embodiment, as described below, a recess is formed in the lead frame before the plating layer 25 is formed during the manufacturing process. Therefore, the recess plating portion 25a is disposed over the entire recess 513. It is sufficient that the recess plating portion 25a is disposed in at least a portion of the recess 513.

[0032] As shown in FIGS. 3 , 5 , and 9 , each first terminal 51 includes a first bent portion 516 and a second bent portion 517. The first bent portion 516 and the second bent portion 517 are portions of the first terminal 51 exposed from the sealing resin 7 and formed by bending. The first bent portion 516 is a portion bent in the z-direction z2. As shown in FIG. 9 , the minimum value R1 of the radius of curvature of the inner surface of the first bent portion 516 is equal to or greater than the dimension T2 in the z-direction of the total thickness portion 514 of the first terminal 51 (the portion of the first terminal 51 where the bottom surface 512 is located) (i.e., the thickness dimension of the first terminal 51). The second bent portion 517 is located between the first bent portion 516 and the tip surface 511 and is a portion bent in the x-direction x1. As shown in FIG. 9, the minimum value R2 of the radius of curvature of the inner surface of the second bent portion 517 is also equal to or greater than the dimension T2 of the total thickness portion 514 of the first terminal 51 in the z direction.

[0033] The plurality of first terminals 51 include a first terminal 51 a and a first terminal 51 b. The first terminal 51 a is arranged closest to the y1 side in the y direction among the plurality of first terminals 51. The first terminal 51 b is arranged closest to the y2 side in the y direction among the plurality of first terminals 51.

[0034] The pads 53 are connected to the first terminals 51 other than the first terminals 51a and 51b on the x2 side in the x direction. The shape of each pad 53 as viewed in the z direction is not limited. The top surface (the surface facing the z1 side) of each pad 53 is flat (or substantially flat) and is bonded to a wire 61 (described later). The top surface of each pad 53 may be plated. A plating layer formed by this plating process is made of a metal containing Ag, for example, and covers the top surface of the pad 53. The plating layer increases the bonding strength of the wire 61 while protecting the lead frame 81 (described later) from impact during wire bonding of the wire 61. The pad 53 is entirely covered with a sealing resin 7.

[0035] Each of the pair of connection portions 54 is connected to the first terminal 51a or the first terminal 51b and the first die pad 3. The connection portion 54 connected to the first terminal 51a extends in the y direction, with its end on the y2 side in the y direction connected to the end of the first die pad 3 on the y1 side in the y direction near the center in the x direction of the end of the first die pad 3 on the y1 side in the y direction. The connection portion 54 connected to the first terminal 51b extends in the y direction, with its end on the y1 side in the y direction connected to the end of the first die pad 3 on the y2 side in the y direction near the center in the x direction of the end of the first die pad 3 on the y2 side in the y direction. In this way, the first terminal 51a and the first terminal 51b are connected to the first die pad 3 via the pair of connection portions 54 and support the first die pad 3. The upper surface (the surface facing the z1 side) of each connection portion 54 is flat (or approximately flat), and a wire 61 (described later) is bonded to the upper surface of each connection portion 54. Like the upper surface of the pad portion 53, the upper surface of each connection portion 54 may be covered with a plating layer (e.g., a metal containing Ag). The entire surface of the connection portion 54 is covered with the sealing resin 7.

[0036] Like the first terminals 51, the second terminals 52 are bonded to the wiring board of the inverter device to form a conductive path between the semiconductor device A10 and the wiring board. Each second terminal 52 is appropriately electrically connected to the second semiconductor element 12 and is an element of the aforementioned output circuit. As shown in FIGS. 1 and 2 , the second terminals 52 are spaced apart from one another and arranged at equal intervals along the y direction. Each of the second terminals 52 is located on the x2 side of the second die pad 4 in the x direction and protrudes from the sealing resin 7 (the resin side surface 74 described below) toward the x2 side in the x direction. The second terminals 52 include a power supply terminal for supplying a voltage, a ground terminal, an output terminal for outputting a drive signal, an input terminal for inputting other electrical signals, and an output terminal for outputting other electrical signals. In this embodiment, the semiconductor device A10 includes ten second terminals 52. The number of second terminals 52 is not limited. Furthermore, the signals input and output by each second terminal 52 are not limited.

[0037] Each second terminal 52 has an elongated rectangular shape extending along the x direction, and includes a portion exposed from the sealing resin 7 and a portion covered by the sealing resin 7. As shown in Figures 3 and 5 , the portion of each second terminal 52 exposed from the sealing resin 7 is bent into a gull-wing shape bent toward the z-direction z2.

[0038] As shown in FIG. 5 , each second terminal 52 has a tip surface 521, a bottom surface 522, and a recess 523. The tip surface 521 is the end surface of the second terminal 52 that protrudes from the sealing resin 7. The tip surface 521 is a cross section formed by cutting the lead frame in a cutting process described below. The bottom surface 522 is the surface that faces and is bonded to a wiring board of an inverter device when the semiconductor device A10 is surface-mounted on the wiring board, and faces the z-direction z2. The recess 523 is recessed from the tip surface 521 toward the x-direction x1 and from the bottom surface 522 toward the z-direction z1. As with the first terminal 51, the z-direction dimension of the recess 523 is between ¼ and ¾ of the z-direction dimension of the total thickness portion 524 of the second terminal 52, which is the portion where the bottom surface 522 is located. The x-direction dimension of the recess 523 is not particularly limited, but is approximately the same as the z-direction dimension. In this embodiment, the recess 523 extends over the entire second terminal 52 in the y direction.

[0039] Of the portion of the second terminal 52 exposed from the sealing resin 7, the plating layer 25 is disposed on the entire surface except for the tip surface 521, similar to the first terminal 51. Note that the region where the plating layer 25 is disposed is not limited to the above. Similar to the recess 513, the recess 523 also has a recess plating portion 25a disposed therein.

[0040] 3 and 5 , each second terminal 52 includes a first bent portion 526 and a second bent portion 527. The first bent portion 526 and the second bent portion 527 are portions of the second terminal 52 exposed from the sealing resin 7 and formed by bending. The first bent portion 526 is a portion bent toward the z-direction z2. The minimum value of the radius of curvature of the inner surface of the first bent portion 526 is equal to or greater than the dimension in the z-direction of the total thickness portion 524 of the second terminal 52 (i.e., the thickness dimension of the second terminal 52). The second bent portion 527 is located between the first bent portion 526 and the tip surface 521 and is a portion bent toward the x-direction x2. The minimum value of the radius of curvature of the inner surface of the second bent portion 527 is also equal to or greater than the dimension in the z-direction of the total thickness portion 524 of the second terminal 52.

[0041] The plurality of second terminals 52 include second terminal 52a and second terminal 52b. The second terminal 52a is arranged second from the y1 side in the y direction among the plurality of second terminals 52. The second terminal 52b is arranged second from the y2 side in the y direction among the plurality of second terminals 52.

[0042] The pads 55 are connected to the second terminals 52 other than the second terminals 52a and 52b on the x1 side in the x direction. The shape of each pad 55 as viewed in the z direction is not limited. The top surface of each pad 55 (the surface facing the z1 side) is flat (or approximately flat), and a wire 62 (described later) is bonded to it. The top surface of each pad 55 may be covered with a plating layer (e.g., a metal containing Ag), similar to the top surface of the pad 53. The pads 55 are entirely covered with sealing resin 7.

[0043] Each of the pair of connection portions 56 is connected to the second terminal 52a or the second terminal 52b and the second die pad 4. The end of the connection portion 56 connected to the second terminal 52a on the y2 side in the y direction is connected to the end of the second die pad 4 on the y1 side in the y direction near the center in the x direction of the end of the second die pad 4 on the y2 side in the y direction. The end of the connection portion 56 connected to the second terminal 52b on the y1 side in the y direction is connected to the end of the second die pad 4 on the y2 side in the y direction near the center in the x direction of the end of the second die pad 4 on the y2 side in the y direction. In this way, the second terminal 52a and the second terminal 52b are connected to the second die pad 4 via the pair of connection portions 56 and support the second die pad 4. The upper surface (the surface facing the z1 side) of each connection portion 56 is flat (or approximately flat) and is connected to a wire 62 (described later). The upper surface of each connection portion 56 may be covered with a plating layer (e.g., a metal containing Ag), similar to the upper surface of the pad portion 53. The entire surface of the connection portion 56 is covered with the sealing resin 7.

[0044] The shape of the conductive member 2 is not limited to the above. For example, the first die pad 3 may be supported by any of the first terminals 51. That is, the pair of connection portions 54 may be connected to the first die pad 3 and any of the first terminals 51. Furthermore, the second die pad 4 may be supported by any of the second terminals 52. That is, the pair of connection portions 56 may be connected to any of the second terminals 52 and the second die pad 4.

[0045] 2, the plurality of wires 61 to 64, together with the conductive member 2, form a conductive path that enables the first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 to perform predetermined functions. The material of each of the plurality of wires 61 to 64 is a metal containing, for example, Au, Cu, or Al.

[0046] As shown in Figures 2 and 5, the multiple wires 61 form a conductive path between the first semiconductor element 11 and the multiple first terminals 51. The multiple wires 61 electrically connect the first semiconductor element 11 to at least one of the multiple first terminals 51. The multiple wires 61 are one element of the input side circuit described above. As shown in Figure 2, one end of each of the multiple wires 61 is conductively connected to one of the electrodes 11A of the first semiconductor element 11, and the other end is conductively connected to one of the multiple pad portions 53 and a pair of connecting portions 54. The number of wires 61 connected to each pad portion 53 and each connecting portion 54 is not limited.

[0047] 2 and 5, the plurality of wires 62 form a conductive path between the second semiconductor element 12 and the plurality of second terminals 52. The plurality of wires 62 electrically connect the second semiconductor element 12 to at least one of the plurality of second terminals 52. The plurality of wires 62 are elements of the output circuit described above. As shown in FIG. 2, one end of each of the plurality of wires 62 is electrically connected to one of the electrodes 12A of the second semiconductor element 12, and the other end is electrically connected to one of the plurality of pad portions 55 and a pair of connecting portions 56. The number of wires 62 connected to each pad portion 55 and each connecting portion 54 is not limited.

[0048] 2 and 5, the plurality of wires 63 form a conductive path between the first semiconductor element 11 and the insulating element 13. The plurality of wires 63 electrically connect the first semiconductor element 11 and the insulating element 13. The plurality of wires 63 are elements of the input-side circuit described above. As shown in FIG. 2, each of the plurality of wires 63 is electrically connected to one of the electrodes 11A of the first semiconductor element 11 and one of the first electrodes 13A of the insulating element 13.

[0049] 2 and 5, the plurality of wires 64 form a conductive path between the second semiconductor element 12 and the insulating element 13. The second semiconductor element 12 and the insulating element 13 are electrically connected to each other by the plurality of wires 64. The plurality of wires 64 is one element of the output side circuit described above. As shown in FIG. 2, each of the plurality of wires 64 is electrically connected to one of the electrodes 12A of the second semiconductor element 12 and one of the second electrodes 13B of the insulating element 13.

[0050] 1 , the sealing resin 7 covers the first semiconductor element 11, the second semiconductor element 12, the insulating element 13, the first die pad 3, the second die pad 4, the pair of connecting portions 54, the pair of connecting portions 56, the plurality of pad portions 53, 55, the plurality of wires 61 to 64, and a portion of each of the plurality of first terminals 51 and second terminals 52. The sealing resin 7 has electrical insulation properties. The sealing resin 7 is made of a material containing, for example, black epoxy resin. The sealing resin 7 is rectangular when viewed in the z direction.

[0051] As shown in FIGS. 3 and 4, the sealing resin 7 has a resin top surface 71, a resin bottom surface 72, and resin side surfaces 73 to .

[0052] The resin top surface 71 and the resin bottom surface 72 are located apart from each other in the z direction. The resin top surface 71 and the resin bottom surface 72 face opposite each other in the z direction. The resin top surface 71 is located on the z1 side in the z direction and faces the z1 side, just like the main surface 31 of the first die pad 3. The resin bottom surface 72 is located on the z2 side in the z direction and faces the z2 side, just like the back surface 32 of the first die pad 3. Each of the resin top surface 71 and the resin bottom surface 72 is flat (or approximately flat).

[0053] Each of the resin side surfaces 73 to 76 is connected to the resin top surface 71 and the resin bottom surface 72 and is sandwiched between the resin top surface 71 and the resin bottom surface 72 in the z direction. The resin side surface 73 and the resin side surface 74 are spaced apart from each other in the x direction. The resin side surface 73 and the resin side surface 74 face opposite each other in the x direction. The resin side surface 73 is located on the x1 side of the x direction, and the resin side surface 74 is located on the x2 side of the x direction. The resin side surface 75 and the resin side surface 76 are spaced apart from each other in the y direction and are connected to the resin side surface 73 and the resin side surface 74. The resin side surface 75 and the resin side surface 76 face opposite each other in the y direction. The resin side surface 75 is located on the y1 side of the y direction, and the resin side surface 76 is located on the y2 side of the y direction. As shown in FIG. 1 , a portion of each of the multiple first terminals 51 protrudes from the resin side surface 73. Furthermore, a portion of each of the multiple second terminals 52 protrudes from the resin side surface 74.

[0054] As shown in FIGS. 3 and 4 , the resin side surface 73 includes a resin first region 731, a resin second region 732, and a resin third region 733. One end of the resin first region 731 in the z direction is connected to the resin top surface 71, and the other end in the z direction is connected to the resin third region 733. The resin first region 731 is inclined with respect to the resin top surface 71 and the yz plane. One end of the resin second region 732 in the z direction is connected to the resin bottom surface 72, and the other end in the z direction is connected to the resin third region 733. The resin second region 732 is inclined with respect to the resin bottom surface 72 and the yz plane. One end of the resin third region 733 in the z direction is connected to the resin first region 731, and the other end in the z direction is connected to the resin second region 732. The resin third region 733 is aligned along the yz plane. When viewed in the z direction, the third resin region 733 is located outward from the resin top surface 71 and the resin bottom surface 72. From the third resin region 733, a portion of each of the plurality of first terminals 51 is exposed.

[0055] As shown in FIG. 3 , the resin side surface 74 includes a fourth resin region 741, a fifth resin region 742, and a sixth resin region 743. One end of the fourth resin region 741 in the z direction is connected to the resin top surface 71, and the other end in the z direction is connected to the sixth resin region 743. The fourth resin region 741 is inclined with respect to the resin top surface 71 and the yz plane. One end of the fifth resin region 742 in the z direction is connected to the bottom resin surface 72, and the other end in the z direction is connected to the sixth resin region 743. The fifth resin region 742 is inclined with respect to the bottom resin surface 72 and the yz plane. One end of the sixth resin region 743 in the z direction is connected to the fourth resin region 741, and the other end in the z direction is connected to the fifth resin region 742. The sixth resin region 743 is aligned along the yz plane. When viewed in the z direction, the sixth resin region 743 is located outward from the resin top surface 71 and the resin bottom surface 72. From the sixth resin region 743, a portion of each of the plurality of second terminals 52 is exposed.

[0056] As shown in FIG. 4 , the resin side surface 75 includes a seventh resin region 751, an eighth resin region 752, and a ninth resin region 753. The seventh resin region 751 has one end in the z direction connected to the resin top surface 71 and the other end in the z direction connected to the ninth resin region 753. The seventh resin region 751 is inclined with respect to the resin top surface 71 and the xz plane. The eighth resin region 752 has one end in the z direction connected to the resin bottom surface 72 and the other end in the z direction connected to the ninth resin region 753. The eighth resin region 752 is inclined with respect to the resin bottom surface 72 and the xz plane. The ninth resin region 753 has one end in the z direction connected to the seventh resin region 751 and the other end in the z direction connected to the eighth resin region 752. The ninth resin region 753 is aligned along the xz plane. When viewed in the z direction, the ninth resin region 753 is located outward from the resin top surface 71 and the resin bottom surface 72 .

[0057] As shown in FIGS. 3 and 4 , the resin side surface 76 includes a tenth resin region 761, an eleventh resin region 762, and a twelfth resin region 763. One end of the tenth resin region 761 in the z direction is connected to the resin top surface 71, and the other end in the z direction is connected to the twelfth resin region 763. The tenth resin region 761 is inclined with respect to the resin top surface 71 and the xz plane. The eleventh resin region 762 is inclined with respect to the resin bottom surface 72 and the xz plane. The twelfth resin region 763 is inclined with respect to the tenth resin region 761 and the xz plane. One end of the twelfth resin region 763 in the z direction is connected to the tenth resin region 761, and the other end in the z direction is connected to the eleventh resin region 762. The twelfth resin region 763 is aligned along the xz plane. When viewed in the z direction, the twelfth resin region 763 is located outward from the resin top surface 71 and the resin bottom surface 72 .

[0058] Next, an example of a method for manufacturing the semiconductor device A10 will be described below with reference to FIGS. 10 to 20. FIGS. 10, 13, and 14 are plan views showing steps in the method for manufacturing the semiconductor device A10. FIG. 11 is a bottom view showing steps in the method for manufacturing the semiconductor device A10. FIGS. 12, 15 to 16, and 18 to 19 are cross-sectional views showing steps in the method for manufacturing the semiconductor device A10, and show cross sections corresponding to the cross section along line V-V in FIG. 2. FIG. 17 is a partial enlarged view of FIG. 16. FIG. 20 is a partial enlarged view of FIG. 19. Note that the x, y, and z directions shown in these figures are the same as those in FIGS. 1 to 8.

[0059] First, as shown in FIGS. 10 to 12 , a lead frame 81 is prepared. The lead frame 81 is a plate-shaped material. In this embodiment, the base material of the lead frame 81 is Cu. The lead frame 81 may be formed by etching a metal plate or by punching a metal plate. In this embodiment, the lead frame 81 is formed by etching. The lead frame 81 has a main surface 81A and a back surface 81B that are spaced apart in the z direction. The lead frame 81 also includes an outer frame 811, a first die pad 812A, a second die pad 812B, a plurality of first leads 813, a plurality of second leads 814, a plurality of connection portions 815, and a dam bar 816. Of these, the outer frame 811 and the dam bar 816 do not constitute the semiconductor device A10. The first die pad 812A is a portion that will later become the first die pad 3. The second die pad 812B is a portion that will later become the second die pad 4. The plurality of first leads 813 are portions that will later become the plurality of first terminals 51 and pad portions 53. The plurality of second leads 814 are portions that will later become the plurality of second terminals 52 and pad portions 55. The plurality of connecting portions 815 are portions that will later become a pair of connecting portions 54 and a pair of connecting portions 56.

[0060] As shown in FIGS. 11 and 12 , a terminal portion 813a of the first lead 813, including a portion that will become the first terminal 51, has a recess 813b formed therein, and a terminal portion 814a of the second lead 814, including a portion that will become the second terminal 52, has a recess 814b formed therein. In FIG. 11 , the recesses 813b and 814b are indicated by dotted lines. The recesses 813b and 814b are recessed from the rear surface 81B toward the z-direction z1. The recesses 813b and 814b are formed by, for example, half etching. Note that the method for forming the recesses 813b and 814b is not limited. Each recess 813b extends across the entire terminal portion 813a in the y-direction. Each recess 814b extends across the entire terminal portion 814a in the y-direction.

[0061] 13, the first semiconductor element 11 and the insulating element 13 are bonded to the first die pad 812A by die bonding, and the second semiconductor element 12 is bonded to the second die pad 812B by die bonding. Next, each of the plurality of wires 61 to 64 is formed by wire bonding.

[0062] Next, as shown in FIGS. 14 and 15 , the sealing resin 7 is formed. The sealing resin 7 is formed by transfer molding. In this process, the lead frame 81 is placed in a mold having multiple cavities. At this time, the portion of the lead frame 81 that will become the conductive member 2 covered by the sealing resin 7 in the semiconductor device A10 is placed in one of the multiple cavities. Then, fluidized resin is poured from the pot through a runner into each of the multiple cavities. After the fluidized sealing resin 7 solidifies in the multiple cavities, resin burrs located outside each of the multiple cavities are removed using high-pressure water or the like. This completes the formation of the sealing resin 7.

[0063] Next, the plating layer 25 is formed on the lead frame 81 exposed from the sealing resin 7. As a result, the plating layer 25 is disposed on the terminal portion 813a and the terminal portion 814a. At this time, the plating layer 25 is also disposed in the recessed portion 813b of the terminal portion 813a and the recessed portion 814b of the terminal portion 814a.

[0064] Next, as shown in FIGS. 16 and 17 , the lead frame 81 is bent. In this step, the terminal portions 813a and 814a are bent using a forming mold 86. The forming mold 86 includes a forming die 861, a forming punch 862, and a stripper block 863. The lead frame 81 covered with the sealing resin 7 is placed on the forming die 861. The stripper block 863 presses and fixes the terminal portions 813a and 814a between itself and the forming die 861. The forming punch 862 then moves in the z-direction z2, thereby bending the terminal portions 813a and 814a. As a result, as shown in FIG. 18 , the terminal portions 813a and 814a are formed into a gull-wing shape bent toward the z-direction z2.

[0065] As shown in FIG. 17 , the terminal portion 813a of the lead frame 81 is bent at a portion that abuts against the shoulder portion 861a of the forming die 861, thereby forming a first bent portion 813c. The first bent portion 813c becomes the first bent portion 516. The minimum value R3 of the radius of curvature of the shoulder portion 861a of the forming die 861 is equal to or greater than the thickness dimension T2 of the lead frame 81. As a result, the minimum value R1 (see FIG. 9 ) of the radius of curvature of the inner surface of the first bent portion 813c becomes equal to or greater than the thickness dimension T2 of the lead frame 81. Furthermore, the terminal portion 813a is bent at a portion that abuts against the shoulder portion 862a of the forming punch 862, thereby forming a second bent portion 813d. The second bent portion 813d becomes the second bent portion 517. The minimum value R4 of the radius of curvature of the shoulder portion 862a of the forming punch 862 is equal to or greater than the thickness dimension T2 of the lead frame 81. As a result, the minimum value R2 (see FIG. 9 ) of the radius of curvature of the inner surface of second bent portion 813d is equal to or greater than the thickness dimension T2 of lead frame 81. Similar to terminal portion 813a, terminal portion 814a also has a first bent portion 814c and a second bent portion 814d formed therein. First bent portion 814c becomes first bent portion 526, and second bent portion 814d becomes second bent portion 527. The minimum value of the radius of curvature of the inner surface of first bent portion 814c and the minimum value of the radius of curvature of the inner surface of second bent portion 814d are also equal to or greater than the thickness dimension T2 of lead frame 81.

[0066] Next, as shown in FIGS. 19 and 20 , the lead frame 81 is cut. In this process, a cutting die 85 is used to cut the terminal portions 813a and 814a along the cutting lines CL shown in FIG. 18 . One cutting line CL intersects with each recess 813b and extends in the y direction. The other cutting line CL intersects with each recess 814b and extends in the y direction. In this embodiment, the cutting die 85 employs a so-called upper cut method, which cuts the terminal portions 813a and 814a from the z2 side in the z direction. The cutting die 85 includes a cutting die 851, a cutting punch 852, and a stripper block 853. The lead frame 81 covered with the sealing resin 7 is placed on the stripper block 853. The cutting die 851 presses and fixes the terminal portions 813a and 814a between the cutting die 851 and the stripper block 853. The cut punch 852 is fixed, and the cut die 851 and the stripper block 853 move toward the z2 side in the z direction. As a result, the cut punch 852 moves from the z2 side to the z1 side in the z direction relative to the cut die 851 and the stripper block 853. The cut punch 852 cuts off the terminal portion 813a and the terminal portion 814a that protrude outside the cut die 851 between itself and the cut die 851. By cutting the terminal portion 813a, the first terminal 51 is separated from the first lead 813, and by cutting the terminal portion 814a, the second terminal 52 is separated from the second lead 814. As a result, the portion of the recess 813b that is located at the first terminal 51 becomes the recess 513, and the portion of the recess 814b that is located at the second terminal 52 becomes the recess 523.

[0067] By going through the steps described above, the semiconductor device A10 is manufactured.

[0068] 21 is an enlarged partial cross-sectional view showing the semiconductor device A10 mounted on the wiring substrate 9. The mounting of the semiconductor device A10 on the wiring substrate 9 will now be described.

[0069] 21 , the semiconductor device A10 is mounted on a wiring board 9, and a plurality of first terminals 51 and second terminals 52 are joined to wiring (not shown) formed on the wiring board 9 with solder 95. At this time, since the recess plated portion 25a is arranged in the recess 513 of the first terminal 51, the solder 95 also adheres to the recess 513, forming a solder fillet. Similarly, the second terminal 52 also has the recess plated portion 25a arranged in the recess 523, so the solder 95 also adheres to the recess 523, forming a solder fillet.

[0070] Next, the effects of the semiconductor device A10 will be described.

[0071] According to this embodiment, each first terminal 51 has a recess 513. The recess 513 is recessed from the tip surface 511 toward the x2 direction and from the bottom surface 512 toward the z1 direction. A recess plating portion 25a is disposed in the recess 513. Therefore, when the first terminal 51 is joined to the wiring board 9 with solder 95 during mounting of the semiconductor device A10, the solder 95 adheres to the recess 513 as well, forming a solder fillet. Similarly, the solder 95 adheres to the recess 523 of each second terminal 52 as well, forming a solder fillet. This allows the semiconductor device A10 to suppress poor solder adhesion when mounted on the wiring board 9.

[0072] Furthermore, according to this embodiment, the z-direction dimension T1 of the recess 513 is between ¼ and ¾ of the z-direction dimension T2 of the total thickness portion 514. Furthermore, the z-direction dimension of the recess 523 is between ¼ and ¾ of the z-direction dimension of the total thickness portion 524. Therefore, the semiconductor device A10 maintains the strength of the lead frame 81 in which the recesses 813b, 814b are formed during manufacturing, and can appropriately form solder fillets by the solder 95 attached to the recesses 513, 523 during mounting.

[0073] Furthermore, in this embodiment, the recess 513 extends in the y direction over the entire first terminal 51. Therefore, the solder fillet formed by the solder 95 adhering to the recess 513 has a shape that spreads more in the y direction compared to when the recess 513 is formed only on a portion of the first terminal 51 in the y direction. The same is true for the recess 523. This allows the semiconductor device A10 to further suppress poor solder adhesion when mounted on the wiring substrate 9.

[0074] Furthermore, according to the present embodiment, the minimum value R1 of the radius of curvature of the inner surface of the first bent portion 516 of the first terminal 51 is equal to or greater than the dimension T2 of the entire thickness 514 of the first terminal 51 in the z direction. The first terminal 51 is less likely to develop cracks and plating cracks at the first bent portion 516 during bending, compared to when the minimum value R1 of the radius of curvature of the inner surface of the first bent portion 516 is less than the dimension T2. ​​The minimum value R2 of the radius of curvature of the inner surface of the second bent portion 517 of the first terminal 51 is also equal to or greater than the dimension T2 of the entire thickness 514 of the first terminal 51. The first terminal 51 is less likely to develop cracks and plating cracks at the second bent portion 517 during bending, compared to when the minimum value R2 of the radius of curvature of the inner surface of the second bent portion 517 is less than the dimension T2. Similarly, the minimum value of the radius of curvature of the inner surface of the first bent portion 526 and the second bent portion 527 of the second terminal 52 is equal to or greater than the dimension in the z direction of the total thickness portion 524 of the second terminal 52. Therefore, the occurrence of cracks and plating breakage in the first bent portion 526 and the second bent portion 527 of the second terminal 52 during bending is also suppressed.

[0075] Furthermore, according to this embodiment, the minimum value R3 of the radius of curvature of the shoulder portion 861a of the forming die 861 of the forming mold 86 is equal to or greater than the thickness dimension T2 of the lead frame 81. This allows the forming mold 86 to form the minimum value R1 of the radius of curvature of the inner surface of the first bent portion 813c (516) to be equal to or greater than the thickness dimension T2 of the lead frame 81. Furthermore, the minimum value R4 of the radius of curvature of the shoulder portion 862a of the forming punch 862 is equal to or greater than the thickness dimension T2 of the lead frame 81. This allows the forming mold 86 to form the minimum value R2 of the radius of curvature of the inner surface of the second bent portion 813d (517) to be equal to or greater than the thickness dimension T2 of the lead frame 81. Similarly, the forming mold 86 can form the minimum value of the radius of curvature of the inner surface of the first bend portion 814c (526) to be equal to or greater than the thickness dimension T2 of the lead frame 81, and can form the minimum value of the radius of curvature of the inner surface of the second bend portion 814d (527) to be equal to or greater than the thickness dimension T2 of the lead frame 81.

[0076] In the present embodiment, the cutting die 85 employs an upper-cut method, but this is not limiting. The cutting die 85 may employ a so-called down-cut method, in which the terminal portion 813a and the terminal portion 814a are cut from the z-direction z1 side. Because the first terminal 51 (second terminal 52) has the recess 513 (recess 523), even if a burr protruding toward the z-direction z2 side occurs due to the down-cut method, it does not interfere with bonding the first terminal 51 (second terminal 52) to the wiring substrate 9.

[0077] There are no particular limitations on the package format of the semiconductor device A10, the type and number of semiconductor elements mounted thereon, the shape and arrangement of the conductive member 2, the number of terminals, etc. The semiconductor device A10 may be any type as long as the terminals protrude from the sealing resin 7 and are surface-mounted on a wiring board or the like.

[0078] 22 to 27 show modified examples of the semiconductor device A10 according to the first embodiment. In these figures, elements that are the same as or similar to those in the above embodiment are given the same reference numerals as those in the above embodiment, and redundant explanations will be omitted.

[0079] First Modification: FIGS. 22 and 23 are diagrams illustrating a semiconductor device A11 according to a first modification of the first embodiment. FIG. 22 is a partially enlarged left side view of the semiconductor device A11, corresponding to FIG. 8 . FIG. 23 is a partially enlarged bottom view of the first terminal 51 as viewed from the z2 side in the z direction. In FIGS. 22 and 23 , the plating layer 25 is dotted. The semiconductor device A11 differs from the semiconductor device A10 in the range in which the recess 513 is formed. The recess 513 according to this modification is formed only in a central portion of the first terminal 51 in the y direction. Therefore, the bottom surface 512 is connected to the tip surface 511 on both sides of the recess 513 in the y direction. The recess 513 according to this modification can be formed by forming the recess 813b only in the center of the terminal portion 813a in the y direction, rather than forming it throughout the entire y direction.

[0080] Second Modification: FIGS. 24 and 25 are diagrams illustrating a semiconductor device A12 according to a second modification of the first embodiment. FIG. 24 is a partially enlarged left side view of the semiconductor device A12, corresponding to FIG. 8 . FIG. 25 is a partially enlarged bottom view of the first terminal 51 as viewed from the z2 side in the z direction. In FIGS. 24 and 25 , the plating layer 25 is dotted. The semiconductor device A12 differs from the semiconductor device A10 in the range in which the recess 513 is formed. The recess 513 according to this modification is divided into two parts, each formed at both ends of the first terminal 51 in the y direction. Therefore, at the center of the recess 513 in the y direction, the bottom surface 512 is connected to the tip surface 511. The recess 513 according to this modification can be formed by forming the recess 813b only at both ends of the terminal portion 813a in the y direction, rather than forming the recess 813b over the entire y direction of the lead frame 81.

[0081] As can be seen from the first and second modified examples, there are no limitations on the location and range of the recess 513. However, in order to prevent poor solder adhesion when mounted on the wiring substrate 9, it is desirable that the recess 513 extend over the entire first terminal 51 in the y direction, as in the semiconductor device A10.

[0082] Third Modification: FIGS. 26 and 27 are diagrams illustrating a semiconductor device A13 according to a third modification of the first embodiment. FIG. 26 is a partially enlarged left side view of the semiconductor device A13, corresponding to FIG. 8 . FIG. 27 is a partially enlarged bottom view of the first terminal 51 as viewed from the z-direction z2 side. In FIGS. 26 and 27 , the plating layer 25 is dotted. The recess 513 of the semiconductor device A13 is formed by stamping rather than half-etching. The recess 513 according to this modification is formed by displacing the constituent material to the periphery. Therefore, in the first terminal 51, the width dimension (y-direction dimension) W1 of the recess 513 is larger than the width dimension (y-direction dimension) W2 of the full-thickness portion 514 where the bottom surface 512 is located.

[0083] In the first embodiment, the recess 513 has a rectangular shape when viewed in the z direction, but this is not limiting. The recess 513 may have another shape, such as a semicircular shape, when viewed in the z direction.

[0084] 28 to 33 show other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are denoted by the same reference numerals as those in the above embodiment.

[0085] Second Embodiment: FIGS. 28 to 30 are diagrams illustrating a semiconductor device A20 according to a second embodiment of the present disclosure. FIG. 28 is a partially enlarged cross-sectional view showing the semiconductor device A20, and corresponds to FIG. 7 . FIG. 29 is a partially enlarged left side view showing the semiconductor device A20, and corresponds to FIG. 8 . FIG. 30 is a partially enlarged cross-sectional view showing a step in a manufacturing method for the semiconductor device A20, and corresponds to FIG. 20 . The semiconductor device A20 of this embodiment differs from the first embodiment in that a plating layer 25 is disposed on a portion of the front end surface 511. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that the parts of the first embodiment and each of the modifications described above may be combined in any desired manner.

[0086] In this embodiment, the plating layer 25 includes a tip plating portion 25b. The tip plating portion 25b is located on a portion of the tip surface 511. In FIG. 29, the plating layer 25 including the tip plating portion 25b is indicated by stippling. As shown in FIG. 30, the cutting punch 852 of the cutting mold 85 used in the cutting process has an edge portion 852a that cuts the terminal portion 813a. In this embodiment, the edge portion 852a has a curved surface. The edge portion 852a has a larger radius of curvature than the edge portion 851a of the cutting die 851 that cuts the terminal portion 813a. Therefore, when the terminal portion 813a is cut, a portion of the plating layer 25 (recess plating portion 25a) that was located in the recess 813b of the terminal portion 813a extends and is located as the tip plating portion 25b on the tip surface 511, which is a cross section of the terminal portion 813a. Similarly, the tip plating portion 25b is located on the tip surface 521.

[0087] Furthermore, in this embodiment, in the cutting process, terminal portion 813a and terminal portion 814a are cut from the z-direction z2 side by an upper-cut cutting die 85. Therefore, tip plated portion 25b is disposed on the z2 side of tip surface 511. As a result, tip plated portion 25b that is continuous with plating layer 25 (recess plated portion 25a) of recess 513 is disposed on tip surface 511. Similarly, tip plated portion 25b that is continuous with plating layer 25 (recess plated portion 25a) of recess 523 is disposed on tip surface 521. Furthermore, burrs 511c that protrude toward the z-direction z1 side are formed on tip surface 511, and as shown in FIG. 28 , the portion of tip surface 511 that connects to recess 513 is inclined with respect to the z direction.

[0088] In this embodiment, each first terminal 51 also has a recess 513, and a recess plated portion 25a is disposed in the recess 513. Therefore, when the semiconductor device A10 is mounted, solder 95 adheres to the recess 513 as well, forming a solder fillet. Similarly, solder 95 adheres to the recess 523 of each second terminal 52, forming a solder fillet. This prevents poor solder adhesion when the semiconductor device A20 is mounted on the wiring substrate 9. Furthermore, in this embodiment, the tip surface 511 (tip surface 521) is provided with a tip plated portion 25b that is continuous with the recess plated portion 25a disposed in the recess 513 (recess 523). This allows solder 95 to adhere to a portion of the tip surface 511 (tip surface 521), thereby more appropriately forming a solder fillet. Furthermore, by sharing a configuration common to the semiconductor device A10, the semiconductor device A20 achieves the same effects as the semiconductor device A10.

[0089] Third Embodiment: FIGS. 31 and 32 are diagrams illustrating a semiconductor device A30 according to a third embodiment of the present disclosure. FIG. 31 is a partially enlarged cross-sectional view showing the semiconductor device A30, and corresponds to FIG. 7. FIG. 32 is a partially enlarged left side view showing the semiconductor device A30, and corresponds to FIG. 8. The semiconductor device A30 of this embodiment differs from the second embodiment in that a plating layer 25 is disposed on the z-direction z1 side of the tip surface 511. The configuration and operation of other parts of this embodiment are similar to those of the second embodiment. Note that the parts of the first and second embodiments and their modified examples may be combined in any desired manner.

[0090] In this embodiment, the tip plating portion 25b is located on the z1 side of the tip surface 511 in the z direction. In FIG. 32 , the plating layer 25 including the tip plating portion 25b is dotted. In this embodiment, in the cutting process, a down-cutting die 85 uses a cut punch 852 to cut the terminal portion 813a and the terminal portion 814a from the z1 side in the z direction. By cutting the terminal portion 813a, a portion of the plating layer 25 located on the upper surface 515, which is the surface of the terminal portion 813a facing the z1 side in the z direction, extends and is located as the tip plating portion 25b on the tip surface 511, which is the cross section of the terminal portion 813a. Therefore, the tip plating portion 25b is located on the z1 side of the tip surface 511 in the z direction. Meanwhile, the z2 side of the tip surface 511 in the z direction is exposed from the tip plating portion 25b. The ratio of the area of ​​the tip surface 511 where the tip plating portion 25b is located to the area exposed from the tip plating portion 25b can be adjusted by the radius of curvature of the edge portion 852a of the cut punch 852 or the clearance between the cut die 851 and the cut punch 852. The tip plating portion 25b is similarly located on the tip surface 521. In addition, a burr 511c protruding toward the z-direction z2 is formed on the tip surface 511, and as shown in Figure 31, the portion of the tip surface 511 connected to the upper surface 515 is inclined with respect to the z-direction.

[0091] In this embodiment, each first terminal 51 also has a recess 513, and a recess plated portion 25a is disposed in the recess 513. Therefore, when the semiconductor device A10 is mounted, solder 95 adheres to the recess 513, forming a solder fillet. Similarly, solder 95 adheres to the recess 523 of each second terminal 52, forming a solder fillet. This prevents poor solder adhesion when the semiconductor device A30 is mounted on the wiring substrate 9. Furthermore, in this embodiment, the tip plated portion 25b is disposed on the z1 side of the tip surface 511 (tip surface 521), and the z2 side of the tip surface 511 (tip surface 521) in the z direction is exposed from the tip plated portion 25b. The tip surface 511 (tip surface 521) exposed from the tip plated portion 25b is less likely to receive solder 95. By increasing the exposed area of ​​tip surface 511 (tip surface 521) from tip plating portion 25b, it is possible to prevent a solder fillet from being formed on tip surface 511 (tip surface 521) beyond recess 513 (recess 523). Furthermore, by adopting a configuration common to semiconductor device A10, semiconductor device A30 achieves the same effects as semiconductor device A10.

[0092] Fourth Embodiment: FIG. 33 is a diagram illustrating a semiconductor device A40 according to a fourth embodiment of the present disclosure. FIG. 33 is a partially enlarged cross-sectional view showing the semiconductor device A40, and corresponds to FIG. 7. The semiconductor device A40 of this embodiment differs from the first embodiment in that a plating layer 25 is disposed over the entire surface of the tip surface 511. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that the parts of the first to third embodiments and their modified examples may be combined in any desired manner.

[0093] In this embodiment, the tip plating portion 25b is disposed over the entire tip surface 511 and tip surface 521. The manufacturing method of the semiconductor device A40 according to the fourth embodiment differs from that of the first embodiment. In the manufacturing method according to the fourth embodiment, after forming the sealing resin 7, the terminal portions 813a and 814a are bent and cut before forming the plating layer 25. After cutting the terminal portions 813a and 814a, the plating layer 25 is formed on the first terminals 51 and second terminals 52 exposed from the sealing resin 7. The plating layer 25 formed on the tip surface 511 and tip surface 521 is the tip plating portion 25b. Furthermore, the plating layer 25 formed on the recesses 513 and 523 is the recess plating portion 25a.

[0094] In this embodiment, each first terminal 51 also has a recess 513, and a recess plating portion 25a is disposed in the recess 513. Therefore, when the semiconductor device A10 is mounted, solder 95 adheres to the recess 513 as well, forming a solder fillet. Similarly, solder 95 adheres to the recess 523 of each second terminal 52, forming a solder fillet. This prevents poor solder adhesion when the semiconductor device A40 is mounted on the wiring substrate 9. Furthermore, according to this embodiment, the tip plating portion 25b is disposed over the entire tip surface 511 (tip surface 521). Since solder 95 adheres to the entire tip surface 511 (tip surface 521), a solder fillet can be formed that covers the tip surface 511 (tip surface 521). Furthermore, the semiconductor device A40, having a configuration common to the semiconductor device A10, achieves the same effects as the semiconductor device A10.

[0095] The semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure are not limited to the above-described embodiments. The specific configuration of each part of the semiconductor device according to the present disclosure and the specific processing of each step of the method for manufacturing the semiconductor device according to the present disclosure can be freely designed in various ways. The present disclosure includes the embodiments described in the following appendices.

[0096] Supplementary Note 1. A semiconductor device comprising: a semiconductor element (11); an encapsulating resin (7) covering the semiconductor element; a terminal (51) electrically connected to the semiconductor element and protruding from the encapsulating resin in a first direction (x direction) perpendicular to a thickness direction (z direction); and a plating layer (25) disposed on the terminal, wherein the terminal has a tip surface (511) that is an end surface protruding from the encapsulating resin, a first surface (512) facing a first side in the thickness direction (z direction z2 side), and a recess (513) recessed from both the tip surface and the first surface, and the plating layer includes a recess plating portion (25a) disposed in at least a portion of the recess. Supplementary Note 2. (Fig. 7) The semiconductor device according to Supplementary Note 1, wherein a first dimension (T1) in the thickness direction of the recess is between ¼ and ¾ of a second dimension (T2) in the thickness direction of a full thickness portion (514) where the first surface of the terminal is located. Supplementary Note 3. The semiconductor device according to Supplementary Note 1 or 2, wherein the plating layer includes a tip plating portion (25b) disposed on at least a portion of the tip surface. Supplementary Note 4. (Fourth embodiment, FIG. 33) The semiconductor device according to Supplementary Note 3, wherein the tip plating portion is disposed on the entire tip surface. Supplementary Note 5. (Second embodiment, FIGS. 28 and 29) The semiconductor device according to Supplementary Note 3, wherein the tip plating portion is located on the first side of the tip surface. Supplementary Note 6. (Third embodiment, FIGS. 31 and 32) The semiconductor device according to Supplementary Note 3, wherein the tip plating portion is located on a second side (z1 side in the z direction) opposite to the first side of the tip surface. Supplementary Note 7. The semiconductor device according to any of Supplements 1 to 6, wherein the recess extends over the entire terminal in a second direction (y direction) orthogonal to the thickness direction and the first direction. Supplementary Note 8. (First and second modified examples of the first embodiment, FIGS. 22 to 25) The semiconductor device according to any one of Supplementary Notes 1 to 6, wherein the first surface is connected to the tip surface. Supplementary Note 9. (Third modified example of the first embodiment, FIG. 27) The semiconductor device according to any one of Supplementary Notes 1 to 8, wherein the dimension of the terminal in a second direction orthogonal to the thickness direction and the first direction is larger in a portion where the recess is located than in a portion where the first surface is located.Appendix 10. (Fig. 9) The semiconductor device according to any one of Appendixes 1 to 9, wherein the terminal further comprises a first bent portion (516) bent toward the first side in the thickness direction, and wherein a minimum value (R1) of a radius of curvature of an inner surface of the first bent portion is equal to or greater than a second dimension (T2) in the thickness direction of a total thickness portion where the first surface of the terminal is located. Appendix 11. (Fig. 9) The semiconductor device according to Appendix 10, wherein the terminal further comprises a second bent portion (517) located between the first bent portion and the tip surface, and wherein a minimum value (R2) of a radius of curvature of an inner surface of the second bent portion is equal to or greater than the second dimension. Appendix 12. The semiconductor device according to any one of Appendixes 1 to 11, wherein the plating layer contains Sn. Appendix 13. A method for manufacturing a semiconductor device, comprising the steps of: preparing a lead frame including terminal portions having a first surface facing a first side in a thickness direction and a recess recessed from the first surface in the thickness direction; forming a plating layer on the terminal portions; and cutting the terminal portions along a cutting line intersecting the recess using a cutting mold. Appendix 14. A method for manufacturing a semiconductor device according to Appendix 13, wherein the cutting mold comprises a cutting die and a cutting punch, and the cutting punch cuts the terminal portions from the first side. Appendix 15. A method for manufacturing a semiconductor device according to Appendix 13, wherein the cutting mold comprises a cutting die and a cutting punch, and the cutting punch cuts the terminal portions from a second side opposite the first side in the thickness direction. Appendix 16. A method for manufacturing a semiconductor device according to Appendix 14 or 15, wherein the cutting punch comprises a first edge portion that cuts the terminal portions, and the first edge portion has a curved surface. Appendix 17. (Figure 17) A method for manufacturing a semiconductor device according to any one of appendices 13 to 16, further comprising a step of bending the terminal portion using a forming mold (86) before the cutting step, wherein the forming mold comprises a forming die (861) and a forming punch (862), and a minimum value (R3) of the radius of curvature of a shoulder portion (861a) of the forming die is equal to or greater than the dimension (T2) of the lead frame in the thickness direction.Appendix 18. (FIG. 17) The method for manufacturing a semiconductor device according to Appendix 17, wherein a minimum value (R4) of the radius of curvature of the shoulder portion (862a) of the forming punch is equal to or greater than the dimension of the lead frame in the thickness direction.

[0097] A10, A11, A12, A13, A20, A30, A40: semiconductor device 11: first semiconductor element 111: element main surface 112: element back surface 11A: electrode 12: second semiconductor element 121: element main surface 122: element back surface 12A: electrode 13: insulating element 131: element main surface 132: element back surface 13A: first electrode 13B: second electrode 19: conductive bonding material 25: plating layer 25a: recessed plated portion 25b: tip plated portion 2: conductive member 3: first die pad 31: main surface 32: back surface 4: second die pad 41: main surface 42: back surface 51, 51a, 51b: first terminal 511: tip surface 511c: burr 512: bottom surface 513: recess 514: full thickness portion 515: Upper surface 516: First bent portion 517: Second bent portion 53: Pad portion 54: Connection portion 52, 52a,52b: Second terminal 521: Tip surface 521c: Burr 522: Bottom surface 523: Recess 524: Total thickness portion 525: Top surface 526: First bent portion 527: Second bent portion 55: Pad portion 56: Connection portion 61-64: Wire 7: Sealing resin 71: Resin top surface 72: Resin bottom surface 73-76: Resin side surface 731: Resin first region 732: Resin second region 733: Resin third region 741: Resin fourth region 742: Resin fifth region 743: Resin sixth region 751: Resin seventh region 752: Resin eighth region 753: Resin ninth region 761: Resin tenth region 762: Resin eleventh region 763: Resin twelfth region 81: Lead frame 81A: Main surface 81B: Back surface 811: outer frame 812A: first die pad 812B: second die pad 813: first lead 813a: terminal portion 813b: recess 813c: first bent portion 813d: second bent portion 814: second lead 814a: terminal portion 814b: recess 814c: first bent portion 814d: second bent portion 815: connecting portion 816: dam bar 85: cutting mold 851: cutting die 851a: edge portion 852: cutting punch 852a: edge portion 853: stripper block 86: forming mold 861: die block 861a: shoulder portion 862: punch 862a: shoulder portion 863: stripper block 9: wiring board 95: solder,

Claims

1. A semiconductor element; a sealing resin for covering the semiconductor element; a terminal that is electrically connected to the semiconductor element and protrudes from the sealing resin in a first direction perpendicular to a thickness direction; A plating layer disposed on the terminal; Equipped with the terminal includes a tip surface which is an end surface protruding from the sealing resin, a first surface facing a first side in the thickness direction, and a recess which is recessed from both the tip surface and the first surface, The plating layer includes a recess plating portion disposed in at least a portion of the recess.

2. 2 . The semiconductor device according to claim 1 , wherein a first dimension in the thickness direction of the recess is greater than or equal to ¼ and less than or equal to ¾ of a second dimension in the thickness direction of a full thickness portion where the first surface of the terminal is located.

3. The semiconductor device according to claim 1 , wherein the plating layer includes a tip plating portion disposed on at least a portion of the tip surface.

4. The semiconductor device according to claim 3 , wherein the tip plating portion is disposed over the entire tip surface.

5. The semiconductor device according to claim 3 , wherein the tip plating portion is located on the first side of the tip surface.

6. The semiconductor device according to claim 3 , wherein the tip plating portion is located on a second side of the tip surface opposite the first side.

7. 7. The semiconductor device according to claim 1, wherein the recess extends over the entire terminal in a second direction perpendicular to the thickness direction and the first direction.

8. The semiconductor device according to claim 1 , wherein the first surface is connected to the tip surface.

9. 7. The semiconductor device according to claim 1, wherein a dimension of the terminal in a second direction perpendicular to the thickness direction and the first direction is larger in a portion where the recess is located than in a portion where the first surface is located.

10. The terminal further includes a first bent portion bent toward the first side in the thickness direction, 7. The semiconductor device according to claim 1, wherein a minimum value of a radius of curvature of an inner surface of the first bent portion is equal to or greater than a second dimension in the thickness direction of a full thickness portion where the first surface of the terminal is located.

11. The terminal further includes a second bent portion located between the first bent portion and the tip surface, The semiconductor device according to claim 10 , wherein a minimum value of a radius of curvature of an inner surface of said second bent portion is equal to or greater than said second dimension.

12. 7. The semiconductor device according to claim 1, wherein the plating layer contains Sn.

13. preparing a lead frame including a terminal portion having a first surface facing a first side in a thickness direction and a recessed portion recessed in the thickness direction from the first surface; forming a plating layer on the terminal portion; and cutting the terminal portion along a cutting line that intersects with the recess using a cutting die.

14. The cutting mold includes a cutting die and a cutting punch, The method for manufacturing a semiconductor device according to claim 13 , wherein the cut punch cuts off the terminal portion from the first side.

15. The cutting mold includes a cutting die and a cutting punch, The method for manufacturing a semiconductor device according to claim 13 , wherein the cut punch cuts off the terminal portion from a second side opposite to the first side in the thickness direction.

16. the cut punch has a first edge portion for cutting the terminal portion, The method for manufacturing a semiconductor device according to claim 14 , wherein the first edge portion has a curved surface.

17. The method further includes a step of bending the terminal portion by a forming die before the cutting step, The forming die includes a forming die and a forming punch, The method for manufacturing a semiconductor device according to claim 13 , wherein a minimum value of a radius of curvature of the shoulder portion of the forming die is equal to or greater than a dimension of the lead frame in the thickness direction.

18. 18. The method for manufacturing a semiconductor device according to claim 17, wherein a minimum value of a radius of curvature of the shoulder of the forming punch is equal to or greater than a dimension of the lead frame in the thickness direction.