Semiconductor device and communication system

Abstract

A semiconductor device (1) comprises a first reception unit (11) configured to receive reception data (RX) as serial data from a transmission device (40) via a first bus (BS1), and a first transmission unit (12) configured to connect to a device (10) via a second bus (BS2). The first reception unit and the first transmission unit are configured to perform thru-output of data (DDT) corresponding to the protocol of the device included in the reception data to the second bus when bridge selection data (BR) included in the reception data indicates that thru-ouput, in which bit data is output as-is between the first bus and the second bus, is in an on state.

Description

Semiconductor device and communication system

[0001] The present disclosure relates to a semiconductor device and a communication system.

[0002] Semiconductor devices having a serial communication function are used in a variety of applications.

[0003] An example of circuit technology relating to serial communication is disclosed in Japanese Patent Application Laid-Open No. 2003-222299.

[0004] Japanese Patent Application Laid-Open No. 2017-224946

[0005] In some applications, a communication system may be constructed using a semiconductor device (device) that performs serial communication using a protocol different from that of the semiconductor device itself.

[0006] An object of the present disclosure is to provide a semiconductor device that can effectively build a communication system together with a device that uses a protocol different from that of the semiconductor device itself.

[0007] A semiconductor device (1) according to one aspect of the present disclosure is a semiconductor device connectable to an external transmitting device via a first bus and connectable to an external device via a second bus, and includes: a first receiving unit configured to receive received data, which is serial data, from the transmitting device via the first bus; and a first transmitting unit configured to be connectable to the device via the second bus, wherein the first receiving unit and the first transmitting unit are configured to through-output data corresponding to the protocol of the device included in the received data to the second bus when bridge selection data included in the received data indicates that through-output, which outputs bit data as is between the first bus and the second bus, is on.

[0008] According to the exemplary semiconductor device of the present disclosure, it is possible to effectively build a communication system together with a device that uses a protocol different from that of the semiconductor device itself.

[0009] FIG. 1 is a diagram illustrating a configuration of a communication system according to a first comparative example. FIG. 2 is a diagram illustrating a configuration of a communication system according to a second comparative example. FIG. 3 is a diagram illustrating a configuration of a communication system according to an exemplary embodiment of the present disclosure. FIG. 4 is a block diagram of a semiconductor device according to an exemplary embodiment of the present disclosure. FIG. 5 is a diagram illustrating a data structure of received data RX when writing or reading data to a semiconductor device 1 as a target device. FIG. 6 is a diagram illustrating another exemplary configuration of a communication system according to an embodiment of the present disclosure. FIG. 7 is a diagram illustrating a data structure of received data RX when writing or reading data to a device 10 as a target device. FIG. 8 is a timing chart illustrating communication control when writing data to the device 10. FIG. 9 is a timing chart illustrating communication control when reading data to the device 10. FIG. 10 is a timing chart illustrating communication control when writing data to the device 10 in a modified example. FIG. 11 is a timing chart illustrating communication control when reading data to the device 10 in a modified example. FIG. 12 is a diagram illustrating a modified example of a communication system according to an embodiment of the present disclosure.

[0010] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0011] 1 is a diagram showing the configuration of a communication system 501 according to a first comparative example for comparison with an embodiment of the present disclosure. The communication system 501 includes an MCU (Micro Controller Unit) 20, a CAN (Controller Area Network) transceiver 30, a CAN transceiver 40, a semiconductor device 1, and n devices 10 (n is an integer equal to or greater than 1). The communication system 501 is, as an example, for use in a vehicle, and the same applies to the other communication systems described below.

[0012] Communication between the MCU 20 and the CAN transceiver 30 is performed using UART (Universal Asynchronous Receiver / Transmitter). UART is a protocol for exchanging serial data between two devices. With UART, bidirectional communication is performed between the sending and receiving sides using two lines.

[0013] Communication between the CAN transceivers 30 and 40 is performed via a CAN bus 35. CAN is a serial communication protocol standardized by international standards such as ISO11898.

[0014] The CAN transceiver 30 has a TXD (transmit data input) terminal 30A and an RXD (receive data output) terminal 30B. The CAN transceiver 30 outputs data input to the TXD terminal 30A to the CAN bus 35, and outputs data input from the CAN bus 35 from the RXD terminal 30B.

[0015] The CAN transceiver 40 has an RXD terminal 40A and a TXD terminal 40B. The CAN transceiver 40 outputs data input to the TXD terminal 40B to the CAN bus 35, and outputs data input from the CAN bus 35 from the RXD terminal 40A.

[0016] The semiconductor device 1 is an IC (integrated circuit) in which circuits with predetermined functions are integrated, and is configured as, for example, an LED (light-emitting diode) driver IC. The n devices 10 are ICs in which circuits with predetermined functions are integrated, and are configured as, for example, matrix switch ICs.

[0017] The semiconductor device 1 has an RX (receive data input) terminal 1A and a TX (transmit data output) terminal 1B. The device 10 has an RX terminal 10A and a TX terminal 10B. The RX terminal 1A and the n RX terminals 10A are commonly connected to an RXD terminal 40A. The TX terminal 1B and the n TX terminals 10B are commonly connected to a TXD terminal 40B.

[0018] 1, the semiconductor device 1 and the n devices 10 support the same protocol, so the semiconductor device 1 and the n devices 10 can be commonly connected to the same CAN transceiver 40. Received data RX output from the RXD terminal 40A is input to the RX terminal 1A and the n RX terminals 10A. The received data RX specifies the device address of one of the semiconductor device 1 and the n devices 10. Transmitted data TX output from the TX terminal 1B and the n TX terminals 10B is input to the TXD terminal 40B.

[0019] However, if the protocols supported by the semiconductor device 1 and the n devices 10 are different, it becomes difficult to deal with the configuration of the first comparative example shown in Fig. 1. Therefore, in such a case, the configuration of the second comparative example shown in Fig. 2 can be adopted.

[0020] 2 differs from the first comparative example in that CAN transceiver 40 is replaced with CAN transceiver 40. CAN transceiver 401 is connected to semiconductor device 1, and CAN transceiver 402 is connected to n devices 10. CAN transceivers 401 and 402 perform CAN communication with CAN transceiver 30.

[0021] In this way, by grouping devices with different protocols (a group of semiconductor device 1 and a group of n devices 10), communication control can be performed using devices with different protocols. However, an increase in the number of CAN transceivers, such as CAN transceivers 401 and 402, and an increase in the amount of wiring poses a problem of increased costs.

[0022] Therefore, in order to solve such problems, an embodiment of the present disclosure is implemented as described below. Fig. 3 is a diagram showing the configuration of a communication system 50 according to an exemplary embodiment of the present disclosure.

[0023] In the configuration shown in FIG. 3, UART communication is performed between the CAN transceiver 40, the semiconductor device 1, and n devices 10. In addition to an RX terminal 1A and a TX terminal 1B, the semiconductor device 1 has an RXD (receive data output) terminal 1C and a TXD (transmit data input) terminal 1D. The RX terminal 1A is connected to the RXD terminal 40A of the CAN transceiver 40. The TX terminal 1B is connected to the TXD terminal 40B of the CAN transceiver 40. In other words, the RX terminal 1A and the TX terminal 1B are connected to the RXD terminal 40A and the TXD terminal 40B by a bus BS1. Communication of receive data RX and transmit data TX is possible via the bus BS1. The receive data RX and transmit data TX are serial data.

[0024] The RXD terminal 1C is connected to the RX terminals 10A of the n devices 10. The TXD terminal 1D is connected to the TX terminals 10B of the n devices 10. That is, the RXD terminals 1C and TXD terminals 1D are connected to the RX terminals 10A and TX terminals 10B by a bus (local bus) BS2. Communication of receive data BRX and transmit data BTX is possible via the bus BS2. The receive data BRX and transmit data BTX are serial data.

[0025] 3 , the semiconductor device 1 and the n devices 10 support different protocols. When the CAN transceiver 40 writes or reads data to or from the semiconductor device 1, the received data RX output from the RXD terminal 40A to the RX terminal 1A consists only of data that supports the protocol of the semiconductor device 1. Note that "write" refers to the process of writing data to the target device, and "read" refers to the process of reading data from the target device. In the case of a read, the semiconductor device 1 receives the received data RX and then outputs the transmitted data TX from the TX terminal 1B to the TXD terminal 40B.

[0026] On the other hand, when the CAN transceiver 40 writes to or reads from the device 10, the receive data RX output from the RXD terminal 40A to the RX terminal 1A includes data corresponding to the protocol of the device 10. At this time, the semiconductor device 1 turns on the bridge function and through-outputs the data included in the receive data RX and corresponding to the protocol of the device 10 as receive data BRX from the RXD terminal 1C. Through-output means that bit data is output as is. The device address of the device 10 is specified in the receive data BRX.

[0027] In the case of Read, the device 10, which is the target device (the device specified by the device address), outputs transmission data BTX from the TX terminal 10B to the TXD terminal 1D. Because the bridge function of the semiconductor device 1 is on, the transmission data BTX is output as transmission data TX through the TX terminal 1B.

[0028] As described above, according to the embodiment of the present disclosure, even if the protocols of the semiconductor device 1 and the device 10 are different, the CAN transceiver 40 can write to and read from the semiconductor device 1 and the device 10. Compared to the second comparative example ( FIG. 2 ), the number of CAN transceivers 40 can be reduced, and the amount of wiring can be reduced, thereby reducing costs.

[0029] 4 is a block diagram of a semiconductor device 1 according to an embodiment of the present disclosure. The semiconductor device 1 includes, as functional blocks, a first receiving unit 11, a first transmitting unit 12, a second receiving unit 13, a second transmitting unit 14, and a control unit 15. Note that FIG. 4 illustrates only functional blocks related to the communication function in the communication system 50, and other functional blocks may also be included. For example, if the semiconductor device 1 is an LED driver, it includes a block function related to driving an LED.

[0030] The first receiver 11 receives reception data RX via the RX terminal 1A. The first transmitter 12 outputs reception data BRX via the RXD terminal 1C. The second receiver 13 receives transmission data BTX via the TXD terminal 1D. The second transmitter 14 outputs transmission data TX via the TX terminal 1B.

[0031] The control unit 15 controls the first receiving unit 11, the first transmitting unit 12, the second receiving unit 13, and the second transmitting unit 14. The control unit 15 includes a register 151.

[0032] 5 is a diagram showing the data structure of received data RX when writing or reading is performed with the semiconductor device 1 as the target device. The received data RX shown in FIG. 5 is made up of only data corresponding to the protocol of the semiconductor device 1.

[0033] In UART, communication is carried out in data units called frames. As shown in Fig. 5, a frame FR is made up of bit data from a start bit S to a stop bit P. The start bit S is at a low level, and the stop bit P is at a high level. A predetermined number of bits of bit data are placed between the start bit S and the stop bit P. In the example of Fig. 5, 8 bits of bit data are placed. In other words, the frame FR is made up of 10 bits of bit data.

[0034] As shown in FIG. 5, the received data RX includes, from the beginning, a synchronization frame SYNC, a read / write frame RWD, a data number frame ND, a register address frame AD, a data frame DT, and a CRC (Cyclic Redundancy Check) frame CR.

[0035] The synchronization frame SYNC is bit data for setting the baud rate in the semiconductor device 1 .

[0036] The Read / Write etc. frame RWD includes a device address DA, a bridge bit BR, a broadcast / parity bit B / PA, and a Read / Write bit RW. The device address DA is bit data indicating the address of the target device (semiconductor device 1) (5-bit data in the example of FIG. 5). The bridge bit BR is bit data indicating the on / off status of the bridge function of the semiconductor device 1. The broadcast / parity bit B / PA is bit data indicating the on / off status of the broadcast of the semiconductor device 1 or the parity of the data address DA. The Read / Write bit RW is bit data indicating Read or Write.

[0037] Here, the bridge bit BR = 0 indicates that the bridge function is off, i.e., normal mode (the bridge function is off in the received data RX shown in Figure 5). In this case, the broadcast / parity bit B / PA indicates whether broadcast is on or off. When the broadcast / parity bit B / PA = 0, broadcast is off, and when the broadcast / parity bit B / PA = 1, broadcast is on.

[0038] 6, when broadcasting the semiconductor device 1, a plurality of semiconductor devices 1 are connected to the CAN transceiver 40. A device 10 is connected to each of the semiconductor devices 1. When broadcasting is on, all of the plurality of semiconductor devices 1 become target devices.

[0039] A bridge bit BR = 1 indicates that the bridge function is on (the bridge function is on in the received data RX shown in FIG. 7 , which will be described later). In this case, the broadcast / parity bit B / PA becomes the parity of the device data DA. This makes it possible to detect errors in the device data DA. Note that in the configuration shown in FIG. 6 , if the protocols differ for each group of devices 10 connected to multiple semiconductor devices 1, turning on broadcast in the semiconductor device 1 will result in the same received data RX being sent as received data BRX to devices 10 with different protocols, making the protocols incompatible with some of the devices 10. Therefore, broadcasting is not performed when the bridge function is on.

[0040] The data number frame ND is bit data indicating the number of frames in the data frame DT. The register address frame AD is bit data indicating an address in the register 151. The data frame DT is bit data indicating the data body to be transmitted by the received data RX. The CRC frame CR is bit data indicating an error detection code to be added to the data frame DT. Note that when the Read / Write bit RW indicates Read, the data frame DT and the CRC frame CR are not included in the received data RX.

[0041] 7 is a diagram showing the data structure of received data RX when performing write or read with the device 10 as the target device. The synchronization frame SYN and read / write frame RWD in the received data RX shown in FIG. 7 are as described above.

[0042] In the received data RX shown in Fig. 7, the data number frame ND indicates the number of frames for the end condition of the through output, unlike the case shown in Fig. 6. Control using the data number frame ND will be described later.

[0043] In the receive data RX shown in Figure 7, the device data DDT follows the data number frame ND. The device data DDT is data that complies with the protocol of the device 10 and is the target to be output through as receive data BRX. The device data DDT includes a device address BDA. The device address BDA indicates the address of the device 10, which is the target device. The device address BDA is located in the device data DDT at a position that corresponds to the protocol of the device 10.

[0044] 4. Through Output Control Here, the through output control by the semiconductor device 1, that is, the control when the bridge function is on, will be described.

[0045] 8 is a timing chart showing communication control when performing a write to the device 10. From the top to bottom of Fig. 8, receive data RX, receive data output selection signal (RX output select), transmit data output selection signal (TX output select), receive data BRX, transmit data BTX, and transmit data TX are shown (similar to Figs. 9 to 11). The receive data RX has the configuration shown in Fig. 7.

[0046] The received data RX is received by the first receiving unit 11 (FIG. 4). Upon receiving the start bit S1 (low level) at the beginning of the received data RX, the control unit 15 recognizes the start of reception of the received data RX. Thereafter, the control unit 15 recognizes that the bridge function is on based on the bridge bit BR included in the received data RX, and also recognizes that a write is being performed based on the read / write bit RW.

[0047] Thereafter, when the data number frame ND is received, the control unit 15 changes the received data output selection signal in the register 151 from low to high at the stop bit P1 of the data number frame ND (timing t1). This starts the through output of the received data RX, and the first receiving unit 11 and the first transmitting unit 12 output the received data RX as is as received data BRX. In other words, the device data DDT (FIG. 7) is through output.

[0048] When the received data output selection signal goes high, the control unit 15 starts counting the number of frames of the received data RX (i.e., the number of frames of the device data DDT). When the counted number of frames reaches the number of frames indicated by the received data number frame ND, the control unit 15 switches the received data output selection signal to low, stopping the through output (timing t2). Thereafter, the received data BRX is fixed at high.

[0049] 9 is a timing chart showing communication control when performing a read from the device 10. In this case, the received data RX has the structure shown in FIG.

[0050] After receiving the start bit S1 (low level) at the beginning of the received data RX, the control unit 15 recognizes that the bridge function is on based on the bridge bit BR included in the received data RX, and also recognizes that it is a read based on the read / write bit RW.

[0051] Thereafter, when the data number frame ND is received, the control unit 15 changes both the receive data output selection signal and the transmit data output selection signal in the register 151 from low to high at the stop bit P1 of the data number frame ND (timing t1). This initiates through-output of the receive data RX and the transmit data BTX. The first receiver 11 and the first transmitter 12 output the receive data RX as is as receive data BRX, i.e., through-output of the device data DDT (FIG. 7). After completing output of the receive data BRX, the second receiver 13 and the second transmitter 14 through-output the transmit data BTX sent from the device 10 as transmit data TX.

[0052] When the reception data output selection signal and the transmission data output selection signal go high, the control unit 15 starts counting the total number of frames of the reception data RX and the reception data BTX. When the counted number of frames reaches the number of frames indicated by the received data number frame ND, the control unit 15 switches both the reception data output selection signal and the transmission data output selection signal to low level, stopping the through output (timing t2). After this, the reception data BRX is fixed to high level, and the transmission data TX is fixed to Hi-z (high impedance).

[0053] In this manner, in this embodiment, the condition for ending the through output can be determined based on the number of frames received by the semiconductor device 1. In particular, with this embodiment, even if transmission of the received data RX from the MCU 20 is interrupted due to interrupt processing in the MCU 20, the frame count does not advance during the interruption, so it is possible to avoid erroneously interrupting the through output. In other words, because interruption of the through output can be avoided regardless of the interrupt time, it is less subject to restrictions due to the specifications of the MCU 20.

[0054] 5. Modification of Through Output Control The condition for ending the through output is not limited to the number of frames described above, but may be the number of bits or the time during which the data received by the semiconductor device 1 is continuously at a high level, as in the modification described below.

[0055] 10 is a timing chart showing communication control when writing to the device 10 in this modified example. Here, after the received data output selection signal goes high and through output begins, reception of the received data RX is completed and the received data RX is fixed at a high level. The control unit 15 monitors whether the number of consecutive high-level bits in the received data RX reaches a predetermined number of bits, and when this number is reached (timing t2), the control unit 15 switches the received data output selection signal to a low level to stop through output. Thereafter, the received data BRX is fixed at a high level. The predetermined number of bits may be selectable from a number of options (e.g., 12 bits, 24 bits, 48 ​​bits, or 96 bits).

[0056] Instead of monitoring the number of bits, the control unit 15 may monitor whether the time during which the received data RX remains high reaches a predetermined time. In this case, the predetermined time may be selectable from a number of options (e.g., 10 μs, 20 μs, 30 μs, or 50 μs).

[0057] 11 is a timing chart showing communication control when reading data from the device 10 in this modified example. Here, after the reception data output selection signal and transmission data output selection signal go high and through output begins, reception of the transmission data BTX is completed and the transmission data BTX is fixed at a high level. The control unit 15 monitors whether the number of consecutive high-level bits of the transmission data BTX reaches a predetermined number of bits, and when this occurs (timing t2), the reception data output selection signal and transmission data output selection signal are switched to a low level to stop through output. Thereafter, the reception data BRX is fixed at a high level, and the transmission data TX is fixed at Hi-z. The predetermined number of bits may be selectable from multiple options.

[0058] The control unit 15 may monitor whether the time during which the transmission data BTX is continuously at a high level reaches a predetermined time, instead of the number of bits as described above. In this case, the predetermined time may be selectable from a plurality of options.

[0059] According to this modification, it is not necessary to include the number of data frames ND in the received data RX, and the end condition of the through output can be set. When the predetermined number of bits or the predetermined time is selected from a plurality of candidates, a candidate corresponding to a time longer than the interrupt time in the MCU 20 is selected in order to avoid interruption of the through output.

[0060] <6. Others> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0061] For example, if a command to the RX terminal 10A is always required when outputting transmit data from the TX terminal 10B of the device 10, that is, if the transmit data output of the device 10 can be completely controlled by input to the RX terminal 10A, there is no need to bridge the TX terminal 10B of the device 10. In this case, the TX terminal 10B of the device 10 may be connected to a bus BS1 connected to the TX terminal 1B of the semiconductor device 1, as shown in FIG.

[0062] <7. Supplementary Note> As described above, a semiconductor device (1) according to one aspect of the present disclosure is a semiconductor device connectable to an external transmitting device (40) via a first bus (BS1) and connectable to an external device (10) via a second bus (BS2), and includes: a first receiving unit (11) configured to be able to receive received data (RX), which is serial data, from the transmitting device via the first bus; and a first transmitting unit (12) configured to be connectable to the device via the second bus, wherein when bridge selection data (BR) included in the received data indicates on of a through output that outputs bit data as is between the first bus and the second bus, the first receiving unit and the first transmitting unit are configured to through-output data (DDT) corresponding to a protocol of the device, which is included in the received data, to the second bus (first configuration).

[0063] In addition, in the first configuration, when the read / write selection data (RW) included in the received data (RX) indicates a write, the first receiving unit (11) and the first transmitting unit (12) may be configured to stop through output to the second bus when the number of received frames of the received data reaches a predetermined number of frames (second configuration).

[0064] In the second configuration, the data (ND) indicating the predetermined number of frames may be included in the received data (RX) (third configuration).

[0065] Furthermore, in the first configuration, when the read / write selection data (RW) included in the received data (RX) indicates a write, the first receiving unit (11) and the first transmitting unit (12) may be configured to stop the through output to the second bus when the number of bits or the time during which the received data continuously reaches a predetermined logic level reaches a predetermined number of bits or a predetermined time (fourth configuration).

[0066] In the fourth configuration, the predetermined number of bits or the predetermined time may be selectable from a plurality of candidates (fifth configuration).

[0067] Furthermore, in any of the first to fifth configurations, a sixth configuration may be provided which includes a second receiving unit (13) configured to be connectable to the device (10) via the second bus (BS2), and a second transmitting unit (14) configured to be connectable to the transmitting device (40) via the first bus (BS1), and in which, when the bridge selection data (BR) indicates that through output is on and the read / write selection data (RW) included in the received data (RX) indicates that it is read, the second receiving unit may be configured to through-output transmission data (BTX), which is serial data received from the device, from the second transmitting unit to the first bus.

[0068] Furthermore, in the sixth configuration, when the read / write selection data (RW) included in the received data (RX) indicates a read, the first receiving unit (11), the first transmitting unit (12), the second receiving unit (13), and the second transmitting unit (14) may be configured to stop through output to the first bus (BS1) and the second bus (BS2) when the sum of the number of received frames of the received data and the number of received frames of the transmitted data (BTX) reaches a predetermined number of frames (seventh configuration).

[0069] Furthermore, in the sixth configuration, when the read / write selection data (RW) included in the received data (RX) indicates a read, the first receiving unit (11), the first transmitting unit (12), the second receiving unit (13), and the second transmitting unit (14) may be configured to stop through output to the first bus (BS1) and the second bus (BS2) when the number of bits or the time during which the transmitted data (BTX) consecutively reaches a predetermined logic level reaches a predetermined number of bits or a predetermined time (eighth configuration).

[0070] Furthermore, in any of the first to eighth configurations, the received data (RX) may include a device address (DA) of the semiconductor device (1) and a broadcast / parity bit (B / PA), and when the bridge selection data (BR) indicates that through output is off, the broadcast / parity bit indicates on / off of broadcast to the semiconductor device, and when the bridge selection data indicates that through output is on, the broadcast / parity bit may indicate the parity of the device address (ninth configuration).

[0071] Furthermore, a communication system (50) according to one aspect of the present disclosure includes a semiconductor device (1) having any one of the first to ninth configurations, the transmitting device (40), and the device (10) (tenth configuration).

[0072] The present disclosure can be used, for example, in an in-vehicle communication system.

[0073] 1 Semiconductor device 1A RX terminal 1B TX terminal 1C RXD terminal 1D TXD terminal 10 Device 10A RX terminal 10B TX terminal 11 First receiving unit 12 First transmitting unit 13 Second receiving unit 14 Second transmitting unit 15 Control unit 30, 40 CAN transceiver 30A TXD terminal 30B RXD terminal 35 CAN bus 40 CAN transceiver 40A RXD terminal 40B TXD terminal 50 Communication system 151 Register 401, 402 CAN transceiver 501, 502 Communication system BS1, BS2 bus

Claims

1. A semiconductor device connectable to an external transmitting device via a first bus and connectable to an external device via a second bus, a first receiving unit configured to be able to receive reception data, which is serial data, from the transmitting device via the first bus; A first transmission unit configured to be connectable to the device via the second bus; Equipped with a semiconductor device configured to, when bridge selection data included in the received data indicates that a through output is on, which outputs bit data as is between the first bus and the second bus, outputting data corresponding to a protocol of the device included in the received data to the second bus, the first receiving unit and the first transmitting unit being configured to through-output data included in the received data to the second bus.

2. 2. The semiconductor device according to claim 1, wherein when read / write selection data included in the received data indicates a write, the first receiving unit and the first transmitting unit are configured to stop through output to the second bus when a number of received frames of the received data reaches a predetermined number of frames.

3. The semiconductor device according to claim 2 , wherein the data indicating the predetermined number of frames is included in the received data.

4. 2. The semiconductor device according to claim 1, wherein when read / write selection data included in the received data indicates a write, the first receiving unit and the first transmitting unit are configured to stop through output to the second bus when a number of bits or a time during which the received data continuously reaches a predetermined logic level reaches a predetermined number of bits or a predetermined time.

5. 5. The semiconductor device according to claim 4, wherein said predetermined number of bits or said predetermined time is selectable from a plurality of candidates.

6. A second receiving unit configured to be connectable to the device via the second bus; A second transmission unit configured to be connectable to the transmission device via the first bus; Equipped with 2. The semiconductor device according to claim 1, wherein when the bridge selection data indicates on of a through output and the read / write selection data included in the received data indicates a read, the second receiving unit is configured to output through the transmission data, which is serial data received from the device, from the second transmitting unit to the first bus.

7. 7. The semiconductor device according to claim 6, wherein when read / write selection data included in the received data indicates a read, the first receiving unit, the first transmitting unit, the second receiving unit, and the second transmitting unit are configured to stop through output to the first bus and the second bus when a sum of a number of received frames of the received data and a number of received frames of the transmitted data reaches a predetermined number of frames.

8. 7. The semiconductor device according to claim 6, wherein when read / write selection data included in the received data indicates a read, the first receiving unit, the first transmitting unit, the second receiving unit, and the second transmitting unit are configured to stop through output to the first bus and the second bus when a predetermined number of bits or a predetermined time period during which the transmitted data is continuously at a predetermined logic level reaches a predetermined number of bits or a predetermined time period.

9. the received data includes a device address of the semiconductor device and a broadcast / parity bit; When the bridge selection data indicates that a through output is off, the broadcast / parity bit indicates on / off of a broadcast to the semiconductor device; 2 . The semiconductor device according to claim 1 , wherein, when said bridge selection data indicates an on state of a through output, said broadcast / parity bit indicates parity of said device address.

10. 10. A communication system comprising: the semiconductor device according to claim 1; the transmitting apparatus; and the device.