Phase adjustment circuit

Abstract

In the present invention, a phase adjustment circuit comprises: a sine wave output unit (16) that outputs two sine wave signals with a fixed phase difference; multiplication units (5, 6) that output signals derived by multiplying the amplitude of the two signals outputted from the sine wave output unit (16) sby A, B; an amplitude detection unit (9) that detects the output amplitude of an addition unit (7); a differential amplifier unit (10) that subtracts the detection result from the amplitude detection unit (9) from a target amplitude (Vref), and amplifies the result; a multiplication unit (12) that delivers to the multiplication unit (5), as the control signal that determines variable A, a signal derived by multiplying the amplitude of the output signal of an LPF (11) by Vratio1; and a multiplication unit (13) that delivers to the multiplication unit (6), as the control signal that determines variable B, a signal derived by multiplying the amplitude of the output signal of the LPF (11) by Vratio2.

Description

Phase Adjustment Circuit

[0001] The present invention relates to a sine wave phase adjustment circuit.

[0002] Sine waves play an important role in modern times. In communications, sine waves are used to generate carrier waves and also as clocks. In communications, sine waves are used not only as carrier waves but also as timing references to determine data.

[0003] When using a clock as a timing reference for such data judgment, it is necessary to adjust the phase of the clock and make data judgments at the appropriate timing. One method for making data judgments at the appropriate timing is clock data recovery. A known means for realizing clock data recovery is a configuration that uses a phase comparator and a phase adjustment circuit. In this configuration, the phase is compared using some means, and the desired phase is generated based on the comparison results.

[0004] A configuration disclosed in Non-Patent Document 1 has been known as a phase adjustment circuit. The configuration of a conventional phase adjustment circuit is shown in FIG. 14. In the configuration of FIG. 14, a reference sine wave sinωt and a sine wave cosωt having a fixed phase difference of π / 2 with respect to the sine wave sinωt are added by an adder 203 to generate a waveform with an arbitrary intermediate phase. The sine waves sinωt and cosωt are multiplied by constants A and B by multipliers 201 and 202, respectively. The following equation holds from the trigonometric function synthesis formula:

[0005]

[0006] α in the formula (1) is as follows:

[0007]

[0008] In the configuration of Figure 14, sine waves sinωt and cosωt are generated by using a Quadrature-VCO (Voltage Controlled Oscillator) 200. However, the Quadrature-VCO 200 has a problem in that its oscillation frequency is low due to its structure, making it difficult to use in the device's limit range. In addition, a method of using a 90-degree hybrid is known as a method of creating a sine wave with a fixed phase difference of π / 2 from a sine wave, but when using a 90-degree hybrid, there is a problem in that it only operates at specific frequencies.

[0009] Arun Goyal, et al., “A High-Resolution Digital Phase Interpolator Based CDR with a Half-Rate Hybrid Phase Detector”, 2019 IEEE International Symposium on Circuits and Systems (ISCAS), May 2019

[0010] The present invention has been made to solve the above problems, and has an object to provide a phase adjustment circuit that can be used over a wide range of frequencies.

[0011] The phase adjustment circuit of the present invention includes a sine wave output unit configured to output two sine wave signals with a fixed phase difference; a first multiplier configured to output a signal obtained by multiplying the amplitude of the first sine wave signal output from the sine wave output unit by a first variable; a second multiplier configured to output a signal obtained by multiplying the amplitude of the second sine wave signal output from the sine wave output unit by a second variable; an adder configured to add the signal output from the first multiplier and the signal output from the second multiplier; and an amplitude detector configured to detect the amplitude of the output signal from the adder. The amplifier is characterized by comprising a differential amplifier configured to subtract the detected amplitude from a target amplitude and amplify the result; a first low-pass filter configured to smooth the output result of the differential amplifier; a third multiplier configured to provide a signal obtained by multiplying the amplitude of the signal output from the first low-pass filter by a first constant to the first multiplier as a control signal for determining the first variable; and a fourth multiplier configured to provide a signal obtained by multiplying the amplitude of the signal output from the first low-pass filter by a second constant to the second multiplier as a control signal for determining the second variable.

[0012] According to the present invention, by providing a sine wave output unit, first and second multipliers, and an adder, it is no longer necessary to use a conventional Quadrature-VCO as a clock generator that is the basis of the sine wave signal, and an LC-VCO consisting of a general LC oscillator can be used as the clock generator. Furthermore, unlike configurations that use a 90-degree hybrid as the clock generator, the present invention can be used over a wide range of frequencies. Furthermore, by providing an amplitude detector, a differential amplifier, a first low-pass filter, and third and fourth multipliers, the output amplitude of the adder can be made constant.

[0013] FIG. 1 is a block diagram showing the configuration of a phase adjustment circuit on which the present invention is based. FIG. 2 is a block diagram showing the configuration of a phase adjustment circuit according to a first embodiment of the present invention. FIG. 3 is a diagram showing a signal amplitude control model according to the first embodiment of the present invention. FIG. 4 is a block diagram showing the configuration when noise is input to each node of the control model of FIG. 3. FIG. 5 is a diagram showing simulation results of the phase adjustment circuit of FIG. 1. FIG. 6 is a diagram showing simulation results of the phase adjustment circuit according to the first embodiment of the present invention. FIG. 7 is a circuit diagram showing the configuration of a multiplier unit according to a second embodiment of the present invention. FIG. 8 is a circuit diagram showing the configuration of an adder unit according to a third embodiment of the present invention. FIG. 9 is a circuit diagram showing the configuration of an amplitude detector unit according to a fourth embodiment of the present invention. FIG. 10 is a circuit diagram showing the configuration of a low-pass filter according to a fifth embodiment of the present invention. FIG. 11 is a circuit diagram showing the configuration of an amplitude detector unit according to a sixth embodiment of the present invention. FIG. 12 is a circuit diagram showing another configuration of the amplitude detector unit according to the sixth embodiment of the present invention. FIG. 13 is a circuit diagram showing the configurations of a multiplier unit and an adder unit according to a seventh embodiment of the present invention. FIG. 14 is a block diagram showing the configuration of a conventional phase adjustment circuit.

[0014] [Principle of the Invention] First, the configuration of the phase adjustment circuit that forms the basis of the present invention will be described with reference to Fig. 1. In the present invention, the function of adjusting to an arbitrary phase is realized by adding two sine waves with an arbitrary phase difference at an arbitrary ratio.

[0015] The phase adjustment circuit of FIG. 1 includes a clock generation unit 1 that generates a sinusoidal clock signal, buffer units 2 and 3 that receive as input the signal output from the clock generation unit 1, a delay unit 4 that delays the signal output from the buffer unit 3, a multiplication unit 5 that outputs a signal obtained by multiplying the amplitude of the signal output from the buffer unit 2 by A, a multiplication unit 6 that outputs a signal obtained by multiplying the amplitude of the signal output from the delay unit 4 by B, an addition unit 7 that adds the signal output from the multiplication unit 5 and the signal output from the multiplication unit 6, and an AGC (Automatic Gain Control) unit 8 that maintains the amplitude of the output signal from the addition unit 7 constant.

[0016] In the configuration shown in Figure 1, an arbitrary waveform can be generated by adding a reference sine wave sinωt and a sine wave sin(ωt + φ) that differs in phase by φ at an arbitrary magnification. The clock generation unit 1 does not need to use a conventional Quadrature-VCO, and can use an LC-VCO consisting of a general LC oscillator. Furthermore, the configuration of Figure 1 differs from configurations that use a 90-degree hybrid as the clock generation unit 1, allowing it to be used over a wide range of frequencies. The output signal OUT of the addition unit 7 is expressed by the following equation.

[0017]

[0018] e in formula (3) jωt denotes a reference sine wave. From equation (3), it can be seen that by adding a sine wave of a reference frequency and a sine wave that differs by an arbitrary phase φ, a sine wave that differs in phase from the reference phase by ρ can be generated. Here, the phase angle ρ is given by equation (4).

[0019]

[0020] In the configuration shown in FIG. 1 , it is difficult to maintain a constant amplitude for the output signal OUT of the adder 7. To address this issue, an AGC unit 8 is added. The AGC unit 8 detects the amplitude of the output signal OUT of the adder 7 and adjusts the output amplitude by automatically controlling the gain. However, inserting the AGC unit 8 into the main signal path creates a problem of distortion in the signal due to the nonlinearity of the AGC unit 8. Another problem is increased noise, degrading signal quality. Based on the configuration shown in FIG. 1 , the present invention achieves output amplitude adjustment without using AGC.

[0021] [First embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Fig. 2 is a block diagram showing the configuration of a phase adjustment circuit according to a first embodiment of the present invention. The phase adjustment circuit includes a clock generation unit 1 that generates a sine wave clock signal, buffer units 2 and 3 that receive the signal output from the clock generation unit 1 as an input, a delay unit 4 that delays the signal output from the buffer unit 3, a multiplication unit 5 that outputs a signal obtained by multiplying the amplitude of the signal output from the buffer unit 2 by A (a first variable), a multiplication unit 6 that outputs a signal obtained by multiplying the amplitude of the signal output from the delay unit 4 by B (a second variable), an addition unit 7 that adds the signal output from the multiplication unit 5 and the signal output from the multiplication unit 6, and an amplitude detector that detects the amplitude of the signal output from the addition unit 7. The amplifier includes a width detection unit 9, a differential amplification unit 10 that subtracts the amplitude detected by the amplitude detection unit 9 from a target amplitude Vref and amplifies the result, a low-pass filter (LPF) 11 that flattens the output result from the differential amplification unit 10, a multiplication unit 12 that multiplies the amplitude of the signal output from the LPF 11 by Vratio1 (a first constant) and provides this signal to the multiplication unit 5 as a control signal that determines a first variable, and a multiplication unit 13 that multiplies the amplitude of the signal output from the LPF 11 by Vratio2 (a second constant) and provides this signal to the multiplication unit 6 as a control signal that determines a second variable.

[0022] The clock generating unit 1, buffer units 2 and 3, and delay unit 4 constitute a sine wave output unit 16 that outputs two sine wave signals with a fixed phase difference. The phase difference between the two sine wave signals is not limited to 90 degrees and can be any phase difference. Furthermore, in the present invention, the configuration of the sine wave output unit 16 may be configured other than that shown in FIG. 2. Vratio1 and Vratio2 are arbitrary real numbers that are set in advance. A and B are real numbers determined by control signals output from multiplier units 12 and 13.

[0023] It is clear from equations (3) and (4) that the phase difference applied to the reference phase (the phase of the sine wave sinωt output from the clock generating unit 1) is determined by the ratio of A to B. In this embodiment, the same phase difference is set as when A=Vratio1 and B=Vratio2.

[0024] The configuration of this embodiment includes a feedback circuit that controls signal amplitude. The feedback circuit is composed of multiplication units 5 and 6, an addition unit 7, an amplitude detection unit 9, a differential amplification unit 10, an LPF 11, and multiplication units 12 and 13. The feedback circuit is equivalent to the signal amplitude control model shown in FIG. 3.

[0025] Y indicates the amplitude of the signal output from the adder 7, and P indicates a constant amplitude that is the result of adjusting the amplitude based on the signal output from the adder 7 when A=Vratio1 and B=Vratio2. The control model is made up of a subtractor 100 that subtracts the amplitude Y from the target amplitude Vref, an amplifier 101 that amplifies the result of the subtraction by the subtractor 100, an LPF 102 that passes only the low-frequency components of the output of the amplifier 101, and a multiplier 103 that multiplies the constant amplitude P by the output of the LPF 102.

[0026] As described above, the phase difference applied to the reference phase is determined by the ratio of A to B. This ratio is determined as A:B=Vratio1:Vratio2, and is set to a constant value by Vratio1 and Vratio2.

[0027] The control model shown in Fig. 3 represents a typical feedback system. Assuming that the entire system is stable, applying a low-pass characteristic to the frequency characteristic H(ω) makes it possible to bring the amplitude Y closer to the target amplitude Vref.

[0028] Next, let's consider the stability of the control model. For the control model to be stable, the signal at the output terminal must be stable even when noise is input to each node shown in Figure 3. Figure 4 shows a block diagram of the control model when it is assumed that noise is input to each node. Note that the block diagram has been redrawn here with Vref as the input and Y as the output.

[0029] ΔE is the noise input to the amplifier 101, ΔKo is the noise input to the LPF 102, ΔX is the noise input to the multiplication unit 103, and ΔY is the noise input to the subtraction unit 100. When the transfer characteristic of the amplifier 101 is K and the transfer characteristic is calculated for the configuration in FIG. 4, the result is shown in equation (5).

[0030] {{{Vref-(Y+ΔY)+ΔE}×K+ΔKo}×H+ΔX}×P=Y → {{{Vref-(Y+ΔY)+ΔE}×K+ΔKo}×H+ΔX}=Y / P →{{Vref-(Y+ΔY)+ΔE}×K+ΔKo}×H=Y / P-ΔX →{Vref-(Y+ΔY)+ΔE}×K+ΔKo=Y / PH-ΔX / H →{Vref-(Y+ΔY)+ΔE}×K=Y / PH-ΔX / H-ΔKo →{Vref-(Y+ΔY)+ΔE}=Y / PHK-ΔX / HK-ΔKo / K →{Vref-(ΔY)+ΔE}+ΔX / HK+ΔKo / K=Y(1+1 / PHK) →Y=[{Vref-(ΔY)+ΔE}+ΔX / HK+ΔKo / K] ×PHK / (PHK+1) ...(5)

[0031] Calculating the effect of each noise component on the output amplitude Y results in a superposition of the terms PHK / (1+PHK)×(ΔE-ΔY), P / (1+PHK)×(ΔX), and PH / (1+PHK)×(ΔKo). Therefore, in order for the control model to be stable, it is necessary to satisfy the following three conditions (I) to (III).

[0032] (I) PHK / (1+PHK) is stable. (II) P / (1+PHK) is stable. (III) PH / (1+PHK) is stable.

[0033] Note that, since the amplitude P is a constant, condition (II) may be expressed as "1 / (1+PHK) is stable," and under this condition (II), condition (III) may be expressed as "H is stable," and similarly, condition (I) may be expressed as "K is stable." Based on the above, rearranging the conditions for the control model to be stable, the following three conditions (a) to (c) must be satisfied. Therefore, the feedback circuit should be designed to satisfy conditions (a) to (c).

[0034] (a) The transfer characteristic K of the amplifier is stable. (b) The characteristic H of the LPF is stable. (c) 1 / (1+PHK) is stable.

[0035] Fig. 5 shows the results of a circuit simulation confirming that the phase of a sine wave is changed by the phase adjustment circuit shown in Fig. 1, and Fig. 6 shows the results of a circuit simulation confirming that the phase of a sine wave is changed by the phase adjustment circuit of this embodiment. 50 indicates the sine wave output from the clock generation unit 1, 51 indicates the sine wave (output of the adder unit 7) whose phase has been changed by the phase adjustment circuit shown in Fig. 1, and 52 indicates the sine wave whose phase has been changed by the phase adjustment circuit of this embodiment. In the case of the phase adjustment circuit shown in Fig. 1, if an AGC unit is not added, the output amplitude will fluctuate greatly with respect to the input, but in this embodiment, it can be seen that the output amplitude can be kept constant.

[0036] There are many ways to realize the delay unit 4, but for example, the delay unit 4 may be realized by a propagation delay in wiring. In particular, to accommodate high frequencies, a transmission line may be used as the wiring to realize the delay unit 4. The type and structure of the transmission line are not important. A coplanar line or a microstrip line may be used as the transmission line.

[0037] The delay unit 4 may also be configured by cascading any number of amplifiers. Furthermore, the delay unit 4 may be implemented by lumped elements. For example, the delay unit 4 may be implemented by an LCR resonant circuit. The delay unit 4 may also be implemented by combining wiring, amplifiers, and lumped elements.

[0038] Second Embodiment In this embodiment, a specific example of the multiplication units 5, 6, 12, and 13 of the first embodiment will be described. As the multiplication units 5, 6, 12, and 13, Gilbert cells, which are variable amplifiers, can be used. 7, the multiplication unit 5 includes an NPN bipolar transistor Q1 having a base to which a control signal IN1n (first control signal or third control signal) is input and which outputs a positive-phase output signal OUT1p from its collector, an NPN bipolar transistor Q2 having a base to which a control signal IN1p (second control signal or fourth control signal) is input and which outputs a negative-phase output signal OUT1n from its collector, an NPN bipolar transistor Q3 having a base to which the control signal IN1n is input and which outputs a negative-phase output signal OUT1n from its collector, an NPN bipolar transistor Q4 having a base to which the control signal IN1p is input and which outputs a positive-phase output signal OUT1p from its collector, and an NPN bipolar transistor Q5 having a base to which a positive-phase signal IN2p of the differential signal output from the buffer unit 2 is input and which has a collector connected to the emitters of the transistors Q1 and Q2. The multiplier 5 is made up of an NPN bipolar transistor Q5, an NPN bipolar transistor Q6 having a base to which a signal IN2n, the opposite phase of the differential signal output from the buffer unit 2, is input and whose collector is connected to the emitters of the transistors Q3 and Q4, an NPN bipolar transistor Q7 having a base to which a bias voltage VB is applied, a resistor R1 having one end connected to the power supply voltage VCC and the other end connected to the collectors of the transistors Q1 and Q4, a resistor R2 having one end connected to the power supply voltage VCC and the other end connected to the collectors of the transistors Q2 and Q3, a resistor R3 having one end connected to the emitter of the transistor Q5 and the other end connected to the collector of the transistor Q7, a resistor R4 having one end connected to the emitter of the transistor Q6 and the other end connected to the collector of the transistor Q7, and a resistor R5 having one end connected to the emitter of the transistor Q7 and the other end connected to ground. The amplification factor (the amplitude A) of the multiplier 5 can be controlled by the voltage difference between the control signals IN1p and IN1n.

[0039] The configuration of multiplication unit 6 is the same as that of multiplication unit 5. In the case of multiplication unit 6, differential signals IN2p and IN2n output from delay unit 4 are input to transistors Q5 and Q6. The amplification factor (the above-mentioned amplitude B) of multiplication unit 6 can be controlled by the voltage difference between control signals IN1p and IN1n.

[0040] The configuration of the multiplication unit 12 is the same as that of the multiplication unit 5. In the case of the multiplication unit 12, the differential signals IN2p and IN2n output from the LPF 11 are input to the transistors Q5 and Q6. The amplification factor of the multiplication unit 12 (the above-mentioned constant Vratio1) can be set to a constant value depending on the voltage difference between the control signals IN1p and IN1n.

[0041] The configuration of the multiplication unit 13 is the same as that of the multiplication unit 5. In the case of the multiplication unit 13, the differential signals IN2p and IN2n output from the LPF 11 are input to the transistors Q5 and Q6. The amplification factor of the multiplication unit 13 (the above-mentioned constant Vratio2) can be set to a constant value depending on the voltage difference between the control signals IN1p and IN1n.

[0042] Structurally, the Gilbert cell multiplies (IN1p-IN1n) by (IN2p-IN2n) to produce an output (OUT1p-OUT1n), which is (IN1p-IN1n) x (IN2p-IN2n). Therefore, the differential signals output from the buffer unit 2, delay unit 4, and LPF 11 may be assigned to IN1p and IN1n, and IN2p and IN2n may be used as control signals.

[0043] In the configuration of Fig. 7, the multiplication units 5, 6, 12, and 13 are configured as differential input / differential output types. To accommodate the configuration of Fig. 7, the buffer units 2 and 3 may be configured as differential output type buffer units. Furthermore, the delay unit 4 may be configured as a differential transmission line consisting of two transmission lines, or may be configured as a cascade connection of differential input / differential output type amplifiers.

[0044] Third Embodiment In this embodiment, a specific example of the adder 7 of the first embodiment will be described. As the adder 7, a current-addition-based CML (Current Mode Logic) block can be used. 8, the adder 7 includes an NPN bipolar transistor Q8 having a base input with the negative phase signal IN5n of the differential signals output from the multiplier 5 and outputting a positive phase output signal OUT2p from its collector, an NPN bipolar transistor Q9 having a base input with the positive phase signal IN5p of the differential signals output from the multiplier 5 and outputting a negative phase output signal OUT2n from its collector, an NPN bipolar transistor Q10 having a base input with the positive phase signal IN6p of the differential signals output from the multiplier 6 and outputting a negative phase output signal OUT2n from its collector, an NPN bipolar transistor Q11 having a base input with the negative phase signal IN6n of the differential signals output from the multiplier 6 and outputting a positive phase output signal OUT2p from its collector, NPN bipolar transistors Q12 and Q13 having bases to which a bias voltage Vb is applied, and an NPN bipolar transistor Q14 having one end connected to the power supply voltage VCC. a resistor R6 having one end connected to the emitter of transistor Q8 and the other end connected to the collectors of transistors Q8 and Q11; a resistor R7 having one end connected to the power supply voltage VCC and the other end connected to the collectors of transistors Q9 and Q10; a resistor R8 having one end connected to the emitter of transistor Q8 and the other end connected to the collector of transistor Q12; a resistor R9 having one end connected to the emitter of transistor Q9 and the other end connected to the collector of transistor Q12; a resistor R10 having one end connected to the emitter of transistor Q10 and the other end connected to the collector of transistor Q13; a resistor R11 having one end connected to the emitter of transistor Q11 and the other end connected to the collector of transistor Q13; a resistor R12 having one end connected to the emitter of transistor Q12 and the other end connected to ground; and a resistor R13 having one end connected to the emitter of transistor Q13 and the other end connected to ground.

[0045] 8, the adder 7 has a differential input / differential output configuration. To accommodate the configuration of Fig. 8, the multipliers 5 and 6 may be configured as differential output types as shown in Fig. 7.

[0046] The configuration of FIG. 8 can also be used as the differential amplifier unit 10. When applied to the differential amplifier unit 10, the positive-phase signal of the differential signal indicating the target amplitude Vref is input as IN6p in FIG. 8, and the negative-phase signal of the differential signal indicating the target amplitude Vref is input as IN6n. Alternatively, the negative-phase signal of the differential signal output from the amplitude detector 9 is input as IN5p in FIG. 8, and the positive-phase signal of the differential signal output from the amplitude detector 9 is input as IN5n. It is possible to provide a gain by selecting the circuit constants. To achieve both high speed and high gain, an amplifier circuit can be provided in the subsequent stage of the configuration of FIG. 8, forming a multi-stage configuration.

[0047] [Fourth Embodiment] In this embodiment, a specific example of the amplitude detector 9 of the first embodiment will be described. A circuit based on a Gilbert cell can be used as the amplitude detector 9. As shown in FIG. 9, the amplitude detector 9 includes an NPN bipolar transistor Q14 having a base input with the negative-phase signal IN7n of the differential signal output from the adder 7, an NPN bipolar transistor Q15 having a base input with the positive-phase signal IN7p of the differential signal output from the adder 7, an NPN bipolar transistor Q16 having its base and collector connected together, an NPN bipolar transistor Q17 having its base and collector connected together, an NPN bipolar transistor Q18 having its base supplied with a bias voltage VB and its collector connected to the emitter of the transistor Q16, an NPN bipolar transistor Q19 having its base supplied with a bias voltage VB and its collector connected to the emitter of the transistor Q17, and an NPN bipolar transistor Q19 having its base supplied with the bias voltage VB and its collector connected to the emitter of the transistor Q17. an NPN bipolar transistor Q20 having a base input with a negative phase signal IN7n of the differential signal; an NPN bipolar transistor Q21 having a base input with a positive phase signal IN7p of the differential signal output from the adder 7; an NPN bipolar transistor Q22 having a base input with a negative phase signal IN7n of the differential signal output from the adder 7; an NPN bipolar transistor Q23 having a base input with a positive phase signal IN7p of the differential signal output from the adder 7; an NPN bipolar transistor Q24 having a base connected to the base and collector of the transistor Q16 and a collector connected to the emitters of the transistors Q20 and Q21; an NPN bipolar transistor Q24 having a base connected to the base and collector of the transistor Q17 and a collector connected to the emitters of the transistors Q22 and Q21;an NPN bipolar transistor Q25 connected to the emitter of transistor Q23; an NPN bipolar transistor Q26 having a base to which a bias voltage VB is applied; a resistor R14 having one end connected to the power supply voltage VCC and the other end connected to the collector of transistor Q14; a resistor R15 having one end connected to the power supply voltage VCC and the other end connected to the collector of transistor Q15; a resistor R16 having one end connected to the emitter of transistor Q14 and the other end connected to the base and collector of transistor Q16; a resistor R17 connected to the emitter of transistor Q15 and the other end to the base and collector of transistor Q17; a resistor R18 connected to the emitter of transistor Q18 and the other end to ground; a resistor R19 connected to the emitter of transistor Q19 and the other end to ground; a resistor R20 connected to the power supply voltage VCC and the other end to the collectors of transistors Q20 and Q23; and a resistor R20 connected to the power supply voltage VCC and the other end to the collectors of transistors Q21 and Q22. a resistor R21 connected to the collector of the transistor Q24; a resistor R22 having one end connected to the emitter of the transistor Q24 and the other end connected to the collector of the transistor Q26; a resistor R23 having one end connected to the emitter of the transistor Q25 and the other end connected to the collector of the transistor Q26; a resistor R24 ​​having one end connected to the emitter of the transistor Q26 and the other end connected to the ground; a resistor R25 having one end connected to the collectors of the transistors Q20 and Q23 and outputting a positive phase output signal OUT3p from the other end; It is composed of a resistor R26 connected to the collectors of the transistors Q21 and Q22 and outputting an output signal OUT3n of the opposite phase from the other end, a capacitor C1 connected to the collectors of the transistors Q20 and Q23 at one end and to the ground at the other end, a capacitor C2 connected to the collectors of the transistors Q21 and Q22 at one end and to the ground at the other end, a capacitor C3 connected to the other end of the resistor R25 at one end and to the ground at the other end, and a capacitor C4 connected to the other end of the resistor R26 at one end and to the ground at the other end.

[0048] In the circuit shown in Figure 9, the output amplitude of the adder 7 is squared by a squarer consisting of transistors Q14 to Q26 and resistors R14 to R24, and the squared amplitude is then flattened by an LPF consisting of resistors R25 and R26 and capacitors C1 to C4 to detect the amplitude. To achieve squaring of the amplitude using a Gilbert cell, it is necessary to absorb the difference in the in-phase signal level between the signals input to transistors Q20 to Q23 and the signals input to transistors Q24 and Q25. Therefore, an emitter follower consisting of transistors Q14 to Q19 and resistors R14 to R19 is inserted in the first stage to adjust the in-phase level of the input signals. Note that the diode-connected transistors Q16 and Q17 can also be replaced with resistors or diodes.

[0049] 9, the amplitude detector 9 has a differential input / differential output configuration. To accommodate the configuration of FIG. 9, the adder 7 may be configured as a differential output type as shown in FIG.

[0050] Fifth Embodiment In this embodiment, a specific example of the LPF 11 of the first embodiment will be described. As shown in Fig. 10, the LPF 11 is composed of a resistor R27 having one end to which a signal output from the differential amplifier 10 is input and the other end connected to the output terminal of the LPF 11, and a capacitor C5 having one end connected to the output terminal of the LPF 11 and the other end connected to ground. An inductor may be used instead of the resistor R27, or a resistor and an inductor may be used together.

[0051] Although a passive LPF configuration is shown in Figure 10, an active filter may also be used. Furthermore, a digital filter may be used instead of an analog filter. That is, the signal may be subjected to analog-to-digital (AD) conversion, digitally processed, and then converted back to an analog signal by digital-to-analog (DA) conversion.

[0052] [Sixth Example] The amplitude detection unit 9 may be configured with a squarer and an LPF as described in the fourth example, but may also be realized with a peak detector as shown in Fig. 11. In the example of Fig. 11, the amplitude detection unit 9 is configured with a diode D1 having an anode to which the signal output from the adder 7 is input and a cathode connected to the output terminal of the amplitude detection unit 9, and a capacitor C6 having one end connected to the output terminal of the amplitude detection unit 9 and the other end connected to ground.

[0053] 12, the amplitude detection unit 9 is made up of a diode D2 having a cathode to which signal IN7p on the positive phase side of the differential signal output from the adder 7 is input, a diode D3 having an anode to which signal IN7p is input, a diode D4 having a cathode to which signal IN7n on the negative phase side of the differential signal output from the adder 7 is input and an anode connected to the anode of the diode D2, a diode D5 having an anode to which signal IN7n is input and a cathode connected to the cathode of the diode D3, an LPF 14 that flattens the signal at the connection point between the anode of the diode D2 and the anode of the diode D4, and an LPF 15 that flattens the signal at the connection point between the cathode of the diode D3 and the cathode of the diode D5. The diodes D2 to D5 form an asynchronous detection circuit.

[0054] [Seventh embodiment] By combining the above-described Gilbert cell and CML, it is possible to realize a configuration in which the multiplication units 5, 6 and the addition unit 7 are integrated. As shown in Fig. 13, this configuration includes an NPN bipolar transistor Q27 having a base to which a control signal IN1n (first control signal) is input and which outputs a positive phase output signal OUT2p from its collector, an NPN bipolar transistor Q28 having a base to which a control signal IN1p (second control signal) is input and which outputs a negative phase output signal OUT2n from its collector, an NPN bipolar transistor Q29 having a base to which the control signal IN1n is input and which outputs a negative phase output signal OUT2n from its collector, and an NPN bipolar transistor Q30 having a base to which a control signal IN1n is input and which outputs a negative phase output signal OUT3n from its collector. An NPN bipolar transistor Q30 receives a control signal IN1p and outputs a positive-phase output signal OUT2p from its collector; an NPN bipolar transistor Q31 receives a positive-phase signal IN2p of the differential signal output from the buffer unit 2 at its base and has its collector connected to the emitters of the transistors Q27 and Q28; and an NPN bipolar transistor Q31 receives a negative-phase signal IN2n of the differential signal output from the buffer unit 2 at its base and has its collector connected to the emitters of the transistors Q29 and Q30. an NPN bipolar transistor Q32, an NPN bipolar transistor Q33 having a base to which a bias voltage VB is applied, an NPN bipolar transistor Q34 having a base to which a control signal IN3n (third control signal) is input and which outputs a positive phase output signal OUT2p from its collector, an NPN bipolar transistor Q35 having a base to which a control signal IN3p (fourth control signal) is input and which outputs a negative phase output signal OUT2n from its collector, and an NPN bipolar transistor Q36 having a base to which a control signal IN3n is input and which outputs a negative phase output signal OUT2p from its collector. an NPN bipolar transistor Q36 having a base to which a control signal IN3p is input and an NPN bipolar transistor Q37 having a collector to which a positive phase output signal OUT2p is output; an NPN bipolar transistor Q38 having a base to which a positive phase signal IN4p of the differential signal output from the delay unit 4 is input and an NPN bipolar transistor Q38 having a base to which a negative phase signal IN4n of the differential signal output from the delay unit 4 is input and an NPN bipolar transistor Q36 having a collector to which a negative phase signal IN4n of the differential signal output from the delay unit 4 is input;an NPN bipolar transistor Q39 connected to the emitter of transistor Q37; an NPN bipolar transistor Q40 having a base to which a bias voltage VB is applied; a resistor R28 having one end connected to the power supply voltage VCC and the other end connected to the collectors of transistors Q27, Q30, Q34, and Q37; a resistor R29 having one end connected to the power supply voltage VCC and the other end connected to the collectors of transistors Q28, Q29, Q35, and Q36; a resistor R30 having one end connected to the emitter of transistor Q31 and the other end connected to the collector of transistor Q33; The resistor R31 is connected to the emitter of transistor Q32 and has the other end connected to the collector of transistor Q33, a resistor R32 is connected to the emitter of transistor Q33 and has the other end connected to ground, a resistor R33 is connected to the emitter of transistor Q38 and has the other end connected to the collector of transistor Q40, a resistor R34 is connected to the emitter of transistor Q39 and has the other end connected to the collector of transistor Q40, and a resistor R35 is connected to the emitter of transistor Q40 and has the other end connected to ground.

[0055] The gain (amplitude A) of the multiplication unit 5 can be controlled by the voltage difference between the control signals IN1p and IN1n, and the gain (amplitude B) of the multiplication unit 6 can be controlled by the voltage difference between the control signals IN3p and IN3n. As described in Fig. 7, the differential signal output from the buffer unit 2 may be assigned to IN1p and IN1n, the differential signal output from the delay unit 4 may be assigned to IN3p and IN3, and IN2p, IN2n, IN4p, and IN4n may be used as control signals.

[0056] With the configuration shown in FIG. 13, the output obtained by adding the result of multiplying (IN1p-IN1n) by (IN2p-IN2n) and the result of multiplying (IN3p-IN3n) by (IN4p-IN4n) together is {(IN1p-IN1n) x (IN2p-IN2n)} + {(IN3p-IN3n) x (IN4p-IN4n)}, which becomes (OUT2p-OUT2n).

[0057] 7 to 9 and 13 show examples in which bipolar transistors are used as the transistors Q1 to Q40, but MOS transistors may also be used. In this case, the base, collector, and emitter in the above description may be replaced with the gate, drain, and source, respectively.

[0058] Furthermore, a resistor or capacitor may be inserted into the emitter or source of the transistor to adjust the gain or frequency response, or both a resistor and a capacitor may be inserted. Furthermore, an optional amplifier circuit such as an emitter follower may be provided as needed to adjust the level or driving force.

[0059] Some or all of the above embodiments can be described as, but are not limited to, the following supplementary notes.

[0060] (Supplementary Note 1) A phase adjustment circuit of the present invention includes a sine wave output unit configured to output two sine wave signals with a fixed phase difference; a first multiplier configured to output a signal obtained by multiplying the amplitude of the first sine wave signal output from the sine wave output unit by a first variable; a second multiplier configured to output a signal obtained by multiplying the amplitude of the second sine wave signal output from the sine wave output unit by a second variable; an adder configured to add the signal output from the first multiplier and the signal output from the second multiplier; an amplitude detector configured to detect the amplitude of the output signal of the adder; The amplifier includes a differential amplifier configured to subtract the amplitude detected by the amplitude detector from a target amplitude and amplify the result; a first low-pass filter configured to smooth the output result of the differential amplifier; a third multiplier configured to multiply the amplitude of the signal output from the first low-pass filter by a first constant and provide the resulting signal to the first multiplier as a control signal for determining the first variable; and a fourth multiplier configured to multiply the amplitude of the signal output from the first low-pass filter by a second constant and provide the resulting signal to the second multiplier as a control signal for determining the second variable.

[0061] (Supplementary Note 2) In the phase adjustment circuit according to Supplementary Note 1, the first multiplier section includes a first transistor having a base or gate to which a first control signal or a signal on the negative phase side of the first sine wave signal in a differential format is input, and which outputs a signal on the positive phase side from a collector or drain; a second transistor having a base or gate to which a second control signal or a signal on the positive phase side of the first sine wave signal is input, and which outputs a signal on the negative phase side from a collector or drain; and a second transistor having a base or gate to which a second control signal or a signal on the negative phase side of the first sine wave signal is input, and which outputs a signal on the negative phase side from a collector or drain. a third transistor that outputs a negative-phase signal from its drain; a fourth transistor that receives the second control signal or the positive-phase signal of the first sine wave signal at its base or gate and outputs a positive-phase signal from its collector or drain; a fifth transistor that receives the positive-phase signal of the first sine wave signal or the second control signal at its base or gate and has its collector or drain connected to the emitters or sources of the first and second transistors; a sixth transistor having a collector or drain connected to the emitter or source of the third and fourth transistors; a seventh transistor having a base or gate to which a bias voltage is applied; a first resistor having one end connected to a power supply voltage and the other end connected to the collectors or drains of the first and fourth transistors; a second resistor having one end connected to the power supply voltage and the other end connected to the collectors or drains of the second and third transistors; and a fifth transistor having one end connected to the emitter or source of the fifth transistor and the other end connected to the emitter or source of the seventh transistor. the second multiplier section comprises an eighth transistor having a base or gate to which a third control signal or a reversed-phase signal of the second sine wave signal in a differential format is input, and a third resistor connected to the collector or drain of the sixth transistor, a fourth resistor having one end connected to the emitter or source of the sixth transistor and the other end connected to the collector or drain of the seventh transistor, and a fifth resistor having one end connected to the emitter or source of the seventh transistor and the other end connected to ground; the second multiplier section comprises an eighth transistor having a base or gate to which a third control signal or a reversed-phase signal of the second sine wave signal in a differential format is input, and which outputs a positive-phase signal from a collector or drain;a ninth transistor having a base or gate to which the fourth control signal or the positive-phase signal of the second sine wave signal is input and which outputs a negative-phase signal from its collector or drain; a tenth transistor having a base or gate to which the third control signal or the negative-phase signal of the second sine wave signal is input and which outputs a negative-phase signal from its collector or drain; an eleventh transistor having a base or gate to which the fourth control signal or the positive-phase signal of the second sine wave signal is input and which outputs a positive-phase signal from its collector or drain; a twelfth transistor having a base or gate to which the positive-phase signal of the second sine wave signal or the fourth control signal is input and which has a collector or drain connected to the emitters or sources of the eighth and ninth transistors; a thirteenth transistor connected to the emitters or sources of the tenth and eleventh transistors, a fourteenth transistor having a base or gate to which a bias voltage is applied, a sixth resistor having one end connected to a power supply voltage and the other end connected to the collectors or drains of the eighth and eleventh transistors, a seventh resistor having one end connected to the power supply voltage and the other end connected to the collectors or drains of the ninth and tenth transistors, an eighth resistor having one end connected to the emitter or source of the twelfth transistor and the other end connected to the collector or drain of the fourteenth transistor, a ninth resistor having one end connected to the emitter or source of the thirteenth transistor and the other end connected to the collector or drain of the fourteenth transistor, and a tenth resistor having one end connected to the emitter or source of the fourteenth transistor and the other end connected to ground.

[0062] (Supplementary Note 3) In the phase adjustment circuit according to Supplementary Note 1, the adder section includes a first transistor having a base or gate to which the negative phase signal of the differential signal output from the first multiplier section is input and which outputs a positive phase signal from a collector or drain; a second transistor having a base or gate to which the positive phase signal of the differential signal output from the first multiplier section is input and which outputs a negative phase signal from a collector or drain; a third transistor having a base or gate to which the positive phase signal of the differential signal output from the second multiplier section is input and which outputs a negative phase signal from a collector or drain; a fourth transistor having a base or gate to which the negative phase signal of the differential signal output from the second multiplier section is input and which outputs a positive phase signal from a collector or drain; fifth and sixth transistors having a bias voltage applied to their bases or gates; a first resistor having one end connected to a power supply voltage and the other end connected to the collectors or drains of the first and fourth transistors; a second resistor having one end connected to the emitter or source of the first transistor and the other end connected to the collector or drain of the second and third transistors; a third resistor having one end connected to the emitter or source of the first transistor and the other end connected to the collector or drain of the fifth transistor; a fourth resistor having one end connected to the emitter or source of the second transistor and the other end connected to the collector or drain of the fifth transistor; a fifth resistor having one end connected to the emitter or source of the third transistor and the other end connected to the collector or drain of the sixth transistor; a sixth resistor having one end connected to the emitter or source of the fourth transistor and the other end connected to the collector or drain of the sixth transistor; a seventh resistor having one end connected to the emitter or source of the fifth transistor and the other end connected to ground; and an eighth resistor having one end connected to the emitter or source of the sixth transistor and the other end connected to ground.

[0063] (Supplementary Note 4) In the phase adjustment circuit described in Supplementary Note 1, the amplitude detection unit includes a squarer configured to square the output amplitude of the addition unit, and a second low-pass filter configured to flatten the amplitude squared by the squarer.

[0064] (Supplementary Note 5) In the phase adjustment circuit according to Supplementary Note 4, the squarer includes a first transistor having a base to which the negative-phase signal of the differential signal output from the adder is input, a second transistor having a base to which the positive-phase signal of the differential signal output from the adder is input, a third transistor having a base and a collector connected together, a fourth transistor having a base and a collector connected together, a fifth transistor having a base to which a bias voltage is applied and a collector connected to the emitter of the third transistor, and a fifth transistor having a base to which a bias voltage is applied and a collector connected to the emitter of the fourth transistor. a sixth transistor connected to the emitter of the first transistor, a seventh transistor having a base to which the negative-phase signal of the differential signal output from the adder is input, an eighth transistor having a base to which the positive-phase signal of the differential signal output from the adder is input, a ninth transistor having a base to which the negative-phase signal of the differential signal output from the adder is input, a tenth transistor having a base to which the positive-phase signal of the differential signal output from the adder is input, and a nin ... negative-phase signal of the differential signal output from the adder is input. an eleventh transistor connected to the emitter of the eighth transistor; a twelfth transistor having a base connected to the base and collector of the fourth transistor and a collector connected to the emitters of the ninth and tenth transistors; a thirteenth transistor having a base to which a bias voltage is applied; a first resistor having one end connected to a power supply voltage and the other end connected to the collector of the first transistor; a second resistor having one end connected to the power supply voltage and the other end connected to the collector of the second transistor; a third resistor having one end connected to the emitter of the second transistor and the other end connected to the base and collector of the third transistor; a fourth resistor having one end connected to the emitter of the second transistor and the other end connected to the base and collector of the fourth transistor; a fifth resistor having one end connected to the emitter of the fifth transistor and the other end connected to ground; a sixth resistor having one end connected to the emitter of the sixth transistor and the other end connected to ground; and a seventh resistor having one end connected to the power supply voltage and the other ends connected to the collectors of the seventh and tenth transistors.The second low-pass filter is composed of an eighth resistor having one end connected to the power supply voltage and the other end connected to the collectors of the eighth and ninth transistors, a ninth resistor having one end connected to the emitter of the eleventh transistor and the other end connected to the collector of the thirteenth transistor, a tenth resistor having one end connected to the emitter of the twelfth transistor and the other end connected to the collector of the thirteenth transistor, and an eleventh resistor having one end connected to the emitter of the thirteenth transistor and the other end connected to ground. a 12th resistor having one end connected to the collectors of the eighth and ninth transistors and outputting a positive phase output signal from the other end; a 13th resistor having one end connected to the collectors of the eighth and ninth transistors and outputting a negative phase output signal from the other end; a first capacitor having one end connected to the collectors of the seventh and tenth transistors and the other end connected to ground; a second capacitor having one end connected to the collectors of the eighth and ninth transistors and the other end connected to ground; a third capacitor having one end connected to the other end of the 12th resistor and the other end connected to ground; and a fourth capacitor having one end connected to the other end of the 13th resistor and the other end connected to ground.

[0065] (Supplementary Note 6) In the phase adjustment circuit described in Supplementary Note 1, the amplitude detection unit includes a first diode having a cathode to which the positive-phase signal of the differential signals output from the adder is input, a second diode having an anode to which the positive-phase signal of the differential signals output from the adder is input, a third diode having a cathode to which the negative-phase signal of the differential signals output from the adder is input and an anode connected to the anode of the first diode, a fourth diode having an anode to which the negative-phase signal of the differential signals output from the adder is input and an anode connected to the cathode of the second diode, a second low-pass filter configured to flatten a signal at a connection point between the anode of the first diode and the anode of the third diode, and a third low-pass filter configured to flatten a signal at a connection point between the cathode of the second diode and the cathode of the fourth diode.

[0066] (Supplementary Note 7) In the phase adjustment circuit according to Supplementary Note 1, the differential amplifier section includes a first transistor having a base or gate to which the positive-phase signal of the differential signal output from the amplitude detection section is input and which outputs the positive-phase signal from a collector or drain; a second transistor having a base or gate to which the negative-phase signal of the differential signal output from the amplitude detection section is input and which outputs the negative-phase signal from a collector or drain; a third transistor having a base or gate to which the positive-phase signal of the differential signal indicating the target amplitude is input and which outputs the negative-phase signal from a collector or drain; a fourth transistor having a base or gate to which the negative-phase signal of the differential signal indicating the target amplitude is input and which outputs the positive-phase signal from a collector or drain; fifth and sixth transistors having bases or gates to which a bias voltage is applied; a first resistor having one end connected to a power supply voltage and the other end connected to the collectors or drains of the first and fourth transistors; a second resistor having one end connected to the collector or drain of the second and third transistors; a third resistor having one end connected to the emitter or source of the first transistor and the other end connected to the collector or drain of the fifth transistor; a fourth resistor having one end connected to the emitter or source of the second transistor and the other end connected to the collector or drain of the fifth transistor; a fifth resistor having one end connected to the emitter or source of the third transistor and the other end connected to the collector or drain of the sixth transistor; a sixth resistor having one end connected to the emitter or source of the fourth transistor and the other end connected to the collector or drain of the sixth transistor; a seventh resistor having one end connected to the emitter or source of the fifth transistor and the other end connected to ground; and an eighth resistor having one end connected to the emitter or source of the sixth transistor and the other end connected to ground.

[0067] (Supplementary Note 8) In the phase adjustment circuit according to Supplementary Note 1, the first and second multiplication units and the addition unit comprise a first transistor having a base or gate to which a first control signal or a signal on the negative phase side of the first sine wave signal in a differential format is input and which outputs a signal on the positive phase side from a collector or drain, a second transistor having a base or gate to which a second control signal or a signal on the positive phase side of the first sine wave signal is input and which outputs a signal on the negative phase side from a collector or drain, and a second transistor having a base or gate to which the first control signal or the signal on the negative phase side of the first sine wave signal is input. a third transistor to which the second control signal or the positive-phase signal of the first sine wave signal is input and outputs a negative-phase signal from its collector or drain; a fourth transistor to which the second control signal or the positive-phase signal of the first sine wave signal is input to its base or gate and outputs a positive-phase signal from its collector or drain; a fifth transistor to which the positive-phase signal of the first sine wave signal or the second control signal is input to its base or gate and whose collector or drain is connected to the emitters or sources of the first and second transistors; or a sixth transistor to which the first control signal is input and whose collector or drain is connected to the emitters or sources of the third and fourth transistors; a seventh transistor to which a bias voltage is applied at its base or gate; an eighth transistor to which the third control signal or the negative-phase signal of the second sine wave signal in a differential format is input at its base or gate and which outputs a positive-phase signal from its collector or drain; a ninth transistor to which the fourth control signal or the positive-phase signal of the second sine wave signal is input at its base or gate and which outputs a negative-phase signal from its collector or drain; a tenth transistor to which the third control signal or the negative-phase signal of the second sine wave signal is input at its base or gate and which outputs a negative-phase signal from its collector or drain; an eleventh transistor to which the fourth control signal or the positive-phase signal of the second sine wave signal is input at its base or gate and which outputs a positive-phase signal from its collector or drain;a twelfth transistor connected to the emitter or source of the ninth transistor; a thirteenth transistor having a base or gate to which the inverted signal of the second sine wave signal or the third control signal is input and a collector or drain to which the tenth and eleventh transistors are connected; a fourteenth transistor having a base or gate to which a bias voltage is applied; a first resistor having one end connected to a power supply voltage and the other end connected to the collectors or drains of the first, fourth, eighth and eleventh transistors; a second resistor having one end connected to the power supply voltage and the other end connected to the collectors or drains of the second, third, ninth and tenth transistors; a third resistor connected to the emitter or drain of the sixth transistor, a fourth resistor having one end connected to the emitter or source of the sixth transistor and the other end connected to the collector or drain of the seventh transistor, a fifth resistor having one end connected to the emitter or source of the seventh transistor and the other end connected to ground, a sixth resistor having one end connected to the emitter or source of the twelfth transistor and the other end connected to the collector or drain of the fourteenth transistor, a seventh resistor having one end connected to the emitter or source of the thirteenth transistor and the other end connected to the collector or drain of the fourteenth transistor, and an eighth resistor having one end connected to the emitter or source of the fourteenth transistor and the other end connected to ground.

[0068] The present invention can be applied to a technique for adjusting the phase of a sine wave.

[0069] 1...clock generation unit, 2, 3...buffer unit, 4...delay unit, 5, 6, 12, 13...multiplication unit, 7...addition unit, 9...amplitude detection unit, 10...differential amplification unit, 11, 14, 15...low-pass filter, 16...sine wave output unit, Q1 to Q40...transistors, D1 to D5...diodes, R1 to R35...resistors, C1 to C6...capacitors.

Claims

1. A sine wave output section configured to output two sine wave signals with a fixed phase difference, A first multiplication section configured to output a signal obtained by multiplying the amplitude of the first sine wave signal output from the sine wave output section by a first variable, A second multiplication section configured to output a signal obtained by multiplying the amplitude of the second sine wave signal output from the sine wave output section by a second variable, An addition section configured to add the signal output from the first multiplication section and the signal output from the second multiplication section A phase adjustment circuit comprising.

2. In the phase adjustment circuit according to claim 1, further, Based on the amplitude of the output signal of the addition section, a first control signal for determining the first variable and a second control signal for determining the second variable are obtained, and the first control signal and the second control signal are respectively given to the first multiplication section and the second multiplication section A phase adjustment circuit comprising a feedback circuit configured to perform the above.

3. In the phase adjustment circuit according to claim 2, The feedback circuit is, An amplitude detection section configured to detect the amplitude of the output signal of the addition section, A differential amplification section configured to subtract the amplitude detected by the amplitude detection section from the target amplitude and amplify it, A first low-pass filter configured to flatten the output result of the differential amplification section, A third multiplication section configured to give a signal obtained by multiplying the amplitude of the signal output from the first low-pass filter by a first constant to the first multiplication section as a control signal for determining the first variable, A phase adjustment circuit characterized by including a fourth multiplication section configured to give a signal obtained by multiplying the amplitude of the signal output from the first low-pass filter by a second constant to the second multiplication section as a control signal for determining the second variable.

4. In the phase adjustment circuit according to claim 2, The first multiplication section is, A first transistor in which a first control signal or a signal on the reverse phase side of the first sine wave signal in differential form is input to the base or gate, and a signal on the positive phase side is output from the collector or drain, A second transistor in which a second control signal or a signal on the positive phase side of the first sine wave signal is input to the base or gate, and a signal on the reverse phase side is output from the collector or drain, A third transistor having the inverted-phase signal of the first control signal or the first sine wave signal input to the base or gate and outputting the inverted-phase signal from the collector or drain; A fourth transistor having the in-phase signal of the second control signal or the first sine wave signal input to the base or gate and outputting the in-phase signal from the collector or drain; A fifth transistor having the in-phase signal of the first sine wave signal or the second control signal input to the base or gate and having the collector or drain connected to the emitter or source of the first and second transistors; A sixth transistor having the inverted-phase signal of the first sine wave signal or the first control signal input to the base or gate and having the collector or drain connected to the emitter or source of the third and fourth transistors; A seventh transistor having a bias voltage applied to the base or gate; A first resistor having one end connected to the power supply voltage and the other end connected to the collector or drain of the first and fourth transistors; A second resistor having one end connected to the power supply voltage and the other end connected to the collector or drain of the second and third transistors; A third resistor having one end connected to the emitter or source of the fifth transistor and the other end connected to the collector or drain of the seventh transistor; A fourth resistor having one end connected to the emitter or source of the sixth transistor and the other end connected to the collector or drain of the seventh transistor; It is composed of a fifth resistor having one end connected to the emitter or source of the seventh transistor and the other end connected to the ground, The second multiplier unit, An eighth transistor having the inverted-phase signal of the third control signal or the second sine wave signal in differential form input to the base or gate and outputting the in-phase signal from the collector or drain; A ninth transistor having the in-phase signal of the fourth control signal or the second sine wave signal input to the base or gate and outputting the inverted-phase signal from the collector or drain; A tenth transistor having the third control signal or the inverted-phase signal of the second sine wave signal input to the base or gate and outputting the inverted-phase signal from the collector or drain; An eleventh transistor in which the fourth control signal or a signal on the positive phase side of the second sine wave signal is input to the base or gate, and the signal on the positive phase side is output from the collector or drain; A twelfth transistor in which the signal on the positive phase side of the second sine wave signal or the fourth control signal is input to the base or gate, and the collector or drain is connected to the emitter or source of the eighth and ninth transistors; A thirteenth transistor in which the signal on the negative phase side of the second sine wave signal or the third control signal is input to the base or gate, and the collector or drain is connected to the emitter or source of the tenth and eleventh transistors; A fourteenth transistor to which a bias voltage is applied to the base or gate; A sixth resistor having one end connected to the power supply voltage and the other end connected to the collector or drain of the eighth and eleventh transistors; A seventh resistor having one end connected to the power supply voltage and the other end connected to the collector or drain of the ninth and tenth transistors; An eighth resistor having one end connected to the emitter or source of the twelfth transistor and the other end connected to the collector or drain of the fourteenth transistor; A ninth resistor having one end connected to the emitter or source of the thirteenth transistor and the other end connected to the collector or drain of the fourteenth transistor; A phase adjustment circuit characterized by comprising a tenth resistor having one end connected to the emitter or source of the fourteenth transistor and the other end connected to the ground.

5. In the phase adjustment circuit according to claim 2, The adding unit includes: A first transistor in which a signal on the negative phase side of the differential signal output from the first multiplying unit is input to the base or gate, and the signal on the positive phase side is output from the collector or drain; A second transistor in which a signal on the positive phase side of the differential signal output from the first multiplying unit is input to the base or gate, and the signal on the negative phase side is output from the collector or drain; A third transistor in which a signal on the positive phase side of the differential signal output from the second multiplying unit is input to the base or gate, and the signal on the negative phase side is output from the collector or drain; A fourth transistor in which a signal on the negative phase side of the differential signal output from the second multiplying unit is input to the base or gate, and the signal on the positive phase side is output from the collector or drain; A fifth and a sixth transistor to which a bias voltage is applied to a base or a gate; A first resistor having one end connected to a power supply voltage and the other end connected to a collector or a drain of the first and fourth transistors; A second resistor having one end connected to the power supply voltage and the other end connected to a collector or a drain of the second and third transistors; A third resistor having one end connected to an emitter or a source of the first transistor and the other end connected to a collector or a drain of the fifth transistor; A fourth resistor having one end connected to an emitter or a source of the second transistor and the other end connected to a collector or a drain of the fifth transistor; A fifth resistor having one end connected to an emitter or a source of the third transistor and the other end connected to a collector or a drain of the sixth transistor; A sixth resistor having one end connected to an emitter or a source of the fourth transistor and the other end connected to a collector or a drain of the sixth transistor; A seventh resistor having one end connected to an emitter or a source of the fifth transistor and the other end connected to ground; A phase adjustment circuit characterized by comprising an eighth resistor having one end connected to an emitter or a source of the sixth transistor and the other end connected to ground.

6. In the phase adjustment circuit according to Claim 3, the amplitude detection unit is composed of a squarer configured to square the output amplitude of the addition unit, and a second low-pass filter configured to flatten the amplitude squared by the squarer. A phase adjustment circuit characterized by this.

7. In the phase adjustment circuit according to Claim 6, the squarer is a first transistor having an inverted-phase side signal output from the addition unit input to its base, a second transistor having a non-inverted-phase side signal output from the addition unit input to its base, a third transistor having its base and collector connected, a fourth transistor having its base and collector connected, a fifth transistor having a bias voltage applied to its base and its collector connected to the emitter of the third transistor, and a sixth transistor having a bias voltage applied to its base and its collector connected to the emitter of the fourth transistor. a seventh transistor having an inverted-phase side signal of the differential signal output from the addition unit input to its base; an eighth transistor having a non-inverted-phase side signal of the differential signal output from the addition unit input to its base; a ninth transistor having an inverted-phase side signal of the differential signal output from the addition unit input to its base; a tenth transistor having a non-inverted-phase side signal of the differential signal output from the addition unit input to its base; an eleventh transistor having its base connected to the base and collector of the third transistor and its collector connected to the emitters of the seventh and eighth transistors; a twelfth transistor having its base connected to the base and collector of the fourth transistor and its collector connected to the emitters of the ninth and tenth transistors; a thirteenth transistor having a bias voltage applied to its base; a first resistor having one end connected to a power supply voltage and the other end connected to the collector of the first transistor; a second resistor having one end connected to the power supply voltage and the other end connected to the collector of the second transistor; a third resistor having one end connected to the emitter of the first transistor and the other end connected to the base and collector of the third transistor; a fourth resistor having one end connected to the emitter of the second transistor and the other end connected to the base and collector of the fourth transistor; a fifth resistor having one end connected to the emitter of the fifth transistor and the other end connected to ground; a sixth resistor having one end connected to the emitter of the sixth transistor and the other end connected to ground; a seventh resistor having one end connected to the power supply voltage and the other end connected to the collectors of the seventh and tenth transistors; an eighth resistor having one end connected to the power supply voltage and the other end connected to the collectors of the eighth and ninth transistors; a ninth resistor having one end connected to the emitter of the eleventh transistor and the other end connected to the collector of the thirteenth transistor; a tenth resistor having one end connected to the emitter of the twelfth transistor and the other end connected to the collector of the thirteenth transistor; and an eleventh resistor having one end connected to the emitter of the thirteenth transistor and the other end connected to ground, The second low-pass filter is A 12th resistor having one end connected to the collectors of the 7th and 10th transistors and outputting a positive-phase output signal from the other end, A 13th resistor having one end connected to the collectors of the 8th and 9th transistors and outputting a negative-phase output signal from the other end, A first capacitor having one end connected to the collectors of the 7th and 10th transistors and the other end connected to ground, A second capacitor having one end connected to the collectors of the 8th and 9th transistors and the other end connected to ground, A third capacitor having one end connected to the other end of the 12th resistor and the other end connected to ground, A phase adjustment circuit characterized by comprising a fourth capacitor having one end connected to the other end of the 13th resistor and the other end connected to ground.

8. In the phase adjustment circuit according to Claim 3, The amplitude detection unit A first diode having a positive-phase signal of the differential signal output from the addition unit input to the cathode, A second diode having a positive-phase signal of the differential signal output from the addition unit input to the anode, A third diode having a negative-phase signal of the differential signal output from the addition unit input to the cathode and the anode connected to the anode of the first diode, A fourth diode having a negative-phase signal of the differential signal output from the addition unit input to the anode and the cathode connected to the cathode of the second diode, A second low-pass filter configured to flatten the signal at the connection point of the anode of the first diode and the anode of the third diode, A phase adjustment circuit characterized by comprising a third low-pass filter configured to flatten the signal at the connection point of the cathode of the second diode and the cathode of the fourth diode.

9. In the phase adjustment circuit according to Claim 3, The differential amplification unit A first transistor having a positive-phase signal of the differential signal output from the amplitude detection unit input to the base or gate and outputting a positive-phase signal from the collector or drain, A second transistor having a negative-phase signal of the differential signal output from the amplitude detection unit input to the base or gate and outputting a negative-phase signal from the collector or drain, A third transistor having a positive-phase signal of the differential signal indicating the target amplitude input to the base or gate and outputting a negative-phase signal from the collector or drain, A fourth transistor to which a signal on the inverted phase side of a differential signal indicating the target amplitude is input to the base or gate, and a signal on the non-inverted phase side is output from the collector or drain; Fifth and sixth transistors to which a bias voltage is applied to the base or gate; A first resistor having one end connected to the power supply voltage and the other end connected to the collector or drain of the first and fourth transistors; A second resistor having one end connected to the power supply voltage and the other end connected to the collector or drain of the second and third transistors; A third resistor having one end connected to the emitter or source of the first transistor and the other end connected to the collector or drain of the fifth transistor; A fourth resistor having one end connected to the emitter or source of the second transistor and the other end connected to the collector or drain of the fifth transistor; A fifth resistor having one end connected to the emitter or source of the third transistor and the other end connected to the collector or drain of the sixth transistor; A sixth resistor having one end connected to the emitter or source of the fourth transistor and the other end connected to the collector or drain of the sixth transistor; A seventh resistor having one end connected to the emitter or source of the fifth transistor and the other end connected to ground; A phase adjustment circuit comprising an eighth resistor having one end connected to the emitter or source of the sixth transistor and the other end connected to ground.

10. In the phase adjustment circuit according to claim 2, The first and second multiplier sections and the adder section A first transistor to which a first control signal or a signal on the inverted phase side of the first sine wave signal in differential form is input to the base or gate, and a signal on the non-inverted phase side is output from the collector or drain; A second transistor to which a second control signal or a signal on the non-inverted phase side of the first sine wave signal is input to the base or gate, and a signal on the inverted phase side is output from the collector or drain; A third transistor to which the first control signal or a signal on the inverted phase side of the first sine wave signal is input to the base or gate, and a signal on the inverted phase side is output from the collector or drain; A fourth transistor to which the second control signal or a signal on the non-inverted phase side of the first sine wave signal is input to the base or gate, and a signal on the non-inverted phase side is output from the collector or drain; A fifth transistor having the positive-phase signal of the first sine-wave signal or the second control signal input to its base or gate and having its collector or drain connected to the emitter or source of the first and second transistors; A sixth transistor having the negative-phase signal of the first sine-wave signal or the first control signal input to its base or gate and having its collector or drain connected to the emitter or source of the third and fourth transistors; A seventh transistor having a bias voltage applied to its base or gate; An eighth transistor having the third control signal or the negative-phase signal of the second sine-wave signal in differential form input to its base or gate and outputting a positive-phase signal from its collector or drain; A ninth transistor having the fourth control signal or the positive-phase signal of the second sine-wave signal input to its base or gate and outputting a negative-phase signal from its collector or drain; A tenth transistor having the third control signal or the negative-phase signal of the second sine-wave signal input to its base or gate and outputting a negative-phase signal from its collector or drain; An eleventh transistor having the fourth control signal or the positive-phase signal of the second sine-wave signal input to its base or gate and outputting a positive-phase signal from its collector or drain; A twelfth transistor having the positive-phase signal of the second sine-wave signal or the fourth control signal input to its base or gate and having its collector or drain connected to the emitter or source of the eighth and ninth transistors; A thirteenth transistor having the negative-phase signal of the second sine-wave signal or the third control signal input to its base or gate and having its collector or drain connected to the emitter or source of the tenth and eleventh transistors; A fourteenth transistor having a bias voltage applied to its base or gate; A first resistor having one end connected to the power supply voltage and the other end connected to the collector or drain of the first, fourth, eighth, and eleventh transistors; A second resistor having one end connected to the power supply voltage and the other end connected to the collector or drain of the second, third, ninth, and tenth transistors; A third resistor having one end connected to the emitter or source of the fifth transistor and the other end connected to the collector or drain of the seventh transistor; A fourth resistor having one end connected to the emitter or source of the sixth transistor and the other end connected to the collector or drain of the seventh transistor; A fifth resistor having one end connected to the emitter or source of the seventh transistor and the other end connected to ground; A sixth resistor having one end connected to the emitter or source of the twelfth transistor and the other end connected to the collector or drain of the fourteenth transistor; A seventh resistor having one end connected to the emitter or source of the thirteenth transistor and the other end connected to the collector or drain of the fourteenth transistor; A phase adjustment circuit characterized by comprising an eighth resistor having one end connected to the emitter or source of the fourteenth transistor and the other end connected to ground.