Multilayer ceramic electronic component and mounting structure of multilayer ceramic electronic component

Abstract

Provided is a multilayer ceramic electronic component capable of suppressing deterioration in insulation resistance due to hydrogen.　In a multilayer ceramic electronic component according to the present invention, a first external electrode 30a has: a first base electrode layer 32a; a first lower plating layer 34a1 disposed on the first base electrode layer 32a; and a first upper plating layer 34a2 that is disposed on the first lower plating layer 34a1 excluding a first plating exposed region 35a, such that the first lower plating layer 34a1 has the first plating exposed region 35a exposed to a surface of the first external electrode 30a. A second external electrode 30b has: a second base electrode layer 32b; a second lower plating layer 34b1 disposed on the second base electrode layer 32b; and a second upper plating layer 34b2 that is disposed on the second lower plating layer 34b1 excluding a second plating exposed region 35b, such that the second lower plating layer 34b1 has the second plating exposed region 35b exposed to a surface of the second external electrode 30b.

Description

Multilayer ceramic electronic component and mounting structure for the same

[0001] The present invention relates to a multilayer ceramic electronic component and a mounting structure for the multilayer ceramic electronic component.

[0002] The multilayer ceramic capacitor includes a laminate and external electrodes. The laminate includes an inner layer portion and an outer layer portion. The inner layer portion is formed by alternately stacking multiple ceramic layers and multiple internal electrode layers in a predetermined stacking direction. The outer layer portion is formed by arranging ceramic layers on the surface of the inner layer portion so as to sandwich the inner layer portion in the stacking direction. The multiple internal electrode layers are exposed at both end faces in the longitudinal direction perpendicular to the stacking direction. The external electrodes are arranged on the surfaces of the end faces so as to be electrically connected to the internal electrode layers exposed from the end faces. The external electrodes include a Ni plating layer for preventing solder erosion when the multilayer ceramic capacitor is mounted on a substrate using solder, and a Sn plating layer arranged on the Ni plating layer for improving solder application performance. The Ni plating layer and the Sn plating layer are usually formed using an electrolytic plating method.

[0003] Patent Document 1 discloses that hydrogen generated by a chemical reaction during the plating process for forming a plating layer degrades the performance of a multilayer ceramic capacitor. Specifically, hydrogen generated during the plating process is absorbed by the internal electrode layers, causing problems such as deterioration of dielectric loss and insulation resistance. To solve this problem, Patent Document 1 describes that, for example, by adding a metal such as Ni to internal electrode layers whose main component is an Ag-Pd alloy, absorption of hydrogen by the internal electrode layers is suppressed, thereby suppressing deterioration of the ceramic layers.

[0004] Japanese Unexamined Patent Publication No. 64-80011

[0005] However, although Patent Document 1 describes that Ni inactivates the hydrogen absorption function, research by the inventors of the present application has shown that even when Ni or the like is contained in the materials constituting the internal electrode layers and external electrodes, etc., hydrogen is absorbed into the internal electrode layers and external electrodes, etc., and the absorbed hydrogen is released from the metal depending on the temperature conditions, and this hydrogen causes deterioration of the insulation resistance. In particular, when a high-temperature, high-humidity load test such as a PCBT (Pressure Cooker Bias Test) is performed, the hydrogen released from the metal that has absorbed hydrogen causes significant deterioration of the insulation resistance, which may lead to deterioration of the multilayer ceramic capacitor.

[0006] SUMMARY OF THE INVENTION Therefore, a primary object of the present invention is to provide a multilayer ceramic electronic component and a mounting structure for the multilayer ceramic electronic component that are capable of suppressing deterioration of insulation resistance due to hydrogen.

[0007] A multilayer ceramic electronic component according to the present invention comprises a laminate having a plurality of laminated ceramic layers, the laminate having first and second main surfaces opposing each other in a height direction, first end faces and second end faces opposing each other in a length direction perpendicular to the height direction, and first and second side surfaces opposing each other in a width direction perpendicular to the height direction and the length direction; a plurality of first internal electrode layers arranged on the plurality of ceramic layers and extended to the first end faces; a plurality of second internal electrode layers arranged on the plurality of ceramic layers and extended to the second end faces; a first external electrode arranged on the first end face and extending from the first end face to a portion of the first main surface, a portion of the second main surface, a portion of the first side face, and a portion of the second side face, the first external electrode being connected to the first internal electrode layers; and a second external electrode arranged on the second end face and extending from the second end face to a portion of the first main surface, a portion of the second main surface, and the second side face. a second external electrode disposed on a portion of the first side surface and a portion of the second side surface and connected to the second internal electrode layer, wherein the first external electrode comprises a first base electrode layer disposed on the laminate, a first lower plating layer disposed on the first base electrode layer, and a first upper plating layer disposed on the first lower plating layer excluding the first exposed plating region such that the first lower plating layer has a first exposed plating region exposed on the surface of the first external electrode; and the second external electrode comprises a second base electrode layer disposed on the laminate, a second lower plating layer disposed on the second base electrode layer, and a second upper plating layer disposed on the second lower plating layer excluding the second exposed plating region such that the second lower plating layer has a second exposed plating region exposed on the surface of the second external electrode.

[0008] In the multilayer ceramic electronic component according to the present invention, the first lower-layer plating layer is exposed on the surface of the first external electrode in the first exposed plating region, allowing hydrogen within the multilayer ceramic electronic component to be released from the first exposed plating region to the outside of the multilayer ceramic electronic component. Furthermore, the second lower-layer plating layer is exposed on the surface of the second external electrode in the second exposed plating region, allowing hydrogen within the multilayer ceramic electronic component to be released from the second exposed plating region to the outside of the multilayer ceramic electronic component. Hydrogen ions are generated by chemical reactions during the plating process for forming the first and second lower-layer plating layers and the first and second upper-layer plating layers. These hydrogen ions may be absorbed as hydrogen by at least one of the first and second lower-layer plating layers, the first and second internal electrode layers, and the first and second base electrode layers. With the above configuration, hydrogen absorbed in at least one layer (absorption layer) of the first and second lower-layer plating layers, the first and second internal electrode layers, and the first and second base electrode layers can be released from the first and second exposed plating regions to the outside of the multilayer ceramic electronic component. Therefore, hydrogen is prevented from remaining absorbed in the absorption layer, and deterioration of insulation resistance due to hydrogen can be suppressed. In particular, even when the absorption layer contains a metal such as Ni that does not easily absorb hydrogen, deterioration of insulation resistance of the ceramic layer can be suppressed by releasing hydrogen from the first and second exposed plating regions to the outside of the multilayer ceramic electronic component. Note that when the first and second exposed plating regions are formed on the first main surface side, the second main surface side serves as the mounting surface for the multilayer ceramic capacitor to a mounting substrate, and solder is applied mainly to the first and second end face sides, hydrogen in the absorption layer can be efficiently released from the first main surface, which is not applied with solder and does not face the mounting substrate, via the first and second exposed plating regions.

[0009] According to the present invention, it is possible to provide a multilayer ceramic electronic component and a mounting structure for the multilayer ceramic electronic component that can suppress deterioration of insulation resistance due to hydrogen.

[0010] The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0011] 1 is an external perspective view showing an example of a two-terminal multilayer ceramic capacitor as a multilayer ceramic electronic component according to a first embodiment of the present invention. It is a cross-sectional view taken along line II-II in FIG. 1 . It is a cross-sectional view taken along line III-III in FIG. 1 . It is a cross-sectional view taken along line IV-IV in FIG. 2 . It is a cross-sectional view taken along line V-V in FIG. 2 . It is a side view showing an example of a two-terminal multilayer ceramic capacitor mounted on a mounting board using solder. It is an explanatory view for explaining a first example of a method for calculating an exposed area. It is an explanatory view for explaining a second example of a method for calculating an exposed area. It is a partial cross-sectional view showing an aspect in which a base electrode layer is exposed. It is a partial cross-sectional view showing another aspect in which a base electrode layer is exposed. It is an external perspective view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention. It is a top view showing an example of a three-terminal multilayer ceramic capacitor according to the second embodiment of the present invention. It is a front view showing an example of a three-terminal multilayer ceramic capacitor according to the second embodiment of the present invention. It is a cross-sectional view taken along line XIV-XIV in FIG. 11 . It is a cross-sectional view taken along line XV-XV in FIG. 11 . It is a cross-sectional view taken along line XVI-XVI in FIG. 14 . 17 is a cross-sectional view taken along line XVII-XVII in FIG. 14.

[0012] A. First Embodiment 1. Two-Terminal Multilayer Ceramic Capacitor A two-terminal multilayer ceramic capacitor will be described as an example of a multilayer ceramic electronic component according to a first embodiment of the present invention.

[0013] Fig. 1 is an external perspective view showing an example of a two-terminal multilayer ceramic capacitor as a multilayer ceramic electronic component according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 1. Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 2. Fig. 5 is a cross-sectional view taken along line V-V in Fig. 2.

[0014] As shown in FIGS. 1 to 3, a two-terminal multilayer ceramic capacitor 10 includes a rectangular parallelepiped laminate 12 and external electrodes 30 disposed on both ends of the laminate 12 .

[0015] (1) Laminate The laminate 12 has a first main surface 12a and a second main surface 12b that face each other in a height direction x (stacking direction), a first side surface 12c and a second side surface 12d that face each other in a width direction y that is perpendicular to the height direction x, and a first end surface 12e and a second end surface 12f that face each other in a length direction z that is perpendicular to the height direction x and the width direction y. The laminate 12 of this embodiment has rounded corners and ridges. Note that the corners refer to the intersections of three adjacent surfaces of the laminate 12, and the ridges refer to the intersections of two adjacent surfaces of the laminate 12. In addition, unevenness or the like may be formed on some or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f.

[0016] The laminate 12 includes an outer layer portion 14a composed of multiple ceramic layers 14 and an inner layer portion 14b composed of one or more ceramic layers 14 and multiple internal electrode layers 16 disposed thereon. The outer layer portion 14a is located on the first main surface 12a side and the second main surface 12b side of the laminate 12. The outer layer portion 14a is an assembly of multiple ceramic layers 14 (first outer layer portion) located between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a, and multiple ceramic layers 14 (second outer layer portion) located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b. The region sandwiched between the two outer layer portions 14a is the inner layer portion 14b. In the inner layer portion 14b, the ceramic layers 14 and the internal electrode layers 16 are alternately stacked in the height direction x.

[0017] The portion of the laminate 12 sandwiched between the first outer layer portion and the second outer layer portion, where a first internal electrode layer 16a (described later) and a second internal electrode layer 16b (described later) face each other, is referred to as a facing portion (effective layer portion). The portions between the facing portion and the first side surface 12c and between the facing portion and the second side surface 12d are also referred to as W gaps or side gaps. The portions between the facing portion and the first end surface 12e and between the facing portion and the second end surface 12f, which include the lead electrode portion of either the first internal electrode layer 16a or the second internal electrode layer 16b, are also referred to as L gaps or end gaps.

[0018] The dimensions of the laminate 12 are not particularly limited.

[0019] The dielectric material for forming the ceramic layer 14 may be, for example, a dielectric ceramic containing a component such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. When the dielectric material contains the above-mentioned dielectric material as a main component, a component containing a minor component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound in a smaller amount than the main component may be added depending on the desired properties of the laminate 12.

[0020] When a piezoelectric ceramic material is used for the ceramic layers 14, the multilayer ceramic electronic component functions as a piezoelectric component. Specific examples of piezoelectric ceramic materials include PZT (lead zirconate titanate) ceramic materials. Furthermore, when a semiconductor ceramic material is used for the ceramic layers 14, the multilayer ceramic electronic component functions as a thermistor element. Specific examples of semiconductor ceramic materials include spinel ceramic materials. Furthermore, when a magnetic ceramic material is used for the ceramic layers 14, the multilayer ceramic electronic component functions as an inductor element. Furthermore, when functioning as an inductor element, the internal electrode layers 16 become coil-shaped conductors. Specific examples of magnetic ceramic materials include ferrite ceramic materials.

[0021] The thickness of the ceramic layer 14 after firing is preferably 0.35 μm or more and 0.60 μm or less. The number of laminated ceramic layers 14 is preferably 10 to 2000. Note that this number of ceramic layers 14 is the total number of the ceramic layers 14 in the inner layer portion 14b and the outer layer portion 14a on the first main surface 12a side and the outer layer portion 14a on the second main surface 12b side.

[0022] The laminate 12 has, as the multiple internal electrode layers 16, multiple first internal electrode layers 16a extended to the first end face 12e and multiple second internal electrode layers 16b extended to the second end face 12f. The multiple first internal electrode layers 16a and multiple second internal electrode layers 16b are embedded in the inner layer portion 14b so as to be alternately arranged at equal intervals with the ceramic layers 14 sandwiched between them along the height direction x of the laminate 12. The surfaces of the multiple first internal electrode layers 16a and the multiple second internal electrode layers 16b are generally parallel to the first main surface 12a and the second main surface 12b, and are, for example, substantially rectangular in plan view.

[0023] As shown in FIG. 4 , the first internal electrode layer 16a is disposed on the plurality of ceramic layers 14 and is located inside the laminate 12. The first internal electrode layer 16a has a first opposing electrode portion 26a facing the second internal electrode layer 16b and a first lead electrode portion 28a located on one end side of the first internal electrode layer 16a and extending from the first opposing electrode portion 26a to the first end face 12e of the laminate 12. The end of the first lead electrode portion 28a is extended to the surface of the first end face 12e and exposed from the laminate 12. In other words, the first lead electrode portion 28a is not exposed on the first main surface 12a, the second main surface 12b, the first side face 12c, the second side face 12d, or the second end face 12f. The end of the first opposing electrode portion 26a is located receding in the width direction from the surface of the second end face 12f.

[0024] The shape of the first opposing electrode portion 26a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first opposing electrode portion 26a may be tapered in plan view, with a slope increasing in either direction.

[0025] The shape of the first lead electrode portion 28a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first lead electrode portion 28a may be tapered in plan view, with a slope increasing in either direction.

[0026] The width of the first opposing electrode portion 26a of the first internal electrode layer 16a and the width of the first extraction electrode portion 28a of the first internal electrode layer 16a may be formed to be the same width, or one of the widths may be formed to be narrower.

[0027] As shown in FIG. 5 , the second internal electrode layer 16b is disposed on the plurality of ceramic layers 14 and is located inside the laminate 12. The second internal electrode layer 16b has a second opposing electrode portion 26b facing the first internal electrode layer 16a and a second lead electrode portion 28b located on one end side of the second internal electrode layer 16b and extending from the second opposing electrode portion 26b to the second end face 12f of the laminate 12. The end of the second lead electrode portion 28b is extended to the surface of the second end face 12f and exposed from the laminate 12. In other words, the second lead electrode portion 28b is not exposed on the first main surface 12a, the second main surface 12b, the first side face 12c, the second side face 12d, or the first end face 12e. The end of the second opposing electrode portion 26b is located receding in the width direction from the surface of the first end face 12e.

[0028] The shape of the second opposing electrode portion 26b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second opposing electrode portion 26b may be tapered in plan view, with a slope increasing in either direction.

[0029] The shape of the second lead electrode portion 28b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second lead electrode portion 28b may be tapered in plan view, with a slope increasing in either direction.

[0030] The width of the second opposing electrode portion 26b of the second internal electrode layer 16b and the width of the second extraction electrode portion 28b of the second internal electrode layer 16b may be formed to be the same width, or one of the widths may be formed to be narrower.

[0031] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of an appropriate conductive material, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy. When the laminate 12 including the internal electrode layer 16 and an integrated body including the external electrode 30 on the surface of the laminate 12 are simultaneously fired, the metal constituting the internal electrode layer 16 forms a compound with the metal contained in the external electrode 30.

[0032] The thickness of each of the internal electrode layers 16, i.e., the first internal electrode layers 16a and the second internal electrode layers 16b, is preferably 0.40 μm or more and 0.50 μm or less. The total number of the first internal electrode layers 16a and the second internal electrode layers 16b is preferably 10 or more and 2000 or less.

[0033] (2) External Electrodes As shown in FIGS. 1 to 3, external electrodes 30 are disposed on the first end face 12e side and the second end face 12f side of the laminate 12.

[0034] The external electrode 30 includes a first external electrode 30a and a second external electrode 30b.

[0035] The first external electrode 30a is connected to the first internal electrode layer 16a and is disposed on at least the surface of the first end face 12e. In this case, the first external electrode 30a is electrically connected to the first lead electrode portion 28a of the first internal electrode layer 16a. In this embodiment, the first external electrode 30a extends from the first end face 12e of the laminate 12 and is disposed on part of the first main surface 12a, part of the second main surface 12b, and part of the first side surface 12c, and part of the second side surface 12d.

[0036] The second external electrode 30b is connected to the second internal electrode layer 16b and is disposed on at least the surface of the second end face 12f. In this case, the second external electrode 30b is electrically connected to the second lead electrode portion 28b of the second internal electrode layer 16b. In this embodiment, the second external electrode 30b extends from the second end face 12f and is disposed on a part of the first main surface 12a and a part of the second main surface 12b, as well as a part of the first side surface 12c and a part of the second side surface 12d.

[0037] In the laminate 12, capacitance is formed by the first opposing electrode portion 26a of the first internal electrode layer 16a and the second opposing electrode portion 26b of the second internal electrode layer 16b facing each other via the ceramic layer 14. Therefore, capacitance can be obtained between the first external electrode 30a connected to the first internal electrode layer 16a and the second external electrode 30b connected to the second internal electrode layer 16b, and the characteristics of a capacitor are exhibited.

[0038] The external electrode 30 is preferably composed of a base electrode layer 32 and a plating layer 34. In this embodiment, the external electrode 30 includes a base electrode layer 32 containing a metal component and a plating layer 34 disposed on the base electrode layer 32. The plating layer 34 includes a first plating layer 34a and a second plating layer 34b. The first external electrode 30a includes a first base electrode layer 32a containing a metal component, a first lower-layer plating layer 34a1 disposed on the first base electrode layer 32a, and a first upper-layer plating layer 34a2 disposed on the first lower-layer plating layer 34a1. The first external electrode 30a also has a first exposed plating region 35a exposed on the surface of the first external electrode 30a. The second external electrode 30b has a second base electrode layer 32b containing a metal component, a second lower-layer plating layer 34b disposed on the second base electrode layer 32b, and a second upper-layer plating layer 34b disposed on the second lower-layer plating layer 34b. The second external electrode 30b also has a second exposed plating region 35b exposed on the surface of the second external electrode 30b.

[0039] (2-1) Base Electrode Layer The first base electrode layer 32a is connected to the first internal electrode layer 16a and is disposed on the surface of the first end face 12e. In this case, the first base electrode layer 32a is electrically connected to the first lead electrode portion 28a of the first internal electrode layer 16a. In this embodiment, the first base electrode layer 32a extends from the first end face 12e and is disposed on a part of the first main surface 12a, a part of the second main surface 12b, and a part of the first side surface 12c, and a part of the second side surface 12d.

[0040] The second base electrode layer 32b is connected to the second internal electrode layer 16b and is disposed on the surface of the second end face 12f. In this case, the second base electrode layer 32b is electrically connected to the second lead electrode portion 28b of the second internal electrode layer 16b. In this embodiment, the second base electrode layer 32b extends from the second end face 12f and is disposed on a part of the first main surface 12a, a part of the second main surface 12b, a part of the first side surface 12c, and a part of the second side surface 12d.

[0041] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, etc. Hereinafter, each configuration when the base electrode layer 32 is the baked layer, the conductive resin layer, or the thin film layer will be described.

[0042] (When the base electrode layer includes a baking layer) The baking layer includes a glass component and a metal component. The glass component of the baking layer includes at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baking layer includes at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The baking layer may include multiple layers. The baking layer is formed by applying a conductive paste containing a glass component and a metal component to the laminate 12 and baking it. The baking layer may be co-fired with the internal electrode layers 16 and the ceramic layers 14, or may be baked after the internal electrode layers 16 and the ceramic layers 14 are baked. Note that when the baking layer is co-fired with the internal electrode layers 16 and the ceramic layers 14, it is preferable to form the baking layer by adding a ceramic component instead of a glass component. The ceramic component may be the same type of ceramic material as the ceramic layers 14, or a different type of ceramic material. The ceramic component includes at least one selected from, for example, BaTiO3, CaTiO3, (Ba, Ca)TiO3, SrTiO3, CaZrO3, etc. When the baking layer includes a glass component or a ceramic component, it is possible to improve the adhesion between the laminate 12 and the baking layer, which is the base electrode layer 32. The baking layer may include both a glass component and a ceramic component.

[0043] The thicknesses of the first and second baked layers at the center in the height direction x of the first and second base electrode layers 32 a, 32 b located on the first end face 12 e and the second end face 12 f are preferably, for example, about 3 μm to 20 μm. Furthermore, when the base electrode layer 32 is provided on the first and second main faces 12 a, 12 b and the first and second side faces 12 c, 12 d, the thicknesses of the first and second baked layers at the center in the length direction z of the first and second base electrode layers 32 a, 32 b located on the first and second main faces 12 a, 12 b and the first and second side faces 12 c, 12 d are preferably, for example, about 1 μm to 20 μm.

[0044] (When the Base Electrode Layer Includes a Conductive Resin Layer) The conductive resin layer may be multiple layers. The conductive resin layer may be disposed on the baked layer so as to cover the baked layer, or the conductive resin layer may be disposed directly on the laminate 12. Further explaining the case where the conductive resin layer is disposed on the baked layer, the conductive resin layer is disposed so as to cover the baked layer, which is the base electrode layer 32. The conductive resin layer includes a first conductive resin layer and a second conductive resin layer. The first conductive resin layer is disposed so as to cover the first base electrode layer 32a, and the second conductive resin layer is disposed so as to cover the second base electrode layer 32b. Specifically, the first and second conductive resin layers are disposed on the first base electrode layer 32a and the second base electrode layer 32b located on the first end face 12e and the second end face 12f. Furthermore, the first and second conductive resin layers are preferably arranged so as to extend onto the first principal surface 12 a and the second principal surface 12 b, as well as the first side surface 12 c and the second side surface 12 d. However, the first and second conductive resin layers may be arranged only on the first base electrode layer 32 a and the second base electrode layer 32 b located on the first end surface 12 e and the second end surface 12 f. Note that, when the external electrode 30 has a plating layer 34, the conductive resin layer can be arranged so as to be located between the base electrode layer 32 and the plating layer 34.

[0045] The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than a conductive layer made of, for example, a plating film or a fired conductive paste. Therefore, even if the two-terminal multilayer ceramic capacitor 10 is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer functions as a buffer layer and can prevent cracks in the two-terminal multilayer ceramic capacitor 10.

[0046] The metal contained in the conductive resin layer can be Ag, Cu, Ni, Sn, Bi, or an alloy containing these. Alternatively, a metal powder whose surface is coated with Ag can also be used. When using a metal powder whose surface is coated with Ag, it is preferable to use Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder. The reason for using Ag conductive metal powder as the conductive metal is that Ag has the lowest resistivity among metals, making it suitable as an electrode material, and Ag is a noble metal that does not oxidize and has high weather resistance. The reason for using Ag-coated metal powder is that it allows the base metal to be made inexpensive while maintaining the properties of Ag.

[0047] Furthermore, the metal contained in the conductive resin layer may be Cu or Ni that has been subjected to an anti-oxidation treatment. The metal contained in the conductive resin layer may be a metal powder whose surface is coated with Sn, Ni, or Cu. When using a metal powder whose surface is coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder.

[0048] The metal contained in the conductive resin layer is preferably contained in an amount of 35 vol% or more and 75 vol% or less relative to the volume of the entire conductive resin. The average particle size of the metal contained in the conductive resin layer is not particularly limited. The average particle size of the conductive filler may be, for example, approximately 0.3 μm or more and 10 μm or less. The metal contained in the conductive resin layer is mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, contact between conductive fillers forms an electrical path inside the conductive resin layer.

[0049] The shape of the metal contained in the conductive resin layer is not particularly limited, and spherical, flat, etc. It is preferable to use a mixture of spherical metal powder and flat metal powder as the metal contained in the conductive resin layer.

[0050] As the resin for the conductive resin layer, various known thermosetting resins such as epoxy resin, phenoxy resin, phenol resin, urethane resin, silicone resin, and polyimide resin can be used. Among them, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, and adhesion. The resin contained in the conductive resin layer is preferably contained in an amount of 25 vol% to 65 vol% of the total volume of the conductive resin.

[0051] The conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide-imide-based compounds can be used as the curing agent for the epoxy resin.

[0052] The thickness of the conductive resin layer located at the center in the height direction x of the laminate 12 located at the first end face 12e and the second end face 12f is preferably, for example, about 3 μm or more and 30 μm or less.

[0053] Furthermore, when a conductive resin layer is also provided on the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d, it is preferable that the thickness of the conductive resin layer at the center in the longitudinal direction z of the conductive resin layer located on the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d is, for example, approximately 3 μm or more and 30 μm or less.

[0054] (When the Underlying Electrode Layer Includes a Thin Film Layer) The thin film layer is formed by a thin film forming method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0055] (2-2) Plating Layer Next, the first plating layer 34a and the second plating layer 34b, which are the plating layer 34 disposed on the base electrode layer 32, will be described with reference to Figures 2 to 5. This plating layer 34 has an exposed plating region 35.

[0056] The first plating layer 34a is disposed so as to cover the first base electrode layer 32a on the first end face 12e side. Furthermore, the first plating layer 34a may be disposed so as to cover the first base electrode layer 32a on the first principal surface 12a, the second principal surface 12b, the first side surface 12c, and the second side surface 12d side. Alternatively, the first plating layer 34a may be disposed only on the first base electrode layer 32a on the first end face 12e side. The first plating layer 34a includes a first lower-layer plating layer 34a1 disposed on the first base electrode layer 32a and a first upper-layer plating layer 34a2 disposed on the first lower-layer plating layer 34a1. The first upper-layer plating layer 34a2 is disposed on the first lower-layer plating layer 34a1 so as to expose a portion of the first lower-layer plating layer 34a1. In other words, the first upper layer plating layer 34a2 is arranged on the first lower layer plating layer 34a1 except for the first exposed plating region 35a so that the first lower layer plating layer 34a1 has a first exposed plating region 35a exposed on the surface of the first external electrode 30a.

[0057] In this embodiment, the first exposed plating region 35a is located on the first principal surface 12a. In this case, as shown in FIG. 6, the second principal surface 12b of the two-terminal multilayer ceramic capacitor 10 serves as a mounting surface for a mounting substrate 40. FIG. 6 is a side view showing an example of a two-terminal multilayer ceramic capacitor mounted using solder. As shown in FIG. 6, a pair of planar lands 41 for mounting the two-terminal multilayer ceramic capacitor 10 is formed on the mounting substrate 40. The two-terminal multilayer ceramic capacitor 10 is disposed such that the second principal surface 12b faces the mounting surface of the mounting substrate 40 and the first principal surface 12a is furthest from the mounting surface, with the first external electrode 30a and the second external electrode 30b positioned on the pair of lands 41, respectively. In this state, solder 42 is applied to the first end face 12e and the second end face 12f, thereby mounting the two-terminal multilayer ceramic capacitor 10 on the mounting substrate 40.

[0058] Although not limited thereto, it is preferable that the first upper plating layer 34a2 covers the end portion of the first lower plating layer 34a1. Specifically, it is preferable that the tip portion of the first lower plating layer 34a1 on the second end face 12f side is covered by the tip portion of the first upper plating layer 34a2 on the second end face 12f side. This can suppress peeling of the first lower plating layer 34a1.

[0059] A first ratio of the area of ​​the first exposed plating region 35a to the area of ​​the exposed region of the first external electrode 30a on the first main surface 12a when viewed in the height direction x of the laminate 12 is preferably 0.4% or more and 83.4% or less. Because the first ratio is 0.4% or more, hydrogen released from, for example, the first and second internal electrode layers 16a, 16b, the first and second base electrode layers 32a, 32b, and the first and second lower plating layers 34a1, 34b1 can be sufficiently released from the first exposed plating region 35a to the outside of the two-terminal multilayer ceramic capacitor 10, thereby suppressing deterioration of insulation resistance due to hydrogen. Furthermore, because the first ratio is 83.4% or less, the proportion of the first lower plating layer 34a1 that is not covered by the first upper plating layer 34a2 can be suppressed. This suppresses deterioration of moisture resistance due to water vapor penetration from the first exposed plating region 35a into the two-terminal multilayer ceramic capacitor 10. More preferably, the first ratio is 1.17% or greater and 83.4% or less. Still more preferably, the first ratio is 1.40% or greater and 83.4% or less. Still more preferably, the first ratio is 1.40% or greater and 25.0% or less.

[0060] As a first example, the first ratio can be determined as follows. First, the area of ​​the exposed region of the first external electrode 30a can be determined from the area of ​​the region where the first external electrode 30a faces the outside of the two-terminal multilayer ceramic capacitor 10. For example, the area of ​​the exposed region of the first external electrode 30a can be determined from the area of ​​the region where the first external electrode 30a faces the outside of the two-terminal multilayer ceramic capacitor 10 on the first principal surface 12a, the second principal surface 12b, the first end face 12e, the first side surface 12c, and the second side surface 12d. Furthermore, the area of ​​the first exposed plating region 35a can be determined from the area of ​​the region where the first lower plating layer 34a1 faces the outside of the two-terminal multilayer ceramic capacitor 10. For example, the area of ​​the first exposed plating region 35a can be determined from the area of ​​the region of the first lower-layer plating layer 34a1 on the first principal surface 12a, the second principal surface 12b, the second end face 12f, the first side surface 12c, and the second side surface 12d where the first lower-layer plating layer 34a1 faces the outside of the two-terminal multilayer ceramic capacitor 10. Then, the first ratio can be determined from the ratio of the area of ​​the first exposed plating region 35a to the area of ​​the exposed region of the first external electrode 30a.

[0061] 7 , in the first example, in this embodiment, the area S30a of the exposed region of the first external electrode 30a, when viewed from the first principal surface 12a side (as viewed in the first principal surface direction), can be determined from the region on the first principal surface 12a where the first external electrode 30a (first base electrode layer 32a, first lower-layer plating layer 34a, and first upper-layer plating layer 34a) faces the outside of the two-terminal multilayer ceramic capacitor 10. Also, in this embodiment, the area S35a of the first exposed plating region 35a can be determined from the region where the first lower-layer plating layer 34a faces the outside of the two-terminal multilayer ceramic capacitor 10 on all of the first principal surface 12a, the second principal surface 12b, the first end face 12e, the first side surface 12c, and the second side surface 12d. 7 shows an example in which the first exposed plating region 35a is located on the first main surface 12a. The first ratio can be calculated from the ratio of the area S35a of the first exposed plating region 35a to the area S30a of the exposed region of the first external electrode 30a. The areas S30a and S35a can be observed at a magnification of 200x and in a bright field using, for example, a microscope (e.g., a VHX series microscope manufactured by Keyence Corporation (hereinafter, referred to as VHX)).

[0062] As a second example, the first ratio can be calculated as follows. The area of ​​the exposed region of the first external electrode 30a is calculated in the same manner as in the first example. Furthermore, if the first lower-layer plating layer 34a1 has been removed in addition to the first upper-layer plating layer 34a2, causing the first exposed plating region 35a to intersect with the first main surface 12a, the second main surface 12b, the first end face 12e, the first side surface 12c, or the second side surface 12d, the area of ​​the first exposed plating region 35a can be calculated by multiplying the thickness of the exposed first lower-layer plating layer 34a1 by the perimeter of the first exposed plating region 35a. The first ratio can then be calculated from the ratio of the area of ​​the first exposed plating region 35a to the area of ​​the exposed region of the first external electrode 30a.

[0063] 7 , in the present embodiment, the area S30a of the exposed region of the first external electrode 30a, when viewed from the first main surface 12a (as viewed in the first main surface direction), can be determined from the region of the first external electrode 30a on the first main surface 12a that faces the outside of the two-terminal multilayer ceramic capacitor 10. Furthermore, when the first exposed plating region 35a intersects the first main surface 12a, the second main surface 12b, the first end face 12e, the first side surface 12c, or the second side surface 12d, the area SS35a of the first exposed plating region 35a can be determined by multiplying the thickness t35a of the exposed first lower-layer plating layer 34a1 by the perimeter of the first exposed plating region 35a (the sum of l35a1, l35a2, l35a3, and l35a4). 8 shows an example in which the first exposed plating region 35a intersects with the first principal surface 12a. The first ratio can be calculated from the ratio of the area SS35a of the first exposed plating region 35a to the area S30a of the exposed region of the first external electrode 30a. The lengths l35a1 to l35a4 can be observed, for example, using a microscope (VHX) at a magnification of 200x in a bright field. The thickness t35a can be observed, for example, using a microscope (VHX) at a magnification of 2000x in a bright field after polishing the cross section to, for example, half the dimension W in the width direction y of the two-terminal multilayer ceramic capacitor 10.

[0064] The second plating layer 34b is disposed so as to cover the second base electrode layer 32b on the second end surface 12f side. Furthermore, the second plating layer 34b may be disposed so as to cover the second base electrode layer 32b on the first principal surface 12a, the second principal surface 12b, the first side surface 12c, and the second side surface 12d side. Alternatively, the second plating layer 34b may be disposed only on the second base electrode layer 32b on the second end surface 12f side. The second plating layer 34b includes a second lower-layer plating layer 34b1 disposed on the second base electrode layer 32b and a second upper-layer plating layer 34b2 disposed on the second lower-layer plating layer 34b1. The second upper-layer plating layer 34b2 is disposed on the second lower-layer plating layer 34b1 so as to expose a portion of the second lower-layer plating layer 34b1. In other words, the second upper-layer plating layer 34b2 is disposed on the second lower-layer plating layer 34b1, excluding the second exposed plating region 35b, so that the second lower-layer plating layer 34b1 has a second exposed plating region 35b that is exposed on the surface of the second external electrode 30b. In this embodiment, the second exposed plating region 35b is disposed on the first principal surface 12a. In this case, the second principal surface 12b of the two-terminal multilayer ceramic capacitor 10 serves as the mounting surface for the mounting board.

[0065] Although not limited thereto, it is preferable that the second upper plating layer 34b2 covers the end portion of the second lower plating layer 34b1. Specifically, it is preferable that the tip portion of the second lower plating layer 34b1 on the first end face 12e side is covered by the tip portion of the second upper plating layer 34b2 on the first end face 12e side. This can suppress peeling of the second lower plating layer 34b1.

[0066] For the same reasons as for the first ratio, the second ratio of the area of ​​the second exposed plating region 35b to the area of ​​the exposed region of the second external electrode 30b on the first main surface 12a when viewed in the height direction x of the laminate 12 is preferably 0.4% or more and 83.4% or less. Because the second ratio is 0.4% or more, for example, hydrogen released from the first and second internal electrode layers 16a, 16b, the first and second base electrode layers 32a, 32b, and the first and second lower plating layers 34a1, 34b1 can be sufficiently released from the second exposed plating region 35b to the outside of the two-terminal multilayer ceramic capacitor 10, thereby suppressing deterioration of insulation resistance due to hydrogen. Furthermore, because the second ratio is 83.4% or less, deterioration of moisture resistance due to water vapor penetration from the second exposed plating region 35b into the two-terminal multilayer ceramic capacitor 10 can be suppressed. More preferably, the second ratio is 1.17% or more and 83.4% or less. More preferably, the second ratio is equal to or greater than 1.40% and equal to or less than 83.4%. Still more preferably, the second ratio is equal to or greater than 1.40% and equal to or less than 25.0%.

[0067] The second ratio can be determined in the same manner as the first ratio. In the case of the first example described above, in this embodiment, the area of ​​the exposed region of the second external electrode 30b can be determined from the area of ​​the region on the first main surface 12a where the second external electrode 30b (the second base electrode layer 32b, the second lower-layer plating layer 34b1, and the second upper-layer plating layer 34b2) faces the outside of the two-terminal multilayer ceramic capacitor 10 when viewed from the first main surface 12a. In addition, in this embodiment, the area of ​​the second exposed plating region 35b can be determined from the area of ​​the region where the second lower-layer plating layer 34b1 faces the outside of the two-terminal multilayer ceramic capacitor 10 when viewed from all of the first main surface 12a, the second main surface 12b, the second end face 12f, the first side surface 12c, and the second side surface 12d.

[0068] Furthermore, in the case of the second example described above, in this embodiment, the area of ​​the exposed region of the second external electrode 30b can be determined in the same manner as in the first example. Furthermore, in this embodiment, when the second exposed plating region 35b intersects the first principal surface 12a, the second principal surface 12b, the second end face 12f, the first side surface 12c, or the second side surface 12d, the area of ​​the second exposed plating region 35b can be determined from the area obtained by multiplying the thickness of the exposed second lower-layer plating layer 34b by the perimeter of the second exposed plating region 35b. The second ratio can be determined from the ratio of the area of ​​the second exposed plating region 35b to the area of ​​the exposed region of the second external electrode 30b.

[0069] In the above, the first and second ratios are calculated as the exposed ratio, but the exposed ratio may be the ratio of the total area of ​​the first exposed plating region 35a and the second exposed plating region 35b to the total area of ​​the exposed regions of the first external electrode 30a and the second external electrode 30b. It is preferable that this total exposed ratio is 0.4% or more and 83.4% or less.

[0070] The first plating layer 34a and the second plating layer 34b contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag--Pd alloy, Au, and the like.

[0071] Preferably, the first lower plating layer 34a1 and the second lower plating layer 34b1 are Ni plating layers, and the first upper plating layer 34a2 and the second upper plating layer 34b2 are Sn plating layers.

[0072] The first and second lower plating layers 34a1, 34b1 made of Ni plating are used to prevent the base electrode layer 32 from being eroded by solder when mounting the two-terminal multilayer ceramic capacitor 10. The first and second upper plating layers 34a2, 34b2 made of Sn plating are used to improve the wettability of solder when mounting the two-terminal multilayer ceramic capacitor 10, thereby facilitating mounting.

[0073] The thicknesses of the first lower-layer plating layer 34a1 and the first upper-layer plating layer 34a2 on the first main surface 12a, the second main surface 12b, the first end face 12e, the first side surface 12c, and the second side surface 12d are preferably 2 μm or more and 7 μm or less. The thicknesses of the second lower-layer plating layer 34b1 and the second upper-layer plating layer 34b2 on the first main surface 12a, the second main surface 12b, the second end face 12f, the first side surface 12c, and the second side surface 12d are preferably 2 μm or more and 7 μm or less.

[0074] When a conductive resin layer is formed on the base electrode layer 32, the plating layer 34 is disposed so as to cover the conductive resin layer. Even in this case, the Ni plating layer, which is the lower plating layer of the plating layer 34, prevents the conductive resin layer from being eroded by solder, and the Sn plating layer, which is the upper plating layer, improves the wettability of the solder.

[0075] (3) Dimensions of the Two-Terminal Multilayer Ceramic Capacitor The dimension in the length direction z of the two-terminal multilayer ceramic capacitor 10 including the laminate 12, the first external electrodes 30a, and the second external electrodes 30b is defined as dimension L, the dimension in the height direction x of the two-terminal multilayer ceramic capacitor 10 including the laminate 12, the first external electrodes 30a, and the second external electrodes 30b is defined as dimension T, and the dimension in the width direction y of the two-terminal multilayer ceramic capacitor 10 including the laminate 12, the first external electrodes 30a, and the second external electrodes 30b is defined as dimension W. The dimensions of the two-terminal multilayer ceramic capacitor 10 are as follows: L in the length direction z is 0.2 mm to 6.5 mm, W in the width direction y is 0.1 mm to 5.5 mm, and T in the height direction x is 0.1 mm to 6.5 mm. The dimensions of the two-terminal multilayer ceramic capacitor 10 can be measured using a microscope.

[0076] 2. Method for Manufacturing Two-Terminal Multilayer Ceramic Capacitor Next, a method for manufacturing the two-terminal multilayer ceramic capacitor 10 will be described.

[0077] (Step 1) First, a dielectric sheet for the ceramic layer 14 and a conductive paste for the internal electrode layer 16 are prepared. The dielectric sheet and the conductive paste for the internal electrode layer 16 contain a binder and a solvent. The binder and the solvent may be known.

[0078] (Step 2) Then, a conductive paste for the internal electrode layer 16 is printed in a predetermined pattern on the dielectric sheet by, for example, screen printing, gravure printing, etc. In this way, a dielectric sheet on which the pattern of the first internal electrode layer 16a is formed, and a dielectric sheet on which the pattern of the second internal electrode layer 16b is formed are prepared.

[0079] Furthermore, with regard to the dielectric sheets, outer layer dielectric sheets on which no internal electrode layer patterns are printed are also prepared.

[0080] (Step 3) A predetermined number of dielectric sheets for outer layers, on which no internal electrode layer patterns are printed, are stacked to form the outer layer portion 14a on the second main surface 12b (outer layer portion forming step). A dielectric sheet on which the pattern of the first internal electrode layer 16a is printed and a dielectric sheet on which the pattern of the second internal electrode layer 16b is printed are sequentially stacked on the outer layer portion 14a on the second main surface 12b to form the structure of the present invention (inner layer portion forming step). Subsequently, a predetermined number of dielectric sheets for outer layers, on which no internal electrode layer patterns are printed, are stacked on the inner layer. This forms the outer layer portion 14a on the first main surface 12a on the inner layer portion 14b (outer layer portion forming step).

[0081] (Step 4) Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0082] (Step 5) The laminated block is then cut to a predetermined size to obtain laminated chips. At this time, the corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0083] (Step 6) Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the materials of the ceramic layers, which are dielectrics, and the internal electrode layers, but is preferably 900°C or higher and 1400°C or lower.

[0084] (Step 7) Next, a conductive paste for external electrodes is applied to both end faces 12e, 12f, etc. of the laminate 12 to form the base electrode layer 32. The manufacturing process will be described below for each of the cases where the base electrode layer 32 is a baked layer, a conductive resin layer, and a thin film layer.

[0085] (When the base electrode layer is a baked layer) When the base electrode layer 32 is a baked layer, a conductive paste containing a glass component and a metal is applied by a method such as dipping or screen printing, and then a baking process is performed to form the base electrode layer 32. The baking temperature at this time is preferably 700°C or higher and 900°C or lower.

[0086] The baking layer may contain a ceramic component instead of a glass component, or may contain both. The ceramic component is preferably, for example, the same type of ceramic material as the laminate. When the baking layer contains a ceramic component, it is preferable to apply a conductive paste to the laminated chip before firing, and then simultaneously bake (fire) the laminated chip before firing and the conductive paste applied to the laminated chip before firing to form a laminate with a baked layer. The baking temperature (firing temperature) at this time is preferably 900°C or higher and 1400°C or lower.

[0087] (When the base electrode layer is a conductive resin layer) When the base electrode layer 32 is a conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied onto the baking layer or the laminate 12, and heat treatment is performed at a temperature of 250°C to 550°C to thermally cure the resin, forming a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent the resin from scattering and the various metal components from oxidizing, it is preferable to keep the oxygen concentration at 100 ppm or less.

[0088] (When the base electrode layer is a thin film layer) When the base electrode layer 32 is a thin film layer, the base electrode layer 32 can be formed by a thin film formation method such as a sputtering method or a vapor deposition method. The base electrode layer 32 formed as a thin film layer is a layer of 1 μm or less in which metal particles are deposited.

[0089] (Step 8) After the base electrode layer 32 is formed, a plating layer 34 is formed on the surface of the base electrode layer 32. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating requires pretreatment using a catalyst or the like to improve the plating deposition rate, which has the disadvantage of complicating the process. Therefore, electrolytic plating is usually preferred. Barrel plating is preferably used as the plating method. In this embodiment, the plating layer 34 is formed sequentially on the base electrode layer 32, consisting of a first lower plating layer 34a1 and a second lower plating layer 34b1 (Ni plating layers), and a first upper plating layer 34a2 and a second upper plating layer 34b2 (Sn plating layers).

[0090] When forming a conductive resin layer on the base electrode layer 32, a conductive resin paste containing a resin component and a metal component is prepared, and the conductive resin paste is applied onto the base electrode layer 32 by a dipping method. Thereafter, the plating layer 34 is formed on the conductive resin layer.

[0091] (Step 9) Next, the first upper plating layer 34a2 and the second upper plating layer 34b2 (Sn plating layer) are processed so that the first lower plating layer 34a1 and the second lower plating layer 34b1 (Ni plating layer) have a predetermined exposed ratio. Examples of processing methods that can be used include scraping, melting, laser processing, and resist-based methods. In the scraping method, a metal terminal having a diameter of approximately 30 to 100 μm is brought into contact with the first upper plating layer 34a2 and the second upper plating layer 34b2 (Sn plating layer) to scrape away the soft Sn plating layer so that the first lower plating layer 34a1 and the second lower plating layer 34b1 (Ni plating layer) have a predetermined exposed ratio. In the melting method, the molded body after the plating layer 34 formation is immersed in an enstrip agent (strip remover). For example, after the plating layer 34 is formed, the heights of multiple molded bodies are aligned using an alignment jig, and one surface of the molded body is immersed in an ensemble stripping agent to dissolve the first upper layer plating layer 34a2 and the second upper layer plating layer 34b2 (Sn plating layer) so that the first lower layer plating layer 34a1 and the second lower layer plating layer 34b1 (Ni plating layer) are exposed to a predetermined extent. At this time, it is preferable to immerse the first main surface 12a (and / or the second main surface 12b) side. This prevents the internal electrode layers 16 on the first end face 12e, second end face 12f, first side face 12c, and second side face 12d sides from being immersed. In the laser processing method, a plurality of molded bodies after the formation of the plating layer 34 are aligned, and a predetermined area of ​​the first upper plating layer 34a2 and the second upper plating layer 34b2 (Sn plating layer) of each molded body is removed by a laser so that the first lower plating layer 34a1 and the second lower plating layer 34b1 (Ni plating layer) have a predetermined exposed ratio. The first and second lower plating layers 34a1, 34b1 (Ni plating layers) having a predetermined exposed ratio can also be formed by using a resist.

[0092] In the manner described above, the two-terminal multilayer ceramic capacitor 10 according to this embodiment is manufactured.

[0093] Because the first lower-layer plating layer 34a1 is exposed on the surface of the first external electrode 30a in the first exposed plating region 35a, hydrogen within the two-terminal multilayer ceramic capacitor 10 can be released from the first exposed plating region 35a to the outside of the two-terminal multilayer ceramic capacitor 10. Similarly, because the second lower-layer plating layer 34b1 is exposed on the surface of the second external electrode 30b in the second exposed plating region 35b, hydrogen within the two-terminal multilayer ceramic capacitor 10 can be released from the second exposed plating region 35b to the outside of the two-terminal multilayer ceramic capacitor 10. This will be explained further below.

[0094] During the plating process for forming the first and second lower plating layers 34a1 and 34b1 and the first and second upper plating layers 34a2 and 34b2, hydrogen ions are generated by a chemical reaction. These hydrogen ions may be absorbed as hydrogen by at least one of the first and second lower plating layers 34a1 and 34b1, the first and second internal electrode layers 16a and 16b, and the first and second base electrode layers 32a and 32b. According to the above configuration, hydrogen absorbed in at least one of the first and second lower plating layers 34a1 and 34b1, the first and second internal electrode layers 16a and 16b, and the first and second base electrode layers 32a and 32b (absorption layers) can be released from the first and second exposed plating regions 35a and 35b to the outside of the two-terminal multilayer ceramic capacitor 10. This prevents hydrogen from remaining absorbed in the absorption layers, thereby suppressing deterioration of insulation resistance due to hydrogen. In particular, even when the absorption layer contains a metal such as Ni that does not easily absorb hydrogen, deterioration of the insulation resistance of the ceramic layer 14 can be suppressed by releasing hydrogen from the first and second exposed plating regions 35 a and 35 b to the outside of the two-terminal multilayer ceramic capacitor 10. Note that when the first and second exposed plating regions 35 a and 35 b are formed on the first main surface 12 a side, the second main surface 12 b side serves as the mounting surface for the two-terminal multilayer ceramic capacitor 10 to be mounted on a mounting board, and solder is applied mainly to the first and second end faces 12 e, 12 f sides, hydrogen from the absorption layer can be efficiently released from the first main surface 12 a, which is not applied with solder and does not face the mounting board 40, via the first and second exposed plating regions 35 a and 35 b.

[0095] 3. Modified Examples of Two-Terminal Multilayer Ceramic Capacitor Next, modified examples of the two-terminal multilayer ceramic capacitor 10 will be described.

[0096] (1) The external electrode 30 of the first embodiment described above includes a base electrode layer 32 and a plating layer 34. Alternatively, the external electrode 30 may include the plating layer 34 and not include the base electrode layer 32. Although not shown, a structure in which the plating layer 34 is provided without providing the base electrode layer 32 will be described below for the first and second external electrodes 30a, 30b.

[0097] The first and second external electrodes 30a, 30b may each be provided without a base electrode layer 32, with the plating layer 34 formed directly on the surface of the laminate 12. That is, the two-terminal multilayer ceramic capacitor 10 may have a structure in which the first end face 12e and the second end face 12f are plated to form the plating layer 34 electrically connected to the first internal electrode layer 16a or the second internal electrode layer 16b. In such a case, the plating layer 34 may be formed by plating after a catalyst is applied to the surface of the laminate 12 as a pretreatment. Either electrolytic plating or electroless plating may be used for the plating. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferred. Barrel plating is preferred as the plating method.

[0098] In addition, when the plating layer 34 is formed directly on the laminate 12 without providing the base electrode layer 32, the amount of reduction in the thickness of the base electrode layer 32 can be converted into a lower profile, i.e., a thinner laminate, or into the thickness of the laminate, i.e., the thickness of the effective layer portion, thereby improving the design freedom of the thickness of the laminate 12.

[0099] The plating layer 34 includes first and second lower plating layers 34a1, 34b1 (lower plating layers) formed on the surface of the laminate 12, and first and second upper plating layers 34a2, 34b2 (upper plating layers) formed on the surfaces of the first and second lower plating layers 34a1, 34b1. As in the above embodiment, the lower plating layers have exposed plating regions that are not covered by the upper plating layers. The lower plating layer and the upper plating layer each preferably contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such a metal. Furthermore, the lower plating layer is preferably formed using Ni, which has solder barrier properties, and the upper plating layer is preferably formed using Sn or Au, which have good solder wettability.

[0100] Furthermore, for example, when the first internal electrode layer 16 a and the second internal electrode layer 16 b are formed using Ni, the lower plating layer is preferably formed using Cu, which has good bonding properties with Ni. The plating layer 34 may have the upper plating layer as the outermost layer, or another plating electrode may be further formed on the surface of the upper plating layer.

[0101] When the external electrode 30 is formed only with the plating layer 34 without providing the base electrode layer 32, the thickness of each plating layer 34 disposed without providing the base electrode layer 32 is preferably 1.0 μm or more and 20.0 μm or less. Furthermore, it is preferable that the plating layer 34 does not contain glass. The metal ratio per unit volume of the plating layer 34 is preferably 99 volume % or more.

[0102] (2) In the first embodiment described above, the first lower-layer plating layer 34a1 has a first exposed plating region 35a that is not covered by the first upper-layer plating layer 34a2, and the second lower-layer plating layer 34b1 has a second exposed plating region 35b that is not covered by the second upper-layer plating layer 34b2. However, the form of the exposed regions is not limited to this, and the external electrode 30 may have an exposed base region 36 where the base electrode layer 32 is not covered by the plating layer 34.

[0103] Specifically, the first base electrode layer 32a has a first exposed base region 36a that is not covered by the first plating layer 34a. Such a first exposed base region 36a can be formed, for example, in the manner shown in FIGS. 9 and 10 . In FIG. 9 , a first exposed plating region 35a is formed to expose the first main surface 12a side of the first lower-layer plating layer 34a, and a first exposed base region 36a is formed within this first exposed plating region 35a. In the first exposed base region 36a, the first main surface 12a side of the first base electrode layer 32a is exposed and not covered by the first lower-layer plating layer 34a and the first upper-layer plating layer 34a. Also, in FIG. 10 , the first exposed plating region 35a and the first exposed base region 36a are located at different positions on the first main surface 12a.

[0104] 9 and 10 , the first exposed base region 36 a is preferably disposed on the first main surface 12 a. The second main surface 12 b is preferably the mounting surface. This allows hydrogen from the absorbing layer to be efficiently released from the first main surface 12 a, which is not soldered and does not face the mounting substrate 40, via the first exposed base region 36 a, when solder is applied mainly to the first and second end faces 12 e and 12 f as shown in FIG. 6 .

[0105] The first exposed base region 36a may be located on any of the second main surface 12b, the first end face 12e, the first side surface 12c, and the second side surface 12d other than the first main surface 12a, as long as solder is not applied thereto.

[0106] Alternatively, the first exposed plating region 35 a and the first exposed underlayer region 36 a may be formed on different surfaces. For example, the first exposed plating region 35 a may be disposed on the first end face 12 e, and the first exposed underlayer region 36 a may be disposed on the first main surface 12 a.

[0107] Furthermore, the first exposed base region 36a is preferably formed closer to the first end face 12e than the tip of the first lower-layer plating layer 34a1 on the second end face 12f side. In other words, the tip of the first lower electrode layer 32a on the second end face 12f side is preferably covered by the tip of the first lower-layer plating layer 34a1 on the second end face 12f side. This makes it possible to prevent peeling of the first lower electrode layer 32a.

[0108] The first exposed base region 36a, like the first exposed plating region 35a, can be formed by removing the first lower plating layer 34a1 and the first upper plating layer 34a2 using a scraping method, a melting method, a laser processing method, a method using a resist, or the like.

[0109] Although not shown, the second base electrode layer 32b can also have a second exposed base region that is not covered by the second plating layer 34b.

[0110] (3) In the first embodiment described above, the first exposed plating region 35a, where the first lower-layer plating layer 34a is not covered by the first upper-layer plating layer 34a, is provided on the first main surface 12a. Similarly, the second exposed plating region 35b, where the second lower-layer plating layer 34b is not covered by the second upper-layer plating layer 34b, is provided on the first main surface 12a. However, the present invention is not limited to this, and the exposed plating region 35 may be provided on at least one of the first main surface 12a, the second main surface 12b, the first end face 12e, the second end face 12f, the first side face 12c, and the second side face 12d.

[0111] (4) In the first embodiment described above, the first external electrode 30a has the first exposed plating region 35a and the second external electrode 30b has the second exposed plating region 35b. However, it is sufficient if at least one of the first exposed plating region 35a and the second exposed plating region 35b is provided.

[0112] (5) In the first embodiment described above, the first lower-layer plating layer 34a is disposed so as to cover the entire first base electrode layer 32a, and the second lower-layer plating layer 34b is disposed so as to cover the entire second base electrode layer 32b. However, this is not limiting, and the first lower-layer plating layer 34a may be disposed so as to cover a portion of the first base electrode layer 32a, and the second lower-layer plating layer 34b may be disposed so as to cover a portion of the second base electrode layer 32b.

[0113] B. Second Embodiment 1. Three-Terminal Multilayer Ceramic Capacitor A three-terminal multilayer ceramic capacitor will be described as an example of a multilayer ceramic electronic component according to a second embodiment of the present invention.

[0114] FIG. 11 is an external perspective view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention. FIG. 12 is a top view showing an example of a three-terminal multilayer ceramic capacitor according to the second embodiment of the present invention. FIG. 13 is a front view showing an example of a three-terminal multilayer ceramic capacitor according to the second embodiment of the present invention. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 11. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 11. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 14. FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 14.

[0115] As shown in FIG. 11, a three-terminal multilayer ceramic capacitor 100 includes, for example, a laminate 12 having a substantially rectangular parallelepiped shape and external electrodes 30 .

[0116] (1) Laminate The laminate 12 has a plurality of laminated ceramic layers 14 and a plurality of internal electrode layers 16 laminated on the ceramic layers 14. The ceramic layers 14 and the internal electrode layers 16 are laminated in the height direction x.

[0117] The laminate 12 has a first main surface 12a and a second main surface 12b that face each other in the height direction x, a first side surface 12c and a second side surface 12d that face each other in the width direction y that is perpendicular to the height direction x, and a first end surface 12e and a second end surface 12f that face each other in the length direction z that is perpendicular to the height direction x and the width direction y. The laminate 12 has rounded corners and ridges. Note that a corner refers to a portion where three adjacent surfaces of the laminate intersect, and a ridge refers to a portion where two adjacent surfaces of the laminate intersect. Furthermore, unevenness may be formed on some or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f. Note that the dimension L of the laminate 12 in the length direction z is not necessarily longer than the dimension W in the width direction y.

[0118] The laminate 12 has an inner layer portion 18, and a first outer layer portion 20a and a second outer layer portion 20b arranged to sandwich the inner layer portion 18 in the stacking direction.

[0119] The inner layer portion 18 includes a plurality of ceramic layers 14 and a plurality of internal electrode layers 16. The inner layer portion 18 includes the internal electrode layer 16 located closest to the first main surface 12a in the stacking direction to the internal electrode layer 16 located closest to the second main surface 12b. The internal electrode layers 16 have first internal electrode layers 16a extending to the first end face 12e and the second end face 12f and second internal electrode layers 16b extending to the first side face 12c and the second side face 12d, and in the inner layer portion 18, the plurality of first internal electrode layers 16a and second internal electrode layers 16b face each other with the ceramic layers 14 interposed therebetween. The inner layer portion 18 generates electrostatic capacitance and essentially functions as a capacitor.

[0120] The laminate 12 has a first main surface side outer layer portion 20a located on the first main surface 12a side and formed from a plurality of ceramic layers 14 located between the first main surface 12a and the outermost surface of the inner layer portion 18 on the first main surface 12a side and a straight line on that outermost surface. The first main surface side outer layer portion 20a is an assembly of a plurality of ceramic layers 14 located between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a. The ceramic layers 14 used in the first main surface side outer layer portion 20a may be the same as the ceramic layers 14 used in the inner layer portion 18. Similarly, the laminate 12 has a second main surface side outer layer portion 20b located on the second main surface 12b side and formed from a plurality of ceramic layers 14 located between the second main surface 12b and the outermost surface of the inner layer portion 18 on the second main surface 12b side and a straight line on that outermost surface. The second main surface side outer layer portion 20b is an assembly of a plurality of ceramic layers 14 located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b. The ceramic layers 14 used in the second main surface side outer layer portion 20b may be the same as the ceramic layers 14 used in the internal layer portion 18.

[0121] The laminate 12 also has a first side surface side outer layer portion 22a located on the first side surface 12c side and formed from a plurality of ceramic layers 14 located between the first side surface 12c and the outermost surface of the inner layer portion 18 on the first side surface 12c side. Similarly, the laminate 12 has a second side surface side outer layer portion 22b located on the second side surface 12d side and formed from a plurality of ceramic layers 14 located between the second side surface 12d and the outermost surface of the inner layer portion 18 on the second side surface 12d side. The first side surface side outer layer portion 22a and the second side surface side outer layer portion 22b are also referred to as W gaps or side gaps.

[0122] Furthermore, the laminate 12 has a first end face side outer layer portion 24a located on the first end face 12e side and formed from a plurality of ceramic layers 14 located between the first end face 12e and the outermost surface of the inner layer portion 18 on the first end face 12e side. Similarly, the laminate 12 has a second end face side outer layer portion 24b located on the second end face 12f side and formed from a plurality of ceramic layers 14 located between the second end face 12f and the outermost surface of the inner layer portion 18 on the second end face 12f side. The first end face side outer layer portion 24a and the second end face side outer layer portion 24b are also referred to as L gaps or end gaps.

[0123] The dimensions of the laminate 12 are not particularly limited.

[0124] The ceramic layer 14 can be formed, for example, from a dielectric material as the ceramic material. Examples of such dielectric materials include dielectric ceramics containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. When the dielectric material is a primary component, it may contain a secondary component, such as a manganese compound, an iron compound, a chromium compound, a cobalt compound, or a nickel compound, in a smaller amount than the primary component, depending on the desired characteristics of the laminate 12.

[0125] The thickness of the ceramic layer 14 after firing is preferably 0.35 μm or more and 0.60 μm or less. The number of laminated ceramic layers 14 is preferably 10 to 2000. Note that this number of ceramic layers 14 is the total number of ceramic layers 14 in the inner layer portion 18 and the first and second outer layer portions 20 a and 20 b.

[0126] The laminate 12 has a plurality of first internal electrode layers 16a and a plurality of second internal electrode layers 16b as the plurality of internal electrode layers 16. The plurality of first internal electrode layers 16a and the plurality of second internal electrode layers 16b may be alternately laminated with ceramic layers 14 interposed therebetween, or a plurality of ceramic layers 14 on which the first internal electrode layers 16a are arranged may be laminated, and then a ceramic layer 14 on which the second internal electrode layers 16b are arranged may be laminated. In this way, the lamination pattern can be changed depending on the capacitance value that is desired to be realized.

[0127] 16 , the first internal electrode layer 16a includes a first opposing electrode portion 26a facing the second internal electrode layer 16b, a first extraction electrode portion 28a extending from the first opposing electrode portion 26a to the surface of the first end face 12e of the laminate 12, and a second extraction electrode portion 28a extending from the first opposing electrode portion 26a to the surface of the second end face 12f of the laminate 12. Specifically, the first extraction electrode portion 28a is exposed on the surface of the first end face 12e of the laminate 12, and the second extraction electrode portion 28a is exposed on the surface of the second end face 12f of the laminate 12. Therefore, the first internal electrode layer 16a is not exposed on the surfaces of the first side face 12c and the second side face 12d of the laminate 12.

[0128] The shapes of the first opposing electrode portion 26a and the first and second lead electrode portions 28a1 and 28a2 are not particularly limited, but are preferably rectangular, although the corners may be rounded.

[0129] The length in the width direction y of the first extracted electrode portion 28a1 and the second extracted electrode portion 28a2 may be the same as the length in the width direction y of the first opposing electrode portion 26a, or may be shorter. The shape of the first extracted electrode portion 28a1 and the second extracted electrode portion 28a2 may be tapered.

[0130] 17 , the second internal electrode layer 16b has a substantially cross shape and includes a second opposing electrode portion 26b opposing the first internal electrode layer 16a, a third extraction electrode portion 28b extending from the second opposing electrode portion 26b to the surface of the first side face 12c of the laminate 12, and a fourth extraction electrode portion 28b extending from the second opposing electrode portion 26b to the surface of the second side face 12d of the laminate 12. Specifically, the third extraction electrode portion 28b is exposed on the surface of the first side face 12c of the laminate 12, and the fourth extraction electrode portion 28b is exposed on the surface of the second side face 12d of the laminate 12. Therefore, the second internal electrode layer 16b is not exposed on the surface of the first end face 12e or the surface of the second end face 12f of the laminate 12.

[0131] The second opposing electrode portion 26b and the third and fourth lead electrode portions 28b1 and 28b2 are preferably rectangular in shape, although the corners may be rounded.

[0132] It is preferable that the relationship between the dimension A in the longitudinal direction z connecting the side of the second opposing electrode portion 26b on the first end face 12e side and the side on the second end face 12f side and the dimension B in the longitudinal direction z connecting the side of the third extraction electrode portion 28b1 and the fourth extraction electrode portion 28b2 on the first end face 12e side and the side on the second end face 12f side satisfies A≧B.

[0133] The third extraction electrode portion 28b1 may have a tapered shape in which the width narrows toward the first side surface 12c, and the fourth extraction electrode portion 28b2 may have a tapered shape in which the width narrows toward the second side surface 12d.

[0134] The laminate 12 has an opposing electrode portion 27. The opposing electrode portion 27 is a portion where the first opposing electrode portion 26a of the first internal electrode layer 16a and the second opposing electrode portion 26b of the second internal electrode layer 16b face each other. The opposing electrode portion 27 is configured as a part of the inner layer portion 18. The opposing electrode portion 27 is also called an effective portion of the capacitor.

[0135] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of an appropriate conductive material, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.

[0136] The number of the first internal electrode layers 16a and the second internal electrode layers 16b is not particularly limited, but is preferably, for example, about 10 to 2000 in total.

[0137] The thickness of the first internal electrode layer 16a is not particularly limited, but is preferably, for example, about 0.40 μm or more and 0.50 μm or less. The thickness of the second internal electrode layer 16b is not particularly limited, but is preferably, for example, about 0.40 μm or more and 0.50 μm or less.

[0138] (2) External Electrodes External electrodes 30 are arranged on the first end face 12e side and the second end face 12f side, the first side face 12c side and the second side face 12d side, and the first main face 12a and the second main face 12b of the laminate 12.

[0139] The external electrodes 30 include a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0140] The first external electrode 30a is connected to the first internal electrode layer 16a and is disposed on the surface of the first end face 12e. The first external electrode 30a also extends from the first end face 12e of the laminate 12 and is disposed on part of the first principal surface 12a, part of the second principal surface 12b, and part of the first side surface 12c, part of the second side surface 12d. In this case, the first external electrode 30a is electrically connected to the first extraction electrode portion 28a1 of the first internal electrode layer 16a.

[0141] The second external electrode 30b is connected to the first internal electrode layer 16a and is disposed on the surface of the second end face 12f. The second external electrode 30b also extends from the second end face 12f of the laminate 12 and is disposed on part of the first main surface 12a, part of the second main surface 12b, and part of the first side surface 12c, part of the second side surface 12d. In this case, the second external electrode 30b is electrically connected to the second extraction electrode portion 28a2 of the first internal electrode layer 16a.

[0142] The third external electrode 30c is connected to the second internal electrode layer 16b and is arranged on the surface of the first side surface 12c. The third external electrode 30c also extends from the first side surface 12c of the laminate 12 and is arranged on part of the first main surface 12a and part of the second main surface 12b. In this case, the third external electrode 30c is electrically connected to the third extraction electrode portion 28b1 of the second internal electrode layer 16b. The third external electrode 30c may be arranged only on the surface of the first side surface 12c.

[0143] The fourth external electrode 30d is connected to the second internal electrode layer 16b and is arranged on the surface of the second side surface 12d. The fourth external electrode 30d also extends from the second side surface 12d of the laminate 12 and is arranged on part of the first main surface 12a and part of the second main surface 12b. In this case, the fourth external electrode 30d is electrically connected to the fourth extraction electrode portion 28b2 of the second internal electrode layer 16b. The fourth external electrode 30d may be arranged only on the surface of the second side surface 12d.

[0144] Within the laminate 12, capacitance is formed by the first opposing electrode portion 26a of the first internal electrode layer 16a and the second opposing electrode portion 26b of the second internal electrode layer 16b opposing each other via the ceramic layer 14. Therefore, capacitance can be obtained between the first external electrode 30a and the second external electrode 30b to which the first internal electrode layer 16a is connected and the third external electrode 30c and the fourth external electrode 30d to which the second internal electrode layer 16b is connected, and capacitor characteristics are exhibited.

[0145] The external electrode 30 includes a base electrode layer 32 containing a metal component and a glass component, and a plating layer 34 disposed on the surface of the base electrode layer 32. The plating layer 34 includes a lower-layer plating layer and an upper-layer plating layer. The first external electrode 30a includes a first base electrode layer 32a containing a metal component, a first lower-layer plating layer 34a1 disposed on the first base electrode layer 32a, and a first upper-layer plating layer 34a2 disposed on the first lower-layer plating layer 34a1. The first external electrode 30a also includes a first exposed plating region 35a exposed on the surface of the first external electrode 30a. The second external electrode 30b includes a second base electrode layer 32b containing a metal component, a second lower-layer plating layer 34b1 disposed on the second base electrode layer 32b, and a second upper-layer plating layer 34b2 disposed on the second lower-layer plating layer 34b1. The second external electrode 30b has a second exposed plating region 35b exposed on the surface of the second external electrode 30b. The third external electrode 30c has a third base electrode layer 32c containing a metal component, a third lower plating layer 34c1 disposed on the third base electrode layer 32c, and a third upper plating layer 34c2 disposed on the third lower plating layer 34c1. The fourth external electrode 30d has a fourth base electrode layer 32d containing a metal component, a fourth lower plating layer 34d1 disposed on the fourth base electrode layer 32d, and a fourth upper plating layer 34d2 disposed on the fourth lower plating layer 34d1.

[0146] (2-1) Base Electrode Layer The base electrode layer 32 includes a first base electrode layer 32a, a second base electrode layer 32b, a third base electrode layer 32c, and a fourth base electrode layer 32d.

[0147] The first base electrode layer 32a is connected to the first internal electrode layer 16a and is disposed on the surface of the first end face 12e. The first base electrode layer 32a also extends from the first end face 12e and is disposed on parts of the first and second main faces 12a and 12b, as well as parts of the first and second side faces 12c and 12d. In this case, the first base electrode layer 32a is electrically connected to the first lead electrode portion 28a1 of the first internal electrode layer 16a. The second base electrode layer 32b is connected to the first internal electrode layer 16a and is disposed on the surface of the second end face 12f. The second base electrode layer 32b also extends from the second end face 12f and is disposed on parts of the first and second main faces 12a and 12b, as well as parts of the first and second side faces 12c and 12d. In this case, the second base electrode layer 32b is electrically connected to the second lead electrode portion 28a2 of the first internal electrode layer 16a.

[0148] The third base electrode layer 32c is connected to the second internal electrode layer 16b and is disposed on the surface of the first side surface 12c. The third base electrode layer 32c also extends from the first side surface 12c and is disposed on a portion of the first main surface 12a and a portion of the second main surface 12b. In this case, the third base electrode layer 32c is electrically connected to the third lead electrode portion 28b1 of the second internal electrode layer 16b. The fourth base electrode layer 32d is connected to the second internal electrode layer 16b and is disposed on the surface of the second side surface 12d. The fourth base electrode layer 32d also extends from the second side surface 12d and is disposed on a portion of the first main surface 12a and a portion of the second main surface 12b. In this case, the fourth base electrode layer 32d is electrically connected to the fourth lead electrode portion 28b2 of the second internal electrode layer 16b.

[0149] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, etc. Hereinafter, each configuration when the base electrode layer 32 is the baked layer, the conductive resin layer, or the thin film layer will be described.

[0150] (When the base electrode layer is a baking layer) The baking layer contains a glass component and a metal component. The glass component of the baking layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baking layer contains at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The baking layer is formed by applying a conductive paste containing a glass component and a metal component to the laminate 12 and baking it. The baking layer may be formed by simultaneously baking a laminated chip having an internal electrode layer 16 and a ceramic layer 14 with a conductive paste applied to the laminated chip, or by baking a laminated chip having an internal electrode layer 16 and a ceramic layer 14 to obtain the laminate 12 and then baking the conductive paste onto the laminate 12. When the baked layer is formed by simultaneously baking the laminated chip having the internal electrode layers 16 and the ceramic layers 14 and the conductive paste applied to the laminated chip, it is preferable to form the baked layer by baking a material to which a dielectric material is added instead of the glass component. The baked layer may be a multi-layered layer.

[0151] When the base electrode layer 32 contains a dielectric material instead of a glass component, it is possible to improve the adhesion between the laminate 12 and the base electrode layer 32. The base electrode layer 32 may contain both a glass component and a dielectric component.

[0152] The dielectric material contained in the base electrode layer 32 may be the same as or different from that of the ceramic layer 14. The dielectric component includes at least one selected from the group consisting of BaTiO, CaTiO, (Ba, Ca)TiO, SrTiO, and CaZrO.

[0153] When the first base electrode layer 32a is formed as a baked layer, the thickness in the length direction z of the first base electrode layer 32a at the center in the height direction x of the first end face 12e is preferably, for example, about 3 μm to 20 μm. When the second base electrode layer 32b is formed as a baked layer, the thickness in the length direction z of the second base electrode layer 32b at the center in the height direction x of the second end face 12f is preferably, for example, about 3 μm to 20 μm.

[0154] Furthermore, when the base electrode layer 32 is provided on the first main surface 12a and the second main surface 12b using a baked layer, the thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the center in the length direction z of the first base electrode layer 32a located on the first main surface 12a and the second main surface 12b is preferably, for example, 3 μm or more and 20 μm or less (thickness of the base electrode layer in the central portion of the e dimension), and the thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the center in the length direction z of the second base electrode layer 32b located on the first main surface 12a and the second main surface 12b is preferably, for example, 3 μm or more and 20 μm or less (thickness of the base electrode layer in the central portion of the e dimension).

[0155] Furthermore, when the base electrode layer 32 is provided on the first side surface 12c and the second side surface 12d using a baked layer, the thickness in the width direction y connecting the first side surface 12c and the second side surface 12d at the center in the longitudinal direction z of the first base electrode layer 32a located on the first side surface 12c and the second side surface 12d is preferably, for example, 3 μm or more and 20 μm or less (thickness of the base electrode layer at the center part of the end surface), and the thickness in the width direction y connecting the first side surface 12c and the second side surface 12d at the center in the longitudinal direction z of the second base electrode layer 32b located on the first side surface 12c and the second side surface 12d is preferably, for example, 3 μm or more and 20 μm or less (thickness of the base electrode layer at the center part of the side surface).

[0156] (When the base electrode layer is a conductive resin layer) When a conductive resin layer is provided as the base electrode layer 32, the conductive resin layer may be disposed on the baked layer so as to cover the baked layer, or may be disposed directly on the laminate 12. The conductive resin layer contains a metal and a thermosetting resin. The conductive resin layer may completely cover the base electrode layer, or may cover a portion of the base electrode layer.

[0157] Since the conductive resin layer contains a thermosetting resin, it is more flexible than a conductive layer made of, for example, a plating film or a fired conductive paste. Therefore, even if the three-terminal multilayer ceramic capacitor 100 is subjected to a physical shock or a shock due to a thermal cycle, the conductive resin layer functions as a buffer layer and can prevent cracks in the three-terminal multilayer ceramic capacitor 100.

[0158] The metal contained in the conductive resin layer can be Ag, Cu, Ni, Sn, Bi, or an alloy containing these. Alternatively, a metal powder whose surface is coated with Ag can also be used. When using a metal powder whose surface is coated with Ag, it is preferable to use Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder. The reason for using Ag conductive metal powder as the conductive metal is that Ag has the lowest resistivity among metals, making it suitable as an electrode material, and Ag is a noble metal that does not oxidize and has high weather resistance. The reason for using Ag-coated metal powder is that it allows the base metal to be made inexpensive while maintaining the above-mentioned properties of Ag.

[0159] Furthermore, the metal contained in the conductive resin layer may be Cu or Ni that has been subjected to an anti-oxidation treatment. The metal contained in the conductive resin layer may be a metal powder whose surface is coated with Sn, Ni, or Cu. When using a metal powder whose surface is coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder.

[0160] The metal contained in the conductive resin layer is preferably contained in an amount of 35 vol% or more and 75 vol% or less relative to the volume of the entire conductive resin. The average particle size of the metal contained in the conductive resin layer is not particularly limited. The average particle size of the conductive filler may be, for example, approximately 0.3 μm or more and 10 μm or less. The metal contained in the conductive resin layer is mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, contact between conductive fillers forms an electrical path inside the conductive resin layer.

[0161] The metal contained in the conductive resin layer may be spherical or flat, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0162] As the resin for the conductive resin layer, various known thermosetting resins such as epoxy resin, phenoxy resin, phenol resin, urethane resin, silicone resin, and polyimide resin can be used. Among them, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, and adhesion. The resin contained in the conductive resin layer is preferably contained in an amount of 25 vol% to 65 vol% of the total volume of the conductive resin.

[0163] The conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide-imide-based compounds can be used as the curing agent for the epoxy resin.

[0164] The conductive resin layer may be a multi-layered layer.

[0165] The thickness of the conductive resin layer located at the center in the height direction x of the laminate 12 located at the first end face 12e and the second end face 12f is preferably, for example, about 3 μm or more and 30 μm or less.

[0166] Furthermore, when a conductive resin layer is also provided on the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d, it is preferable that the thickness of the conductive resin layer at the center in the longitudinal direction z of the conductive resin layer located on the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d is, for example, approximately 3 μm or more and 30 μm or less.

[0167] (When the base electrode layer is a thin film layer) When a thin film layer is provided as the base electrode layer 32, the thin film layer is formed by a thin film formation method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0168] (2-2) Plating Layers The first plating layer 34a, the second plating layer 34b, the third plating layer 34c, and the fourth plating layer 34d, which are plating layers 34 that can be disposed on the base electrode layer 32, will be described with reference to Figures 14 to 17. The plating layers 34 have exposed plating regions 35.

[0169] The first plating layer 34a is disposed so as to cover the first base electrode layer 32a on the first end face 12e side. Furthermore, the first plating layer 34a may be disposed so as to cover the first base electrode layer 32a on the first principal surface 12a, the second principal surface 12b, the first side surface 12c, and the second side surface 12d side. Alternatively, the first plating layer 34a may be disposed only on the first base electrode layer 32a on the first end face 12e side. The first plating layer 34a includes a first lower-layer plating layer 34a1 disposed on the first base electrode layer 32a and a first upper-layer plating layer 34a2 disposed on the first lower-layer plating layer 34a1. The first upper-layer plating layer 34a2 is disposed on the first lower-layer plating layer 34a1 so as to expose a portion of the first lower-layer plating layer 34a1. In other words, the first upper-layer plating layer 34a2 is disposed on the first lower-layer plating layer 34a1, excluding the first exposed plating region 35a, so that the first lower-layer plating layer 34a1 has a first exposed plating region 35a that is exposed on the surface of the first external electrode 30a. In this embodiment, the first exposed plating region 35a is disposed on the first main surface 12a. In this case, the second main surface 12b of the three-terminal multilayer ceramic capacitor 100 serves as the mounting surface for the mounting board.

[0170] It is preferable that the first upper plating layer 34a2 covers the end portions of the first lower plating layer 34a1, thereby preventing the first lower plating layer 34a1 from peeling off.

[0171] A first ratio of the area of ​​the first exposed plating region 35a to the area of ​​the exposed region of the first external electrode 30a on the first main surface 12a when viewed in the height direction x of the laminate 12 is preferably 0.4% or more and 83.4% or less. Because the first ratio is 0.4% or more, hydrogen released from, for example, the first and second internal electrode layers 16a, 16b, the first and second base electrode layers 32a, 32b, and the first and second lower plating layers 34a1, 34b1 can be sufficiently released from the first exposed plating region 35a to the outside of the three-terminal multilayer ceramic capacitor 100, thereby suppressing deterioration of insulation resistance due to hydrogen. Furthermore, because the first ratio is 83.4% or less, the proportion of the first lower plating layer 34a1 that is not covered by the first upper plating layer 34a2 can be suppressed. This suppresses deterioration of moisture resistance due to water vapor penetration from the first exposed plating region 35a into the three-terminal multilayer ceramic capacitor 100. More preferably, the first ratio is 1.17% or more and 83.4% or less. Even more preferably, the first ratio is 1.40% or more and 83.4% or less. Even more preferably, the first ratio is 1.40% or more and 25.0% or less. The method of calculating the first ratio is the same as in the first embodiment.

[0172] The second plating layer 34b is disposed so as to cover the second base electrode layer 32b on the second end surface 12f side. Furthermore, the second plating layer 34b may be disposed so as to cover the second base electrode layer 32b on the first principal surface 12a, the second principal surface 12b, the first side surface 12c, and the second side surface 12d side. Alternatively, the second plating layer 34b may be disposed only on the second base electrode layer 32b on the second end surface 12f side. The second plating layer 34b includes a second lower-layer plating layer 34b1 disposed on the second base electrode layer 32b and a second upper-layer plating layer 34b2 disposed on the second lower-layer plating layer 34b1. The second upper-layer plating layer 34b2 is disposed on the second lower-layer plating layer 34b1 so as to expose a portion of the second lower-layer plating layer 34b1. In other words, the second upper-layer plating layer 34b2 is disposed on the second lower-layer plating layer 34b1, excluding the second exposed plating region 35b, so that the second lower-layer plating layer 34b1 has a second exposed plating region 35b that is exposed on the surface of the second external electrode 30b. In this embodiment, the second exposed plating region 35b is disposed on the first main surface 12a. In this case, the second main surface 12b of the three-terminal multilayer ceramic capacitor 100 serves as the mounting surface for the mounting board.

[0173] The second upper plating layer 34b2 preferably covers the ends of the second lower plating layer 34b1, thereby preventing the second lower plating layer 34b1 from peeling off.

[0174] For the same reasons as for the first ratio, the second ratio of the second plated exposed region 35b to the exposed region of the second external electrode 30b on the first main surface 12a when viewed in the height direction x of the laminate 12 is preferably 0.4% or more and 83.4% or less. More preferably, the second ratio is 1.17% or more and 83.4% or less. Even more preferably, the second ratio is 1.40% or more and 83.4% or less. Even more preferably, the second ratio is 1.40% or more and 25.0% or less. The method of calculating the second ratio is the same as in the first embodiment.

[0175] In the above, the first and second ratios are calculated as the exposed ratio, but the exposed ratio may be the ratio of the total area of ​​the first exposed plating region 35a and the second exposed plating region 35b to the total area of ​​the exposed regions of the first external electrode 30a and the second external electrode 30b. It is preferable that this total exposed ratio is 0.4% or more and 83.4% or less.

[0176] The third plating layer 34c is disposed so as to cover the third base electrode layer 32c on the first side surface 12c side. Furthermore, the third plating layer 34c may be disposed so as to cover the third base electrode layer 32c on the first principal surface 12a and the second principal surface 12b side. However, the third plating layer 34c may be disposed only on the third base electrode layer 32c on the first side surface 12c side. This third plating layer 34c includes a third lower-layer plating layer 34c1 disposed on the third base electrode layer 32c and a third upper-layer plating layer 34c2 disposed on the third lower-layer plating layer 34c1. The third upper-layer plating layer 34c2 covers the third lower-layer plating layer 34c1, and the third lower-layer plating layer 34c1 has no exposed region.

[0177] The fourth plating layer 34d is disposed so as to cover the fourth base electrode layer 32d on the second side surface 12d. Furthermore, the fourth plating layer 34d may be disposed so as to cover the fourth base electrode layer 32d on the first principal surface 12a and the second principal surface 12b. However, the fourth plating layer 34d may be disposed only on the fourth base electrode layer 32d on the second side surface 12d. This fourth plating layer 34d includes a fourth lower-layer plating layer 34d1 disposed on the fourth base electrode layer 32d and a fourth upper-layer plating layer 34d2 disposed on the fourth lower-layer plating layer 34d1. The fourth upper-layer plating layer 34d2 covers the fourth lower-layer plating layer 34d1, and the fourth lower-layer plating layer 34d1 has no exposed region.

[0178] In the three-terminal multilayer ceramic capacitor 100 of this embodiment, a positive potential is applied to the first external electrode 30a having the first exposed plating region 35a and the second external electrode 30b having the second exposed plating region 35b, and a negative potential is applied to the third external electrode 30c and the fourth external electrode 30d.

[0179] The first to fourth plating layers 34a to 34d include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag--Pd alloy, Au, and the like.

[0180] Preferably, the first to fourth lower plating layers 34a1 to 34d1 are Ni plating layers, and the first to fourth upper plating layers 34a2 to 34d2 are Sn plating layers.

[0181] The first to fourth lower plating layers 34a1 to 34d1 made of Ni plating are used to prevent the base electrode layer 32 from being eroded by solder when mounting the three-terminal multilayer ceramic capacitor 100. The first to fourth upper plating layers 34a2 to 34d2 made of Sn plating are used to improve the wettability of solder when mounting the three-terminal multilayer ceramic capacitor 100, thereby facilitating mounting.

[0182] The thicknesses of the first lower-layer plating layer 34a1 and the first upper-layer plating layer 34a2 on the first main surface 12a, the second main surface 12b, the first end surface 12e, the first side surface 12c, and the second side surface 12d are preferably 2 μm or more and 7 μm or less. The thicknesses of the second lower-layer plating layer 34b1 and the second upper-layer plating layer 34b2 on the first main surface 12a, the second main surface 12b, the second end surface 12f, the first side surface 12c, and the second side surface 12d are preferably 2 μm or more and 7 μm or less. Furthermore, the thicknesses of the third lower-layer plating layer 34c1 and the third upper-layer plating layer 34c2 on the first main surface 12a, the second main surface 12b, and the first side surface 12c are preferably 2 μm or more and 7 μm or less. The thickness of the fourth lower plating layer 34d1 and the fourth upper plating layer 34d2 on the first main surface 12a, the second main surface 12b, and the second side surface 12d is preferably 2 μm or more and 7 μm or less.

[0183] When a conductive resin layer is formed on the base electrode layer 32, the plating layer 34 is disposed so as to cover the conductive resin layer. Even in this case, the Ni plating layer, which is the lower plating layer of the plating layer 34, prevents the conductive resin layer from being eroded by solder, and the Sn plating layer, which is the upper plating layer, improves the wettability of the solder.

[0184] (3) Dimensions of the Three-Terminal Multilayer Ceramic Capacitor The dimension in the length direction z of the three-terminal multilayer ceramic capacitor 100 including the laminate 12 and the first external electrodes 30a to 30d is defined as dimension L, the dimension in the height direction x of the three-terminal multilayer ceramic capacitor 100 including the laminate 12 and the first external electrodes 30a to 30d is defined as dimension T, and the dimension in the width direction y of the three-terminal multilayer ceramic capacitor 100 including the laminate 12 and the first external electrodes 30a to 30d is defined as dimension W. The dimensions of the three-terminal multilayer ceramic capacitor 100 are not particularly limited, but are preferably such that the dimension L in the length direction z is 0.2 mm to 6.5 mm, the dimension W in the width direction y is 0.1 mm to 5.5 mm, and the dimension T in the height direction x is 0.1 mm to 6.5 mm. The dimensions of the three-terminal multilayer ceramic capacitor 100 can be measured using a microscope.

[0185] 2. Method for Manufacturing a Three-Terminal Multilayer Ceramic Capacitor Next, a method for manufacturing a three-terminal multilayer ceramic capacitor will be described.

[0186] (Step 1) First, a dielectric sheet for the ceramic layer and a conductive paste for the internal electrode layer are prepared. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and the solvent may be known.

[0187] (Step 2) Then, on the dielectric sheet, the conductive paste for the internal electrode layers is printed in a predetermined pattern by, for example, screen printing or gravure printing. Thereby, a dielectric sheet on which the pattern of the first internal electrode layer is formed, and a dielectric sheet on which the pattern of the second internal electrode layer is formed are prepared. More specifically, a screen plate for printing the first internal electrode layer and a screen plate for printing the second internal electrode layer are separately prepared, and the patterns of each internal electrode layer can be printed using a printer that can print the two types of screen plates separately.

[0188] (Step 3) Subsequently, a predetermined number of dielectric sheets for outer layers, on which the pattern of the internal electrode layer is not printed, are laminated to form a portion that will become the second main surface side outer layer portion on the second main surface side. Then, a dielectric sheet on which the pattern of the first internal electrode layer is printed and a dielectric sheet on which the pattern of the second internal electrode layer is printed are sequentially laminated on the portion that will become the second main surface side outer layer portion so as to form the structure of the present invention, to form a portion that will become the internal layer portion. A predetermined number of dielectric sheets for outer layers, on which the pattern of the internal electrode layer is not printed, are laminated on this portion that will become the internal layer portion, to form a portion that will become the first main surface side outer layer portion on the first main surface side. In this way, a laminated sheet is produced.

[0189] (Step 4) Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0190] (Step 5) The laminated block is then cut to a predetermined size to obtain laminated chips. At this time, the corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0191] (Step 6) The cut-out laminated chips are then fired to produce a laminate. The firing temperature depends on the materials of the ceramic layers and internal electrode layers, but is preferably 900° C. or higher and 1400° C. or lower.

[0192] (Step 7) Next, a third base electrode layer 32c of the third external electrode 30c is formed on the first side surface 12c of the laminate 12 obtained by firing, and a fourth base electrode layer 32d of the fourth external electrode 30d is formed on the second side surface 12d of the laminate 12. (When the base electrode layer is a baked layer) When forming baked layers as the third base electrode layer 32c and the fourth base electrode layer 32d, a conductive paste containing a glass component and a metal component is applied, and then a baking process is performed to form the base electrode layers. The baking temperature at this time is preferably 700°C or higher and 900°C or lower.

[0193] Various methods can be used to form the baked layer. For example, a method of applying a conductive paste by extruding it through a slit can be used. With this method, by increasing the amount of conductive paste extruded, the base electrode layer 32 can be formed not only on the first side surface 12c and the second side surface 12d but also on portions of the first principal surface 12a and the second principal surface 12b. The baked layer can also be formed using a roller transfer method. With the roller transfer method, when the base electrode layer 32 is formed not only on the first side surface 12c and the second side surface 12d but also on portions of the first principal surface 12a and the second principal surface 12b, the base electrode layer 32 can be formed on portions of the first principal surface 12a and the second principal surface 12b by increasing the pressing pressure during roller transfer.

[0194] Next, the first base electrode layer 32a of the first external electrode 30a is formed on the first end face 12e of the fired laminate, and the second base electrode layer 32b of the second external electrode 30b is formed on the second end face 12f. As with the third and fourth base electrode layers 32c and 32d, when forming baked layers as the first and second base electrode layers 32a and 32b, a conductive paste containing a glass component and a metal component is applied, followed by a baking process to form the base electrode layers. The baking temperature is preferably 700°C or higher and 900°C or lower. The conductive paste can be applied to both end faces of the laminate by, for example, a dipping method or a screen printing method.

[0195] In the baking process, the third base electrode layer 32c, the fourth base electrode layer 32d, the first base electrode layer 32a, and the second base electrode layer 32b may be baked simultaneously, or they may be baked separately on both side surfaces 12c and 12d and both end surfaces 12e and 12f.

[0196] When the base electrode layer is formed as a baking layer, the baking layer may contain a dielectric component. In this case, the dielectric component may be contained instead of the glass component, or both may be contained.

[0197] The dielectric component is preferably, for example, the same dielectric material as the laminate. When the baked layer contains the dielectric component, it is preferable to apply a conductive paste to the pre-fired laminated chip, and then simultaneously bake (fire) the pre-fired laminated chip and the conductive paste applied to the pre-fired laminated chip to form a laminate with a baked layer. The baking temperature (baking temperature) at this time is preferably 900°C or higher and 1400°C or lower.

[0198] (When the Base Electrode Layer is a Conductive Resin Layer) When the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of a baked layer, or the conductive resin layer may be formed alone directly on the laminate 12 without forming a baked layer.

[0199] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto the baking layer or the laminate 12, and then performing a heat treatment at a temperature of 250°C to 550°C to thermally cure the resin and form the conductive resin layer. The heat treatment is preferably performed in an N2 atmosphere. Furthermore, to prevent the resin from scattering and the various metal components from oxidizing, it is preferable to keep the oxygen concentration below 100 ppm.

[0200] The conductive resin paste can be applied using a method similar to the method of forming the base electrode layer 32 as a baked layer, for example, a method of applying the conductive resin paste by extruding it through a slit or a roller transfer method.

[0201] (When the base electrode layer is a thin film layer) When the base electrode layer 32 is formed as a thin film layer, masking or the like is performed, and the base electrode layer can be formed by a thin film formation method such as sputtering or vapor deposition in the area where the external electrode 30 is to be formed. The base electrode layer formed as a thin film layer is a layer of deposited metal particles having a thickness of 1 μm or less.

[0202] (Step 8) Next, the plating layer 34 is formed. The plating layer 34 is formed on the surface of the base electrode layer 32. More specifically, a Ni plating layer is formed on the base electrode layer 32 as the lower plating layer, and a Sn plating layer is formed as the upper plating layer. In this embodiment, the plating layers 34 are formed on the base electrode layer 32 in the following order: a first lower plating layer 34a1, a second lower plating layer 34b1, a third lower plating layer 34c1, and a fourth lower plating layer 34d1, which are Ni plating layers; and a first upper plating layer 34a2, a second upper plating layer 34b2, a third upper plating layer 34c2, and a fourth upper plating layer 34d2, which are Sn plating layers. The Ni plating layer and the Sn plating layer are formed in this order, for example, by barrel plating. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment with a catalyst or the like to improve the plating deposition rate, which makes the process more complicated. Therefore, it is usually preferable to use electrolytic plating.

[0203] (Step 9) Next, the first and second upper plating layers 34a2, 34b2 (Sn plating layers) are treated so that the first and second lower plating layers 34a1, 34b1 (Ni plating layers) have a predetermined exposed ratio. Treatment methods that can be used include, for example, scraping, melting, laser processing, and resist-based methods. In the scraping method, a metal terminal having a diameter of approximately 30 to 100 μm is brought into contact with the first and second upper plating layers 34a2, 34b2 to scrape away the soft Sn plating layer so that the first and second lower plating layers 34a1, 34b1 (Ni plating layers) have a predetermined exposed ratio. In the melting method, the molded body after plating layer 34 formation is immersed in an enstrip agent (strip agent). For example, the heights of multiple molded bodies after the plating layer 34 formation are aligned using an alignment jig, and one surface of each molded body is immersed in an enstrip agent to dissolve the Sn plating layer so that the first and second underlayer plating layers 34a, 34b (Ni plating layers) are exposed to a predetermined ratio. At this time, it is preferable to immerse the first main surface 12a (and / or the second main surface 12b) side. This prevents the internal electrode layer 16 on the first end face 12e, second end face 12f, first side face 12c, and second side face 12d sides from being immersed. In the laser processing method, multiple molded bodies after the plating layer 34 formation are aligned, and a predetermined area of ​​the Sn plating layer of each molded body is removed with a laser so that the first and second underlayer plating layers 34a, 34b (Ni plating layers) are exposed to a predetermined ratio. Furthermore, by using a resist, the first and second lower plating layers 34a1, 34b1 (Ni plating layers) can be formed with a predetermined exposure ratio.

[0204] In the manner described above, the three-terminal multilayer ceramic capacitor 100 according to this embodiment is manufactured.

[0205] The three-terminal multilayer ceramic capacitor 100 according to this embodiment has the same effects as the two-terminal multilayer ceramic capacitor 10 according to the first embodiment.

[0206] 3. Modified Examples of Three-Terminal Multilayer Ceramic Capacitor Next, modified examples of the three-terminal multilayer ceramic capacitor 100 will be described.

[0207] (1) The external electrode 30 of the second embodiment described above includes a base electrode layer 32 and a plating layer 34. Alternatively, the external electrode 30 may include the plating layer 34 and not include the base electrode layer 32. Although not shown, the following describes a structure in which the plating layer 34 is provided without providing the base electrode layer 32 for the first to fourth external electrodes 30a to 30d.

[0208] Each of the first to fourth external electrodes 30a to 30d may not be provided with a base electrode layer 32, and the plating layer 34 may be formed directly on the surface of the laminate 12. That is, the three-terminal multilayer ceramic capacitor 100 may have a structure in which the first end face 12e, the second end face 12f, the first side face 12c, and the second side face 12d are plated to form a plating layer 34 electrically connected to the first internal electrode layer 16a or the second internal electrode layer 16b. In such a case, the plating layer 34 may be formed by plating after a catalyst is applied to the surface of the laminate 12 as a pretreatment. Either electrolytic plating or electroless plating may be used for the plating. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferred. Barrel plating is preferred as the plating method.

[0209] In addition, when the plating layer 34 is formed directly on the laminate 12 without providing the base electrode layer 32, the amount of reduction in the thickness of the base electrode layer 32 can be converted into a lower profile, i.e., a thinner laminate, or into the thickness of the laminate, i.e., the thickness of the effective layer portion, thereby improving the design freedom of the thickness of the laminate 12.

[0210] The plating layer 34 includes first to fourth lower plating layers 34a1 to 34d1 (lower plating layers) formed on the surface of the laminate 12, and first to fourth upper plating layers 34a2 to 34d2 (upper plating layers) formed on the surfaces of the first to fourth lower plating layers 34a1 to 34d1. The first and second lower plating layers 34a1 and 34b1 have exposed plating regions that are not covered by the upper plating layers, as in the above-described embodiment. The lower plating layer and the upper plating layer each preferably contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such a metal. Furthermore, the lower plating layer is preferably formed using Ni, which has solder barrier properties, and the upper plating layer is preferably formed using Sn or Au, which have good solder wettability.

[0211] Furthermore, for example, when the first internal electrode layer 16 a and the second internal electrode layer 16 b are formed using Ni, the lower plating layer is preferably formed using Cu, which has good bonding properties with Ni. The plating layer may be an upper plating layer as the outermost layer, or another plating electrode may be further formed on the surface of the upper plating layer.

[0212] When the external electrode 30 is formed only with the plating layer 34 without providing the base electrode layer 32, the thickness of each plating layer 34 disposed without providing the base electrode layer 32 is preferably 1.0 μm or more and 20.0 μm or less. Furthermore, it is preferable that the plating layer 34 does not contain glass. The metal ratio per unit volume of the plating layer 34 is preferably 99 volume % or more.

[0213] (2) In the second embodiment described above, the first lower-layer plating layer 34a1 has a first exposed plating region 35a that is not covered by the first upper-layer plating layer 34a2, and the second lower-layer plating layer 34b1 has a second exposed plating region 35b that is not covered by the second upper-layer plating layer 34b2. However, the form of the exposed regions is not limited to this. As described in the modified example of the first embodiment (see FIGS. 9 and 10 ), the external electrode 30 may have an exposed base region 36 in which the base electrode layer 32 is not covered by the plating layer 34. For example, the first base electrode layer 32a may have a first exposed base region that is not covered by the first plating layer 34a. Furthermore, the second base electrode layer 32b may have a second exposed base region that is not covered by the second plating layer 34b. At this time, the first external electrode 30a has a first exposed base region 36a together with a first exposed plating region 35a, and the second external electrode 30b has a second exposed base region together with a second exposed plating region 35b, and a positive potential is applied to the first external electrode 30a and the second external electrode 30b.

[0214] The exposed base region 36 is preferably disposed on the first main surface 12 a. The second main surface 12 b is preferably the mounting surface. This allows hydrogen in the absorbing layer to be efficiently released through the exposed base region 36 from the first main surface 12 a, which is not soldered and does not face the mounting substrate 40, when solder is applied mainly to the first and second end faces 12 e and 12 f as shown in FIG. 6 .

[0215] As long as solder is not applied, the exposed base area 36 may be located on any of the second main surface 12b, the first end surface 12e, the second end surface 12f, the first side surface 12c, and the second side surface 12d other than the first main surface 12a.

[0216] Furthermore, the first exposed plating region 35a and the first exposed base region 36a may be formed on different surfaces.

[0217] In addition, the first exposed base region 36a is preferably formed closer to the first end face 12e than the tip end portion of the first lower plating layer 34a1 on the second end face 12f side.

[0218] The first exposed base region 36a can be formed by the same method as that for the first exposed plating region 35a.

[0219] Although not shown, the third base electrode layer 32c may have a third exposed base region that is not covered by the third plating layer 34c, and the fourth base electrode layer 32d may have a fourth exposed base region that is not covered by the fourth plating layer 34d.

[0220] (3) In the second embodiment described above, the first exposed plating region 35a, where the first lower-layer plating layer 34a is not covered by the first upper-layer plating layer 34a, is provided on the first main surface 12a. Similarly, the second exposed plating region 35b, where the second lower-layer plating layer 34b is not covered by the second upper-layer plating layer 34b, is provided on the first main surface 12a. However, the present invention is not limited to this, and the exposed plating region 35 may be provided on at least one of the first main surface 12a, the second main surface 12b, the first end face 12e, the second end face 12f, the first side face 12c, and the second side face 12d.

[0221] (4) In the second embodiment described above, the first external electrode 30a has a first exposed plating region 35a and the second external electrode 30b has a second exposed plating region 35b. However, in addition to the first exposed plating region 35a of the first external electrode 30a and the second exposed plating region 35b of the second external electrode 30b, the third external electrode 30c may have a third exposed plating region in which the third lower-layer plating layer 34c1 is not covered by the third upper-layer plating layer 34c2, and the fourth external electrode 30d may have a fourth exposed plating region in which the fourth lower-layer plating layer 34d1 is not covered by the fourth upper-layer plating layer 34d2. In this case, a positive potential is applied to either the first or second external electrode 30a, 30b or the third or fourth external electrode 30c, 30d, and a negative potential is applied to the other.

[0222] A third ratio of the area of ​​the third exposed plating region to the area of ​​the exposed region of the third external electrode 30c on the first main surface 12a when viewed in the first main surface direction is preferably 0.4% or more and 83.4% or less. Similarly, a fourth ratio of the area of ​​the fourth exposed plating region to the area of ​​the exposed region of the fourth external electrode 30d on the first main surface 12a when viewed in the first main surface direction is preferably 0.4% or more and 83.4% or less. Furthermore, a ratio of the total of the first to fourth exposed plating regions 35a to 35d to the total exposed area of ​​the first to fourth external electrodes 30a to 30d is preferably 0.4% or more and 83.4% or less.

[0223] Furthermore, the first external electrode 30a may not have the first exposed plating region 35a, the second external electrode 30b may not have the second exposed plating region 35b, the third external electrode 30c may have a third exposed plating region in which the third lower-layer plating layer 34c1 is not covered by the third upper-layer plating layer 34c2, and the fourth external electrode 30d may have a fourth exposed plating region in which the fourth lower-layer plating layer 34d1 is not covered by the fourth upper-layer plating layer 34d2. In this case, a positive potential is applied to the third and fourth external electrodes 30c, 30d.

[0224] (5) In the second embodiment described above, the first to fourth lower-layer plating layers 34a1 to 34d1 are arranged to cover all of the first to fourth base electrode layers 32a to 32d. However, this is not limiting, and the first lower-layer plating layer 34a1 may be arranged to cover a portion of the first base electrode layer 32a, the second lower-layer plating layer 34b1 may be arranged to cover a portion of the second base electrode layer 32b, the third lower-layer plating layer 34c1 may be arranged to cover a portion of the third base electrode layer 32c, and the fourth lower-layer plating layer 34d1 may be arranged to cover a portion of the fourth base electrode layer 32d.

[0225] C. Experimental Examples (1) Samples of Experimental Examples First, two-terminal multilayer ceramic capacitors according to the examples having the following specifications were fabricated according to the above-described method for manufacturing a multilayer ceramic capacitor.

[0226] ◎ Structure of multilayer ceramic capacitor: 2 terminals (see Figure 1) ◎ Dimensions of multilayer ceramic capacitor L x W x T (including design values): 1.13 mm x 0.63 mm x 0.63 mm ◎ Ceramic layer material: BaTiO3 ◎ Capacitance: 22 μF ◎ Rated voltage: 4 V

[0227] ◎ Structure of external electrodes Base electrode layer: electrode containing conductive metal (Cu) and glass component Film thickness of base electrode layer on end faces: film thickness of base electrode layer at height center portion located on the first end face and second end face = 12 μm Film thickness of base electrode layer on main faces and side faces: film thickness of base electrode layer at length center portion located on the first main face and second main face, first side face and second side face = 12 μm Plating layer: two-layer structure of Ni plating layer and Sn plating layer Film thickness of Ni plating layer on end faces: film thickness of Ni plating layer at height center portion located on the first end face and second end face = 2 μm Film thickness of Ni plating layer on main faces and side faces: film thickness of Ni plating layer at length center portion located on the first main face and second main face, first side face and second side face = 2 μm - Thickness of the Sn plating layer on the end faces: Thickness of the Sn plating layer at the center in the height direction of the Sn plating layer located on the first end face and the second end face = 3 μm - Thickness of the Sn plating layer on the main faces and side faces: Thickness of the Sn plating layer at the center in the length direction of the Sn plating layer located on the first main face and the second main face, the first side face and the second side face = 3 μm

[0228] ◎ Exposure ratio of the first lower-layer plating layer and the second lower-layer plating layer (Ni plating layer) on the first principal surface Exposure ratio = (exposed area of ​​the first lower-layer plating layer and the second lower-layer plating layer) / area of ​​the first external electrode and the second external electrode on the first principal surface × 100 The areas of the first external electrode and the second external electrode on the first principal surface were each set to L (200 μm) × W (600 μm). The exposure ratios for Examples 1 to 8 and Comparative Example 1 are as follows: (Example 1) 0.2% (Example 2) 0.4% (Example 3) 1.17% (Example 4) 1.4% (Example 5) 1.67% (Example 6) 25% (Example 7) 83.4% (Example 8) 89.2% (Comparative Example 1) 0%

[0229] (2) Experimental Results The deterioration of insulation resistance (IR) was confirmed for 100 samples each of Examples 1 to 8 and Comparative Example 1 in a PCBT test (125°C, 95% RH, 2V, 72 hours) after solder mounting, and the number of deteriorated samples was counted. Table 1 shows the experimental results.

[0230]

[0231] From the results in Table 1, in Comparative Example 1, 11 out of 100 samples were judged to have deteriorated insulation resistance. Meanwhile, in Examples 1 to 8, 8 or fewer out of 100 samples were judged to have deteriorated insulation resistance. Furthermore, in Examples 2 to 7, 4 or fewer out of 100 samples were judged to have deteriorated insulation resistance, and in Examples 3 to 7, 4 or fewer out of 100 samples were judged to have deteriorated insulation resistance. Furthermore, in Examples 4 to 6, 0 out of 100 samples were judged to have deteriorated insulation resistance. Therefore, it was found that deterioration of insulation resistance was suppressed when the exposed ratio was greater than 0%. It was also found that deterioration of insulation resistance was further suppressed when the exposed ratio was 0.4% or more and 83.4% or less. It was also found that deterioration of insulation resistance was suppressed when the exposed ratio was 1.17% or more and 83.4% or less, and further when the exposed ratio was 1.40% or more and 83.4% or less. Furthermore, it was found that when the exposed ratio was 1.40% or more and 25.0% or less, the deterioration of the insulation resistance was further suppressed.

[0232] As described above, although the embodiments of the present invention have been disclosed in the above description, the present invention is not limited thereto. In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and such modifications are included in the present invention.

[0233] <1> A laminate having a plurality of stacked ceramic layers, the laminate having a first main surface and a second main surface opposing each other in a height direction, a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction and the length direction; a plurality of first internal electrode layers arranged on the plurality of ceramic layers and extended to the first end surface; a plurality of second internal electrode layers arranged on the plurality of ceramic layers and extended to the second end surface; a first external electrode arranged on the first end surface and extending from the first end surface to be arranged on a part of the first main surface, a part of the second main surface, a part of the first side surface, and a part of the second side surface, and connected to the first internal electrode layer; and a second external electrode arranged on the second end surface and extending from the second end surface to be arranged on a part of the first main surface, a part of the second main surface, a part of the first side surface, and a part of the second side surface, and connected to the second internal electrode layer, the first external electrode comprises a first base electrode layer disposed on the laminate, a first base electrode layer disposed on the first base electrode layer, and a first upper plating layer disposed on the first base electrode layer excluding the first exposed plating region so that the first base plating layer has a first exposed plating region exposed on the surface of the first external electrode; and the second external electrode comprises a second base electrode layer disposed on the laminate, a second base electrode layer disposed on the second base electrode layer, and a second upper plating layer disposed on the second base plating layer excluding the second exposed plating region so that the second base plating layer has a second exposed plating region exposed on the surface of the second external electrode.

[0234] <2> A laminate having a plurality of laminated ceramic layers, the laminate having a first main surface and a second main surface opposing each other in a height direction, a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction and the length direction; a plurality of first internal electrode layers arranged on the plurality of ceramic layers and drawn out to the first end surface and the second end surface; a plurality of second internal electrode layers arranged on the plurality of ceramic layers and drawn out to the first side surface and the second side surface; a first external electrode arranged on the first end surface and extending from the first end surface to be arranged on a part of the first main surface, a part of the second main surface, a part of the first side surface, and a part of the second side surface, and connected to the first internal electrode layer; and a second external electrode arranged on the second end surface and extending from the second end surface to be arranged on a part of the first main surface, a part of the second main surface, a part of the first side surface, and a part of the second side surface, and connected to the first internal electrode layer. a third external electrode disposed on the first side surface, extending from the first side surface to be disposed on a portion of the first main surface and a portion of the second main surface, and connected to the second internal electrode layer; and a fourth external electrode disposed on the second side surface, extending from the second side surface to be disposed on a portion of the first main surface and a portion of the second main surface, and connected to the second internal electrode layer, wherein the first external electrode has a first base electrode layer disposed on the laminate, a first lower-layer plating layer disposed on the first base electrode layer, and a first upper-layer plating layer disposed on the first lower-layer plating layer excluding the first exposed plating region so that the first lower-layer plating layer has a first exposed plating region exposed on a surface of the first external electrode, the second external electrode includes a second base electrode layer disposed on the laminate, a second lower-layer plating layer disposed on the second base electrode layer, and a second upper-layer plating layer disposed on the second lower-layer plating layer excluding the second exposed plating region so that the second lower-layer plating layer has a second exposed plating region exposed on the surface of the second external electrode;the third external electrode has a third base electrode layer disposed on the laminate, a third lower-layer plating layer disposed on the third base electrode layer, and a third upper-layer plating layer disposed on the third lower-layer plating layer; and the fourth external electrode has a fourth base electrode layer disposed on the laminate, a fourth lower-layer plating layer disposed on the fourth base electrode layer, and a fourth upper-layer plating layer disposed on the fourth lower-layer plating layer.

[0235] <3> The multilayer ceramic electronic component according to <2>, wherein the third upper-layer plating layer is disposed on the third lower-layer plating layer excluding the third exposed plating region so that the third lower-layer plating layer has a third exposed plating region exposed on the surface of the third external electrode, and the fourth upper-layer plating layer is disposed on the fourth lower-layer plating layer excluding the fourth exposed plating region so that the fourth lower-layer plating layer has a fourth exposed plating region exposed on the surface of the fourth external electrode.

[0236] <4> A laminate having a plurality of stacked ceramic layers, the laminate having a first main surface and a second main surface opposing each other in a height direction, a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction and the length direction; a plurality of first internal electrode layers arranged on the plurality of ceramic layers and drawn out to the first end surface and the second end surface; a plurality of second internal electrode layers arranged on the plurality of ceramic layers and drawn out to the first side surface and the second side surface; a first external electrode arranged on the first end surface and extending from the first end surface to be arranged on a part of the first main surface, a part of the second main surface, a part of the first side surface, and a part of the second side surface, and connected to the first internal electrode layer; and a second external electrode arranged on the second end surface and extending from the second end surface to be arranged on a part of the first main surface, a part of the second main surface, a part of the first side surface, and a part of the second side surface, and connected to the first internal electrode layer. a third external electrode arranged on the first side surface, extending from the first side surface to be arranged on a part of the first main surface and a part of the second main surface, and connected to the second internal electrode layer; and a fourth external electrode arranged on the second side surface, extending from the second side surface to be arranged on a part of the first main surface and a part of the second main surface, and connected to the second internal electrode layer, wherein the first external electrode has a first base electrode layer arranged on the laminate, a first base plating layer arranged on the first base electrode layer, and a first upper plating layer arranged on the first base plating layer, and the second external electrode has a second base electrode layer arranged on the laminate, a second base plating layer arranged on the second base electrode layer, and a second upper plating layer arranged on the second base plating layer, the third external electrode comprises a third base electrode layer disposed on the laminate, a third lower-layer plating layer disposed on the third base electrode layer, and a third upper-layer plating layer disposed on the third lower-layer plating layer excluding the third exposed plating region so that the third lower-layer plating layer has a third exposed plating region exposed on a surface of the third external electrode;the fourth external electrode comprises: a fourth base electrode layer disposed on the laminate; a fourth lower-layer plating layer disposed on the fourth base electrode layer; and a fourth upper-layer plating layer disposed on the fourth lower-layer plating layer excluding the fourth exposed plating region so that the fourth lower-layer plating layer has a fourth exposed plating region exposed on a surface of the fourth external electrode.

[0237] <5> The multilayer ceramic electronic component according to any one of <1> to <3>, wherein a first ratio of an area of ​​the first exposed plating region to an area of ​​the exposed region of the first external electrode on the first main surface as viewed in the first main surface direction is 0.4% or more and 83.4% or less, and a second ratio of an area of ​​the second exposed plating region to an area of ​​the exposed region of the second external electrode on the first main surface as viewed in the first main surface direction is 0.4% or more and 83.4% or less.

[0238] <6> The multilayer ceramic electronic component according to <5>, wherein the first ratio and the second ratio are 1.17% or more and 83.4% or less.

[0239] <7> The multilayer ceramic electronic component according to <6>, wherein the first ratio and the second ratio are 1.40% or more and 83.4% or less.

[0240] <8> The multilayer ceramic electronic component according to <7>, wherein the first ratio and the second ratio are 1.40% or more and 25.0% or less.

[0241] <9> The multilayer ceramic electronic component according to any one of <1> to <8>, wherein the first exposed plating region is disposed on the first main surface.

[0242] <10> The multilayer ceramic electronic component according to any one of <1> to <9>, wherein the first lower plating layer has a thickness of 2 μm or more and 7 μm or less.

[0243] <11> The multilayer ceramic electronic component according to any one of <1> to <10>, wherein a portion of the first base electrode layer is exposed on the first main surface.

[0244] <12> The multilayer ceramic electronic component according to <3> or <4>, wherein a third ratio of an area of ​​the third exposed plating region to an area of ​​the exposed region of the third external electrode on the first main surface as viewed in the first main surface direction and / or a fourth ratio of an area of ​​the fourth exposed plating region to an area of ​​the exposed region of the fourth external electrode on the first main surface as viewed in the first main surface direction is 0.4% or more and 83.4% or less.

[0245] <13> A mounting structure for a multilayer ceramic electronic component, comprising: the multilayer ceramic electronic component according to any one of <1> to <12>; and a mounting substrate on which the multilayer ceramic electronic component is mounted, in which the first exposed plating region is disposed on the first main surface, and the multilayer ceramic electronic component is mounted so that the second main surface faces the mounting substrate.

[0246] <14> A mounting structure for a multilayer ceramic electronic component, comprising: the multilayer ceramic electronic component according to any one of <2>, <3>, and <12>; and a mounting substrate on which the multilayer ceramic electronic component is mounted, wherein the first external electrode and the second external electrode are electrodes to which a positive potential is applied.

[0247] <15> A mounting structure for a multilayer ceramic electronic component, comprising: the multilayer ceramic electronic component according to <4>; and a mounting substrate on which the multilayer ceramic electronic component is mounted, wherein the third external electrode and the fourth external electrode are electrodes to which a positive potential is applied.

[0248] 10: Two-terminal multilayer ceramic capacitor 12: Laminate 12a: First main surface 12b: Second main surface 12c: First side surface 12d: Second side surface 12e: First end surface 12f: Second end surface 14: Ceramic layer 14a: Outer layer portion 14b: Inner layer portion 16: Internal electrode layer 16a, 16b: First and second internal electrode layers 18: Inner layer portion 20a: First main surface outer layer portion 20b: Second main surface outer layer portion 22a: First side surface outer layer portion 22b: Second side surface outer layer portion 24a: First end surface outer layer portion 24b: Second end surface outer layer portion 26a: First opposing electrode portion 26b : Second opposing electrode portion 27 : Counter electrode portion 28a : First extracted electrode portion 28b : Second extracted electrode portion 28a1 : First extracted electrode portion 28a2 : Second extracted electrode portion 28b1 : Third extracted electrode portion 28b2 : Fourth extracted electrode portion 30 : External electrodes 30a to 30d : First to fourth external electrodes 32 : Base electrode layers 32a to 32d : First to fourth base electrode layers 34 : Plating layers 34a to 34d : First to fourth plating layers 34a1 to 34d1 : First to fourth lower plating layers 34a2 to 34d2 : First to fourth upper plating layers 35 : Exposed plating regions 35a to 35d : First to fourth exposed plating regions 36: Exposed base region 36a: First exposed base region 40: Mounting substrate 41: Land 42: Solder 100: Three-terminal multilayer ceramic capacitor

Claims

1. a laminate having a plurality of laminated ceramic layers, the laminate having a first main surface and a second main surface opposed to each other in a height direction, a first end surface and a second end surface opposed to each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposed to each other in a width direction perpendicular to the height direction and the length direction; a plurality of first internal electrode layers disposed on the plurality of ceramic layers and extending to the first end surface; a plurality of second internal electrode layers disposed on the plurality of ceramic layers and extending to the second end surface; a first external electrode that is disposed on the first end face, extends from the first end face, and is disposed on a part of the first main face, a part of the second main face, a part of the first side face, and a part of the second side face, and is connected to the first internal electrode layer; a second external electrode that is disposed on the second end face, extends from the second end face, and is disposed on a part of the first main face, a part of the second main face, a part of the first side face, and a part of the second side face, and is connected to the second internal electrode layer; the first external electrode has a first base electrode layer disposed on the laminate, a first underlayer plating layer disposed on the first base electrode layer, and a first upper-layer plating layer disposed on the first underlayer plating layer excluding the first exposed plating region such that the first underlayer plating layer has a first exposed plating region exposed on a surface of the first external electrode; the second external electrode having a second base electrode layer disposed on the laminate, a second lower-layer plating layer disposed on the second base electrode layer, and a second upper-layer plating layer disposed on the second lower-layer plating layer excluding the second plating exposed region such that the second lower-layer plating layer has a second plating exposed region exposed on a surface of the second external electrode.

2. a laminate having a plurality of laminated ceramic layers, the laminate having a first main surface and a second main surface opposed to each other in a height direction, a first end surface and a second end surface opposed to each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposed to each other in a width direction perpendicular to the height direction and the length direction; a plurality of first internal electrode layers disposed on the plurality of ceramic layers and extending to the first end surface and the second end surface; a plurality of second internal electrode layers disposed on the plurality of ceramic layers and extending to the first side surface and the second side surface; a first external electrode that is disposed on the first end face, extends from the first end face, and is disposed on a part of the first main face, a part of the second main face, a part of the first side face, and a part of the second side face, and is connected to the first internal electrode layer; a second external electrode that is disposed on the second end face, extends from the second end face, and is disposed on a part of the first main face, a part of the second main face, a part of the first side face, and a part of the second side face, and is connected to the first internal electrode layer; a third external electrode disposed on the first side surface, extending from the first side surface to a portion of the first main surface and a portion of the second main surface, and connected to the second internal electrode layer; a fourth external electrode that is disposed on the second side surface, extends from the second side surface, is disposed on a part of the first main surface and a part of the second main surface, and is connected to the second internal electrode layer; the first external electrode has a first base electrode layer disposed on the laminate, a first underlayer plating layer disposed on the first base electrode layer, and a first upper-layer plating layer disposed on the first underlayer plating layer excluding the first exposed plating region such that the first underlayer plating layer has a first exposed plating region exposed on a surface of the first external electrode; the second external electrode has a second base electrode layer disposed on the laminate, a second underlayer plating layer disposed on the second base electrode layer, and a second upper layer plating layer disposed on the second underlayer plating layer excluding the second plating exposed region such that the second underlayer plating layer has a second plating exposed region exposed on a surface of the second external electrode, the third external electrode has a third base electrode layer disposed on the laminate, a third lower-layer plating layer disposed on the third base electrode layer, and a third upper-layer plating layer disposed on the third lower-layer plating layer, the fourth external electrode having a fourth base electrode layer disposed on the laminate, a fourth lower-layer plating layer disposed on the fourth base electrode layer, and a fourth upper-layer plating layer disposed on the fourth lower-layer plating layer.

3. the third upper-layer plating layer is disposed on the third lower-layer plating layer except for the third exposed plating region, such that the third lower-layer plating layer has a third exposed plating region exposed on a surface of the third external electrode; 3. The multilayer ceramic electronic component according to claim 2, wherein the fourth upper-layer plating layer is disposed on the fourth lower-layer plating layer except for the fourth exposed plating region, such that the fourth lower-layer plating layer has a fourth exposed plating region exposed on a surface of the fourth external electrode.

4. a laminate having a plurality of laminated ceramic layers, the laminate having a first main surface and a second main surface opposed to each other in a height direction, a first end surface and a second end surface opposed to each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposed to each other in a width direction perpendicular to the height direction and the length direction; a plurality of first internal electrode layers disposed on the plurality of ceramic layers and extending to the first end surface and the second end surface; a plurality of second internal electrode layers disposed on the plurality of ceramic layers and extending to the first side surface and the second side surface; a first external electrode that is disposed on the first end face, extends from the first end face, and is disposed on a part of the first main face, a part of the second main face, a part of the first side face, and a part of the second side face, and is connected to the first internal electrode layer; a second external electrode that is disposed on the second end face, extends from the second end face, and is disposed on a part of the first main face, a part of the second main face, a part of the first side face, and a part of the second side face, and is connected to the first internal electrode layer; a third external electrode disposed on the first side surface, extending from the first side surface to a portion of the first main surface and a portion of the second main surface, and connected to the second internal electrode layer; a fourth external electrode that is disposed on the second side surface, extends from the second side surface, is disposed on a part of the first main surface and a part of the second main surface, and is connected to the second internal electrode layer; the first external electrode has a first base electrode layer disposed on the laminate, a first lower-layer plating layer disposed on the first base electrode layer, and a first upper-layer plating layer disposed on the first lower-layer plating layer, the second external electrode has a second base electrode layer disposed on the laminate, a second lower-layer plating layer disposed on the second base electrode layer, and a second upper-layer plating layer disposed on the second lower-layer plating layer, the third external electrode includes a third base electrode layer disposed on the laminate, a third lower-layer plating layer disposed on the third base electrode layer, and a third upper-layer plating layer disposed on the third lower-layer plating layer excluding the third exposed plating region such that the third lower-layer plating layer has a third exposed plating region exposed on a surface of the third external electrode, the fourth external electrode having a fourth base electrode layer disposed on the laminate, a fourth lower-layer plating layer disposed on the fourth base electrode layer, and a fourth upper-layer plating layer disposed on the fourth lower-layer plating layer excluding the fourth plating exposed region such that the fourth lower-layer plating layer has a fourth plating exposed region exposed on a surface of the fourth external electrode.

5. a first ratio of an area of ​​the first plating exposed region to an area of ​​the exposed region of the first external electrode on the first main surface as viewed in a direction of the first main surface is 0.4% or more and 83.4% or less; 4. The multilayer ceramic electronic component according to claim 1, wherein a second ratio of an area of ​​the second plating exposed region to an area of ​​the exposed region of the second external electrode on the first main surface when viewed in the first main surface direction is 0.4% or more and 83.4% or less.

6. 6. The multilayer ceramic electronic component according to claim 5, wherein the first ratio and the second ratio are not less than 1.17% and not more than 83.4%.

7. 7. The multilayer ceramic electronic component according to claim 6, wherein the first ratio and the second ratio are equal to or greater than 1.40% and equal to or less than 83.4%.

8. 8. The multilayer ceramic electronic component according to claim 7, wherein the first rate and the second rate are equal to or greater than 1.40% and equal to or less than 25.0%.

9. 4. The multilayer ceramic electronic component according to claim 1, wherein the first exposed plating region is disposed on the first main surface.

10. 4. The multilayer ceramic electronic component according to claim 1, wherein the first lower plating layer has a thickness of 2 [mu]m or more and 7 [mu]m or less.

11. 4. The multilayer ceramic electronic component according to claim 1, wherein a portion of said first base electrode layer is exposed at said first main surface.

12. 5. The multilayer ceramic electronic component according to claim 3, wherein a third ratio of an area of ​​the third plating exposed region to an area of ​​the exposed region of the third external electrode on the first main surface when viewed in the first main surface direction and / or a fourth ratio of an area of ​​the fourth plating exposed region to an area of ​​the exposed region of the fourth external electrode on the first main surface when viewed in the first main surface direction is 0.4% or more and 83.4% or less.

13. A multilayer ceramic electronic component according to any one of claims 1 to 3, a mounting substrate on which the multilayer ceramic electronic component is mounted, a mounting structure for a multilayer ceramic electronic component, the first plating exposed region being disposed on the first main surface, and the multilayer ceramic electronic component being mounted such that the second main surface faces the mounting substrate.

14. A multilayer ceramic electronic component according to claim 2 or 3; a mounting substrate on which the multilayer ceramic electronic component is mounted, A mounting structure for a multilayer ceramic electronic component, wherein the first external electrode and the second external electrode are electrodes to which a positive potential is applied.

15. The multilayer ceramic electronic component according to claim 4 ; a mounting substrate on which the multilayer ceramic electronic component is mounted, A mounting structure for a multilayer ceramic electronic component, wherein the third external electrode and the fourth external electrode are electrodes to which a positive potential is applied.