Multilayer ceramic capacitor

Abstract

The present invention addresses the problem of providing an LW reversal type multilayer ceramic capacitor which is capable of suppressing deterioration of a self-alignment effect and achieving a stable mounting.　The present invention provides a multilayer ceramic capacitor 1 wherein if l is the length in the longitudinal direction connecting a first end surface LS1 and a second end surface LS2 of a multilayer body 10, w is the length in the width direction connecting a first lateral surface WS1 and a second lateral surface WS2 of the multilayer body 10, and t is the length in the height direction connecting a first main surface TS1 and a second main surface TS2 of the multilayer body 10, the dimensional relationship w > l > t is satisfied. With respect to this multilayer ceramic capacitor 1, the dimensions in the longitudinal direction L of a fourth surface part 40A4 and a fifth surface part 40A5 of a first external electrode 40A are larger than the dimensions in the longitudinal direction of a second surface part 40A2 and a third surface part of the first external electrode 40A; and the dimensions in the longitudinal direction L of a ninth surface part 40B4 and a tenth surface part 40B5 of a second external electrode 40B are larger than the dimensions in the longitudinal direction L of a seventh surface part 40B2 and an eighth surface part 40B3 of the second external electrode 40B.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Conventionally, multilayer ceramic capacitors have been known. A typical multilayer ceramic capacitor has a laminate body in a substantially rectangular parallelepiped shape, with the length direction L being longer than the width direction W, and external electrodes are provided on both ends of the laminate body in the length direction L. Meanwhile, so-called LW-reversed multilayer ceramic capacitors are also known, in which the magnitude relationship between the length direction L and the width direction W of the laminate body is reversed in order to reduce ESL (see Patent Documents 1 and 2).

[0003] Furthermore, in recent years, as the mounting density of circuit boards has increased, the mounting area for multilayer ceramic capacitors has decreased. Therefore, the PoP (Package on Package) mounting format has been adopted, and there has been an increase in demand for multilayer ceramic capacitors mounted on the bottom edge of a circuit board as an LSC (Land Side Capacitor) type. Multilayer ceramic capacitors mounted as such an LSC (Land Side Capacitor) type require low-profile multilayer ceramic capacitors with a thin height.

[0004] JP 2020-57753 A JP 2020-61524 A

[0005] Patent Document 2 discloses an LW-reversed type multilayer ceramic electronic component in which a recess is provided on the edge of at least one of the fourth and fifth surface portions of the external electrode, recessed from the edge toward the first surface portion, and both side portions of the recess in the third direction form covering portions that cover the ridges of the two surfaces of the component body in the second direction.

[0006] However, in the multilayer ceramic electronic component disclosed in Patent Document 2, variations in the area and shape of the coating covering the ridges of the two surfaces of the component body in the second direction may occur due to variations in the formation position and thickness of the underlying conductor layer and the coated conductor layer formed thereon. When mounting an LW-reversed multilayer ceramic electronic component to a mounting substrate using solder, differences in the area and shape of the coating may cause differences in the wetting of the solder on each surface of the coating, resulting in differences in the way the solder applies tensile stress. This may result in a deterioration of the self-alignment effect. As a result, the multilayer ceramic electronic component may be prone to rotation or tilt, reducing mountability. Furthermore, because the distance between lands on the substrate on which an LW-reversed multilayer ceramic electronic component is mounted is short, the self-alignment effect is reduced. If the multilayer ceramic electronic component rotates significantly, one external electrode may be mounted across lands of opposite polarity, potentially resulting in a short circuit.

[0007] An object of the present invention is to provide an LW-reversed type multilayer ceramic capacitor that can suppress deterioration of the self-alignment effect and enable stable mounting.

[0008] The multilayer ceramic capacitor according to the present invention includes a laminate including a plurality of dielectric layers and a plurality of internal electrode layers alternately stacked in a height direction, and having first and second main surfaces opposing each other in the height direction, a first end face and a second end face opposing each other in a length direction perpendicular to the height direction, and a first side face and a second side face opposing each other in a width direction perpendicular to the height direction and the length direction; first external electrodes having a first surface portion located on the first end face, at least one of a second surface portion located on a portion of the first main surface and a third surface portion located on a portion of the second main surface, a fourth surface portion located on a portion of the first side face, and a fifth surface portion located on a portion of the second side face; a sixth surface portion located on the second end face, a seventh surface portion located on a portion of the first main surface, and a fifth surface portion located on a portion of the second main surface. a second external electrode having at least one of an eighth surface portion located on a portion of the first side surface, a ninth surface portion located on a portion of the first side surface, and a tenth surface portion located on a portion of the second side surface, wherein, when the length in the longitudinal direction connecting the first end surface and the second end surface of the laminate is l, the length in the width direction connecting the first side surface and the second side surface is w, and the length in the height direction connecting the first main surface and the second main surface is t, a dimensional relationship of w>l>t is satisfied, and the lengthwise dimension of the fourth surface portion and the fifth surface portion of the first external electrode is greater than the lengthwise dimension of the second surface portion and the third surface portion, and the lengthwise dimension of the ninth surface portion and the tenth surface portion of the second external electrode is greater than the lengthwise dimension of the seventh surface portion and the eighth surface portion.

[0009] According to the present invention, it is possible to provide an LW-reversed type multilayer ceramic capacitor that can suppress deterioration of the self-alignment effect and enable stable mounting.

[0010] 1 is an external perspective view of a multilayer ceramic capacitor according to an embodiment;

[0023] FIG. 1 is an arrow view of the multilayer ceramic capacitor shown in FIG. 1 when viewed from a first side surface along the direction of arrow II;

[0024] FIG. 1 is an arrow view of the multilayer ceramic capacitor shown in FIG. 1 when viewed from a second side surface along the direction of arrow III;

[0025] FIG. 2 is an arrow view of the multilayer ceramic capacitor shown in FIG. 2 when viewed from a first main surface along the direction of arrow IV;

[0026] FIG. 2 is an arrow view of the multilayer ceramic capacitor shown in FIG. 2 when viewed from a second main surface along the direction of arrow V;

[0027] FIG. 4 is a cross-sectional view taken along line VI-VI of the multilayer ceramic capacitor shown in FIG. 4;

[0028] FIG. 6 is a cross-sectional view taken along line VII-VII of the multilayer ceramic capacitor shown in FIG. 6;

[0029] FIG. 7 is a cross-sectional view taken along line VIIIA-VIIIA of the multilayer ceramic capacitor shown in FIG. 6, illustrating a first internal electrode layer;

[0029] FIG. 8 is a cross-sectional view taken along line VIIIB-VIIIB of the multilayer ceramic capacitor shown in FIG. 6, illustrating a second internal electrode layer;

[0029] FIG. 9 is a cross-sectional view taken along line IX-IX of the multilayer ceramic capacitor shown in FIG. 4, illustrating a first side surface of a laminate;

[0029] FIG. 10 is an enlarged view of portion XA in FIG. 6, illustrating a cross section of a first external electrode. 10B 。 FIG. 10C is an enlarged view of a portion XB in FIG. 6 , showing a cross section of a second external electrode. FIG. 10D is a cross section showing a modified example of the layer structure of the external electrodes of the multilayer ceramic capacitor of the embodiment, corresponding to FIG. 10A . FIG. 10E is a cross section showing a modified example of the layer structure of the external electrodes of the multilayer ceramic capacitor of the embodiment, corresponding to FIG. 10B . FIG. 10F is a cross section showing a state during a manufacturing process of the multilayer ceramic capacitor of the embodiment. FIG. 10G is a cross section showing a modified example of the arrangement position of the external electrodes of the multilayer ceramic capacitor of the embodiment, corresponding to FIG. 1 . FIG. 1C is an external perspective view of a multilayer ceramic capacitor of Comparative Example 1, corresponding to FIG. 1 . FIG. 1D is a view showing a first internal electrode layer of the multilayer ceramic capacitor of the comparative example, corresponding to FIG. 8A . FIG. 1D is a view showing a second internal electrode layer of the multilayer ceramic capacitor of the comparative example, corresponding to FIG. 8B . FIG. 1C is an external perspective view of a multilayer ceramic capacitor of Comparative Example 2, corresponding to FIG. 1 .8B is a diagram showing a first internal electrode layer of the multilayer ceramic capacitor of the comparative example, and corresponds to FIG. 8A. FIG. 8C is a diagram showing a second internal electrode layer of the multilayer ceramic capacitor of the comparative example, and corresponds to FIG. 8B. FIG. 8D is a diagram for explaining a method for evaluating mountability in an experimental example. FIG. 8E is a diagram for explaining a method for evaluating mountability in an experimental example. FIG. 8F is a diagram for explaining a method for evaluating mountability in an experimental example. FIG. 8G is a diagram for explaining a method for evaluating mountability in an experimental example.

[0011] A multilayer ceramic capacitor 1 according to an embodiment of the present disclosure will now be described. FIG. 1 is an external perspective view of the multilayer ceramic capacitor 1 of this embodiment. FIG. 2 is a view of the multilayer ceramic capacitor 1 shown in FIG. 1 as viewed from the first side surface WS1 side along the direction of arrow II. FIG. 3 is a view of the multilayer ceramic capacitor 1 shown in FIG. 1 as viewed from the second side surface WS2 side along the direction of arrow III. FIG. 4 is a view of the multilayer ceramic capacitor 1 shown in FIG. 2 as viewed from the first main surface TS1 side along the direction of arrow IV. FIG. 5 is a view of the multilayer ceramic capacitor 1 shown in FIG. 2 as viewed from the second main surface TS2 side along the direction of arrow V. FIG. 6 is a cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 4 taken along line VI-VI. FIG. 7 is a cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 6 taken along line VII-VII. FIG. 8A is a cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 6 taken along line VIIIA-VIIIA. Fig. 8B is a cross-sectional view taken along line VIIIB-VIIIB of the multilayer ceramic capacitor 1 shown in Fig. 6. Fig. 9 is a cross-sectional view taken along line IX-IX of the multilayer ceramic capacitor 1 shown in Fig. 4, showing the first side surface WS1 of the laminate 10. Fig. 10A is an enlarged view of portion XA in Fig. 6, showing a cross-section of the first external electrode 40A. Fig. 10B is an enlarged view of portion XB in Fig. 6, showing a cross-section of the second external electrode 40B.

[0012] The multilayer ceramic capacitor 1 includes a laminate 10 and external electrodes 40 .

[0013] 1 to 9 show an XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The height direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in FIG. 6 is also referred to as the LT cross section. The cross section shown in FIG. 7 is also referred to as the WT cross section. The cross sections shown in FIGS. 8A and 8B are also referred to as the LW cross sections.

[0014] As shown in Figures 1 to 5, the laminate 10 includes a first main surface TS1 and a second main surface TS2 that face each other in a height direction T, a first end surface LS1 and a second end surface LS2 that face each other in a length direction L that is perpendicular to the height direction T, and a first side surface WS1 and a second side surface WS2 that face each other in a width direction W that is perpendicular to the height direction T and the length direction L.

[0015] The laminate 10 has a substantially rectangular parallelepiped shape. The corners and ridges of the laminate 10 are preferably rounded. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect. Note that unevenness may be formed on part or all of the surfaces constituting the laminate 10.

[0016] As shown in Figures 6 and 7, the laminate 10 has an inner layer portion 11, and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged to sandwich the inner layer portion 11 in the height direction T.

[0017] The inner layer portion 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30. The inner layer portion 11 includes, in the height direction T, the internal electrode layer 30 located closest to the first main surface TS1 to the internal electrode layer 30 located closest to the second main surface TS2. In the inner layer portion 11, the multiple internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The inner layer portion 11 is a portion that generates electrostatic capacitance and essentially functions as a capacitor. The inner layer portion 11 is also referred to as an effective layer portion.

[0018] The plurality of dielectric layers 20 are made of a dielectric material, such as a ceramic material, for example, BaTiO ３, CaTiO ３ , SrTiO ３ , or CaZrO ３ When these components are the main components, sub-components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may be added in amounts less than the main components depending on the desired properties of the laminate.

[0019] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 10 μm or less. The number of laminated dielectric layers 20 is preferably 15 to 700. Note that this number of dielectric layers 20 is the total number of the dielectric layers in the inner layer portion 11 and the dielectric layers in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0020] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The first internal electrode layers 31 are disposed on the multiple dielectric layers 20 and extend to the first end face LS1. The second internal electrode layers 32 are disposed on the multiple dielectric layers 20 and extend to the second end face LS2. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are alternately disposed in the height direction T of the laminate 10, with the dielectric layers 20 interposed between them. The first internal electrode layers 31 and the second internal electrode layers 32 are disposed so as to sandwich the dielectric layers 20 therebetween.

[0021] 8A , the first internal electrode layer 31 has a first opposing electrode portion 31A facing the second internal electrode layer 32, and a first lead portion 31B extending from the first opposing electrode portion 31A to the first end face LS1, a portion of the first side face WS1, and a portion of the second side face WS2. The first opposing electrode portion 31A is located inside the laminate 10. The first lead portion 31B is connected to the first opposing electrode portion 31A and exposed to the first end face LS1, a portion of the first side face WS1, and a portion of the second side face WS2.

[0022] This ensures the width of the first lead portion 31B of the first internal electrode layer 31, thereby increasing the connection area between the first lead portion 31B and the first external electrode 40A and thereby increasing the current path. As a result, the ESL can be reduced. Furthermore, because the first lead portion 31B of the first internal electrode layer 31 extends to a portion of the first side surface WS1 and the second side surface WS2 of the laminate 10, the distance between the first lead portion 31B and the second lead portion 32B (described later) of the second internal electrode layer 32 can be shortened, thereby further reducing the ESL.

[0023] 8B , the second internal electrode layer 32 has a second opposing electrode portion 32A facing the first internal electrode layer 31, and a second lead portion 32B extending from the second opposing electrode portion 32A to the second end face LS2, a portion of the first side face WS1, and a portion of the second side face WS2. The second opposing electrode portion 32A is located inside the laminate 10. The second lead portion 32B is connected to the second opposing electrode portion 32A and exposed to the second end face LS2, a portion of the first side face WS1, and a portion of the second side face WS2.

[0024] This ensures the width of the second lead portion 32B of the second internal electrode layer 32, thereby increasing the connection area between the second lead portion 32B and the second external electrode 40B and thereby enlarging the current path. As a result, the ESL can be reduced. Furthermore, because the second lead portion 32B of the second internal electrode layer 32 extends to a portion of the first side surface WS1 and the second side surface WS2 of the laminate 10, the distance between the second lead portion 32B and the first lead portion 31B of the first internal electrode layer 31 can be shortened, thereby further reducing the ESL.

[0025] Fig. 9 is a cross-sectional view taken along line IX-IX of the multilayer ceramic capacitor 1 shown in Fig. 4, showing the first side surface WS1 of the laminate 10. Note that line IX-IX indicating the position of the cross-sectional view of Fig. 9 is also shown in Fig. 8A and Fig. 8B. As shown in Fig. 9, the first lead portion 31B of the first internal electrode layer 31 and the second lead portion 32B of the second internal electrode layer 32 are exposed on the first side surface WS1 of the laminate 10.

[0026] As shown in Figure 9, the length direction L dimensions of the multiple first extraction portions 31B arranged in the height direction T are all larger than the length direction L dimensions of the second surface portion 40A2 and the third surface portion 40A3 of the first external electrode 40A, which will be described later.

[0027] On the other hand, the same is true for the multiple second draw-out portions 32B of the second internal electrode layer 32 that are arranged in the height direction T, and the dimensions in the length direction L of these multiple second draw-out portions 32B are all larger than the dimensions in the length direction L of the seventh surface portion 40B2 and the eighth surface portion 40B3 of the second external electrode 40B, which will be described later.

[0028] Although not shown, similarly to the first side surface WS1 side, the first lead portion 31B of the first internal electrode layer 31 and the second lead portion 32B of the second internal electrode layer 32 are exposed on the second side surface WS2 side. As with the first side surface WS1 side, the dimensions in the length direction L of the plurality of first lead portions 31B on the second side surface WS2 side are all larger than the dimensions in the length direction L of the second surface portion 40A2 and the third surface portion 40A3 of the first external electrode 40A. Furthermore, the dimensions in the length direction L of the plurality of second lead portions 31B are all larger than the dimensions in the length direction L of the seventh surface portion 40B2 and the eighth surface portion 40B3 of the second external electrode 40B.

[0029] The length L of the portions of the first lead portion 31B and the second lead portion 32B exposed on the first side surface WS1 is preferably 30 μm or more and 230 μm or less. The length L of the portions of the first lead portion 31B and the second lead portion 32B exposed on the second side surface WS2 is preferably 30 μm or more and 230 μm or less. The dimensions of each lead portion exposed on the side surface of the laminate 10 may be approximately equal.

[0030] This makes it possible to realize the shapes of the first external electrode 40A and ninth surface portion 40B4 having the fourth surface portion 40A4 and the fifth surface portion 40A5, and the shape of the second external electrode 40B having the tenth surface portion 40B5, which will be described later. Furthermore, since the distance between the first lead portion 31B of the first internal electrode layer 31 and the second lead portion 32B of the second internal electrode layer 32 can be shortened, it is possible to shorten the path through which current flows. Consequently, the ESL can be reduced.

[0031] In this embodiment, the first opposing electrode portion 31A and the second opposing electrode portion 32A face each other via the dielectric layer 20, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0032] The shapes of the first opposing electrode portion 31A and the second opposing electrode portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or may be oblique.

[0033] The shapes of the first drawer portion 31B and the second drawer portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangle may be rounded or angled. In this embodiment, the first drawer portion 31B and the second drawer portion 32B are substantially T-shaped with some of the corners of the rectangle removed.

[0034] The width W of the portion of the first lead portion 31B exposed at the first end surface LS1 is larger than the width W of the first opposing electrode portion 31A. The width W of the portion of the second lead portion 32B exposed at the second end surface LS2 is larger than the width W of the second opposing electrode portion 32A.

[0035] The first internal electrode layer 31 and the second internal electrode layer 32 are made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0036] The thickness of each of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably, for example, about 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 15 or more and 200 or less.

[0037] The first main surface side outer layer portion 12 is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer portion 12 is an assembly of a plurality of dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. That is, the first main surface side outer layer portion 12 is formed from a plurality of dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 located closest to the first main surface TS1 side among the plurality of internal electrode layers 30. The dielectric layer 20 used in the first main surface side outer layer portion 12 may be the same as the dielectric layer 20 used in the internal layer portion 11.

[0038] The second main surface side outer layer portion 13 is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer portion 13 is an aggregate of a plurality of dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. That is, the second main surface side outer layer portion 13 is formed from a plurality of dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 located closest to the second main surface TS2 among the plurality of internal electrode layers 30. The dielectric layer 20 used in the second main surface side outer layer portion 13 may be the same as the dielectric layer 20 used in the internal layer portion 11.

[0039] As described above, the laminate 10 has a plurality of laminated dielectric layers 20 and a plurality of internal electrode layers 30 laminated on the dielectric layers 20. That is, the multilayer ceramic capacitor 1 has the laminate 10 in which the dielectric layers 20 and the internal electrode layers 30 are alternately laminated.

[0040] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is a portion where the first counter electrode portion 31A of the first internal electrode layer 31 and the second counter electrode portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as a part of the inner layer portion 11. Figures 8A and 8B show the range of the counter electrode portion 11E in the width direction W and length direction L. The counter electrode portion 11E is also referred to as the effective portion of the capacitor.

[0041] The laminate 10 has an end surface side outer layer portion. The end surface side outer layer portion includes a first end surface side outer layer portion LG1 located on the first end surface LS1 side and a second end surface side outer layer portion LG2 located on the second end surface LS2 side. The first end surface side outer layer portion LG1 is a portion including the dielectric layer 20 and the first lead portion 31B located between the counter electrode portion 11E and the first end surface LS1. In other words, the first end surface side outer layer portion LG1 is an aggregate of the portions of the multiple dielectric layers 20 on the first end surface LS1 side and the multiple first lead portions 31B. The second end surface side outer layer portion LG2 is a portion including the dielectric layer 20 and the second lead portion 32B located between the counter electrode portion 11E and the second end surface LS2. That is, the second end surface side outer layer portion LG2 is an aggregate of the portions of the plurality of dielectric layers 20 on the second end surface LS2 side and the plurality of second lead portions 32B. Figures 6, 8A, and 8B show the ranges of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 in the length direction L. The first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 are also referred to as L gaps or end gaps.

[0042] The laminate 10 has a side surface side outer layer portion. The side surface side outer layer portion has a first side surface side outer layer portion WG1 located on the first side surface WS1 side and a second side surface side outer layer portion WG2 located on the second side surface WS2 side. The first side surface side outer layer portion WG1 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the first side surface WS1. In other words, the first side surface side outer layer portion WG1 is an aggregate of portions of the multiple dielectric layers 20 on the first side surface WS1 side. The second side surface side outer layer portion WG2 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the second side surface WS2. In other words, the second side surface side outer layer portion WG2 is an aggregate of portions of the multiple dielectric layers 20 on the second side surface WS2 side. 7, 8A, and 8B show the ranges of the first and second side surface outer layer portions WG1 and WG2 in the width direction W. The first and second side surface outer layer portions WG1 and WG2 are also referred to as W gaps or side gaps.

[0043] 6 to 8B , when the length in the longitudinal direction L connecting the first end face LS1 and the second end face LS2 of the laminate 10 is l, the length in the width direction W connecting the first side face WS1 and the second side face WS2 is w, and the length in the height direction T connecting the first main face TS1 and the second main face TS2 is t, the dimensional relationship between these is w>l>t. This makes it possible to increase the width of the lead-out portion at the end face of the internal electrode layer 30. Furthermore, since the distance between the first external electrode 40A and the second external electrode 40B can be shortened, the ESL of the multilayer ceramic capacitor 1 can be reduced.

[0044] The length l in the length direction L connecting the first end surface LS1 and the second end surface LS2 of the laminate 10 is preferably 0.05 mm or more and 0.7 mm or less. The length w in the width direction W connecting the first side surface WS1 and the second side surface WS2 of the laminate 10 is preferably 0.15 mm or more and 1.5 mm or less. The length t in the height direction T connecting the first main surface TS1 and the second main surface TS2 of the laminate 10 is preferably 150 μm or less. This enables high-density packaging. The length t in the height direction T connecting the first main surface TS1 and the second main surface TS2 of the laminate 10 is preferably 100 μm or less, and more preferably 50 μm or less. This enables higher-density packaging.

[0045] The dimensions l, w, and t of the laminate 10 are measured by the following method.

[0046] First, the w dimension of the laminate 10 is measured. Specifically, the w dimension of the laminate 10 is measured with a micrometer at the center position in the length direction L of the laminate ceramic capacitor 1, that is, at a position L / 2 of the laminate ceramic capacitor 1.

[0047] Next, the l dimension and t dimension of the laminate 10 are measured. First, a multilayer ceramic capacitor 1 identical to the multilayer ceramic capacitor 1 whose w dimension has been measured is polished to the center position in the width direction W of the multilayer ceramic capacitor 1, i.e., to a position W / 2 of the multilayer ceramic capacitor 1, so as to be parallel to the LT plane. The LT cross section exposed by polishing is then observed using a microscope. The l dimension of the laminate 10 is measured using a microscope at the center position in the height direction T of the laminate 10, i.e., at a position t / 2 of the laminate 10. The t dimension of the laminate 10 is measured using a microscope at the center position in the length direction L of the laminate 10, i.e., at a position l / 2 of the laminate 10.

[0048] The external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side and a second external electrode 40B arranged on the second end face LS2 side.

[0049] The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A of this embodiment has a first surface portion 40A1 located on the first end face LS1, a second surface portion 40A2 located on a portion of the first main surface TS1, a third surface portion 40A3 located on a portion of the second main surface TS2, a fourth surface portion 40A4 located on a portion of the first side surface WS1, and a fifth surface portion 40A5 located on a portion of the second side surface WS2. It is preferable that the first external electrode 40A has at least one of a second surface portion 40A2 located on a portion of the first main surface TS1 and a third surface portion 40A3 located on a portion of the second main surface TS2, a first surface portion 40A1 located on the first end face LS1, a fourth surface portion 40A4 located on a portion of the first side surface WS1, and a fifth surface portion 40A5 located on a portion of the second side surface WS2.

[0050] The first surface portion 40A1 covers the entire first end face LS1 and is the portion connected to the first internal electrode layer 31. Either the second surface portion 40A2 or the third surface portion 40A3 is the portion connected to a land of the mounting substrate.

[0051] The fourth surface 40A4 is connected to the first lead portion 31B exposed on the first side surface WS1. As shown in FIGS. 2, 4, and 5, the dimension L4 of the fourth surface 40A4 in the longitudinal direction L is greater than the dimension L2 of the second surface 40A2 in the longitudinal direction L. The dimension L4 of the fourth surface 40A4 in the longitudinal direction L is also greater than the dimension L3 of the third surface 40A3 in the longitudinal direction L. That is, the longitudinal center side of the fourth surface 40A4 protrudes toward the longitudinal center more than the end 40A2a of the second surface 40A2 and more than the end 40A3a of the third surface 40A3.

[0052] The fifth surface 40A5 is connected to the first lead portion 31B exposed on the second side surface WS2. As shown in FIGS. 3 to 5, the dimension L5 of the fifth surface 40A5 in the longitudinal direction L is greater than the dimension L2 of the second surface 40A2 in the longitudinal direction L. Furthermore, the dimension L5 of the fifth surface 40A5 in the longitudinal direction L is greater than the dimension L3 of the third surface 40A3 in the longitudinal direction L. That is, the longitudinal center side of the fifth surface 40A5 protrudes toward the longitudinal center more than the end 40A2a of the second surface 40A2, and also protrudes toward the longitudinal center more than the end 40A3a of the third surface 40A3.

[0053] It is preferable that the dimension L4 in the length direction L of the fourth surface portion 40A4 of the first external electrode 40A and the dimension L5 in the length direction L of the fifth surface portion 40A5 are 110% or more and 245% or less of the dimension L2 in the length direction L of the second surface portion 40A2 and the dimension L3 in the length direction L of the third surface portion 40A3.

[0054] The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B of this embodiment has a sixth surface 40B1 located on the second end surface LS2, a seventh surface 40B2 located on a portion of the first main surface TS1, an eighth surface 40B3 located on a portion of the second main surface TS2, a ninth surface 40B4 located on a portion of the first side surface WS1, and a tenth surface 40B5 located on a portion of the second side surface WS2. It is preferable that the second external electrode 40B has at least one of a seventh surface portion 40B2 located on a portion of the first main surface TS1 and an eighth surface portion 40B3 located on a portion of the second main surface TS2, the first external electrode 40A, a sixth surface portion 40B1 located on the second end surface LS2, a ninth surface portion 40B4 located on a portion of the first side surface WS1, and a tenth surface portion 40B5 located on a portion of the second side surface WS2.

[0055] The sixth surface portion 40B1 covers the entire second end surface LS2 and is the portion connected to the second internal electrode layer 32. Either the seventh surface portion 40B2 or the eighth surface portion 40B3 is the portion connected to a land of the mounting substrate.

[0056] The ninth surface 40B4 is connected to the second lead portion 32B exposed on the first side surface WS1. As shown in FIGS. 2, 4, and 5, the dimension L9 of the ninth surface 40B4 in the longitudinal direction L is greater than the dimension L7 of the seventh surface 40B2 in the longitudinal direction L. Furthermore, the dimension L9 of the ninth surface 40B4 in the longitudinal direction L is greater than the dimension L8 of the eighth surface 40B3 in the longitudinal direction L. That is, the longitudinal center side of the ninth surface 40B4 protrudes toward the longitudinal center more than the end 40B2a of the seventh surface 40B2 and more than the end 40B3a of the eighth surface 40B3.

[0057] The tenth surface 40B5 is connected to the second lead portion 32B exposed on the second side surface WS2. As shown in FIGS. 3 to 5, the dimension L10 of the tenth surface 40B5 in the length direction L is greater than the dimension L7 of the seventh surface 40B2 in the length direction L. The dimension L10 of the tenth surface 40B5 in the length direction L is also greater than the dimension L8 of the eighth surface 40B3 in the length direction L. In other words, the center of the length direction of the tenth surface 40B5 protrudes toward the center of the length direction more than the end 40B2a of the seventh surface 40B2, and more than the end 40B3a of the eighth surface 40B3.

[0058] It is preferable that the dimension L9 in the length direction L of the ninth surface portion 40B4 of the second external electrode 40B and the dimension L10 in the length direction L of the tenth surface portion 40B5 are 110% or more and 245% or less of the dimension L7 in the length direction L of the seventh surface portion 40B2 and the dimension L8 in the length direction L of the eighth surface portion 40B3.

[0059] The dimensions in the length direction L of the second surface portion 40A2 and the third surface portion 40A3 of the first external electrode 40A and the seventh surface portion 40B2 and the eighth surface portion 40B3 of the second external electrode 40B, which are the surfaces on the main surface side, and the dimensions in the length direction L of the fourth surface portion 40A4 and the fifth surface portion 40A5 of the first external electrode 40A and the ninth surface portion 40B4 and the tenth surface portion 40B5 of the second external electrode 40B, which are the surfaces on the side surface side, are measured using the following method.

[0060] The dimensions in the length direction L of the second surface portion 40A2 and the seventh surface portion 40B2 are measured with a microscope at a position halfway in the width direction W when observed from the first main surface TS1 of the laminate 10. Similarly, the dimensions in the length direction L of the third surface portion 40A3 and the eighth surface portion 40B3 are measured with a microscope at a position halfway in the width direction W when observed from the second main surface TS2 of the laminate 10.

[0061] The dimensions in the length direction L of the fourth surface portion 40A4 and the ninth surface portion 40B4 are measured with a microscope at a position halfway in the height direction T when observed from the first side surface WS1 of the laminate 10. Similarly, the dimensions in the length direction L of the fifth surface portion 40A5 and the tenth surface portion 40B5 are measured with a microscope at a position halfway in the height direction T when observed from the second side surface WS2 of the laminate 10.

[0062] From the dimension in the length direction L of the surface portion on the main surface side and the dimension in the length direction L of the surface portion on the side surface side measured in this manner, the ratio of the dimension in the length direction L of the surface portion on the side surface side to the dimension in the length direction L of the surface portion on the main surface side can be determined.

[0063] 10A , the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. The first base electrode layer 50A is disposed on the surface of the laminate 10. The first plating layer 60A is disposed so as to cover the first base electrode layer 50A.

[0064] 10B , the second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B. The second base electrode layer 50B is disposed on the surface of the laminate 10. The second plating layer 60B is disposed so as to cover the second base electrode layer 50B.

[0065] The first underlying electrode layer 50A and the second underlying electrode layer 50B include at least one selected from a baked layer, a thin film layer, and the like.

[0066] In this embodiment, the first underlying electrode layer 50A and the second underlying electrode layer 50B are thin film layers, which are layers on which metal particles are deposited.

[0067] When the first and second underlying electrode layers 50A and 50B are formed as thin film layers, they are preferably formed by a thin film formation method such as sputtering or vapor deposition. Here, a sputtered electrode formed by sputtering will be described.

[0068] In this embodiment, the first base electrode layer 50A is composed of a first thin film layer 51A formed by a sputtered electrode. The second base electrode layer 50B is composed of a second thin film layer 51B formed by a sputtered electrode. When the base electrode layer is formed by a sputtered electrode, it is preferable to form the sputtered electrode directly on the first main surface TS1 and the second main surface TS2 of the laminate 10.

[0069] 6 and 10A, the first thin film layer 51A formed of a sputtered electrode is disposed on a portion of the first main surface TS1 on the first end face LS1 side and on a portion of the second main surface TS2 on the first end face LS1 side. Specifically, the first thin film layer 51A is preferably disposed on the first main surface TS1 in a portion covered by the first external electrode 40A shown in FIG. 4. The first thin film layer 51A is preferably disposed on the second main surface TS2 in a portion covered by the first external electrode 40A shown in FIG. 5.

[0070] 9, the first thin film layer 51A is preferably disposed on a portion of the first main surface TS1 and a portion of the first side surface WS1 that is continuous with the first main surface TS1. The first thin film layer 51A is preferably disposed on a portion of the second main surface TS2 and a portion of the second main surface TS2 that is continuous with the second main surface TS2 and a portion of the first side surface WS1 that is continuous with the second main surface TS2.

[0071] Although not shown, similarly to the first side surface WS1, the first thin film layer 51A is preferably disposed on the second side surface WS2 as well, extending from a portion of the first main surface TS1 to a portion of the second side surface WS2. The first thin film layer 51A is preferably disposed on a portion of the second main surface TS2 to a portion of the second main surface TS2 to a portion of the second side surface WS2.

[0072] For example, when a chamfered portion such as a rounded portion is formed on the ridge line portion of the laminate 10, the first thin film layer 51A is preferably disposed on a portion of the first main surface TS1 on the first end face LS1 side, and on the chamfered portion on the first side face WS1 side and the chamfered portion on the second side face WS2 side that are continuous with that portion. The first thin film layer 51A is preferably disposed on a portion of the second main surface TS2 on the first end face LS1 side, and on the chamfered portion on the first side face WS1 side and the chamfered portion on the second side face WS2 side that are continuous with that portion. This facilitates the formation of the thin film layer by a method such as sputtering.

[0073] The longitudinal center side of the first lead portion 31B protrudes more toward the longitudinal center than the longitudinal center end of the first thin film layer 51A disposed on the first main surface TS1 and the longitudinal center end of the first thin film layer 51A disposed on the second main surface TS2. Similarly, the longitudinal center side of the second lead portion 32B protrudes more toward the longitudinal center than the longitudinal center end of the second thin film layer 51B disposed on the first main surface TS1 and the longitudinal center end of the second thin film layer 51B disposed on the second main surface TS2.

[0074] By the above method, when forming a plating layer, it is possible to control the distance between the first thin film layer 51A arranged on a part of the first side surface WS1 and a part of the second side surface WS2 and the internal electrode layer 30 exposed on the first side surface WS1 and the second side surface WS2. Therefore, it becomes easy to deposit a plating layer also on the surface of the laminate 10 between the first thin film layer 51A arranged on a part of the first side surface WS1 and a part of the second side surface WS2 and the internal electrode layer 30 exposed on the first side surface WS1 and the second side surface WS2.

[0075] 6 and 10B, the second thin film layer 51B formed of a sputtered electrode is disposed on a portion of the first main surface TS1 facing the second end face LS2 and on a portion of the second main surface TS2 facing the second end face LS2. Specifically, the second thin film layer 51B is preferably disposed on the first main surface TS1 in a portion covered by the second external electrode 40B shown in FIG. 4. The second thin film layer 51B is preferably disposed on the second main surface TS2 in a portion covered by the second external electrode 40B shown in FIG. 5.

[0076] 9, the second thin film layer 51B is preferably disposed on a portion of the first main surface TS1 and a portion of the first side surface WS1, continuing from that portion. The second thin film layer 51B is preferably disposed on a portion of the second main surface TS2 and a portion of the second main surface TS2, continuing from that portion to a portion of the first side surface WS1, continuing from that portion.

[0077] Although not shown, similarly to the first side surface WS1, the second thin film layer 51B is preferably disposed on the second side surface WS2 as well, extending from a portion of the first main surface TS1 to a portion of the second side surface WS2. The second thin film layer 51B is preferably disposed on a portion of the second main surface TS2 as well as from a portion of the second main surface TS2 to a portion of the second side surface WS2.

[0078] For example, when a chamfered portion such as a rounded portion is formed on the ridge line portion of the laminate 10, the second thin film layer 51B is preferably disposed on a portion of the first main surface TS1 on the second end face LS2 side, and on the chamfered portion on the first side face WS1 side and the chamfered portion on the second side face WS2 side that are continuous with that portion. The second thin film layer 51B is preferably disposed on a portion of the second main surface TS2 on the second end face LS2 side, and on the chamfered portion on the first side face WS1 side and the chamfered portion on the second side face WS2 side that are continuous with that portion. This facilitates the formation of the thin film layer by a method such as sputtering.

[0079] By the above method, when forming a plating layer, it is possible to control the distance between the second thin film layer 51B arranged on a part of the first side surface WS1 and a part of the second side surface WS2 and the internal electrode layer 30 exposed on the first side surface WS1 and the second side surface WS2. Therefore, it becomes easy to deposit a plating layer also on the surface of the laminate 10 between the second thin film layer 51B arranged on a part of the first side surface WS1 and a part of the second side surface WS2 and the internal electrode layer 30 exposed on the first side surface WS1 and the second side surface WS2.

[0080] The thin film layer formed by the sputtered electrode preferably contains at least one metal selected from the group consisting of Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo, and V. This increases the adhesive strength of the external electrode 40 to the laminate 10. The thin film layer may be a single layer or may be formed of multiple layers. For example, it may be formed of a two-layer structure consisting of a layer of Ni—Cr alloy and a layer of Ni—Cu alloy.

[0081] The thickness of the sputtered electrode in the stacking direction connecting the first main surface TS1 and the second main surface TS2 is preferably 50 nm or more and 400 nm or less, and more preferably 50 nm or more and 130 nm or less.

[0082] When forming sputtered electrodes directly on the first main surface TS1 and the second main surface TS2 of the laminate 10 to provide base electrode layers, it is preferable to form baked base electrode layers on the first end surface LS1 and the second end surface LS2, or to form plating layers (described later) directly without forming base electrode layers. In this embodiment, plating layers (described later) are formed directly on the first end surface LS1 and the second end surface LS2 without forming base electrode layers.

[0083] As will be described later in a modified example, the first base electrode layer 50A and the second base electrode layer 50B may be baked layers. The baked layer preferably contains a metal component and either a glass component or a ceramic component, or both. The metal component includes, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The glass component includes, for example, at least one selected from B, Si, Ba, Mg, Al, Li, etc. The ceramic component may be the same type of ceramic material as that of the dielectric layer 20, or a different type of ceramic material. The ceramic component may be, for example, BaTiO ３ , CaTiO ３ , (Ba,Ca)TiO ３ , SrTiO ３ , CaZrO ３ It includes at least one selected from the following:

[0084] The baked layer is formed by, for example, applying and baking a conductive paste containing glass and metal to the laminate 10. The baked layer may be formed by simultaneously firing a laminated chip having an internal electrode layer and a dielectric layer with a conductive paste applied to the laminated chip, or by simultaneously firing a laminated chip having an internal electrode layer and a dielectric layer to obtain the laminate 10 and then applying and baking a conductive paste to the laminate 10. When simultaneously firing a laminated chip having an internal electrode layer and a dielectric layer with a conductive paste applied to the laminated chip, the baked layer is preferably formed by adding a ceramic material instead of a glass component and baking it. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may be a multi-layered layer.

[0085] Alternatively, a configuration may be adopted in which the first plating layer 60A and the second plating layer 60B described below are disposed directly on the laminate 10 without providing the first base electrode layer 50A and the second base electrode layer 50B.

[0086] The first plating layer 60A is disposed so as to cover the first base electrode layer 50A.

[0087] The second plating layer 60B is disposed so as to cover the second base electrode layer 50B.

[0088] The first plating layer 60A and the second plating layer 60B may contain, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed of multiple layers.

[0089] When the base electrode layer is formed as a thin film layer, the plating layer preferably has a three-layer structure including a Cu plating layer as a lower plating layer, a Ni plating layer as a middle plating layer, and a Sn plating layer as an upper plating layer. That is, the first plating layer 60A preferably has a first Cu plating layer 61A, a first Ni plating layer 62A, and a first Sn plating layer 63A. The second plating layer 60B preferably has a second Cu plating layer 61B, a second Ni plating layer 62B, and a second Sn plating layer 63B. However, the first plating layer 60A and the second plating layer 60B are not limited to a three-layer structure and may have other layer configurations.

[0090] The first Cu plating layer 61A is arranged so as to cover the first end face LS1 of the laminate 10 and the first thin film layer 51A serving as the first base electrode layer 50A arranged on the first main surface TS1 and the second main surface TS2 of the laminate 10. In this embodiment, the first Cu plating layer 61A is further arranged so as to cover the portions of the first side surface WS1 and the second side surface WS2 of the laminate 10 where the internal electrode layer 30 is exposed. At this time, since the gaps between the first thin film layer 51A and the internal electrode layer 30 exposed on the surface of the laminate 10 and the gaps between the multiple internal electrode layers 30 exposed on the surface of the laminate 10 are narrow, the plating layer is also deposited in the regions of these gaps.

[0091] The first Ni plating layer 62A is disposed so as to cover the first Cu plating layer 61 A. The first Sn plating layer 63A is disposed so as to cover the first Ni plating layer 62 A. In this embodiment, the first plating layer 60A is directly electrically connected to the first internal electrode layer 31.

[0092] The second Cu plating layer 61B is arranged so as to cover the second end face LS2 of the laminate 10 and the second thin film layer 51B serving as the second base electrode layer 50B arranged on the first main surface TS1 and the second main surface TS2 of the laminate 10. In this embodiment, the second Cu plating layer 61B is further arranged so as to cover the portions of the first side surface WS1 and the second side surface WS2 of the laminate 10 where the internal electrode layer 30 is exposed. At this time, since the gaps between the second thin film layer 51B and the internal electrode layer 30 exposed on the surface of the laminate 10 and the gaps between the multiple internal electrode layers 30 exposed on the surface of the laminate 10 are narrow, the plating layer is also deposited in the regions of these gaps.

[0093] The second Ni plating layer 62B is disposed so as to cover the second Cu plating layer 61 B. The second Sn plating layer 63B is disposed so as to cover the second Ni plating layer 62 B. In this embodiment, the second plating layer 60B is directly electrically connected to the second internal electrode layer 32.

[0094] By providing a plating layer consisting of a Cu plating layer and a Ni plating layer so as to cover the base electrode layer, the base electrode layer is prevented from being eroded by solder when mounting the multilayer ceramic capacitor 1. Furthermore, by providing an Sn plating layer on the surface of the Ni plating layer, the wettability of the solder when mounting the multilayer ceramic capacitor 1 is improved, thereby making it possible to easily mount the multilayer ceramic capacitor 1.

[0095] The thickness of each plating layer is preferably 2 μm or more and 15 μm or less. That is, the average thickness of each of the first Cu plating layer 61A, the first Ni plating layer 62A, the first Sn plating layer 63A, the second Cu plating layer 61B, the second Ni plating layer 62B, and the second Sn plating layer 63B is preferably 2 μm or more and 15 μm or less. More specifically, the average thickness of each of the first Cu plating layer 61A and the second Cu plating layer 61B is more preferably 5 μm or more and 8 μm or less. Furthermore, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is more preferably 2 μm or more and 4 μm or less.

[0096] The lengthwise dimension connecting the first end face LS1 and the second end face LS2 of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrodes 40 is defined as L, and the L dimension is preferably 0.1 mm or more and 0.8 mm or less. The widthwise dimension connecting the first side face WS1 and the second side face WS2 of the multilayer ceramic capacitor 1 is defined as W, and the W dimension is preferably 0.2 mm or more and 1.6 mm or less. The heightwise dimension connecting the first main face TS1 and the second main face TS2 of the multilayer ceramic capacitor 1 is defined as T, and the T dimension is preferably 0.05 mm or more and 0.2 mm or less. The lengthwise dimension L of the multilayer ceramic capacitor 1 of this embodiment is smaller than the widthwise dimension W of the multilayer ceramic capacitor 1. In this embodiment, the heightwise direction connecting the first main face TS1 and the second main face TS2 of the multilayer ceramic capacitor 1 is the stacking direction of the dielectric layers 20 and the internal electrode layers 30.

[0097] As described above, in the multilayer ceramic capacitor 1 of this embodiment, when the length in the length direction L connecting the first end face LS1 and the second end face LS2 of the laminate 10 is l, the length in the width direction W connecting the first side face WS1 and the second side face WS2 is w, and the length in the height direction T connecting the first main face TS1 and the second main face TS2 is t, the dimensional relationship is w>l>t. This makes it possible to increase the width of the lead-out portion at the end face of the internal electrode layer 30. Furthermore, since the distance between the first external electrode 40A and the second external electrode 40B can be shortened, the ESL of the multilayer ceramic capacitor 1 can be reduced.

[0098] Furthermore, in the multilayer ceramic capacitor 1 of this embodiment, the dimension L4 in the length direction L of the fourth surface portion 40A4 of the first external electrode 40A and the dimension L5 in the length direction L of the fifth surface portion 40A5 are larger than the dimension L2 in the length direction L of the second surface portion 40A2 and the dimension L3 in the length direction L of the third surface portion 40A3, and the dimension L9 in the length direction L of the ninth surface portion 40B4 of the second external electrode 40B and the dimension L10 in the length direction L of the tenth surface portion 40B5 are larger than the dimension L7 in the length direction L of the seventh surface portion 40B2 and the dimension L8 in the length direction L of the eighth surface portion 40B3. This allows the solder to sufficiently wet and rise even on the fourth surface 40A4 and fifth surface 40A5 of the first external electrode 40A and the ninth surface 40B4 and tenth surface 40B5 of the second external electrode 40B, where the amount of solder wetting and rising tends to be small, when the first external electrode 40A and the second external electrode 40B are soldered to the lands and the multilayer ceramic capacitor 1 is mounted on a substrate. This prevents variations in the amount of solder on the fourth surface 40A4 and fifth surface 40A5 and the ninth surface 40B4 and tenth surface 40B5 of the second external electrode 40B, and also reduces differences in tensile stress caused by the solder. This prevents deterioration of the self-alignment effect and enables stable mounting. As a result, tilting or rotation of the multilayer ceramic capacitor 1, which can lead to short-circuiting, can be prevented. The self-alignment effect is a phenomenon in which the surface tension of the molten solder acts to reduce its surface area, causing the electronic element supported by the molten solder to move and be positioned properly. This self-alignment effect prevents misalignment during mounting.

[0099] As described above, the dimension L4 in the length direction L of the fourth surface portion 40A4 and the dimension L5 in the length direction L of the fifth surface portion 40A5 of the first external electrode 40A are preferably 110% to 245% of the dimension L2 in the length direction L of the second surface portion 40A2 and the dimension L3 in the length direction L of the third surface portion 40A3. Furthermore, the dimension L9 in the length direction L of the ninth surface portion 40B4 and the dimension L10 in the length direction L of the tenth surface portion 40B5 of the second external electrode 40B are preferably 110% to 245% of the dimension L7 in the length direction L of the seventh surface portion 40B2 and the dimension L8 in the length direction L of the eighth surface portion 40B3. If the ratio is less than 110%, it becomes difficult to suppress changes in the amount of solder on the fourth surface portion 40A4 and the fifth surface portion 40A5 and the ninth surface portion 40B4 and the tenth surface portion 40B5 of the second external electrode 40B. This makes it difficult to suppress the difference in tensile stress caused by the solder, which may cause the multilayer ceramic capacitor 1 to rotate when mounted. On the other hand, if the ratio is greater than 245%, depending on the amount of solder, the first external electrode 40A and the second external electrode 40B may become conductive, causing a short circuit. Therefore, it is preferable that the ratio be 110% or greater and 245% or less.

[0100] Modified examples of the layer structure of the external electrodes 40 of the multilayer ceramic capacitor 1 of this embodiment will be described below. In the following description, the same components as those in the above embodiment will be denoted by the same reference numerals, and detailed description will be omitted. Figures 11A and 11B are cross-sectional views showing modified examples of the layer structure of the external electrodes 40 of the multilayer ceramic capacitor 1 of this embodiment, and correspond to Figures 10A and 10B.

[0101] In this modification, the configuration of the external electrode 40 is different from that of the above embodiment.

[0102] The first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A. The first base electrode layer 50A of this modification is composed of a first baked layer 52A. The first plating layer 60A of this modification has a first Ni plating layer 62A and a first Sn plating layer 63A.

[0103] The second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B. The second base electrode layer 50B of this modification is composed of a second baked layer 52B. The second plating layer 60B of this modification has a second Ni plating layer 62B and a second Sn plating layer 63B.

[0104] In this modification, the first base electrode layer 50A has, for example, a first surface portion located on the first end face LS1, a second surface portion located on a portion of the first main surface TS1, a third surface portion located on a portion of the second main surface TS2, a fourth surface portion located on a portion of the first side surface WS1, and a fifth surface portion located on a portion of the second side surface WS2, similar to the above-described first external electrode 40A. Note that in this modification, the first base electrode layer 50A is connected to the first internal electrode layer 31.

[0105] The first Ni plating layer 62A is disposed so as to cover the first base electrode layer 50A. The first Sn plating layer 63A is disposed so as to cover the first Ni plating layer 62A.

[0106] In this modification, the second base electrode layer 50B has, for example, a sixth surface portion located on the second end face LS2, a seventh surface portion located on a portion of the first main surface TS1, an eighth surface portion located on a portion of the second main surface TS2, a ninth surface portion located on a portion of the first side surface WS1, and a tenth surface portion located on a portion of the second side surface WS2, similar to the above-described second external electrode 40B. Note that in this modification, the second base electrode layer 50B is connected to the second internal electrode layer 32.

[0107] The second Ni plating layer 62B is disposed so as to cover the second base electrode layer 50B. The second Sn plating layer 63B is disposed so as to cover the second Ni plating layer 62B.

[0108] The first baking layer 52A constituting the first base electrode layer 50A and the second baking layer 52B constituting the second base electrode layer 50B may be formed by applying a conductive paste containing glass and metal to the laminate and baking it, for example. When simultaneously firing the unfired laminated chip and the conductive paste applied to the laminated chip, it is preferable to form the baking layer by baking a layer containing a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the ceramic material to be added.

[0109] When the base electrode layer is formed as a baked layer, the first plating layer 60A and the second plating layer 60B preferably have a two-layer structure in which a Sn plating layer is formed on a Ni plating layer. In this case, the Ni plating layer prevents the base electrode layer from being eroded by solder when mounting the multilayer ceramic capacitor 1. Furthermore, the Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. This makes it easier to mount the multilayer ceramic capacitor 1.

[0110] The first plating layer 60A and the second plating layer 60B are not limited to a two-layer structure, but may be formed as a three-layer structure including Cu plating, as in the above embodiment, or may have other layer configurations.

[0111] The thickness of each plating layer is preferably 2 μm or more and 15 μm or less. That is, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is preferably 2 μm or more and 15 μm or less. More specifically, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is more preferably 2 μm or more and 4 μm or less.

[0112] Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described.

[0113] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The conductive paste for the dielectric sheet and the internal electrode contains a binder and a solvent. The binder and the solvent may be known. The paste made of the conductive material is, for example, a metal powder to which an organic binder and an organic solvent are added.

[0114] On the dielectric sheet, a conductive paste for the internal electrode layer 30 is printed by, for example, screen printing or gravure printing using a printing plate patterned to have the shape of the internal electrode layer 30 of this embodiment. In this way, a dielectric sheet on which the pattern of the first internal electrode layer 31 is formed and a dielectric sheet on which the pattern of the second internal electrode layer 32 is formed are prepared.

[0115] A predetermined number of dielectric sheets on which no pattern of internal electrode layers is printed are stacked to form a portion that will become the first main surface side outer layer portion 12 on the first main surface TS1 side. Dielectric sheets on which the pattern of the first internal electrode layer 31 is printed and dielectric sheets on which the pattern of the second internal electrode layer 32 is printed are stacked alternately in sequence on top of that to form a portion that will become the internal layer portion 11. A predetermined number of dielectric sheets on which the pattern of the internal electrode layer is not printed are stacked on top of this portion that will become the second main surface side outer layer portion 13 on the second main surface TS2 side. In this way, a laminated sheet is produced.

[0116] The laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0117] The laminated block is cut to a predetermined size to obtain laminated chips, and at this time, corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0118] The laminated chip is fired to produce the laminate 10. The firing temperature depends on the materials of the dielectric layers 20 and the internal electrode layers 30, but is preferably 900°C or higher and 1400°C or lower.

[0119] In this embodiment, the base electrode layer is formed of a thin film layer. When forming the base electrode layer as a thin film layer, the thin film layer is formed on the portion of the laminate 10 where the external electrode is to be formed by performing masking or the like. The thin film layer is formed by a thin film formation method such as sputtering or vapor deposition. In this embodiment, a sputtered electrode is formed as a thin film layer by sputtering.

[0120] 12 to 14 are diagrams showing intermediate states in the manufacturing process of the multilayer ceramic capacitor of this embodiment, showing the state after thin film layers have been arranged on the laminate 10 but before plating layers have been arranged. FIG. 12 is a diagram showing the state in which a first thin film layer 51A and a second thin film layer 51B have been arranged on the laminate 10, and corresponds to the LT cross section of FIG. 6. FIG. 13 is a diagram showing the state in which a first thin film layer 51A has been arranged on the laminate 10, and corresponds to the WT cross section of FIG. 7. FIG. 14 is a diagram showing the state in which the first thin film layer 51A and the second thin film layer 51B have been arranged on the laminate 10, and corresponds to FIG. 9, showing the surface of the first side surface WS1 of the laminate 10.

[0121] The first thin film layer 51A formed by the sputtering electrode is disposed on a portion of the first main surface TS1 facing the first end face LS1 and a portion of the second main surface TS2 facing the first end face LS1. The second thin film layer 51B formed by the sputtering electrode is disposed on a portion of the first main surface TS1 facing the second end face LS2 and a portion of the second main surface TS2 facing the second end face LS2.

[0122] In this embodiment, the thin film layer formed by the sputtered electrode is disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, and is disposed continuously from a portion of the first main surface TS1 and a portion of the second main surface TS2 to a portion of the first side surface WS1 and a portion of the second side surface WS2, slightly wrapping around a portion of the first side surface WS1 and a portion of the second side surface WS2. This makes it possible to control the distance between the thin film layer disposed on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode film exposed on the first side surface WS1 and the second side surface WS2. Therefore, it is possible to deposit a plating layer on the surface of the laminate 10 between the thin film layer disposed on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode layer exposed on the first side surface WS1 and the second side surface WS2.

[0123] Thereafter, plating layers are formed on the surfaces of the base electrode layer made of the thin film layer and the laminate. In this embodiment, three plating layers are formed, namely, a Cu plating layer, a Ni plating layer, and a Sn plating layer.

[0124] The plating layer is formed by electrolytic plating, preferably barrel plating.

[0125] Here, when the thin film layer is formed so as to extend over a portion of the first side surface WS1 and a portion of the second side surface WS2, it is possible to control the distance between the thin film layer and the internal electrode layer exposed on the first side surface WS1 and the second side surface WS2 of the laminate 10. This makes it easy to deposit a plating layer also on the surface of the laminate 10 between the thin film layer disposed on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode layer exposed on the first side surface WS1 and the second side surface WS2.

[0126] The plating layer is also disposed so as to cover the exposed portions of the internal electrode layers on the first side surface WS1 and the second side surface WS2 of the laminate 10. At this time, since the gaps between the thin film layers and the internal electrode layers exposed on the surface of the laminate 10 and the gaps between the multiple internal electrode layers exposed on the surface of the laminate 10 are narrow, the plating layer is also deposited in these gap regions.

[0127] When the base electrode layer is formed as a baked layer, a conductive paste to serve as the first base electrode layer is applied to a first surface portion located on the first end surface LS1 of the laminate 10, a second surface portion located on a portion of the first main surface TS1, a third surface portion located on a portion of the second main surface TS2, a fourth surface portion located on a portion of the first side surface WS1, and a fifth surface portion located on a portion of the second side surface WS2 on the first end surface LS1 side of the laminate 10. Furthermore, a conductive paste to serve as the second base electrode layer is applied to a sixth surface portion located on the second end surface LS2 of the laminate 10, a seventh surface portion located on a portion of the first main surface TS1, an eighth surface portion located on a portion of the second main surface TS2, a ninth surface portion located on a portion of the first side surface WS1, and a tenth surface portion located on a portion of the second side surface WS2 on the second end surface LS2 side of the laminate 10.

[0128] When the unfired laminated chip and the conductive paste applied to the laminated chip are simultaneously fired, the fired layer is preferably formed by firing a material containing a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as that of the dielectric layer 20 as the ceramic material added. In this case, the conductive paste is applied to the unfired laminated chip, and the laminated chip and the conductive paste applied to the laminated chip are simultaneously fired to form the laminate 10 with the fired layer formed thereon.

[0129] Thereafter, a plating layer is formed on the surface of the base electrode layer made of a baked layer and the laminate 10. When the base electrode layer is formed of a baked layer, two plating layers, for example, a Ni plating layer and a Sn plating layer, are formed as the plating layer. The plating layer is formed by an electrolytic plating method. As the plating method, barrel plating is preferably used.

[0130] Through these manufacturing steps, the multilayer ceramic capacitor 1 is manufactured.

[0131] The configuration of the external electrodes 40 is not limited to the configuration described above. Modified examples of the arrangement positions of the external electrodes 40 of the multilayer ceramic capacitor 1 of this embodiment will be described below. In the following description, the same components as those in the above embodiment will be given the same reference numerals, and detailed description will be omitted. Fig. 15 is a cross-sectional view showing a modified example of the arrangement positions of the external electrodes 40 of the multilayer ceramic capacitor 1 of this embodiment, and is a view corresponding to Fig. 1.

[0132] This modification differs from the above embodiment in the arrangement positions of the external electrodes 40. In this modification, the first external electrode 40A and the second external electrode 40B are arranged on only one of the first main surface TS1 or the second main surface TS2.

[0133] For example, the first external electrode 40A of this modification has a first surface 40A1 located on the first end face LS1, a third surface 40A3 located on a portion of the second main surface TS2, a fourth surface 40A4 located on a portion of the first side surface WS1, and a fifth surface 40A5 located on a portion of the second side surface WS2. In other words, the first external electrode 40A of this modification is not formed on the first main surface TS1.

[0134] For example, the second external electrode 40B of this modification has a sixth surface 40B1 located on the second end surface LS2, an eighth surface 40B3 located on a portion of the second main surface TS2, a ninth surface 40B4 located on a portion of the first side surface WS1, and a tenth surface 40B5 located on a portion of the second side surface WS2. In other words, the second external electrode 40B of this modification is not formed on the first main surface TS1.

[0135] This configuration also suppresses deterioration of the self-alignment effect and enables stable mounting. Furthermore, by not arranging the first external electrode 40A and the second external electrode 40B on either the first main surface TS1 or the second main surface TS2, the dimension of the multilayer ceramic capacitor 1 in the height direction T can be reduced, thereby achieving a further low profile of the multilayer ceramic capacitor 1. Furthermore, by not arranging the first external electrode 40A and the second external electrode 40B on either the first main surface TS1 or the second main surface TS2, the height dimension of the laminate 10 can be ensured by the thickness of the external electrodes 40. This makes it possible to increase the volume of the effective layer portion of the laminate 10, thereby achieving a high capacitance of the multilayer ceramic capacitor 1.

[0136] The multilayer ceramic capacitor 1 of this embodiment has the following advantages.

[0137] (1) The multilayer ceramic capacitor 1 of this embodiment includes a laminate 10 having a plurality of laminated dielectric layers 20 and a plurality of internal electrode layers 30 laminated on the dielectric layers 20, and having a first main surface TS1 and a second main surface TS2 opposing each other in a height direction, a first end surface LS1 and a second end surface LS2 opposing each other in a length direction perpendicular to the height direction, and a first side surface WS1 and a second side surface WS2 opposing each other in a width direction perpendicular to the height direction and the length direction; a first surface portion 40A1 located on the first end surface LS1; a first external electrode 40A having at least one of a second surface 40A2 located on a portion of the first main surface TS1 and a third surface 40A3 located on a portion of the second main surface TS2, a fourth surface 40A4 located on a portion of the first side surface WS1, and a fifth surface 40A5 located on a portion of the second side surface WS2; a sixth surface 40B1 located on the second end surface LS2; and at least one of a seventh surface 40B2 located on a portion of the first main surface TS1 and an eighth surface 40B3 located on a portion of the second main surface TS2. a second external electrode 40B having at least one of the first end face LS1 and the second end face LS2, a ninth face portion 40B4 located on a portion of the first side face WS1, and a tenth face portion 40B5 located on a portion of the second side face WS2, wherein, when the length in the length direction connecting the first end face LS1 and the second end face LS2 of the multilayer body 10 is l, the length in the width direction connecting the first side face WS1 and the second side face WS2 is w, and the length in the height direction connecting the first main face TS1 and the second main face TS2 is t, The dimensions L4, L5 of the fourth surface portion 40A4 and the fifth surface portion 40A5 of the first external electrode 40A in the length direction L are greater than the dimension L2, L3 of the second surface portion 40A2 and the dimension L3 of the third surface portion 40A3 in the length direction L, respectively. The dimensions L9, L10 of the ninth surface portion 40B4 and the tenth surface portion 40B5 in the length direction L are greater than the dimension L7, L7 of the seventh surface portion 40B2 and the dimension L8 of the eighth surface portion 40B3 in the length direction L. This allows the width of the lead-out portion at the end face of the internal electrode layer 30 to be increased. Furthermore, the distance between the first external electrode 40A and the second external electrode 40B can be shortened, thereby reducing the ESL of the multilayer ceramic capacitor 1.

[0138] Furthermore, when the first external electrode 40A and the second external electrode 40B are soldered to mount the multilayer ceramic capacitor 1 on a substrate, the solder can be sufficiently wetted up even on the fourth surface 40A4 and the fifth surface 40A5 of the first external electrode 40A and the ninth surface 40B4 and the tenth surface 40B5 of the second external electrode 40B, where the amount of solder wetting up tends to be small. This prevents variations in the amount of solder on the fourth surface 40A4 and the fifth surface 40A5 and the ninth surface 40B4 and the tenth surface 40B5 of the second external electrode 40B, and also prevents differences in tensile stress caused by the solder. This makes it possible to provide an LW-reversed multilayer ceramic capacitor that prevents deterioration of the self-alignment effect and enables stable mounting.

[0139] (2) In the multilayer ceramic capacitor 1 of this embodiment, the dimension L4 in the length direction L of the fourth surface portion 40A4 of the first external electrode 40A and the dimension L5 in the length direction L of the fifth surface portion 40A5 are 110% to 245% of the dimension L2 in the length direction L of the second surface portion 40A2 and the dimension L3 in the length direction L of the third surface portion 40A3, and the dimension L9 in the length direction L of the ninth surface portion 40B4 of the second external electrode 40B and the dimension L10 in the length direction L of the tenth surface portion 40B5 are 110% to 245% of the dimension L7 in the length direction L of the seventh surface portion 40B2 and the dimension L8 in the length direction L of the eighth surface portion 40B3. This makes the above-mentioned effects more pronounced.

[0140] (3) In the multilayer ceramic capacitor 1 of this embodiment, the internal electrode layers 30 include first internal electrode layers 31 and second internal electrode layers 32. The first internal electrode layer 31 includes a first opposing electrode portion 31A located inside the laminate 10 and a first lead portion 31B connected to the first opposing electrode portion 31A and exposed at the first end face LS1, a portion of the first side face WS1, and a portion of the second side face WS2. The second internal electrode layer 32 includes a second opposing electrode portion 32A located inside the laminate 10 and a second lead portion 32B connected to the second opposing electrode portion 32A and exposed at the second end face LS2, a portion of the first side face WS1, and a portion of the second side face WS2. This shortens the distance between the second lead portion 31B of the first internal electrode layer 31 and the second lead portion 32B of the second external electrode 40B, thereby shortening the path through which current flows. Therefore, the ESL can be reduced.

[0141] (4) In the multilayer ceramic capacitor 1 of this embodiment, the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A, and the second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B, with the first base electrode layer 50A and the second base electrode layer 50B being sputtered electrodes. This allows the external electrodes to be formed thin, making it easier to ensure the thickness of the laminate 10, and therefore ensuring the capacitance and strength of the laminate 10.

[0142] (5) In the multilayer ceramic capacitor 1 of this embodiment, the length t in the height direction T connecting the first main surface TS1 and the second main surface TS2 of the laminate 10 is 150 μm or less. In such a low-profile multilayer ceramic capacitor, the effects of this embodiment can be appropriately obtained.

[0143] (6) In the multilayer ceramic capacitor 1 of this embodiment, the length t in the height direction T connecting the first main surface TS1 and the second main surface TS2 of the laminate 10 is 100 μm or less. In such a low-profile multilayer ceramic capacitor, the effects of this embodiment can be appropriately obtained.

[0144] (7) In the multilayer ceramic capacitor 1 of this embodiment, the length t in the height direction T connecting the first main surface TS1 and the second main surface TS2 of the laminate 10 is 50 μm or less. In such a low-profile multilayer ceramic capacitor, the effects of this embodiment can be appropriately obtained.

[0145] <Experimental Example> A multilayer ceramic capacitor was fabricated as a sample for an experimental example, and its mountability was evaluated.

[0146] First, as a sample of Example 1, a multilayer ceramic capacitor 1 having the following specifications, shown in FIGS. 1 to 10B , was fabricated according to the above-described manufacturing method. Furthermore, as a sample of Comparative Example 1, a multilayer ceramic capacitor 101 was fabricated as shown in FIG. 16A , in which the lengthwise dimension of the surface portions on the side surfaces of the external electrodes 140 (first external electrode 140A, second external electrode 140B) was equivalent to the lengthwise dimension of the surface portions on the main surfaces. Furthermore, as a sample of Comparative Example 2, a multilayer ceramic capacitor 201 was fabricated as shown in FIG. 17A , in which the lengthwise dimension of the surface portions on the side surfaces of the external electrodes 240 (first external electrode 240A, second external electrode 240B) was equivalent to the lengthwise dimension of the surface portions on the main surfaces, and in which a recess R was provided recessed from the edge of the external electrode toward the end face of the laminate 10.

[0147] FIG. 16A is an external perspective view of the multilayer ceramic capacitor 101 of Comparative Example 1, and corresponds to FIG. 1 . FIG. 16B is a view showing a first internal electrode layer 131 of the multilayer ceramic capacitor 101 of Comparative Example 1, and corresponds to FIG. 8A . FIG. 16C is a view showing a second internal electrode layer 132 of the multilayer ceramic capacitor 101 of Comparative Example 1, and corresponds to FIG. 8B . FIG. 17A is an external perspective view of the multilayer ceramic capacitor 201 of Comparative Example 2, and corresponds to FIG. 1 . FIG. 17B is a view showing a first internal electrode layer 231 of the multilayer ceramic capacitor 201 of Comparative Example 2, and corresponds to FIG. 8A . FIG. 17C is a view showing a second internal electrode layer 232 of the multilayer ceramic capacitor 201 of Comparative Example 2, and corresponds to FIG. 8B . Note that external electrodes are omitted in FIGS. 16B , 16C , 17B , and 17C .

[0148] (Configuration of Example 1) Dimensions of multilayer ceramic capacitor: L×W×T=0.520 mm×1.000 mm×0.100 mm Ceramic material of dielectric layer: BaTiO ３ ・Capacitance: 0.47 μF ・Rated voltage: 4 V ・Material of internal electrode layer: Ni ・Pattern of internal electrode layer: Pattern shown in Figures 8A and 8B ・Structure of external electrode: Base electrode layer: thin film layer (sputtered electrode) Material of base electrode layer: two-layer structure of NiCr layer and NiCu layer Thickness of base electrode layer: main surface thickness 0.2 μm (thickness of base electrode layer disposed on each of first main surface TS1 and second main surface TS2) Plating layer: three-layer structure of Cu plating, Ni plating, and Sn plating Cu plating thickness: 5.5 μm Ni plating thickness: 2.5 μm Sn plating thickness: 3.2 μm ・The lengthwise dimension of each surface portion (fourth surface portion and fifth surface portion) on the side surface of the first external electrode is 180% of the lengthwise dimension of each surface portion (second surface portion and third surface portion) on the main surface of the first external electrode The lengthwise dimension of each face portion (the ninth face portion and the tenth face portion) on the side surface side of the second external electrode is 180% of the lengthwise dimension of each face portion (the seventh face portion and the eighth face portion) on the main surface side of the second external electrode.

[0149] (Configuration of Comparative Example 1) Dimensions of multilayer ceramic capacitor: L×W×T=0.520 mm×1.000 mm×0.100 mm Ceramic material of dielectric layer: BaTiO ３ ・Capacitance: 0.47 μF ・Rated voltage: 4 V ・Material of internal electrode layer: Ni ・Pattern of internal electrode layer: Pattern shown in Figures 16B and 16C ・Structure of external electrode: Base electrode layer: Baked layer formed by applying and baking conductive paste Base electrode layer material: Ni Base electrode layer thickness: End face thickness 10 μm, side face thickness 5 μm, main face thickness 5 μm (thickness of the base electrode layer disposed on each of the first main surface TS1 and the second main surface TS2) Plating layer: Three-layer structure of Cu plating, Ni plating, and Sn plating Cu plating thickness: 5.5 μm Ni plating thickness: 2.5 μm Sn plating thickness: 3.2 μm

[0150] (Configuration of Comparative Example 2) Dimensions of multilayer ceramic capacitor: L×W×T=0.520 mm×1.000 mm×0.100 mm Ceramic material of dielectric layer: BaTiO ３ ・Capacitance: 0.47 μF ・Rated voltage: 4 V ・Material of internal electrode layer: Ni ・Pattern of internal electrode layer: Pattern shown in Figures 17B and 17C ・Structure of external electrode: Base electrode layer: thin film layer (sputtered electrode) Material of base electrode layer: two layers of NiCr layer and NiCu layer Base electrode layer thickness: main surface thickness 0.2 μm (thickness of base electrode layer disposed on each of first main surface TS1 and second main surface TS2) Plating layer: three-layer structure of Cu plating, Ni plating, and Sn plating Cu plating thickness: 5.5 μm Ni plating thickness: 2.5 μm Sn plating thickness: 3.2 μm

[0151] Next, the fabricated samples were used to evaluate the mountability.

[0152] (Evaluation of Mountability 1) Mountability was evaluated using the sample of Example 1 and the samples of Comparative Examples 1 and 2. The evaluation was performed using 100 samples for each. Table 1 shows the results of the evaluation of mountability.

[0153]

[0154] In Comparative Example 1, eight samples exhibited poor rotation. It is presumed that the evaluation was performed with a large amount of solder, which resulted in a difference in the way the solder wetted onto the first external electrode and the second external electrode, causing the poor rotation.

[0155] In Comparative Example 2, 15 samples exhibited rotation defects. Two of these samples had a large amount of rotation, resulting in short circuits due to mounting with one external electrode straddling lands of opposite polarity. In the samples of Comparative Example 2, variations in the position and thickness of the base electrode layer and the plating layer formed thereon caused variations in the area and shape of the external electrodes covering the ridges of the first and second side surfaces of the laminate. This likely led to variations in the way the solder wetted the external electrodes on the first and second side surfaces, resulting in significant differences in the amount of solder wetting. It is believed that this resulted in variations in the way the tensile stress of the solder was applied to the multilayer ceramic capacitor, causing the rotation defects.

[0156] The evaluation methods used in this experiment are as follows.

[0157] (Method for Evaluating Mountability) FIGS. 18A to 18D are diagrams illustrating a method for evaluating mountability. First, solder (solder composition Sn-3.0Ag-0.5Cu) was printed on each of two lands 310A and 310B arranged on a glass epoxy substrate 300 shown in FIG. 18A. The amount of solder used was 1.5 times that of a normal test to create more severe conditions than those used in a normal test. Specifically, a thickness of 150 μm of solder was printed on each land. As shown in FIG. 18A, the width of the land was 1.0 mm, the length of the land in the longitudinal direction was 0.3 mm, and the distance between the two lands was 0.2 mm.

[0158] Next, the multilayer ceramic capacitor is placed on the solder-coated lands. At this time, as shown in Fig. 18B, a reference line is drawn perpendicular to the width direction of the land at the center of the land's width, and the multilayer ceramic capacitor is placed so that the center of the multilayer ceramic capacitor in the width direction W is located 0.1 mm off the reference line in the width direction of the land. At this time, the angle θ formed between the land and the multilayer ceramic capacitor shown in Fig. 18C, i.e., the acute angle θ formed between one of the opposing inner sides of the two lands and the surface of the external electrode of the multilayer ceramic capacitor facing the first end face LS1 or the surface facing the second end face LS2, is within 5°.

[0159] Then, the external electrodes of the multilayer ceramic capacitor are soldered to the lands by reflow soldering, and the multilayer ceramic capacitor is mounted on a substrate. After mounting, the mounted state of the multilayer ceramic capacitor is observed, and a case where the angle θ between the land and the multilayer ceramic capacitor is 5° or more is determined to be a rotation defect. Furthermore, as shown in Figure 18D, a case where the multilayer ceramic capacitor is rotated significantly and the first external electrode or the second external electrode is mounted so as to straddle two lands is determined to be a short circuit defect.

[0160] (Mountability Evaluation 2) In the multilayer ceramic capacitor of Example 1 having the above specifications, 100 additional samples of Examples 2 to 5 were produced by varying the following ratios A and B, and the mountability was evaluated in the same manner as above. Table 2 shows ratios A and B for Examples 1 to 6, along with the results of the mountability evaluation.

[0161] "Ratio A": The ratio of the lengthwise dimension of each surface portion (fourth surface portion and fifth surface portion) on the side surface of the first external electrode to the lengthwise dimension of each surface portion (second surface portion and third surface portion) on the main surface of the first external electrode. "Ratio B": The ratio of the lengthwise dimension of each surface portion (ninth surface portion and tenth surface portion) on the side surface of the second external electrode to the lengthwise dimension of each surface portion (seventh surface portion and eighth surface portion) on the main surface of the second external electrode.

[0162]

[0163] In Example 2, where Ratio A and Ratio B were 105%, one sample experienced rotation. It is believed that this was caused by the difference in tensile stress due to the solder becoming difficult to suppress, resulting in rotation. On the other hand, in Example 6, where Ratio A and Ratio B were 250%, it is believed that the distance between the surface of the first external electrode and the surface of the second external electrode on the side surface became shorter, causing solder to adhere to both electrodes, resulting in electrical conduction and a short circuit. Therefore, it is preferable that Ratio A and Ratio B be 110% or more and 245% or less.

[0164] In calculating the ratios A and B, the dimensions in the length direction L of the second surface portion 40A2 and the third surface portion 40A3 of the first external electrode 40A and the seventh surface portion 40B2 and the eighth surface portion 40B3 of the second external electrode 40B, which are the surfaces on the main surface side, and the dimensions in the length direction L of the fourth surface portion 40A4 and the fifth surface portion 40A5 of the first external electrode 40A and the ninth surface portion 40B4 and the tenth surface portion 40B5 of the second external electrode 40B, which are the surfaces on the side surface side, are measured using the following method.

[0165] (Method of measuring surface portions on the principal surface side) The dimensions in the length direction L of the second surface portion 40A2 and the seventh surface portion 40B2 are measured with a microscope at a position halfway in the width direction W when observed from the first principal surface TS1 of the laminate 10. Similarly, the dimensions in the length direction L of the third surface portion 40A3 and the eighth surface portion 40B3 are measured with a microscope at a position halfway in the width direction W when observed from the second principal surface TS2 of the laminate 10.

[0166] (Method of measuring surface portions on the side surfaces) The dimensions in the length direction L of the fourth surface portion 40A4 and the ninth surface portion 40B4 are measured with a microscope at a position halfway in the height direction T when observed from the first side surface WS1 of the laminate 10. Similarly, the dimensions in the length direction L of the fifth surface portion 40A5 and the tenth surface portion 40B5 are measured with a microscope at a position halfway in the height direction T when observed from the second side surface WS2 of the laminate 10.

[0167] The present invention is not limited to the configurations of the above-described embodiments, and can be applied by making appropriate modifications within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual desirable configurations described in the above-described embodiments.

[0168] (1) A laminate including a plurality of dielectric layers and a plurality of internal electrode layers alternately stacked in a height direction, and having a first main surface and a second main surface opposing each other in the height direction, a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction and the length direction; a first external electrode having a first surface portion located on the first end surface, at least one of a second surface portion located on a portion of the first main surface and a third surface portion located on a portion of the second main surface, a fourth surface portion located on a portion of the first side surface, and a fifth surface portion located on a portion of the second side surface; a multilayer ceramic capacitor having a second external electrode having a sixth surface portion located on the second end surface, at least one of a seventh surface portion located on a portion of the first main surface and an eighth surface portion located on a portion of the second main surface, a ninth surface portion located on a portion of the first side surface, and a tenth surface portion located on a portion of the second side surface, wherein, when the length in the longitudinal direction connecting the first end surface and the second end surface of the laminate is l, the length in the width direction connecting the first side surface and the second side surface is w, and the length in the height direction connecting the first main surface and the second main surface is t, a dimensional relationship of w>l>t is satisfied, and the lengthwise dimension of the fourth surface portion and the fifth surface portion of the first external electrode is greater than the lengthwise dimension of the second surface portion and the third surface portion, and the lengthwise dimension of the ninth surface portion and the tenth surface portion of the second external electrode is greater than the lengthwise dimension of the seventh surface portion and the eighth surface portion.

[0169] (2) The multilayer ceramic capacitor according to (1), wherein the lengthwise dimensions of the fourth and fifth surface portions of the first external electrode are 110% or more and 245% or less of the lengthwise dimensions of the second and third surface portions, and the lengthwise dimensions of the ninth and tenth surface portions of the second external electrode are 110% or more and 245% or less of the lengthwise dimensions of the seventh and eighth surface portions.

[0170] (3) The multilayer ceramic capacitor according to (1) or (2), wherein the internal electrode layers include first internal electrode layers and second internal electrode layers, the first internal electrode layers include a first opposing electrode portion located inside the laminate and a first lead portion connected to the first opposing electrode portion and exposed to the first end face, a portion of the first side face, and a portion of the second side face, and the second internal electrode layers include a second opposing electrode portion located inside the laminate and a second lead portion connected to the second opposing electrode portion and exposed to the second end face, a portion of the first side face, and a portion of the second side face.

[0171] (4) The multilayer ceramic capacitor according to any one of (1) to (3), wherein the first external electrode has a first base electrode layer and a first plating layer disposed on the first base electrode layer, the second external electrode has a second base electrode layer and a second plating layer disposed on the second base electrode layer, and the first base electrode layer and the second base electrode layer are sputtered electrodes.

[0172] (5) The multilayer ceramic capacitor according to any one of (1) to (4), wherein the length in the height direction connecting the first main surface and the second main surface of the laminate is 150 μm or less.

[0173] (6) The multilayer ceramic capacitor according to any one of (1) to (4), wherein the length in the height direction connecting the first main surface and the second main surface of the laminate is 100 μm or less.

[0174] (7) The multilayer ceramic capacitor according to any one of (1) to (4), wherein the length in the height direction connecting the first main surface and the second main surface of the laminate is 50 μm or less.

[0175] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 10 Laminate 11 Inner layer portion 12 First principal surface side outer layer portion 13 Second principal surface side outer layer portion 20 Dielectric layer 30 Internal electrode layer 31 First internal electrode layer 31A First opposing electrode portion 31B First lead portion 31C Second lead portion 31D Third lead portion 32 Second internal electrode layer 32A Second opposing electrode portion 32B Fourth lead portion 32C Fifth lead portion 32D Sixth lead portion 40 External electrode 40A First external electrode 40A1 First surface portion 40A2 Second surface portion 40A3 Third surface portion 40A4 Fourth surface portion 40A5 Fifth surface portion 40B Second external electrode 40B1 Sixth surface portion 40B2 Seventh surface portion 40B3 Eighth surface portion 40B4 Ninth surface portion 40B5 Tenth surface portion 50A First base electrode layer 50B Second base electrode layer 51A First thin film layer 51B Second thin film layer 60A First plating layer 60B Second plating layer L Length direction W Width direction T Stacking direction LS1 First end face LS2 Second end face WS1 First side face WS2 Second side face TS1 First main surface TS2 Second main surface l Length in the length direction w Length in the width direction t Length in the height direction

Claims

1. a laminate including a plurality of dielectric layers and a plurality of internal electrode layers alternately stacked in a height direction, and having a first main surface and a second main surface opposed to each other in the height direction, a first end surface and a second end surface opposed to each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposed to each other in a width direction perpendicular to the height direction and the length direction; a first external electrode having a first surface portion located on the first end face, at least one of a second surface portion located on a portion of the first main surface and a third surface portion located on a portion of the second main surface, a fourth surface portion located on a portion of the first side surface, and a fifth surface portion located on a portion of the second side surface; a second external electrode having a sixth surface portion located on the second end face, at least one of a seventh surface portion located on a portion of the first main surface and an eighth surface portion located on a portion of the second main surface, a ninth surface portion located on a portion of the first side surface, and a tenth surface portion located on a portion of the second side surface, a length in the longitudinal direction connecting the first end surface and the second end surface of the laminate is l, a length in the width direction connecting the first side surface and the second side surface is w, and a length in the height direction connecting the first main surface and the second main surface is t, where w>l>t is a dimensional relationship between the length in the longitudinal direction connecting the first end surface and the second end surface of the laminate, the fourth surface portion and the fifth surface portion of the first external electrode have a dimension in the longitudinal direction larger than a dimension in the longitudinal direction of the second surface portion and the third surface portion of the first external electrode; a lengthwise dimension of the ninth surface portion and the tenth surface portion of the second external electrode is greater than a lengthwise dimension of the seventh surface portion and the eighth surface portion of the second external electrode.

2. a dimension in the longitudinal direction of the fourth surface portion and the fifth surface portion of the first external electrode is 110% or more and 245% or less of a dimension in the longitudinal direction of the second surface portion and the third surface portion, 2. The multilayer ceramic capacitor according to claim 1, wherein the lengthwise dimension of the ninth surface portion and the tenth surface portion of the second external electrode is 110% or more and 245% or less of the lengthwise dimension of the seventh surface portion and the eighth surface portion.

3. The internal electrode layer includes a first internal electrode layer and a second internal electrode layer, the first internal electrode layer has a first opposing electrode portion located inside the laminate, and a first lead portion connected to the first opposing electrode portion and exposed to the first end face, a portion of the first side face, and a portion of the second side face, 3. The multilayer ceramic capacitor according to claim 1, wherein the second internal electrode layer has a second opposing electrode portion located inside the laminate, and a second lead portion connected to the second opposing electrode portion and exposed on the second end face, a portion of the first side face, and a portion of the second side face.

4. the first external electrode has a first base electrode layer and a first plating layer disposed on the first base electrode layer; the second external electrode has a second base electrode layer and a second plating layer disposed on the second base electrode layer, 3. The multilayer ceramic capacitor according to claim 1, wherein the first and second underlying electrode layers are sputtered electrodes.

5. 3. The multilayer ceramic capacitor according to claim 1, wherein a length in a height direction connecting said first main surface and said second main surface of said laminate is 150 μm or less.

6. 3. The multilayer ceramic capacitor according to claim 1, wherein a length in a height direction connecting said first main surface and said second main surface of said laminate is 100 [mu]m or less.

7. 3. The multilayer ceramic capacitor according to claim 1, wherein a length in a height direction connecting said first main surface and said second main surface of said laminate is 50 μm or less.