Signal transmitting apparatus

Abstract

In the present invention, an output terminal is connected to a power supply voltage application end through a pull-up resistor. An output transistor is provided between the output terminal and ground. A capacitor is connected between the gate of the output transistor and the output terminal. A charge-discharge circuit charges or discharges the gate of the output transistor in accordance with an input signal, turns on or off the output transistor accordingly, to thereby generate an output signal, corresponding to the input signal, at the output terminal. When switching on and off the output transistor, the charge-discharge circuit variably sets the values of charging current and discharging current for the gate of the output transistor.

Description

signal transmitting device

[0001] The present disclosure relates to a signal transmission device.

[0002] There are signal transmission devices that transmit an output signal from an output terminal. One type of signal transmission device reduces radiated noise by controlling the slew rate of the output signal.

[0003] Japanese Patent Application Laid-Open No. 2017-200103

[0004] However, there is room for improvement in technology aimed at reducing radiated noise.

[0005] An object of the present disclosure is to provide a signal transmission device that contributes to reducing radiated noise.

[0006] A signal transmission device according to the present disclosure comprises an output terminal configured to be connected to an application terminal of a power supply voltage via a pull-up resistor, an output transistor provided between the output terminal and ground, a capacitor connected between the gate of the output transistor and the output terminal, and a charge / discharge circuit configured to charge or discharge the gate of the output transistor in accordance with an input signal, and generates an output signal at the output terminal in accordance with the input signal by turning the output transistor on or off through charging or discharging the gate of the output transistor, and when the input signal has a first level, the charge / discharge circuit supplies a charging current to the gate of the output transistor to increase the gate voltage of the output transistor, thereby turning on the output transistor, and when the input signal has a second level, draws a discharging current from the gate of the output transistor to decrease the gate voltage, thereby turning off the output transistor, and the charge / discharge circuit variably sets the value of the charging current or the discharging current when switching the output transistor between on and off in response to a change in the level of the input signal.

[0007] According to the present disclosure, it is possible to provide a signal transmission device that contributes to reducing radiation noise.

[0008] FIG. 1 is a diagram illustrating the overall configuration of a communication system according to an embodiment of the present disclosure. FIG. 2 is a perspective view of the exterior of a transceiver according to an embodiment of the present disclosure. FIG. 3 is a diagram illustrating the configuration of a transmission circuit in a transceiver according to an embodiment of the present disclosure. FIG. 4 is a timing chart illustrating a reference operation. FIG. 5 is a waveform diagram of a control input signal, a charging current, and a discharging current according to a first example of the present disclosure. FIG. 6 is a timing chart illustrating the operation of a transmission circuit according to the first example of the present disclosure. FIG. 7 is a diagram illustrating the configuration of a charging / discharging circuit according to the first example of the present disclosure. FIG. 8 is a diagram illustrating several waveforms relating to the operation of the charging / discharging circuit of FIG. 7. FIG. 9 is a diagram illustrating the operation of the charging / discharging circuit of FIG. 7. FIG. 10 is a diagram illustrating the operation of the charging / discharging circuit of FIG. 7. FIG. 11 is a diagram illustrating the operation of the charging / discharging circuit of FIG. 7. FIG. 12 is a diagram illustrating a modified configuration of a charging / discharging circuit according to the first example of the present disclosure. FIG. 13 is a waveform diagram of a control input signal, a charging current, and a discharging current according to a second example of the present disclosure. Fig. 14 is a diagram showing the configuration of a charge / discharge circuit according to a second example belonging to an embodiment of the present disclosure. Fig. 15 is a diagram showing several waveforms related to the operation of the charge / discharge circuit of Fig. 14. Fig. 16 is a diagram showing the configuration of a transmission circuit according to a third example belonging to an embodiment of the present disclosure. Fig. 17 is a diagram showing the configuration of a control input signal S according to the third example belonging to an embodiment of the present disclosure. IN 18 is a diagram showing the waveform of the gate voltage in relation to . FIG. 18 is a configuration diagram of a boost circuit according to a third example belonging to an embodiment of the present disclosure. FIG. 19 is a configuration diagram of a charging circuit according to a fourth example belonging to an embodiment of the present disclosure. FIG. 20 is a diagram showing several waveforms related to the operation of the charging circuit of FIG. 19. FIG. 21 is a configuration diagram of a discharging circuit according to a fifth example belonging to an embodiment of the present disclosure. FIG. 22 is a diagram showing several waveforms related to the operation of the discharging circuit of FIG. 21.

[0009] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, identical parts are designated by the same reference numerals, and duplicate descriptions of identical parts will be omitted as a general rule. For the sake of simplicity, this specification may use symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components, and may omit or abbreviate the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs. For example, the bus connection terminal BUS referred to by "BUS" (see FIG. 1) described below may be written as a bus connection terminal BUS or abbreviated as a terminal BUS, but they all refer to the same thing.

[0010] First, some terms used in describing the embodiments of the present disclosure will be explained. A line refers to a wiring through which an electrical signal is propagated or applied. A ground refers to a reference conductive portion having a reference potential of 0 V (zero volts), or refers to the 0 V potential itself. The reference conductive portion may be formed using a conductor such as metal. A potential of 0 V is sometimes referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a particular reference represents a potential seen from ground.

[0011] A level refers to the level of potential, and for any given signal or voltage, a high level has a higher potential than a low level. For any given signal or voltage, a high level of the signal or voltage strictly means that the level of the signal or voltage is high, and a low level of the signal or voltage strictly means that the level of the signal or voltage is low. A level of a signal may be expressed as a signal level, and a level of a voltage may be expressed as a voltage level. For any given signal, when the signal is high, the inverted signal of the signal is low, and when the signal is low, the inverted signal of the signal is high.

[0012] In any signal or voltage of interest, a transition from a low level to a high level is referred to as an up-edge. The timing at which an up-edge occurs is referred to as up-edge timing. An up-edge may be read as a rising edge. In any signal or voltage of interest, a transition from a high level to a low level is referred to as a down-edge. The timing at which a down-edge occurs is referred to as down-edge timing. A down-edge may be read as a falling edge.

[0013] For any transistor configured as a FET (field effect transistor), including a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-type MOSFET. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Furthermore, unless otherwise specified, the back gate of any MOSFET can be considered to be short-circuited to the source.

[0014] Any switch can be configured with one or more FETs (field effect transistors), and when a switch is in the on state, both ends of the switch are conductive, while when a switch is in the off state, both ends of the switch are non-conductive. Hereinafter, the on and off states of any transistor or switch may be simply referred to as on and off.

[0015] For any signal that takes a high or low signal level, the period during which the signal level is high is referred to as a high-level period, and the period during which the signal level is low is referred to as a low-level period. The same applies to any voltage that takes a high or low voltage level.

[0016] Unless otherwise specified, the connection between a plurality of parts that form a circuit, such as any circuit element, wiring (line), node, etc., may be understood to refer to an electrical connection.

[0017] 1 shows an overall configuration diagram of a communication system 1 according to an embodiment of the present disclosure. The communication system 1 includes a transceiver 10, a microcomputer 20, and a counterpart device 30. The components of the communication system 1 also include a bus line 51, a pull-up resistor 52, a backflow prevention diode 53, a capacitor 54, a data line 61, a data line 62, and a pull-up resistor 63.

[0018] FIG. 2 is a perspective view of the transceiver 10. The transceiver 10 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and multiple external terminals exposed from the housing to the outside of the transceiver 10. The transceiver 10 is formed by encapsulating the semiconductor chip in a housing (package) made of resin. Note that the number of external terminals and the type of housing of the transceiver 10 shown in FIG. 2 are merely examples and can be designed as desired. FIG. 1 shows the multiple external terminals, including a power supply terminal VIN, a bus connection terminal BUS, a ground terminal GND, a receive data output terminal RXD, and a transmit data input terminal TXD. Other external terminals (such as a sleep control input terminal) may also be provided in the transceiver 10.

[0019] A power supply voltage VDD is supplied to the power supply terminal VIN from a voltage source (not shown). The power supply voltage VDD has a predetermined positive DC voltage value. The transceiver 10 is driven based on the power supply voltage VDD. The ground terminal GND is connected to ground. The bus connection terminal BUS is connected to one end of a bus line 51, and the other end of the bus line 51 is connected to the counterpart device 30. That is, the bus connection terminal BUS is connected to the counterpart device 30 via the bus line 51. The counterpart device 30 also has a terminal that receives the power supply voltage VDD and a terminal that is connected to ground, and is driven based on the power supply voltage VDD.

[0020] The bus line 51 is connected to an application terminal 50 of a power supply voltage VDD via a pull-up resistor 52 and a backflow prevention diode 53. The application terminal 50 is a terminal to which the power supply voltage VDD is applied. The forward direction of the backflow prevention diode 53 is from the application terminal 50 toward the bus line 51 and the bus connection terminal BUS. The backflow prevention diode 53 blocks current flow from the bus line 51 to the application terminal 50. More specifically, the anode of the backflow prevention diode 53 is connected to the application terminal 50, the cathode of the backflow prevention diode 53 is connected to one end of the pull-up resistor 52, and the other end of the pull-up resistor 52 is connected to the bus line 51.

[0021] 1, the positions of the pull-up resistor 52 and the blocking diode 53 may be reversed. That is, the application terminal 50 may be connected to the anode of the blocking diode 53 via the pull-up resistor 52, and the cathode of the blocking diode 53 may be connected to the bus line 51. Also, a modification is possible in which the bus line 51 is connected to the application terminal 50 via only the pull-up resistor 52, without providing the blocking diode 53.

[0022] The capacitor 54 is connected between the bus line 51 and the ground. That is, one end of the capacitor 54 is connected to the bus line 51, and the other end of the capacitor 54 is connected to the ground. The capacitor 54 may be composed of a plurality of capacitors that are separated from each other. The capacitor 54 may also be omitted.

[0023] The receive data output terminal RXD is connected to one end of a data line 61, the other end of which is connected to the microcomputer 20. The transmit data input terminal TXD is connected to one end of a data line 62, the other end of which is connected to the microcomputer 20. That is, the terminals RXD and TXD are connected to the microcomputer 20 via the data lines 61 and 62. The data line 61 is connected to the application terminal of the power supply voltage VCC via a pull-up resistor 63. The power supply voltage VCC has a predetermined positive DC voltage value. It does not matter whether the values ​​of the power supply voltages VCC and VDD match or not. The microcomputer 20 has a terminal that receives the power supply voltage VCC and a terminal that is connected to ground, and is driven based on the power supply voltage VCC.

[0024] The transceiver 10 comprises a receiving circuit RX and a transmitting circuit TX. The receiving circuit RX is connected to a receiving data output terminal RXD and a bus connection terminal BUS. The transmitting circuit TX is connected to a transmitting data input terminal TXD and a bus connection terminal BUS.

[0025] The transceiver 10 and the counterpart device 30 perform bidirectional communication in a half-duplex manner via a bus line 51. The bidirectional communication assumed in this embodiment is single-wire serial communication (i.e., serial communication using a single wire, the bus line 51). In the half-duplex bidirectional communication, the transceiver 10 may function as a master and the counterpart device 30 as a slave, or the counterpart device 30 may function as a master and the transceiver 10 as a slave. The bidirectional communication between the transceiver 10 and the counterpart device 30 may be bidirectional communication conforming to, for example, the LIN (Local Interconnect Network) standard or the CXPI (Clock Extension Peripheral Interface) standard.

[0026] In half-duplex two-way communication, either the transceiver 10 or the other device 30 operates as a transmitting device, and the other functions as a receiving device.

[0027] When the transceiver 10 functions as a receiving device, the other device 30 transmits a signal (hereinafter, signal SR The receiving circuit RX receives the signal S transmitted from the other device 30 at the bus connection terminal BUS. R The receiving circuit RX receives the received signal S R is transmitted from terminal RXD to microcomputer 20 via data line 61. When transceiver 10 functions as a receiving device, bus connection terminal BUS functions as an input terminal (signal receiving terminal) that receives a signal transmitted from counterpart device 30.

[0028] When the transceiver 10 functions as a transmitting device, the microcomputer 20 transmits a signal (hereinafter, signal S T ) is transmitted to the transceiver 10. The signal S T When the transceiver 10 functions as a transmitting device, the transmitting circuit TX receives the signal S from the microcomputer 20. T The other device 30 may be configured with a transceiver and a microcomputer set equivalent to the transceiver 10 and the microcomputer 20. In this case, the signal S received from the transceiver 10 is T is transmitted from the transceiver in the remote device 30 to the microcomputer in the remote device 30. When the transceiver 10 functions as a transmitting device, the bus connection terminal BUS functions as an output terminal (signal transmitting terminal) from which a signal to be transmitted from the transceiver 10 appears.

[0029] The transmission of a signal via the bus line 51 is realized by controlling the level of the bus line 51 to a high level or a low level. The level of the bus line 51 and the level of the bus connection terminal BUS are the same. The level of the bus line 51 is a level that is equal to or higher than 0 V and equal to or lower than the power supply voltage VDD. When the bus line 51 is at a voltage (VDD×k H ), the level of the bus line 51 corresponds to a high level, and the bus line 51 has a voltage (VDD×k L ) or less, the level of the bus line 51 corresponds to a low level.H >0.5>k L >0" holds, for example, (k H , k L )=(0.7, 0.3). The voltages at the bus line 51 and the bus connection terminal BUS are represented by the symbol "V BUS " is expressed as

[0030] Unless otherwise specified, the operation and configuration of the transceiver 10 when it functions as a transmitting device will be described below. BUS corresponds to the output voltage (output voltage of the transmitter circuit TX). Therefore, when focusing on the configuration or operation of the transmitter circuit TX, the voltage V BUS may be referred to as the output voltage hereinafter. BUS The signal indicated by V can be referred to as an output signal. When the level of the bus line 51 is transitioned between a high level and a low level in transmitting a signal via the bus line 51, the transmitting circuit TX in the transceiver 10 outputs an output voltage V BUS It has the function of controlling the slew rate.

[0031] [Basic Configuration of Transmitter Circuit TX] Figure 3 shows the basic configuration of the transmitter circuit TX. The transmitter circuit TX according to the basic configuration includes an output transistor 111, a capacitor (feedback capacitor) 112, a blocking diode 113, a charge / discharge circuit 120, a control input signal supply circuit 130, and a gate voltage limiting circuit 140. Note that although the basic configuration of Figure 3 assumes that the blocking diode 53 (see Figure 1) is not provided, the inclusion or exclusion of the blocking diode 53 is optional (the same applies to any of the embodiments described below). Below, unless otherwise specified, the presence of the blocking diode 53 that may be provided in the communication system 1 will be ignored.

[0032] The output transistor 111 is an N-channel MOSFET. The output transistor 111 is provided between the bus connection terminal BUS, which functions as an output terminal, and ground, and the transmission circuit TX transmits signals using the output transistor 111 with an open-drain configuration. However, a backflow prevention diode 113 is provided between the output transistor 111 and the bus connection terminal BUS to block the flow of current from ground toward the bus line 51 via the output transistor 111 and the bus connection terminal BUS. Specifically, the drain of the output transistor 111 is connected to the cathode of the backflow prevention diode 113, and the anode of the backflow prevention diode 113 is connected to the bus connection terminal BUS. The source of the output transistor 111 is connected to ground. The gate voltage of the output transistor 111 (i.e., the voltage applied to the gate of the output transistor 111) is represented by the symbol "V G The gate threshold voltage of the output transistor 111 is represented by the symbol "V G_TH The gate threshold voltage V G_TH has a positive voltage value that depends on the characteristics of the output transistor 111. The gate voltage V of the output transistor 111 G is the gate threshold voltage V G_TH When the gate voltage V G is the gate threshold voltage V G_TH When this is the case, the output transistor 111 is in an ON state.

[0033] It is also possible to modify the transmitter circuit TX so that the backflow prevention diode 113 is not provided, and when this modification is adopted, the drain of the output transistor 111 is directly connected to the bus connection terminal BUS (the same applies to any of the embodiments described below).

[0034] The capacitor 112 is connected between the gate of the output transistor 111 and the bus connection terminal BUS. That is, one end of the capacitor 112 is connected to the gate of the output transistor 111, and the other end of the capacitor 112 is connected to the bus connection terminal BUS.

[0035] The charge / discharge circuit 120 receives a control input signal S INThe charge / discharge circuit 120 can control the output transistor 111 to be in the ON state by charging the gate of the output transistor 111, and can control the output transistor 111 to be in the OFF state by discharging the gate of the output transistor 111. IN is a binary signal having a high or low signal level. A high-level control input signal S IN is essentially the internal power supply voltage V REG and the control input signal S IN The power supply voltage VDD is supplied to the transceiver 10 via a regulator (not shown) to generate an internal power supply voltage V REG The charge / discharge circuit 120 includes a charging circuit 121 and a discharging circuit 122.

[0036] The charging circuit 121 receives a control input signal S IN During the high level period, a charging current is supplied to the gate of the output transistor 111, thereby increasing the gate voltage V G However, the gate voltage V G There is an upper limit to the gate voltage V G The gate voltage V G The upper limit voltage is the internal power supply voltage V REG or the internal power supply voltage V REG The gate voltage V G The upper limit voltage of the output transistor 111 is the gate threshold voltage V G_TH Higher gate voltage V G In the process of rising from a sufficiently low voltage (for example, 0 V), the gate voltage V G is the gate threshold voltage V G_TH When the gate voltage V reaches the G In the process of rising from a sufficiently low voltage (for example, 0 V), the gate voltage V G is the gate threshold voltage V G_THWhen this occurs, the resistance value of the channel of the output transistor 111 drops sharply, and the resistance value of the channel of the output transistor 111 becomes sufficiently smaller than the resistance value of the pull-up resistor 52, and the voltage V BUS drops to substantially 0 V. The resistance value of the channel of the output transistor 111 refers to the resistance value between the drain and source of the output transistor 111 .

[0037] The discharge circuit 122 receives a control input signal S IN During the low level period, a discharge current is drawn from the gate of the output transistor 111, thereby increasing the gate voltage V G However, the gate voltage V G There is a lower limit to the gate voltage V G The gate voltage V G The lower limit voltage of the gate voltage V G is the gate threshold voltage V G_TH In the process of decreasing from a voltage higher than G is the gate threshold voltage V G_TH When the gate voltage V falls below 0 V, the output transistor 111 switches from the ON state to the OFF state. G is the gate threshold voltage V G_TH In the process of decreasing from a voltage higher than G is the gate threshold voltage V G_TH When the resistance value of the channel of the output transistor 111 becomes less than 1 / 2, the resistance value of the channel of the output transistor 111 increases sharply, and the resistance value of the channel of the output transistor 111 becomes sufficiently larger than the resistance value of the pull-up resistor 52, and the output voltage V BUS increases to the power supply voltage VDD (however, when the backflow prevention diode 53 is provided, the output voltage V BUS rises to a voltage lower than the power supply voltage VDD by the forward voltage of the backflow prevention diode 53).

[0038] 3, the charging circuit 121 is configured with a series circuit of a charging current source 121a and a switch 121b, and the discharging circuit 122 is configured with a series circuit of a discharging current source 122a and a switch 122b. The charging current source 121a is connected to the internal power supply voltage VREG and the switch 121b, and REG Based on the current I C The switch 121b is provided between the charging current source 121a and a node 123. The discharging current source 122a is provided between the ground and the switch 122b, and generates the internal power supply voltage V REG Based on the current I D The switch 122b is provided between the discharging current source 122a and a node 123. The node 123 is connected to the gate of the output transistor 111. The switches 121b and 122b generate a control input signal S IN The power supply is controlled to be on or off based on the power supply voltage.

[0039] Control input signal S IN During the high level period of the control input signal S, the switch 121b is turned on, while the switch 122b is turned off. IN During the high level period, the gate voltage V G Current I to increase C (Hereinafter, charging current I C ) is supplied from the charging current source 121a to the gate of the output transistor 111 via the switch 121b and the node 123. IN During the low level period, no charge is transferred between the gate of the output transistor 111 and the charging circuit 121 .

[0040] Control input signal S IN During the low level period of the control input signal S, the switch 121b is turned off and the switch 122b is turned on. IN During the low level period, the gate voltage V G Current I to reduce D (Hereinafter, discharge current I D ) is drawn from the gate of the output transistor 111 to the discharging current source 122a via the node 123 and the switch 122b. IN During the high level period, no charge is transferred between the gate of the output transistor 111 and the discharge circuit 122 .

[0041] The control input signal supply circuit 130 receives the signal S from the microcomputer 20. T Based on the control input signal S IN and generates a control input signal S IN to the charge / discharge circuit 120. The control input signal supply circuit 130 supplies, for example, a signal S T The binary signal obtained by shaping the waveform of the control input signal S IN It may be generated as

[0042] Incidentally, the control input signal S IN During the high level period, the charging current I C The charging circuit 121 may have any configuration as long as it can supply the control input signal S IN During the low level period, the charging circuit 121 supplies a charging current I C In any case, the generation of the control input signal S IN During the low level period of C is zero. Similarly, the control input signal S IN During the low level period, the discharge current I D The discharge circuit 122 may have any configuration as long as it can draw in the control input signal S from the gate of the output transistor 111. IN During the high level period, the discharge circuit 122 discharges the discharge current I D In any case, the generation of the control input signal S IN During the high level period, a discharge current I flows from the gate of the output transistor 111 to the discharge circuit 122. D is zero.

[0043] The gate voltage limiting circuit 140 is connected to the gate of the output transistor 111 and ground. The gate voltage limiting circuit 140 has two diodes 141 and 142. The anode of the diode 141 is connected to the gate of the output transistor 111, and the cathode of the diode 141 is connected to the anode of the diode 142, and the cathode of the diode 142 is connected to ground. The gate voltage limiting circuit 140 limits the gate voltage V G is a predetermined limit voltage VLIM Any circuit can be used as long as it has the function of preventing the limit voltage V LIM is the gate threshold voltage V G_TH 3, it corresponds to the sum of the forward voltages of the diodes 141 and 142. The circuit 140 may be formed by a series circuit of three or more diodes.

[0044] Charging current I C Gate voltage V based on G In the process in which the output transistor 111 switches from the OFF state to the ON state due to the rise of BUS decreases, and the output voltage V BUS The decrease in the discharge current I is fed back to the gate of the output transistor 111 via the capacitor 112. D Gate voltage V based on G When the output transistor 111 switches from the ON state to the OFF state due to the decrease in BUS rises, and the output voltage V BUS The increase in the capacitance is fed back to the gate of the output transistor 111 via the capacitor 112. Therefore, to the charge / discharge circuit 120, the capacitance value of the capacitor 112 appears to be equivalently larger than the actual capacitance value of the capacitor 112 due to the Miller effect. In other words, the capacitor 112 functions as a Miller capacitance.

[0045] [Reference Operation] Figure 4 shows a timing chart of the reference operation. The reference operation is a signal transmission operation realized using the transmission circuit TX according to the basic configuration of Figure 3. As time passes, times t0, t1, t2, t3, t4, t5, t6 and t7 arrive in this order. At time t0, the control input signal S IN has a low level, and the gate voltage V G is 0V, and the output voltage V BUS is equal to the power supply voltage VDD. In the reference operation, the control input signal S IN During the high level period, the charging current I C is controlled to have a constant value, and the control input signal S IN During the low level period, the discharge current I DHowever, in reality, the control input signal S IN During the low level period of the gate voltage V G After the voltage drops to 0V, no current flows between the gate of the output transistor 111 and the discharge circuit 122. D =0" (in FIG. 4, the control input signal S IN During the low level period of D = 0" is not shown).

[0046] At time t1, the control input signal S IN Therefore, at time t1, the discharge current I D is stopped while the generation of the charging current I C Gate voltage V G At time t2, the gate voltage V G is the gate threshold voltage V G_TH When the resistance value of the channel of the output transistor 111 reaches a value close to t2, the resistance value of the channel of the output transistor 111 decreases from a sufficiently high value, and the output voltage V BUS The output voltage V begins to decrease from the power supply voltage VDD toward 0 V. At time t BUS When the gate voltage V G is the limiting voltage V by the gate voltage limiting circuit 140 LIM and the control input signal S IN until a down edge occurs at the clamping voltage V LIM It is maintained at

[0047] After that, at time t4, the control input signal S IN Therefore, at time t4, the charging current I C is stopped while the discharge current I D Gate voltage V G At time t5, the gate voltage V G is the gate threshold voltage V G_TH When the resistance value of the channel of the output transistor 111 rises from a sufficiently low value, the output voltage V BUSAt time t6, the output voltage V BUS After time t6, the gate voltage V G continues to decrease, and at time t G = 0". After that, the control input signal S IN until the next rising edge occurs. G = 0”, and therefore the output voltage V BUS The control input signal S IN When the next rising edge occurs, the same operation as that from time t1 onwards is repeated.

[0048] Output voltage V BUS The output signal denoted by is the control input signal S IN Specifically, the control input signal S IN The output signal is a logically inverted signal of the control input signal S IN (Therefore, the signal S from the microcomputer 20 T ) can be recognized and restored. By appropriately controlling the slew rate of the output signal, radiation noise from the bus line 51 can be suppressed.

[0049] At time t2, the output voltage V BUS The time t3 corresponds to the start time of the drop of the output voltage V BUS The time t5 corresponds to the end of the decrease in the output voltage V BUS The time t6 corresponds to the start time of the rise of the output voltage V BUS This corresponds to the end of the ascent.

[0050] In the reference operation, at times t2, t3, t5 and t6, the gate voltage V G Therefore, the output voltage V BUS In the waveform of the output voltage V, angles E1, E2, E3, and E4 occur at times t2, t3, t5, and t6, respectively. BUS The corners in the waveform of the output voltage V increase the radiated noise. BUSIf these corners could be eliminated from the waveform of Fig. 1, the radiation noise would be further suppressed. However, among the corners E1 to E4, the corner E4 may not actually occur due to the action of the low-pass filter formed by the pull-up resistor 52 and the capacitor 54.

[0051] Below, configurations, operations, applied techniques, etc. for removing the corners will be described in multiple examples. The matters described above in this embodiment apply to each of the following examples unless otherwise specified and unless there is a contradiction. If there are any matters in each example that contradict the matters described above, the description in that example may take precedence. Furthermore, unless there is a contradiction, matters described in any of the multiple examples shown below can also be applied to any of the other examples (i.e., any two or more of the multiple examples can also be combined).

[0052] <<First Example>> A first example will be described. In order to smooth the corners of the waveform of the output signal, the gate voltage V G In the first embodiment, a technique for smoothing the corners E1 and E3 in FIG. 4 (in other words, removing the corners E1 and E3 from the waveform of the output signal) will be described. In the first embodiment, the charging current source 121a supplies a current I C The discharge current source 122a is configured as a variable current source having a function of continuously varying the value of the current I D It is configured as a variable current source that has the function of continuously varying the value of

[0053] FIG. 5 shows the control input signal S IN , charging current I C and discharge current I D In reality, the control input signal S IN During the low level period of the gate voltage V G After the voltage drops to 0V, no current flows between the gate of the output transistor 111 and the discharge circuit 122. D =0" (in FIG. 5, the control input signal S IN During the low level period of D = 0" is not shown).

[0054] Control input signal S IN During the low level period, the charging current I C is zero. The control input signal S IN During the high level period of C to the gate of the output transistor 111. However, the charging current source 121a according to the first embodiment supplies the control input signal S IN When a rising edge occurs on the C The value of VAL is charged to the initial value VAL. C1 Then, the charging current I C The value of VAL is charged to the initial value VAL. C1 From the charging reference value VAL C2 The control input signal S IN During the high level period, the charging current I C The value is the charging reference value VAL C2 After reaching the charging current I C The value of this is the charging reference value VAL C2 It is good to maintain it.

[0055] Control input signal S IN A lower limit may be set for the length of the high level period of the charging current I C The value is the initial charging value VAL C1 After being set to , the charging reference value VAL C2 The time Tup_C1 until the control input signal S IN If the control input signal S IN After the rising edge of C The value is the charging reference value VAL C2 before the control input signal S IN When a down edge occurs, "I C = 0".

[0056] Control input signal S IN During the high level period, the discharge current I D is zero. The control input signal S IN During the low level period of Dfrom the gate of the output transistor 111. However, the discharging current source 122a according to the first embodiment is IN When a down edge occurs in D The value of this is the initial discharge value VAL D1 Then, the discharge current I D The value of this is the initial discharge value VAL D1 Discharge reference value VAL D2 The control input signal S IN During the low level period, the discharge current I D The value is the discharge reference value VAL D2 After reaching D The value of this is the discharge reference value VAL D2 It is good to maintain it.

[0057] Control input signal S IN A lower limit may be set for the length of the low level period of the discharge current I D The value is the initial discharge value VAL D1 After being set to , the discharge reference value VAL D2 The time Tup_D1 until the control input signal S IN If the control input signal S IN After the falling edge of D The value is the discharge reference value VAL D2 before the control input signal S IN When an up edge of occurs, "I D = 0".

[0058] Initial charging value VAL C1 and charging reference value VAL C2 is "0<VAL C1 <VAL C2 " has a predetermined value that satisfies "0=VAL C1 ". The discharge initial value VAL D1 and discharge reference value VAL D2 is "0<VAL D1 <VAL D2 " has a predetermined value that satisfies "0=VAL D1 ". The initial charging value VALC1 is the initial discharge value VAL D1 The charging reference value VAL may be the same as or different from the charging reference value VAL. C2 is the discharge reference value VAL D2 It may be the same value as or different from.

[0059] 6 is a timing chart according to the first embodiment. According to the first embodiment, the gate voltage V G As a result, the waveform at the corner E1 observed in the reference operation is smoother in the first embodiment than in FIG. 4, and radiation noise is reduced. Also, according to the first embodiment, the gate voltage V G As a result, the waveform observed at the corner E3 in the reference operation is smoother in the first embodiment than in Figure 4, and radiation noise is reduced.

[0060] The charge / discharge circuit 200 shown in Fig. 7 can be used as the charge / discharge circuit 120 in Fig. 3. The charge / discharge circuit 200 includes switches 121b and 122b and components referenced by reference numerals 201 to 212. It can be considered that the components referenced by reference numerals 201 to 212 form the current sources 121a and 122a in Fig. 3.

[0061] The constant voltage generating circuit 201 generates a voltage V REF The operational amplifier 202 generates and outputs a voltage V REF The inverting input terminal and the output terminal of the operational amplifier 202 are shorted. Therefore, the operational amplifier 202 functions as a voltage follower, and outputs a voltage V REFwith low impedance. The output terminal of operational amplifier 202 is connected to one end of resistor 204 and to node 213 via resistor 203. The other end of resistor 204 is connected to node 214. Node 213 is connected to ground via capacitor 205. Node 213 is also connected to one end of switch 209, the other end of which is connected to ground. Node 213 is also connected to one end of switch 207, the other end of which is connected to node 215. Node 214 is also connected to ground via capacitor 206. Node 214 is also connected to one end of switch 210, the other end of which is connected to node 215. One end of switch 208 is connected to node 214, and the other end of switch 208 is connected to ground.

[0062] The voltage applied to node 215 is designated by the symbol "V CNT1 The V / I conversion circuits 211 and 212 are connected to a node 215 to generate a voltage V CNT1 The V / I conversion circuit 211 receives the voltage V CNT1 current I C The V / I conversion circuit 212 converts the voltage V CNT1 current I D Convert to.

[0063] A switch 121b is interposed between the V / I conversion circuit 211 and a node 123 (see FIG. 3). IN The switch 121b is turned on only during the high level period of the current I obtained by the conversion of the V / I conversion circuit 211. C is the charging current I C The control input signal S is supplied to the gate of the output transistor 111. The switch 122b is interposed between the V / I conversion circuit 212 and the node 123 (see FIG. 3). IN The switch 122b is turned on only during the low level period of the current I obtained by the conversion of the V / I conversion circuit 212. D is the discharge current I D is drawn from the gate of the output transistor 111 as

[0064] 8 shows some waveforms relating to the operation of the charge / discharge circuit 200 of FIG. 7. The waveforms shown at the bottom of FIG. 8 are waveforms relating to the operation of the control input signal S IN Charging current I during the high level period C and the control input signal S IN Discharge current I during the low level period D In the charging / discharging circuit 200, the control input signal S IN The signals T_A and T_B are generated based on the control input signal S IN and the signal T_B is the same as the control input signal S IN The signal T_A is supplied to the switches 207 and 208 (i.e., the control input signal S IN The switches 207 and 208 are turned on during a high level period of the signal T_A, and turned off during a low level period of the signal T_A. A signal T_B is supplied to the switches 209 and 210 (i.e., a control input signal S IN (An inverted signal of signal T_B is supplied.) Switches 209 and 210 are turned on during a high level period of signal T_B, and are turned off during a low level period of signal T_B.

[0065] The V / I conversion circuit 211 converts the voltage V CNT1 When is 0V, the current I C The value of VAL is charged to the initial value VAL. C1 and set the voltage V CNT1 As the voltage rises from 0 V, the current I C By increasing the value of the voltage V CNT1 is the voltage V REF When the current I C The value of this is the charging reference value VAL C2 The V / I conversion circuit 212 sets the voltage V CNT1 When is 0V, the current I D The value of this is the initial discharge value VAL D1 and set the voltage V CNT1 As the voltage rises from 0 V, the current I D By increasing the value of the voltage V CNT1 is the voltage V REF When the current I D The value of this is the discharge reference value VAL D2Set to.

[0066] 7 will be described starting from the state of FIG. 9. In the state of FIG. 9, the control input signal S IN has a high level, and the voltage at node 213 is voltage V REF (hence "V CNT1 =V REF ") and the voltage of node 214 is 0V. Starting from the state of FIG. 9, the control input signal S IN 10, the switches 207 and 208 are switched to the OFF state and the switches 209 and 210 are switched to the ON state. Therefore, the voltage of the node 214, which was 0V in the state of FIG. 9, is applied to the node 215, and the voltage V CNT1 The voltage V CNT1 is the voltage V REF 10, the voltage at node 213 is 0V.

[0067] Voltage V CNT1 is the voltage V REF After reaching the control input signal S IN 11, the voltage of node 213, which was 0V in the state of FIG. 10, is applied to node 215, and the voltage V CNT1 The voltage V CNT1 is the voltage V REF The voltage at node 213 rises gradually (and therefore continuously) towards voltage V REF The state where this is reached corresponds to the state shown in Fig. 9. After that, the same operation is repeated.

[0068] The charging current I C and discharge current I DThe circuit configuration of the charge / discharge circuit 120 is arbitrary as long as the change characteristic of S is obtained. For example, the charge / discharge circuit 200a of Fig. 12 may be used as the charge / discharge circuit 120. Using the charge / discharge circuit 200 of Fig. 7 as a reference, the charge / discharge circuit 200 is modified into the charge / discharge circuit 200a by deleting the resistor 203, the capacitor 205, and the switches 207, 209, and 210 from the charge / discharge circuit 200 and adding a one-shot pulse generation circuit 218 to the charge / discharge circuit 200. The one-shot pulse generation circuit 218 generates a control input signal S IN The one-shot pulse generating circuit 218 outputs a signal T_A' based on the control input signal S. The signal T_A' has a low level as a rule. IN At the timing when a rising edge occurs and the timing when a falling edge occurs, the signal T_A' is set to high level for a predetermined short time. In the charging / discharging circuit 200a, the signal T_A' is supplied to the switch 208, and the switch 208 is turned on during the high level period of the signal T_A' and turned off during the low level period of the signal T_A'. Therefore, in the charging / discharging circuit 200a, the voltage of the node 214 is IN Whenever an up edge or down edge occurs in the voltage V REF In the charge / discharge circuit 200a, the voltage at the node 214 is always at the voltage V CNT1 Therefore, the current I generated in the V / I conversion circuits 211 and 212 of the charge / discharge circuit 200a C and I D The waveforms of the voltages are the same as those in the charge / discharge circuit 200.

[0069] <<Second Example>> A second example will be described. In the second example, another technique for smoothing the corners E1 and E3 in FIG. 4 (in other words, removing the corners E1 and E3 from the waveform of the output signal) will be described. In the second example, the charging current source 121a supplies a current I C The discharge current source 122a is configured as a variable current source having a function of varying the value of the current I DThe variable current source has a function of varying the value of the input voltage stepwise. The stepwise change is, in other words, a discontinuous change.

[0070] FIG. 13 shows the control input signal S IN , charging current I C and discharge current I D In reality, the control input signal S IN During the low level period of the gate voltage V G After the voltage drops to 0V, no current flows between the gate of the output transistor 111 and the discharge circuit 122. D =0" (in FIG. 13, the control input signal S IN During the low level period of D = 0" is not shown).

[0071] Control input signal S IN During the low level period, the charging current I C is zero. The control input signal S IN During the high level period of C to the gate of the output transistor 111. However, the charging current source 121a according to the second embodiment receives the control input signal S IN When a rising edge occurs on C The value of VAL is charged to the initial value VAL. C1 and the control input signal S IN After a predetermined time Tup_C2 has elapsed from the rising edge timing of C The value of VAL is charged to the initial value VAL. C1 From the charging reference value VAL C2 (i.e., increased stepwise). IN During the high level period, the charging current I C The value of this is the charging reference value VAL C2 After increasing the charging current to C The value of this is the charging reference value VAL C2 It is good to maintain it.

[0072] Control input signal S INThe time Tup_C2 may be set to a lower limit for the length of the high level period of the control input signal S IN If the control input signal S IN After the rising edge of C The value is the charging reference value VAL C2 before the control input signal S IN When a down edge occurs, "I C = 0".

[0073] Control input signal S IN During the high level period, the discharge current I D is zero. The control input signal S IN During the low level period of D from the gate of the output transistor 111. However, the discharging current source 122a according to the second embodiment is IN When a down edge occurs in D The value of this is the initial discharge value VAL D1 and the control input signal S IN After a predetermined time Tup_D2 has elapsed from the timing of the down edge of D The value of this is the initial discharge value VAL D1 Discharge reference value VAL D2 (i.e., increased stepwise). IN During the low level period, the discharge current I D The value of this is the discharge reference value VAL D2 After increasing the discharge current I D The value of this is the discharge reference value VAL D2 It is good to maintain it.

[0074] Control input signal S IN The time Tup_D2 may be set to a lower limit for the length of the low level period of the control input signal S IN If the control input signal S IN After the falling edge of D The value is the discharge reference value VAL D2 before the control input signal S INWhen an up edge of occurs, "I D = 0".

[0075] Value VAL C1 , VAL C2 , VAL D1 and VAL D2 The setting method is as described in the first embodiment (the same applies to the other embodiments described later).

[0076] As in the first embodiment, in the second embodiment, as shown in FIG. 6, the gate voltage V G Since the steep change in is less pronounced than in the reference operation, the same effect as in the first embodiment can be obtained.

[0077] The charging current I C and discharge current I D The circuit configuration of the charge / discharge circuit 120 is arbitrary as long as the change characteristic of the control input signal S can be obtained. For example, the charge / discharge circuit 250 shown in FIG. 14 can be used as the charge / discharge circuit 120 of FIG. 3. Some waveforms relating to the operation of the charge / discharge circuit 250 are shown in FIG. 15. The waveforms shown at the bottom of FIG. 15 are waveforms relating to the operation of the control input signal S IN Charging current I during the high level period C and the control input signal S IN Discharge current I during the low level period D This corresponds to a combination of the waveforms of

[0078] The charge / discharge circuit 250 includes switches 121b and 122b and components denoted by reference numerals 251 to 257. The components denoted by reference numerals 251 to 257 can be considered to form the current sources 121a and 122a in FIG. 3. The constant voltage generating circuit 251 generates a voltage V REF1 The constant voltage generating circuit 252 generates and outputs a voltage V REF2 where the voltage V REF1 than voltage V REF2 The voltage V REF1 is applied to one end of the switch 254, and the other end of the switch 253 is connected to a node 258. REF2is applied to the other end of switch 254, and the other end of switch 254 is connected to node 258. The voltage applied to node 258 is denoted by the symbol "V CNT2 " is expressed as

[0079] The V / I converter circuits 255 and 256 are connected to a node 258 to provide a voltage V CNT2 The V / I conversion circuit 255 receives the voltage V CNT2 current I C The V / I conversion circuit 256 converts the voltage V CNT2 current I D The switch control circuit 257 converts the control input signal S IN Based on this, the control circuit 210 generates signals T_A and T_B for controlling the on / off of switches 253 and 254. The switch 253 is on during a high level period of the signal T_A and is off during a low level period of the signal T_A. The switch 254 is on during a high level period of the signal T_B and is off during a low level period of the signal T_B.

[0080] The switch control circuit 257 receives a control input signal S IN The switch control circuit 257 is provided with a timer that measures the elapsed time from the rising edge timing or the falling edge timing of the control input signal S IN a first period from the rising edge timing of the control input signal S IN The signal T_A is set to a high level and the signal T_B is set to a low level only during the first period and the second period from the falling edge timing of "V CNT2 =V REF1 In a period different from either the first period or the second period, the switch control circuit 257 sets the signal T_A to a low level and the signal T_B to a high level to turn the switches 253 and 254 off and on, respectively, thereby controlling "V CNT2 =V REF2 " to be realized.

[0081] The V / I conversion circuit 255 converts "V CNT2 =V REF1When ", the current I C The value of VAL is charged to the initial value VAL. C1 Set it to "V CNT2 =V REF2 When ", the current I C The value of this is the charging reference value VAL C2 The V / I conversion circuit 256 is set to "V CNT2 =V REF1 When ", the current I D The value of this is the initial discharge value VAL D1 Set it to "V CNT2 =V REF2 When ", the current I D The value of this is the discharge reference value VAL D2 Set to.

[0082] The switch 121b is interposed between the V / I conversion circuit 255 and the node 123 (see FIG. 3). IN The switch 121b is turned on only during the high level period of the current I obtained by the conversion of the V / I conversion circuit 255. C is the charging current I C The control input signal S is supplied to the gate of the output transistor 111. The switch 122b is interposed between the V / I conversion circuit 256 and the node 123 (see FIG. 3). IN The switch 122b is turned on only during the low level period of the current I obtained by the conversion of the V / I conversion circuit 256. D is the discharge current I D is drawn from the gate of the output transistor 111 as

[0083] Charging current I C or discharge current I D Although the example in which the value of is variably set in two stages has been described, C or discharge current I D The value of the control input signal S may be variably set in three or more stages. IN When a rising edge occurs in C The value of VAL is charged to the initial value VAL. C1 and the control input signal S IN After the first predetermined time has elapsed from the rising edge timing ofC The value of VAL is charged to the initial value VAL. C1 to the charging intermediate value, and then, after a second predetermined time has elapsed, the charging current I C The value of VAL is converted from the intermediate charging value to the reference charging value VAL. C2 The intermediate charging value may be increased to the initial charging value VAL. C1 greater than the charge reference value VAL C2 Similarly, for example, the discharging current source 122a is smaller than the control input signal S IN When a down edge occurs in D The value of this is the initial discharge value VAL D1 and the control input signal S IN After the first predetermined time has elapsed from the timing of the falling edge of D The value of this is the initial discharge value VAL D1 to a discharge intermediate value, and then after a second predetermined time has elapsed, the discharge current I D The value of VAL is converted from the discharge intermediate value to the discharge reference value VAL. D2 The discharge intermediate value may be increased to the discharge initial value VAL. D1 and the discharge reference value VAL D2 Smaller than.

[0084] <<Third Example>> A third example will be described. The gate voltage V of the output transistor 111 G From 0V to the gate threshold voltage V G_TH If it takes a long time to raise the control input signal S IN The rising edge timing of the output voltage V BUS The time until the control input signal S starts to decrease becomes longer. In other words, the responsiveness of the transceiver 10 in relation to transmission decreases. This can be particularly noticeable when the method of the first or second embodiment is employed. When the method of the first or second embodiment is employed, the control input signal S IN The charging current I C This is because the gate voltage V GThe third embodiment can be implemented in particular in combination with the first or second embodiment. However, it is not essential to combine the third embodiment with the first or second embodiment, and the third embodiment can also be combined with other embodiments described below.

[0085] In the third embodiment, as shown in Fig. 16, a boost circuit 150 and a rise suppression diode 114 are added to the transmission circuit TX based on the configuration of the transmission circuit TX shown in Fig. 3. The boost circuit 150 is connected to the gate of the output transistor 111. The boost circuit 150 is connected to the gate of the output transistor 111 in response to a control input signal S IN It operates when a rising edge occurs in the gate voltage V G is a predetermined voltage (for example, a gate threshold voltage V G_TH ) is supplied to the gate of the output transistor 111. The boost current is a charge current I from the charging circuit 121. C is supplied to the gate of the output transistor 111 separately from G Specifically, the charging current I from the charging circuit 121 is increased. C Only the gate voltage V G Compared to the case where the gate voltage V G Increases the rate of ascent.

[0086] As a result, the control input signal S IN In response to the rising edge of the gate voltage V G The gate threshold voltage V G_TH This allows the antenna to be raised to near the ground, thereby improving the response of the transceiver 10 involved in transmission.

[0087] On the other hand, after the output transistor 111 switches from the off state to the on state, the gate voltage V G is the gate threshold voltage V G_TH If the control input signal S IN In response to the falling edge of the gate voltage V G is the gate threshold voltage V G_THThis is also one of the reasons for the slow response of the transceiver 10 in relation to transmission.

[0088] Taking this into consideration, in the third embodiment, a rise suppression diode 114 is provided in the transmission circuit TX, the anode of the rise suppression diode 114 is connected to the gate of the output transistor 111, and the cathode of the rise suppression diode 114 is connected to the drain of the output transistor 111.

[0089] The gate voltage V G is the voltage (V D111 +Vf 114 ) or less. D111 +Vf 114 ) is the drain voltage (V D111 ) than the forward voltage (Vf 114 ) is higher than the gate voltage V G is limited to the forward voltage of the suppression diode 114 or less. G_TH or the gate threshold voltage V G_TH As a result, after the output transistor 111 switches from the OFF state to the ON state, the gate voltage V G is the gate threshold voltage V G_TH Therefore, the response of the transceiver 10 in relation to transmission is improved.

[0090] In FIG. 17, the control input signal S IN In relation to the gate voltage V G In FIG. 17, a waveform 611 indicates the gate voltage V G A waveform 612 represents the gate voltage V G17. The waveform of the signal T_B shown in FIG. 17 will be referred to later. The provision of the boost circuit 150 increases the gate threshold voltage V G_TH Gate voltage V G It can be seen from the comparison of the waveforms 611 and 612 that the rate of rise of the gate voltage V G is the gate threshold voltage V G_TH It can be seen that it is difficult to increase beyond this level.

[0091] 18 shows an example of the configuration of the boost circuit 150. The boost circuit 150 in FIG. 18 includes a current source 151, transistors 152 to 154 which are N-channel MOSFETs, and a resistor 155. The current source 151 is connected to an internal power supply voltage V REG Based on the internal power supply voltage V REG A constant current is output from the application terminal of the node 156. However, due to the output of the constant current, the voltage of the node 156 becomes equal to the internal power supply voltage V REG When the internal power supply voltage V REG is applied. The source of the transistor 152 is connected to one end of a resistor 155 and also to the gate of the output transistor 111. The other end of the resistor 155 is connected to the gate of the transistor 153. The gate of the transistor 152 and the drains of the transistors 153 and 154 are connected to a node 156. The sources of the transistors 153 and 154 are connected to the ground. A signal T_B is supplied to the gate of the transistor 154. As described in the first embodiment, the signal T_B is supplied to the control input signal S IN This is the inverted signal of (see FIG. 17).

[0092] The operation of the boost circuit 150 in FIG. 18 will be described. INDuring the low level period of the control input signal S, the signal T_B is at a high level, so that the transistor 154 is turned on. When the transistor 154 is on, the constant current output from the current source 151 flows through the channel of the transistor 154, so that the potential of the node 156 is sufficiently low, and as a result, the transistor 152 is maintained in an off state. Since the boost current is supplied to the gate of the output transistor 111 via the transistor 152 only when the transistor 152 is on, no boost current is supplied when the transistor 152 is off. In addition, the control input signal S IN Immediately before the rising edge timing of G is set to 0 V, so the transistor 153 is in an off state.

[0093] Control input signal S IN When a rising edge of the control input signal S occurs, the signal T_B goes low, turning off the transistor 154. IN Immediately after the rising edge timing of the gate voltage V G When the internal power supply voltage V REG The drain current of the transistor 152 is supplied from the application terminal of the output transistor 111 to the gate of the output transistor 111 as a boost current.

[0094] Control input signal S IN After the rising edge of G When the potential of the node 156 rises to the gate threshold voltage V of the output transistor 111, the transistor 153 switches from off to on. Then, the potential of the node 156 drops, and the transistor 152 switches from on to off, and the supply of the boost current ends. The gate threshold voltage V of the transistor 153 (predetermined voltage) is G_TH or the gate threshold voltage V G_TH It would be better if it was slightly higher than that.

[0095] <<Fourth Embodiment>> A fourth embodiment will be described. In the fourth embodiment, a technique for smoothing the corner E2 in FIG. 4 (in other words, removing the corner E2 from the waveform of the output signal) will be described. In order to smooth the corner E2, the output voltage V BUS In the process of decreasing the output voltage V BUS When the voltage drops to near 0V, the charging current I C can be temporarily reduced.

[0096] Fig. 19 shows a charging circuit 300C according to a fourth embodiment. The charging circuit 300C can be used as the charging circuit 121 in Fig. 3. Fig. 20 shows some waveforms when the charging circuit 300C in Fig. 19 is used as the charging circuit 121. The output voltage V BUS The waveform in Fig. 4 is a waveform when it is assumed that only measures to smooth the corner E2 are taken, based on the reference operation of Fig. 4.

[0097] The charging circuit 300C includes a switch 121b and components denoted by reference numerals 301 to 308. The components denoted by reference numerals 301 to 308 can be considered to form the charging current source 121a in FIG. 3. The constant voltage generating circuit 301 generates a voltage V REF The operational amplifier 302 generates and outputs a voltage V REF The inverting input terminal and the output terminal of the operational amplifier 302 are shorted. Therefore, the operational amplifier 302 functions as a voltage follower, and outputs a voltage V REF With low impedance, the output terminal of the operational amplifier 302 is connected to one end of a resistor 303. The other end of the resistor 303 is connected to a node 311. The node 311 is connected to ground via a capacitor 304. The node 311 is also connected to one end of a switch 305, and the other end of the switch 305 is connected to ground.

[0098] The voltage applied to node 311 is designated by the symbol "V CNT4 The V / I conversion circuit 306 is connected to the node 311 and outputs a voltage V CNT4 The V / I conversion circuit 306 receives the voltage V CNT4 current I CConvert to.

[0099] The comparator 307 outputs an output voltage V BUS and a predetermined lower determination voltage V DET_L and outputs a signal indicating the comparison result. Specifically, the inverting input terminal and the non-inverting input terminal of the comparator 307 are connected to the output voltage V BUS , lower determination voltage V DET_L is input, and the comparator 307 outputs "V BUS <V DET_L " is established, a high level signal is output, and "V BUS >V DET_L When "V BUS =V DET_L When the voltage V is equal to or less than the threshold voltage V, the output signal of the comparator 307 has a high level or a low level. DET_L has a positive voltage value that is sufficiently smaller than the power supply voltage VDD, and is equal to the above voltage (VDD×k L ) lower is better.

[0100] The one-shot pulse generating circuit 308 outputs a signal T_C based on the output signal of the comparator 307. The signal T_C has a low level as a rule. The one-shot pulse generating circuit 308 sets the signal T_C to a high level for a predetermined short time when a rising edge occurs in the output signal of the comparator 307. The signal T_C is supplied to the switch 305, and the switch 305 is on during the high level period of the signal T_C and off during the low level period of the signal T_C. Therefore, in the charging circuit 300C, the voltage of the node 311 drops sharply to 0 V every time a rising edge occurs in the output signal of the comparator 307, and then rises to a voltage V REF It rises gradually (and therefore continuously) to

[0101] The V / I conversion circuit 306 converts the voltage V CNT4 When is 0V, the current I C The value of VAL is charged to the initial value VAL. C1 and set the voltage V CNT4 As the voltage rises from 0 V, the current I C By increasing the value of the voltage VCNT4 is the voltage V REF When the current I C The value of this is the charging reference value VAL C2 The switch 121b is interposed between the V / I conversion circuit 306 and the node 123 (see FIG. 3). The control input signal S IN The switch 121b is turned on only during the high level period of the current I obtained by the conversion of the V / I conversion circuit 306. C is the charging current I C is supplied to the gate of the output transistor 111 as a

[0102] By using the charging circuit 300C, the control input signal S IN The output voltage V during the high level period BUS During the decrease in output voltage V BUS is a predetermined lower determination voltage V DET_L When the charging current I C The value of is temporarily set to the charging reference value VAL. C2 In detail, the voltage will decrease from BUS <V DET_L " is established, the charging current I C The value is the charging reference value VAL C2 From the initial charging value VAL C1 After that, the charging reference value VAL is gradually (and therefore continuously) decreased over a predetermined period of time. C2 Return to.

[0103] In the charging circuit 121, "V BUS <V DET_L " is established, the charging current I C The value of this is the charging reference value VAL C2 From the initial charging value VAL C1 and the charging current I C The value of VAL is charged to the initial value VAL. C1 After maintaining the charging current I C The value of VAL is charged to the initial value VAL. C1 From the charging reference value VAL C2 That is, the charging current I C The value of VAL is gradually increased (discontinuously) to the reference charge value VAL. C2 At this time, the charging current I CThe value of VAL is charged to the initial value VAL. C1 From multiple stages to the charging reference value VAL C2 It may be possible to return it to .

[0104] According to the fourth embodiment, the gate voltage V G As a result, the waveform observed at the corner E2 in the reference operation is smoother in the fourth embodiment than in Fig. 4, and radiation noise is reduced.

[0105] The fourth embodiment can be combined with the first or second embodiment, and can also be combined with the third embodiment. When the fourth embodiment is combined with the first or second embodiment, the charge / discharge circuit 120 receives the control input signal S IN Charging current I in response to the rising edge of C The value of VAL is charged to the initial value VAL. C1 (see FIG. 5 or FIG. 13), the charging current I C The value of VAL is charged to the initial value VAL. C1 From the charging reference value VAL C2 Then, the control input signal S IN The output voltage V during the high level period BUS During the decrease in output voltage V BUS is a predetermined lower determination voltage V DET_L When the voltage Vcc falls below 1 V, the charging / discharging circuit 120 supplies a charging current I C The value of this is the charging reference value VAL C2 From the initial charging value VAL C1 Then, the charging reference value VAL is decreased to C2 (See FIG. 20).

[0106] <<Fifth Embodiment>> A fifth embodiment will be described. In the fifth embodiment, a technique for smoothing the corner E4 in FIG. 4 (in other words, removing the corner E4 from the waveform of the output signal) will be described. In order to smooth the corner E4, the output voltage V BUS During the rise of the output voltage V BUS When the voltage rises close to the power supply voltage VDD, the discharge current I D can be temporarily reduced.

[0107] Fig. 19 shows a discharge circuit 350D according to a fifth embodiment. The discharge circuit 350D can be used as the discharge circuit 122 in Fig. 3. Fig. 20 shows some waveforms when the discharge circuit 350D in Fig. 19 is used as the discharge circuit 122. Note that the output voltage V BUS The waveform in Fig. 4 is a waveform when it is assumed that only measures to smooth the corner E4 are taken in view of the reference operation in Fig. 4 .

[0108] The discharge circuit 350D includes a switch 122b and components denoted by reference numerals 351 to 358. The components denoted by reference numerals 351 to 358 can be considered to form the discharge current source 122a in FIG. 3. The constant voltage generating circuit 351 generates a voltage V REF The operational amplifier 352 generates and outputs a voltage V REF The inverting input terminal and the output terminal of the operational amplifier 352 are shorted. Therefore, the operational amplifier 352 functions as a voltage follower, and outputs a voltage V REF with low impedance. The output terminal of operational amplifier 352 is connected to one end of resistor 353. The other end of resistor 353 is connected to node 361. Node 361 is connected to ground via capacitor 354. Node 361 is also connected to one end of switch 355, and the other end of switch 355 is connected to ground.

[0109] The voltage applied to node 361 is designated by the symbol "V CNT5 The V / I conversion circuit 356 is connected to a node 361 and outputs a voltage V CNT5 The V / I conversion circuit 356 receives the voltage V CNT5 current I D Convert to.

[0110] The comparator 357 outputs an output voltage V BUS and a predetermined upper judgment voltage V DET_H Specifically, the comparator 357 compares the output voltage V BUS , upper judgment voltage V DET_His input, and the comparator 357 outputs "V BUS >V DET_H " is established, a high level signal is output, and "V BUS <V DET_H When "V BUS =V DET_H When the upper determination voltage V DET_H has a positive voltage value slightly lower than the power supply voltage VDD, and is equal to the above voltage (VDD×k H ) the higher the better.

[0111] The one-shot pulse generation circuit 358 outputs a signal T_D based on the output signal of the comparator 357. The signal T_D has a low level as a rule. The one-shot pulse generation circuit 358 sets the signal T_D to a high level for a predetermined short time at the timing when a rising edge occurs in the output signal of the comparator 357. The signal T_D is supplied to the switch 355, and the switch 355 is on during the high level period of the signal T_D and off during the low level period of the signal T_D. Therefore, in the discharge circuit 350D, the voltage of the node 361 drops sharply to 0 V every time a rising edge occurs in the output signal of the comparator 357, and then rises to a voltage V REF It rises gradually (and therefore continuously) to

[0112] The V / I conversion circuit 356 converts the voltage V CNT5 When is 0V, the current I D The value of this is the initial discharge value VAL D1 and set the voltage V CNT5 As the voltage rises from 0 V, the current I D By increasing the value of the voltage V CNT5 is the voltage V REF When the current I D The value of this is the discharge reference value VAL D2 The switch 122b is interposed between the V / I conversion circuit 356 and the node 123 (see FIG. 3). The control input signal S INThe switch 122b is turned on only during the low level period of the current I obtained by the conversion of the V / I conversion circuit 356. D is the discharge current I D is drawn from the gate of the output transistor 111 as

[0113] By using the discharge circuit 350D, the control input signal S IN The output voltage V BUS During the rise of the output voltage V BUS is a predetermined upper judgment voltage V DET_H When it exceeds the discharge current I D The value of VAL is temporarily set to the discharge reference value VAL. D2 In detail, the voltage will decrease from BUS >V DET_H " triggered the discharge current I D The value is the discharge reference value VAL D2 From discharge initial value VAL D1 After that, it gradually (and therefore continuously) decreases to the discharge reference value VAL over a predetermined period of time. D2 Return to.

[0114] In the discharge circuit 122, BUS >V DET_H " triggered the discharge current I D The value of this is the discharge reference value VAL D2 From discharge initial value VAL D1 and the discharge current I D The value of this is the initial discharge value VAL D1 After maintaining the discharge current I D The value of this is the initial discharge value VAL D1 Discharge reference value VAL D2 That is, the discharge current I D The value of VAL is gradually increased (discontinuously) to the discharge reference value VAL. D2 At this time, the discharge current I D The value of this is the initial discharge value VAL D1 Discharge reference value VAL through multiple stages D2 It may be possible to return it to .

[0115] According to the fifth embodiment, the gate voltage V GThe sharp change in the waveform at corner E4 observed in the reference operation is less pronounced than in the reference operation. As a result, the waveform at corner E4 observed in the reference operation is smoother in the fifth embodiment than in Figure 4, thereby reducing radiated noise. Note that, depending on the values ​​of the pull-up resistor 52 and capacitor 54 (see Figure 3) connected to the bus line 51, the waveform at corner E4 may be sufficiently smooth even without any countermeasures being taken on the transceiver 10 side. Therefore, the countermeasures of the fifth embodiment are not necessarily required in the transceiver 10.

[0116] The fifth embodiment can be combined with the first or second embodiment, and can also be combined with the third embodiment. When the fifth embodiment is combined with the first or second embodiment, the charge / discharge circuit 120 receives the control input signal S IN A discharge current I D The value of this is the initial discharge value VAL D1 (see FIG. 5 or FIG. 13), the discharge current I D The value of this is the initial discharge value VAL D1 Discharge reference value VAL D2 Then, the control input signal S IN The output voltage V BUS During the rise of the output voltage V BUS is a predetermined upper judgment voltage V DET_H When the voltage Vcc exceeds 1 V, the charging / discharging circuit 120 generates a discharge current I D The value of this is the discharge reference value VAL D2 From discharge initial value VAL D1 Then, the discharge reference value VAL is decreased to D2 (See FIG. 22).

[0117] <<Sixth Embodiment>> A sixth embodiment will be described. In the sixth embodiment, supplementary matters, applied techniques, modified techniques, etc. to the above-mentioned techniques will be described.

[0118] The communication system 1 can be mounted in a vehicle such as an automobile. In the vehicle, the communication system 1 can be used as a system for performing two-way communication in accordance with the LIN standard or the CXPI standard. More specifically, the communication between the transceiver 10 and the counterpart device 30 can be used for communication of signals for realizing body control of the vehicle, such as power windows, mirrors, power seats, or door locks.

[0119] However, the communication system 1 is not limited to in-vehicle applications, and can be applied to any application in which relatively low-speed communication is performed.

[0120] The transceiver 10 includes a signal transmitter that generates an output signal corresponding to an input signal at a bus connection terminal BUS that functions as an output terminal (in other words, transmits from the bus connection terminal BUS). Components of the signal transmitter include a transmitter circuit TX and may also include the bus connection terminal BUS. An input signal for the signal transmitter is a control input signal S IN The control input signal S IN is the signal S from the microcomputer 20 T Since the signal is based on the signal S T A semiconductor device incorporating the functions of the transceiver 10 and the microcomputer 20 may be formed, in which case a signal transmitting device is provided within the semiconductor device.

[0121] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0122] The channel types of the FETs (field effect transistors) shown in each embodiment are merely examples. The channel type of any FET may be changed between P-channel and N-channel types without departing from the spirit of the above.

[0123] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor other than an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0124] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0125] <<Supplementary Notes>> Supplementary notes are provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0126] A signal transmission device (10) according to one aspect of the present disclosure includes an output terminal (BUS) configured to be connected to an application terminal (50) of a power supply voltage (VDD) via a pull-up resistor (52), an output transistor (111) provided between the output terminal and ground, a capacitor (112) connected between the gate of the output transistor and the output terminal, and an input signal (S INa charge / discharge circuit (120) configured to charge or discharge the gate of the output transistor in response to the input signal, thereby generating an output signal at the output terminal in response to the input signal by turning on or off the output transistor through charging or discharging the gate of the output transistor, and the charge / discharge circuit supplies a charging current (I) to the gate of the output transistor when the input signal has a first level (e.g., a high level). C ) to turn on the output transistor by raising the gate voltage of the output transistor, and discharging a discharge current (I) from the gate of the output transistor when the input signal has a second level (e.g., a low level). D ) to reduce the gate voltage, thereby turning off the output transistor, and the charge / discharge circuit variably sets the value of the charge current or the discharge current when switching the output transistor between on and off in response to a change in the level of the input signal (first configuration).

[0127] This eliminates the sharp edges in the gate voltage waveform of the output transistor when the output transistor is switched on and off, and in turn eliminates the sharp edges in the output signal waveform, thereby reducing radiation noise.

[0128] In the signal transmission device according to the first configuration, the charge / discharge circuit changes the value of the charging current to a predetermined initial charging value (VAL) in response to the change of the level of the input signal from the second level to the first level. C1 ), and then a predetermined charging reference value (VAL C2 ) (second configuration).

[0129] This makes it possible to remove the corner portion (E1) of the output signal waveform when the output transistor switches from off to on, thereby reducing radiation noise.

[0130] In the signal transmission device according to the first or second configuration, the charge / discharge circuit changes the value of the discharge current to a predetermined discharge initial value (VAL) in response to a change in the level of the input signal from a first level to a second level. D1), and then a predetermined discharge reference value (VAL D2 ) (third configuration).

[0131] This makes it possible to remove the corner portion (E3) of the output signal waveform when the output transistor switches from on to off, thereby reducing radiation noise.

[0132] The signal transmission device according to any one of the first to third configurations may further include a boost circuit (150) connected to the gate of the output transistor, and the boost circuit may be configured to increase the rate of rise of the gate voltage of the output transistor by supplying a boost current to the gate of the output transistor separately from the charging current from the charging / discharging circuit when the level of the input signal switches from the second level to the first level (fourth configuration).

[0133] This increases the responsiveness of the signal transmitting device.

[0134] In the signal transmission device according to the fourth configuration, the boost circuit may be configured to supply the boost current to the gate of the output transistor until the gate voltage of the output transistor rises to a predetermined voltage after the level of the input signal switches from the second level to the first level (fifth configuration).

[0135] In the signal transmission device according to any of the first to fifth configurations, a rise suppression diode (114) having a forward direction from the gate of the output transistor toward the drain of the output transistor may be provided between the gate and drain of the output transistor (sixth configuration).

[0136] This prevents the gate voltage of the output transistor from rising excessively, which contributes to improving the response of the signal transmitting device.

[0137] In the signal transmission device according to any one of the first to sixth configurations, in the process of decreasing the voltage of the output signal during the period in which the input signal has a first level, the voltage of the output signal is lowered to a predetermined lower determination voltage (V DET_L), the charge / discharge circuit may be configured to reduce the value of the charging current (seventh configuration).

[0138] This makes it possible to remove the corresponding angular portion (E2) that may be included in the output signal waveform, thereby reducing radiation noise.

[0139] In the signal transmission device according to any one of the first to seventh configurations, in the process of increasing the voltage of the output signal during the period in which the input signal has the second level, the voltage of the output signal is increased to a predetermined upper determination voltage (V DET_H ) the charge / discharge circuit may be configured to reduce the value of the discharge current (eighth configuration).

[0140] This makes it possible to remove the corresponding angular portion (E4) that may be included in the output signal waveform, thereby reducing radiation noise.

[0141] In the signal transmission device according to any of the first to eighth configurations, the charge / discharge circuit may be configured (ninth configuration) to have a charging circuit (121) configured to supply the charging current to the gate of the output transistor during a period when the input signal has a first level, and a discharging circuit (122) configured to draw the discharging current from the gate of the output transistor during a period when the input signal has a second level.

[0142] In the signal transmission device according to any of the first to ninth configurations, the drain of the output transistor may be connected to the output terminal via a backflow prevention diode (113) having a forward direction from the output terminal toward ground, or the drain of the output transistor may be directly connected to the output terminal (tenth configuration).

[0143] In the signal transmission device according to any of the first to tenth configurations, the output terminal may be connected to the power supply voltage application terminal via the pull-up resistor and a backflow prevention diode (53) having a forward direction from the power supply voltage application terminal toward the output terminal (eleventh configuration).

[0144] 1 Communication system 10 Transceiver 20 Microcomputer 30 Counterpart device 50 Application terminal 51 Bus line 52 Pull-up resistor 53 Backflow prevention diode 54 Capacitor 61, 62 Data line 63 Pull-up resistor VIN Power supply terminal BUS Bus connection terminal GND Ground terminal RXD Received data output terminal TXD Transmitted data input terminal RX Receive circuit TX Transmit circuit 111 Output transistor 112 Capacitor 113 Backflow prevention diode 114 Suppression diode 120 Charging / discharging circuit 121 Charging circuit 121a Charging current source 122 Discharging circuit 122a Discharging current source 121b, 122b Switch 130 Control input signal supply circuit 140 Gate voltage limiting circuit 141, 142 Diode 150 Boost circuit 151 Current source 152 to 154 Transistor 155 Resistor S IN Control input signal V G Gate voltage V BUS Voltage 200, 200a Charging / discharging circuit 201 Constant voltage generating circuit 202 Operational amplifier 203, 204 Resistor 205, 206 Capacitor 207-210 Switch 211, 212 V / I conversion circuit 218 One-shot pulse generating circuit 250 Charging / discharging circuit 251, 252 Constant voltage generating circuit 253, 254 Switch 255, 256 V / I conversion circuit 257 Switch control circuit 300C Charging circuit 350D Discharging circuit 301, 351 Constant voltage generating circuit 302, 352 Operational amplifier 303, 353 Resistor 304, 354 Capacitor 305, 355 Switch 306, 356 V / I conversion circuit 307, 357 Comparator 308, 358 One-shot pulse generator

Claims

1. an output terminal configured to be connected to an application end of a power supply voltage via a pull-up resistor; an output transistor provided between the output terminal and ground; a capacitor connected between the gate of the output transistor and the output terminal; a charge / discharge circuit configured to charge or discharge the gate of the output transistor in response to an input signal, and generating an output signal corresponding to the input signal at the output terminal by turning on or off the output transistor through charging or discharging the gate of the output transistor; the charge / discharge circuit supplies a charging current to a gate of the output transistor to increase a gate voltage of the output transistor when the input signal has a first level, thereby turning on the output transistor, and draws a discharging current from the gate of the output transistor to decrease the gate voltage when the input signal has a second level, thereby turning off the output transistor; The charge / discharge circuit variably sets a value of the charge current or a value of the discharge current when switching the output transistor between on and off in response to a change in the level of the input signal. , signal transmitting device.

2. The charge / discharge circuit sets a value of the charging current to a predetermined charging reference value in response to a change in the level of the input signal from the second level to the first level.

2. A signal transmitting device according to claim 1.

3. The charge / discharge circuit sets a value of the discharge current to a predetermined discharge initial value in response to a change in the level of the input signal from a first level to a second level, and then increases the value of the discharge current to a predetermined discharge reference value.

2. A signal transmitting device according to claim 1.

4. a boost circuit connected to the gate of the output transistor; When the level of the input signal switches from the second level to the first level, the boost circuit supplies a boost current to the gate of the output transistor in addition to the charging current from the charging / discharging circuit, thereby increasing the rate of rise of the gate voltage of the output transistor. A signal transmitting device according to any one of claims 1 to 3.

5. The boost circuit supplies the boost current to the gate of the output transistor until the gate voltage of the output transistor rises to a predetermined voltage after the level of the input signal switches from the second level to the first level.

5. A signal transmitting device according to claim 4.

6. A rise suppression diode having a forward direction from the gate of the output transistor to the drain of the output transistor is provided between the gate and the drain of the output transistor. A signal transmitting device according to any one of claims 1 to 3.

7. When the voltage of the output signal falls below a predetermined lower determination voltage during a process of decreasing the voltage of the output signal while the input signal has a first level, the charge / discharge circuit decreases the value of the charging current. A signal transmitting device according to any one of claims 1 to 3.

8. When the voltage of the output signal exceeds a predetermined upper determination voltage during a process of increasing the voltage of the output signal while the input signal has a second level, the charge / discharge circuit reduces the value of the discharge current. A signal transmitting device according to any one of claims 1 to 3.

9. The charge / discharge circuit includes a charging circuit configured to supply the charging current to the gate of the output transistor during a period when the input signal has a first level, and a discharging circuit configured to sink the discharging current from the gate of the output transistor during a period when the input signal has a second level. A signal transmitting device according to any one of claims 1 to 3.

10. The drain of the output transistor is connected to the output terminal via a reverse current prevention diode having a forward direction from the output terminal to the ground, or the drain of the output transistor is directly connected to the output terminal. A signal transmitting device according to any one of claims 1 to 3.

11. The output terminal is connected to the application terminal of the power supply voltage via the pull-up resistor and a backflow prevention diode having a forward direction from the application terminal of the power supply voltage toward the output terminal. A signal transmitting device according to any one of claims 1 to 3.