Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device according to the present invention is provided with: a support body; a first semiconductor element and a second semiconductor element disposed on a first side, of the support body, in the thickness direction; and a sealing body which covers part of the support body and the first semiconductor element and the second semiconductor element. The support body has a first surface that faces a second side in the thickness direction and is exposed from the sealing body, and the first surface has an uneven region constituted of a plurality of dot-like recesses overlapping each other.

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Semiconductor devices including semiconductor elements are used, for example, as power modules for configuring inverters. Patent Document 1 discloses an example of a conventional semiconductor device. The semiconductor device disclosed in this document includes a plurality of switching elements and a heat sink for dissipating heat from these switching elements. The heat sink is made of a metal plate, one side of which is exposed to the outside. One side of the heat sink is placed on an installation surface, such as an external water-cooled jacket.

[0003] JP 2018-182330 A

[0004] A paste-like substance such as thermal compound is placed between one side of the heat sink and the installation surface. The thermal compound promotes heat dissipation by filling the gap between the one side of the heat sink and the installation surface. For example, if the temperature repeatedly rises and falls during operation of the semiconductor device, the thermal compound may be forced out and leak due to factors such as the difference in thermal expansion between the semiconductor device and the water-cooled jacket.

[0005] An object of the present disclosure is to provide an improved semiconductor device compared to conventional semiconductor devices. In particular, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device and a method for manufacturing a semiconductor device that can prevent objects interposed between the semiconductor device and the installation surface from leaking out.

[0006] A semiconductor device according to a first aspect of the present disclosure includes a support, a semiconductor element disposed on a first side of the support in a thickness direction, and an encapsulant covering a portion of the support and the semiconductor element. The support has a first surface facing a second side in the thickness direction and exposed from the encapsulant. The first surface has an uneven region formed by a plurality of overlapping dot-shaped recesses.

[0007] A second aspect of the present disclosure provides a method for manufacturing a semiconductor device comprising: a support; a semiconductor element arranged on a first side in a thickness direction of the support; and a sealing body covering a portion of the support and the semiconductor element, wherein the support has a first surface facing a second side in the thickness direction and exposed from the sealing body, and the method comprises irradiating the first surface with a pulsed laser to form an uneven region composed of a plurality of overlapping dot-shaped recesses.

[0008] According to the above configuration, it is possible to prevent objects interposed between the device and the installation surface from leaking out.

[0009] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0010] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 3 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 4 is a bottom view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 3. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 3. FIG. 7 is a circuit diagram of a semiconductor device according to a first embodiment of the present disclosure. FIG. 8 is a partial enlarged plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 9 is a partial enlarged cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 10 is a partial enlarged plan view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. FIG. 11 is a partial enlarged cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. FIG. 12 is a bottom view showing a first modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 13 is a bottom view showing a second modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 14 is a bottom view showing a third modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 15 is a bottom view showing a fourth modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 16 is a bottom view showing a fifth modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 17 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present disclosure. FIG. 18 is a cross-sectional view showing a semiconductor device according to the second embodiment of the present disclosure. FIG. 19 is a perspective view showing a semiconductor device according to a third embodiment of the present disclosure. FIG. 20 is a partial plan view showing a semiconductor device according to the third embodiment of the present disclosure. FIG. 21 is a bottom view showing a semiconductor device according to the third embodiment of the present disclosure. FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 20. FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 20. FIG. 24 is a circuit diagram of the semiconductor device according to the third embodiment of the present disclosure. FIG. 25 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present disclosure. FIG. 26 is a cross-sectional view showing a semiconductor device according to the fourth embodiment of the present disclosure.

[0011] Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0012] The terms "first," "second," "third," etc. in this disclosure are used for identification purposes only and are not intended to impose any ranking on their objects.

[0013] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, in the present disclosure, "a surface A faces in (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0014] 1 to 9, a semiconductor device A10 according to a first embodiment of the present disclosure will be described. The semiconductor device A10 includes a support 1, a plurality of first semiconductor elements 2A, a plurality of second semiconductor elements 2B, a sealing body 3, a plurality of main current terminals 4, and a plurality of control terminals 5. For ease of understanding, FIG. 3 shows a transparent view of a sealing resin 32 and a cover 33, which will be described later.

[0015] FIG. 1 is a perspective view showing the semiconductor device A10. FIG. 2 is a plan view showing the semiconductor device A10. FIG. 3 is a partial plan view showing the semiconductor device A10. FIG. 4 is a bottom view showing the semiconductor device A10. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 3. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 3. FIG. 7 is a circuit diagram of the semiconductor device A10. FIG. 8 is a partially enlarged plan view showing the semiconductor device A10. FIG. 9 is a partially enlarged cross-sectional view showing the semiconductor device A10.

[0016] The semiconductor device A10 shown in FIG. 1 is a power module. The semiconductor device A10 is used, for example, in inverter devices for various electrical appliances. As shown in FIGS. 1 and 2 , the semiconductor device A10 is rectangular when viewed from the thickness direction z of the support 1. Here, an example of a direction perpendicular to the thickness direction z is referred to as the "first direction x." The direction perpendicular to the thickness direction z and the first direction x is referred to as the "second direction y." The longitudinal direction of the semiconductor device A10 is the second direction y.

[0017] Support 1: The support 1 supports a plurality of first semiconductor elements 2A and a plurality of second semiconductor elements 2B. The support 1 includes a first metal layer 11, a second metal layer 12, and an insulating layer 13. The specific configuration of the support 1 is not limited in any way. The support 1 of the present disclosure may be configured to include the first metal layer 11.

[0018] First metal layer 11 is a layer containing a metal such as Cu (copper) as a main component. First metal layer 11 has a first surface 111, as shown in FIGS. 5 and 6 . First surface 111 is exposed on the z2 side in the z direction from sealing body 3. Details of first surface 111 will be described later.

[0019] The first metal layer 11 also has a plurality of support holes 115. The plurality of support holes 115 are arranged at the four corners of the first metal layer 11, and each penetrates the first metal layer 11 in the z direction.

[0020] The insulating layer 13 is disposed on the z1 side of the first metal layer 11 in the z direction. The insulating layer 13 is made of an insulating material, mainly composed of ceramics such as AlN (aluminum nitride) or Al2O3 (alumina). In this embodiment, the insulating layer 13 includes a first region 13A, a second region 13B, and a third region 13C. The first region 13A is disposed closest to the x1 side in the x direction. The second region 13B is disposed closest to the x2 side in the x direction. The third region 13C is disposed between the first region 13A and the second region 13B in the x direction.

[0021] In this embodiment, as shown in Figures 5 and 6, the insulating layer 13 is bonded to the first metal layer 11 via a third metal layer 141 and a bonding layer 142. The third metal layer 141 is made of a metal material such as copper foil. The bonding layer 142 is a bonding material interposed between the first metal layer 11 and the third metal layer 141. In the semiconductor device A10, the constituent material of the bonding layer 142 is a lead-free solder containing tin as a main component.

[0022] As shown in FIGS. 5 and 6 , the second metal layer 12 is disposed on the z1 side of the insulating layer 13 in the z direction. The second metal layer 12 is in direct contact with the insulating layer 13. The second metal layer 12 is primarily composed of a metal such as Cu (copper). The second metal layer 12 of this embodiment includes a first region 121A, a first region 122A, a first region 123A, a second region 121B, a second region 122B, a second region 123B, a third region 121C, a third region 122C, and a third region 123C. Furthermore, the second metal layer 12 of the illustrated example includes a plurality of other small regions.

[0023] The first region 121A is disposed on the x1 side in the first direction x with respect to the first region 123A. The first region 122A is disposed on the x2 side in the first direction x with respect to the first region 123A. The second region 123B is disposed on the y2 side in the y direction with respect to the first region 123A. The second region 121B is disposed on the x1 side in the first direction x with respect to the second region 123B. The second region 122B is disposed on the x2 side in the first direction x with respect to the second region 123B. The third region 123C is disposed on the y2 side in the y direction with respect to the second region 123B. The third region 121C is disposed on the x1 side in the first direction x with respect to the third region 123C. The third region 122C is disposed on the x2 side in the first direction x with respect to the third region 123C.

[0024] The first region 121A, the first region 122A, and the first region 123A are electrically connected to one another by a plurality of wires. The second region 121B, the second region 122B, and the second region 123B are electrically connected to one another by a plurality of wires. The third region 121C, the third region 122C, and the third region 123C are electrically connected to one another by a plurality of wires.

[0025] In this embodiment, the second metal layer 12, the insulating layer 13, and the third metal layer 141 constitute a so-called DBC (Direct Bonding Copper) substrate. The DBC substrate and the first metal layer 11 are bonded via a bonding layer 142. Such a configuration of the support 1 is an example of the support of the present disclosure, and is not limited to this.

[0026] Plural first semiconductor elements 2A, plural second semiconductor elements 2B: The plural first semiconductor elements 2A and plural second semiconductor elements 2B are supported by the support body 1. As shown in Fig. 3, the plural first semiconductor elements 2A are mounted on first regions 121A, 122A, and 123A of the second metal layer 12. The plural second semiconductor elements 2B are mounted on second regions 121B, 122B, and 123B of the second metal layer 12.

[0027] The first semiconductor element 2A and the second semiconductor element 2B are MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) configured using semiconductor materials primarily containing, for example, silicon carbide (SiC) or silicon (Si). The first semiconductor element 2A and the second semiconductor element 2B are not limited to MOSFETs and may be insulated gate bipolar transistors (IGBTs). In the description of the semiconductor device A10, the first semiconductor element 2A and the second semiconductor element 2B are n-channel MOSFETs configured using semiconductor materials primarily containing silicon carbide (SiC). In this embodiment, a protection element such as a diode is connected to each of the first semiconductor element 2A and the second semiconductor element 2B.

[0028] The drain electrodes of the plurality of first semiconductor elements 2A are conductively joined to the first region 121A, the first region 122A, and the first region 123A of the second metal layer 12. The drain electrodes of the plurality of second semiconductor elements 2B are conductively joined to the second region 121B, the second region 122B, and the second region 123B of the second metal layer 12. The source electrodes of the plurality of first semiconductor elements 2A are conductively connected to the first region 122A, the second region 122B, and the second region 123B by a plurality of wires. The source electrodes of the plurality of second semiconductor elements 2B are conductively connected to the third region 121C, the third region 122C, and the third region 123C by a plurality of wires.

[0029] Sealing body 3: The sealing body 3 seals and protects the first semiconductor elements 2A and the second semiconductor elements 2B. There are no limitations on the specific configuration of the sealing body 3. In this embodiment, the sealing body 3 includes a case 31, a sealing resin 32, and a cover 33.

[0030] 3 , the case 31 is an electrically insulating member that surrounds the first semiconductor elements 2A, the second semiconductor elements 2B, and the second metal layer 12 when viewed from the thickness direction z. The case 31 is, for example, frame-shaped. The case 31 is mainly composed of a synthetic resin that has electrical insulation properties and excellent heat resistance, such as PPS (polyphenylene sulfide).

[0031] The case 31 of this embodiment has a plurality of mounting holes 39. The positions of the plurality of mounting holes 39 correspond to the plurality of support holes 115 provided in the first metal layer 11. The plurality of mounting holes 39 and the plurality of support holes 115 are used to mount the semiconductor device A10 to, for example, a heat sink (not shown).

[0032] As shown in Figures 5 and 6, the sealing resin 32 is contained in an area surrounded by the support 1 and the case 31. The sealing resin 32 covers the first semiconductor elements 2A and the second semiconductor elements 2B. The sealing resin 32 is preferably a synthetic resin that has excellent heat resistance and adhesion, as well as electrical insulation. The sealing resin 32 is, for example, a silicone gel whose main component is a thermosetting organopolysiloxane.

[0033] 2, 5, and 6, the cover 33 closes the internal region of the semiconductor device A10 formed by the support 1 and the case 31 from the z1 side in the z direction. The cover 33 is made of an electrically insulating synthetic resin.

[0034] Multiple main current terminals 4: The multiple main current terminals 4 are terminals through which the main current switched by the semiconductor device A10 is input and output. In this embodiment, as shown in Figures 1 to 3, 5 and 6, the multiple main current terminals 4 include a first power supply terminal 41, a second power supply terminal 42 and two output terminals 43.

[0035] The first power supply terminal 41 is disposed on the x1 side in the first direction x and is conductively connected to the first region 121A via a plurality of wires, thereby electrically connecting the first power supply terminal 41 to the drain electrodes of a plurality of first semiconductor elements 2A.

[0036] The second power supply terminal 42 is disposed on the x1 side in the first direction x and on the y2 side in the second direction y relative to the first power supply terminal 41. The second power supply terminal 42 is conductively connected to the third region 121C via multiple wires, thereby electrically connecting the second power supply terminal 42 to the source electrodes of multiple second semiconductor elements 2B.

[0037] The two output terminals 43 are arranged on the x2 side in the first direction x. The two output terminals 43 are conductively connected to the second region 122B via multiple wires. As a result, the two output terminals 43 are conductively connected to the source electrodes of the multiple first semiconductor elements 2A and the drain electrodes of the multiple second semiconductor elements 2B.

[0038] Multiple control terminals 5: The multiple control terminals 5 are terminals through which control signals, detection signals, etc. for operating the semiconductor device A10 are input and output. As shown in Figures 1 and 3 , the multiple control terminals 5 are arranged on both ends of the case 31 of the sealing body 3 in the second direction y, and protrude to the z1 side in the z direction.

[0039] The plurality of control terminals 5 include a first gate terminal 51A and a second gate terminal 51B. The first gate terminal 51A is electrically connected to the gate electrodes of the plurality of first semiconductor elements 2A. The second gate terminal 51B is electrically connected to the gate electrodes of the plurality of second semiconductor elements 2B. The other control terminals 5 are used as appropriate, for example, a source sense terminal, a temperature monitoring terminal, a current monitoring terminal, a voltage monitoring terminal, etc.

[0040] 7 shows the circuit configuration of the semiconductor device A10. The semiconductor device A10 has a half-bridge circuit including an upper arm circuit 81 and a lower arm circuit 82. The upper arm circuit 81 is composed of a first region 121A, a first region 122A, and a first region 123A, and a plurality of first semiconductor elements 2A electrically connected thereto. The plurality of first semiconductor elements 2A are connected in parallel between a first power supply terminal 41 and an output terminal 43. The gate electrodes of the plurality of first semiconductor elements 2A in the upper arm circuit 81 are connected in parallel to a first gate terminal 51A. A gate voltage is applied to the first gate terminal 51A by a drive circuit, such as a gate driver, arranged outside the semiconductor device A10, thereby simultaneously driving the plurality of first semiconductor elements 2A in the upper arm circuit 81.

[0041] The lower arm circuit 82 is composed of second regions 121B, 122B, and 123B, and a plurality of second semiconductor elements 2B electrically connected thereto. The plurality of second semiconductor elements 2B are connected in parallel between the output terminal 43 and the second power supply terminal 42. The gate electrodes of the plurality of second semiconductor elements 2B in the lower arm circuit 82 are connected in parallel to the second gate terminal 51B. A gate voltage is applied to the second gate terminal 51B by a drive circuit such as a gate driver arranged outside the semiconductor device A10, thereby simultaneously driving the plurality of second semiconductor elements 2B in the lower arm circuit 82.

[0042] 4, 8, and 9, the first surface 111 of the first metal layer 11 has a concave-convex region 7. The first surface 111 may include the concave-convex region 7 and other regions, or may have the concave-convex region 7 provided over its entire surface. In the illustrated example, the concave-convex region 7 is provided over the entire surface of the first surface 111.

[0043] The concave-convex region 7 is made up of a plurality of overlapping dot-shaped recesses 71. As shown in Figures 8 and 9, adjacent recesses 71 are arranged so that they partially overlap each other. The plurality of recesses 71 are arranged along a plurality of arrangement lines 70. For convenience, the plurality of arrangement lines 70 are shown as lines connecting the centers of the plurality of recesses as viewed in the thickness direction z.

[0044] The shape, size, and arrangement of the multiple placement lines 70 are not limited in any way. In the illustrated example, the multiple placement lines 70 are curved lines with different radii of curvature. The multiple placement lines 70 are arranged concentrically. In the illustrated example, the multiple placement lines 70 are circular.

[0045] 9 is a line obtained by averaging the shape lines of the plurality of recesses 71. In this embodiment, the average line 75 is along a plane including the first direction x and the second direction y.

[0046] The size of each of the plurality of recesses 71 is not limited in any way. For example, the depth of the plurality of recesses 71 in the thickness direction z is 0.5 μm or more and 10 μm or less. Furthermore, the pitch of the plurality of arrangement lines 70 is not limited in any way. For example, the pitch of the plurality of arrangement lines 70 is 10 μm or more and 200 μm or less.

[0047] 10 and 11 show a process of forming the concave-convex region 7 on the first surface 111 in the manufacturing method of the semiconductor device A10. In this process, a pulsed laser L is irradiated onto the first surface 111 to form a plurality of concave portions 71.

[0048] The pulsed laser L is appropriately selected from those capable of forming the desired plurality of recesses 71 on the first surface 111. When the first metal layer 11 is mainly composed of Cu (copper), the pulsed laser L may be, for example, a UV-A (long wavelength ultraviolet) laser with a wavelength of 380 to 320 nm or a green laser with a wavelength of 560 to 500 nm, and the wavelength may be set to, for example, 355 nm or 532 nm.

[0049] For example, by controlling an optical system that irradiates the pulsed laser L, the pulsed laser L is irradiated along a plurality of arrangement lines 70. As a result, a plurality of recesses 71 are sequentially formed on the first surface 111. In the illustrated example, the center-to-center distance between adjacent recesses 71 is smaller than the size of the recess 71 formed by one pulse of the pulsed laser L. As a result, the adjacent recesses 71 are sequentially formed so as to overlap each other. By continuing this irradiation of the pulsed laser L, an uneven region 7 is formed on the first surface 111.

[0050] Next, the operation of the semiconductor device A10 and the method for manufacturing the semiconductor device A10 will be described.

[0051] When the semiconductor device A10 is used, for example, as a power module constituting an on-board inverter, it is installed with the first surface 111 facing the installation surface of a water-cooled jacket, heat sink, or the like. An object, such as a thermal compound, is disposed between the first surface 111 and the installation surface. During operation of the semiconductor device A10, temperature rises and falls. Due to differences in thermal expansion between the first metal layer 11 and the water-cooled jacket, heat sink, or the like, there is a concern that the thermal compound may be extruded to the outside and leak out from between the first surface 111 and the installation surface. According to this embodiment, as shown in FIGS. 4 , 8 , and 9 , the first surface 111 of the support 1 has an uneven region 7. The uneven region 7 is composed of a plurality of adjacent dot-shaped recesses 71. This prevents the thermal compound or other object disposed between the first surface 111 and the first surface 111 from leaking out.

[0052] 10 and 11 , a plurality of recesses 71 are formed by irradiating the first surface 111 with a pulsed laser L. This makes it possible to form a plurality of recesses 71 of a desired depth and size in a desired region at a desired arrangement density.

[0053] The recesses 71 are arranged along the arrangement lines 70. This makes it possible to prevent the arrangement density of the recesses 71 from becoming excessively uneven.

[0054] The plurality of arrangement lines 70 includes a plurality of curves with different radii of curvature. In this embodiment, the plurality of arrangement lines 70 are a plurality of concentrically arranged circles. This allows the plurality of recesses 71 to be arranged more evenly from the center of the concentric arrangement toward the outside.

[0055] The manufacturing method using the pulsed laser L is preferable for forming the plurality of recesses 71 along the plurality of arrangement lines 70, which are curves having different radii of curvature. For example, when forming the uneven region 7 consisting of the plurality of recesses 71 by mechanical cutting, it is very difficult to form the plurality of recesses 71 along the plurality of arrangement lines 70 that are concentrically arranged.

[0056] 12 to 26 show other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are given the same reference numerals. Furthermore, the configurations of the various parts in each of the modified examples and embodiments can be combined with each other as appropriate within the scope of not causing technical contradictions.

[0057] First Modification of First Embodiment: Figure 12 shows a first modification of the semiconductor device A10. The semiconductor device A11 of this modification differs from the semiconductor device A10 described above in the shape of the multiple placement lines 70 in the uneven region 7. In this modification, the multiple placement lines 70 are elliptical, with the major axis direction being the first direction x and the minor axis direction being the second direction y. The multiple placement lines 70 are arranged concentrically.

[0058] This modification also makes it possible to prevent leakage of objects interposed between the first surface 111 and the installation surface. Furthermore, as can be understood from this modification, the configuration in which the multiple arrangement lines 70 are concentrically arranged is not limited to a configuration in which the arrangement lines 70 are circular. Furthermore, the multiple arrangement lines 70 may be configured to include both circles and ellipses.

[0059] Second Modification of First Embodiment: Figure 13 shows a second modification of the semiconductor device A10. The semiconductor device A12 of this modification is an ellipse in which multiple placement lines 70 are concentrically arranged. The placement lines 70 of this modification are elliptical, with the major axis direction being the second direction y and the minor axis direction being the first direction x. In other words, the minor axis direction of the multiple placement lines 70 coincides with the longitudinal direction of the first surface 111.

[0060] This modification also makes it possible to suppress leakage of an object interposed between the first surface 111 and the installation surface. Furthermore, as can be seen from this modification, the major axis direction and the minor axis direction of the arrangement line 70 when the arrangement line 70 is elliptical are not limited in any way. Furthermore, the pitch of the multiple arrangement lines 70 in the first direction x, which is the minor axis direction, is smaller than the pitch in the second direction y, which is the major axis direction. This makes it possible to set the pitch of the multiple arrangement lines 70 in the first direction x, which is the longitudinal direction of the first surface 111, to be smaller. Therefore, this modification is preferable for suppressing leakage of an object, such as a thermal compound, interposed between the first surface 111 and the installation surface in the first direction x.

[0061] 14 shows a third modification of the semiconductor device A10. In the semiconductor device A13 of this modification, the plurality of arrangement lines 70 are straight. In this modification, the plurality of arrangement lines 70 are aligned along the second direction y, which is the short-side direction of the first surface 111.

[0062] This modification also makes it possible to suppress leakage of an object interposed between the first surface 111 and the installation surface. Furthermore, as can be understood from this modification, the multiple arrangement lines 70 may be curved or straight. Furthermore, if the arrangement lines 70 are straight, there is no limitation as to the direction along which the straight lines extend. In this modification, the multiple arrangement lines 70 are straight lines extending along the second direction y, which is the short-side direction of the first surface 111, and are arranged in the first direction x, which is the long-side direction of the first surface 111. This is preferable for suppressing leakage of an object, such as a thermal compound, interposed between the first surface 111 and the installation surface in the first direction x.

[0063] Fourth Modification of First Embodiment: Figure 15 shows a fourth modification of the semiconductor device A10. In the semiconductor device A14 of this modification, the multiple placement lines 70 include curved and straight lines. More specifically, the multiple placement lines 70 include multiple circles arranged concentrically. The multiple placement lines 70 also include multiple straight lines arranged on both sides of the multiple circles in the first direction x. The multiple straight lines extend along the second direction y and are arranged in the first direction x.

[0064] This modification also makes it possible to prevent leakage of an object interposed between the first surface 111 and the installation surface. Furthermore, as can be understood from this modification, the plurality of arrangement lines 70 may be configured to include curved and straight lines. Furthermore, by arranging the plurality of arrangement lines 70, which are a plurality of straight lines along the second direction y, on both sides of the first direction x, which is the longitudinal direction of the first surface 111, it is possible to prevent leakage of an object, such as a thermal compound, interposed between the first surface 111 and the installation surface in the first direction x.

[0065] 16 shows a fifth modification of the semiconductor device A10. The semiconductor device A15 of this modification has a concave-convex region 7 in a portion of the first surface 111. The concave-convex region 7 of this modification has an annular shape when viewed in the thickness direction z, and more specifically, an elongated rectangular annular shape with the first direction x as the longitudinal direction. A flat surface region where the multiple recesses 71 are not formed is provided inside the concave-convex region 7.

[0066] This modification also makes it possible to prevent leakage of matter interposed between first surface 111 and the installation surface. Furthermore, as can be understood from this modification, uneven region 7 may be provided only on a portion of first surface 111. By providing uneven region 7 on the peripheral portion of first surface 111, it is possible to prevent matter such as the thermal compound from leaking from the peripheral portion of first surface 111.

[0067] 17 and 18 show a semiconductor device according to a second embodiment of the present disclosure. In the semiconductor device A20 of this embodiment, the mean line 75 of the concave-convex region 7 on the first surface 111 bulges toward the z2 side in the thickness direction z. The size of the bulging shape of the concave-convex region 7 as viewed in the thickness direction z is not limited in any way. The size of the bulging shape as viewed in the thickness direction z is set to, for example, at least one-third of the size of the first surface 111 in the short direction.

[0068] The uneven region 7, in which the average line 75 bulges toward the z2 side in the thickness direction z, can be formed, for example, by setting the irradiation output or irradiation time of the pulsed laser L that forms the multiple recesses 71 to be smaller or shorter the closer to the center of the first surface 111, and larger or longer the farther away from the center.

[0069] This embodiment also prevents leakage of objects interposed between the first surface 111 and the installation surface. The semiconductor device A20 is installed on the installation surface S shown in FIGS. 17 and 18 by inserting bolts or the like through the support holes 115. During installation, the mean line 75 of the uneven region 7 bulges toward the z2 side in the thickness direction z, so that the center portion of the first surface 111 first contacts the installation surface S. At this time, the four corners of the first surface 111 are relatively spaced apart from the installation surface S. Next, increasing the fastening force of the bolts or the like generates a moment that bends the first metal layer 11 from the four corners toward the z2 side in the thickness direction z. This brings the four corners of the first surface 111 closer to the installation surface S. This allows the entire surface of the first surface 111 to more reliably contact or approach the installation surface S.

[0070] 19 to 24 show a semiconductor device according to a third embodiment of the present disclosure. A semiconductor device A30 of this embodiment includes a support 1, a plurality of first semiconductor elements 2A, a plurality of second semiconductor elements 2B, a sealing body 3, a plurality of main current terminals 4, a plurality of control terminals 5, a first conductive member 61, and a second conductive member 62.

[0071] Fig. 19 is a perspective view showing the semiconductor device A30. Fig. 20 is a plan view of a main part of the semiconductor device A30. Fig. 21 is a bottom view of the semiconductor device A30. Fig. 22 is a cross-sectional view taken along line XXII-XXII in Fig. 20. Fig. 23 is a cross-sectional view taken along line XXIII-XXIII in Fig. 20. Fig. 24 is a circuit diagram of the semiconductor device A30.

[0072] Support 1: The support 1 supports a plurality of first semiconductor elements 2A and a plurality of second semiconductor elements 2B. The specific configuration of the support 1 is not limited in any way, and in this embodiment, it is configured, for example, as a DBC (Direct Bonded Copper) substrate or an AMB (Active Metal Brazing) substrate. The support 1 includes an insulating layer 13, a second metal layer 12, and a first metal layer 11. The second metal layer 12 includes a first region 12A and a second region 12B. The dimension of the support 1 in the thickness direction z is, for example, not less than 0.4 mm and not more than 3.0 mm.

[0073] The first metal layer 11 is formed on the lower surface (surface facing the z2 side in the thickness direction z) of the insulating layer 13. The constituent material of the first metal layer 11 includes, for example, Cu (copper). The first metal layer 11 has a first surface 111. The first surface 111 is a flat surface facing the z2 side in the thickness direction z. As shown in FIGS. 21 , 22 , and 23 , the first surface 111 is exposed from the sealing body 3. In a plan view, the first metal layer 11 overlaps both the first region 12A and the second region 12B.

[0074] In this embodiment as well, the first surface 111 is provided with the concave-convex region 7. The specific configuration of the concave-convex region 7 can be set to various configurations, including the configurations of the above-described embodiment and modified examples.

[0075] The insulating layer 13 is made of, for example, a ceramic having excellent thermal conductivity as a main component, such as silicon nitride (SiN). The insulating layer 13 is not limited to ceramics and may be made of an insulating resin sheet or the like. The insulating layer 13 has, for example, a rectangular shape in a plan view. The dimension of the insulating layer 13 in the thickness direction z is, for example, 0.05 mm or more and 1.0 mm or less.

[0076] The second metal layer 12 is formed on the z1 side of the insulating layer 13 in the z direction. The constituent material of the second metal layer 12 includes, for example, Cu (copper). The constituent material may include, for example, Al (aluminum) other than Cu (copper). The dimension of the second metal layer 12 in the thickness direction z is, for example, 0.1 mm or more and 1.5 mm or less.

[0077] In this embodiment, the second metal layer 12 has a first region 12A and a second region 12B. The first region 12A and the second region 12B are spaced apart in the first direction x. The first region 12A is located on the x1 side of the second region 12B in the first direction x. The first region 12A and the second region 12B each have, for example, a rectangular shape in a plan view. The first region 12A and the second region 12B, together with the first conductive member 61 and the second conductive member 62, form a path for a main circuit current switched by the multiple first semiconductor elements 2A and the multiple second semiconductor elements 2B.

[0078] Multiple first semiconductor elements 2A, multiple second semiconductor elements 2B: The multiple first semiconductor elements 2A and multiple second semiconductor elements 2B are electronic components that are the functional core of the semiconductor device A30. The constituent material of each of the first semiconductor elements 2A and each of the second semiconductor elements 2B is a semiconductor material primarily composed of, for example, silicon carbide (SiC). This semiconductor material is not limited to SiC and may be silicon (Si), gallium nitride (GaN), diamond (C), or the like. Each of the first semiconductor elements 2A and each of the second semiconductor elements 2B is, for example, a power semiconductor chip with a switching function, such as a metal oxide semiconductor field effect transistor (MOSFET).

[0079] In this embodiment, the first semiconductor element 2A and the second semiconductor element 2B are MOSFETs, but are not limited thereto and may be other transistors such as IGBTs (Insulated Gate Bipolar Transistors). Each of the first semiconductor element 2A and each of the second semiconductor elements 2B is the same element. Each of the first semiconductor element 2A and each of the second semiconductor elements 2B is, for example, an n-channel MOSFET, but may also be a p-channel MOSFET.

[0080] The drain electrodes of the plurality of first semiconductor elements 2A are conductively joined to the first region 12A, and the drain electrodes of the plurality of second semiconductor elements 2B are conductively joined to the second region 12B.

[0081] Sealing body 3: The sealing body 3 covers the multiple first semiconductor elements 2A, the multiple second semiconductor elements 2B, the support body 1 (excluding the first surface 111), a portion of each of the multiple main current terminals 4, a portion of each of the multiple control terminals 5, the first conductive member 61, and the second conductive member 62. The sealing body 3 of this embodiment is made of, for example, black epoxy resin. The sealing body 3 is formed, for example, by molding. The sealing body 3 has, for example, a dimension in the first direction x of about 35 mm to 60 mm, a dimension in the second direction y of about 35 mm to 50 mm, and a dimension in the thickness direction z of about 4 mm to 15 mm. These dimensions are the sizes of the largest portions along each direction.

[0082] Multiple main current terminals 4: The multiple main current terminals 4 are terminals through which the main current switched by the semiconductor device A30 is input and output. In this embodiment, the multiple main current terminals 4 include a first power supply terminal 41, two second power supply terminals 42, and two output terminals 43. Each of these main current terminals 4 is made of a plate-shaped metal plate. This metal plate contains, for example, Cu (copper) or a Cu (copper) alloy.

[0083] The first power supply terminal 41 is disposed on the x1 side in the first direction x. The first power supply terminal 41 is conductively joined to the first region 12A. As a result, the first power supply terminal 41 is conductively connected to the drain electrodes of the multiple first semiconductor elements 2A.

[0084] The two second power supply terminals 42 are arranged on the x1 side in the first direction x and on both sides of the first power supply terminal 41 in the second direction y. The two second power supply terminals 42 are conductively connected to the source electrodes of the plurality of second semiconductor elements 2B via second conductive members 62. The second conductive members 62 are made of, for example, a plate-shaped metal plate. The metal plate contains, for example, Cu (copper) or a Cu (copper) alloy. The second conductive members 62 may be formed integrally with the two second power supply terminals 42.

[0085] The two output terminals 43 are arranged on the x2 side in the first direction x. The two output terminals 43 are conductively connected to the second region 12B. The second region 12B is also conductively connected to the source electrodes of the multiple first semiconductor elements 2A via the first conductive members 61. As a result, the two output terminals 43 are conductively connected to the source electrodes of the multiple first semiconductor elements 2A and the drain electrodes of the multiple second semiconductor elements 2B. The first conductive members 61 are made of, for example, a plate-shaped metal plate. This metal plate contains, for example, Cu (copper) or a Cu (copper) alloy.

[0086] Multiple control terminals 5: The multiple control terminals 5 are terminals through which control signals, detection signals, etc. for operating the semiconductor device A30 are input and output. As shown in FIG. 1 , the multiple control terminals 5 protrude from the sealing body 3 to the z1 side in the z direction.

[0087] The plurality of control terminals 5 include a first gate terminal 51A and a second gate terminal 51B. The first gate terminal 51A is electrically connected to the gate electrodes of the plurality of first semiconductor elements 2A. The second gate terminal 51B is electrically connected to the gate electrodes of the plurality of second semiconductor elements 2B. The other control terminals 5 are used as appropriate, for example, a source sense terminal, a temperature monitoring terminal, a current monitoring terminal, a voltage monitoring terminal, etc.

[0088] 24 shows the circuit configuration of the semiconductor device A30. Similar to the semiconductor device A10, the semiconductor device A30 has a half-bridge circuit including an upper arm circuit 81 and a lower arm circuit 82. The upper arm circuit 81 is composed of a first region 12A and a plurality of first semiconductor elements 2A electrically connected thereto. The plurality of first semiconductor elements 2A are connected in parallel between a first power supply terminal 41 and an output terminal 43. The gate electrodes of the plurality of first semiconductor elements 2A in the upper arm circuit 81 are connected in parallel to a first gate terminal 51A. A gate voltage is applied to the first gate terminal 51A by a drive circuit, such as a gate driver, arranged outside the semiconductor device A30, thereby simultaneously driving the plurality of first semiconductor elements 2A in the upper arm circuit 81.

[0089] The lower arm circuit 82 is composed of a second region 12B and a plurality of second semiconductor elements 2B electrically connected thereto. The plurality of second semiconductor elements 2B are connected in parallel between the output terminal 43 and the second power supply terminal 42. The gate electrodes of the plurality of second semiconductor elements 2B in the lower arm circuit 82 are connected in parallel to the second gate terminal 51B. A gate voltage is applied to the second gate terminal 51B by a drive circuit such as a gate driver arranged outside the semiconductor device A30, thereby simultaneously driving the plurality of second semiconductor elements 2B in the lower arm circuit 82.

[0090] This embodiment also makes it possible to prevent leakage of an object interposed between first surface 111 and the installation surface. Furthermore, as can be understood from this embodiment, the specific configuration of the semiconductor device according to the present disclosure configured as a power module is not limited in any way.

[0091] 25 and 26 show a semiconductor device according to a fourth embodiment of the present disclosure. In the semiconductor device A40 of this embodiment, the mean line 75 of the concave-convex region 7 on the first surface 111 is recessed toward the z1 side in the thickness direction z. The size of the recessed shape of the concave-convex region 7 as viewed in the thickness direction z is not limited in any way. The size of the recessed shape as viewed in the thickness direction z is set to, for example, at least one-third of the size of the first surface 111 in the short side direction.

[0092] The uneven region 7, in which the average line 75 is recessed toward the z2 side in the thickness direction z, can be formed, for example, by setting the irradiation output or irradiation time of the pulsed laser L that forms the multiple recesses 71 to be larger or longer the closer to the center of the first surface 111, and smaller or shorter the farther away from the center.

[0093] This embodiment also prevents leakage of an object interposed between the first surface 111 and the installation surface. Furthermore, as shown in FIGS. 25 and 26 , the semiconductor device A40 is installed on the installation surface S by, for example, pressing the central portion of the sealing body 3 on the z1 side in the thickness direction z. During this installation, because the mean line 75 of the uneven region 7 is recessed toward the z1 side in the thickness direction z, the four corners of the first surface 111 first contact the installation surface S. At this time, the central portion of the first surface 111 is relatively spaced apart from the installation surface S. Next, by increasing the force pressing the sealing body 3, the central portion of the first metal layer 11 approaches the installation surface S. Therefore, the entire surface of the first surface 111 can be more reliably brought into contact with or close to the installation surface S.

[0094] The semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure are not limited to the above-described embodiments. The specific configurations of the semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure can be freely designed in various ways. The present disclosure includes the embodiments described in the following appendices.

[0095] Supplementary Note 1. A semiconductor device comprising: a support; a semiconductor element arranged on a first side in a thickness direction of the support; and an encapsulant covering a portion of the support and the semiconductor element, wherein the support has a first surface facing a second side in the thickness direction and exposed from the encapsulant, and the first surface has an uneven region formed by a plurality of overlapping dot-shaped recesses. Supplementary Note 2. The semiconductor device according to Supplementary Note 1, wherein the recesses are arranged along a plurality of arrangement lines. Supplementary Note 3. The semiconductor device according to Supplementary Note 2, wherein the plurality of arrangement lines include a plurality of curves having different radii of curvature. Supplementary Note 4. The semiconductor device according to Supplementary Note 3, wherein the plurality of arrangement lines are arranged concentrically. Supplementary Note 5. The semiconductor device according to Supplementary Note 4, wherein the plurality of arrangement lines are circular or elliptical. Supplementary Note 6. The semiconductor device according to any one of Supplements 2 to 5, wherein the plurality of arrangement lines includes a straight arrangement line. Supplementary Note 7. The semiconductor device according to Supplementary Note 6, wherein the first surface has a shape whose longitudinal direction is a first direction orthogonal to the thickness direction, and the plurality of arrangement lines include straight arrangement lines along the thickness direction and a second direction intersecting the first direction. Supplementary Note 8. The semiconductor device according to any of Supplements 1 to 7, wherein the uneven region is provided on the entire surface of the first surface. Supplementary Note 9. The semiconductor device according to any of Supplements 1 to 8, wherein the uneven region has a shape whose average line is recessed toward the first side in the thickness direction or bulged toward the second side. Supplementary Note 10. The semiconductor device according to any of Supplements 1 to 9, wherein the support includes a first metal layer constituting the first surface. Supplementary Note 11. The semiconductor device according to Supplementary Note 10, wherein the first metal layer is mainly composed of Cu. Supplementary Note 12. The semiconductor device according to Supplementary Note 11, wherein the support includes an insulating layer arranged on the first side in the thickness direction with respect to the first metal layer. Supplementary Note 13. 13. The semiconductor device according to claim 12, wherein the support includes a second metal layer disposed on the first side in the thickness direction with respect to the insulating layer. 14. The semiconductor device according to claim 13, wherein the semiconductor element is mounted on the second metal layer.Appendix 15. The semiconductor device according to Appendix 14, comprising a plurality of the semiconductor elements, wherein the second metal layer includes a first region and a second region spaced apart in a direction intersecting the thickness direction, and the plurality of semiconductor elements includes a first semiconductor element mounted in the first region and a second semiconductor element mounted in the second region. Appendix 16. The semiconductor device according to Appendix 15, wherein the first semiconductor element and the second semiconductor element are switching elements. Appendix 17. The semiconductor device according to Appendix 16, comprising a half-bridge circuit including an upper arm circuit formed by the first semiconductor element and a lower arm circuit formed by the second semiconductor element. Appendix 18. A method for manufacturing a semiconductor device, comprising: a support; semiconductor elements arranged on a first side in a thickness direction of the support; and a sealing body covering a part of the support and the semiconductor elements, wherein the support has a first surface facing a second side in the thickness direction and exposed from the sealing body, the method comprising: irradiating the first surface with a pulsed laser to form a concave-convex region formed by a plurality of overlapping dot-shaped recesses.

[0096] A10, A11, A12, A13, A14, A15, A20, A30, A40: semiconductor device 1: support 2A: first semiconductor element 2B: second semiconductor element 3: sealing body 4: main current terminal 5: control terminal 7: uneven region 11: first metal layer 12: second metal layer 12A: first region 12B: second region 13: insulating layer 13A: first region 13B: second region 13C: third region 31: case 32: sealing resin 33: cover 39: mounting hole 41: first power supply terminal 42: second power supply terminal 43: output terminal 51A: first gate terminal 51B: second gate terminal 61: first conductive member 62: second conductive member 70: arrangement line 71: recess 75: average line 81: upper arm circuit 82: Lower arm circuit 111: First surface 115: Support hole 121A: First region 121B: Second region 121C: Third region 122A: First region 122B: Second region 122C: Third region 123A: First region 123B: Second region 123C: Third region 141: Third metal layer 142: Bonding layer L: Pulse laser S: Installation surface x: First direction y: Second direction z: Thickness direction

Claims

1. A support; A semiconductor element disposed on a first side in a thickness direction of the support; a sealing body that covers a part of the support and the semiconductor element, the support body has a first surface facing a second side in the thickness direction and exposed from the sealing body; The first surface has an uneven area formed of a plurality of overlapping dot-shaped recesses.

2. The semiconductor device according to claim 1 , wherein the recesses are arranged along a plurality of layout lines.

3. The semiconductor device according to claim 2 , wherein said plurality of placement lines include a plurality of curved lines each having a different radius of curvature.

4. The semiconductor device according to claim 3 , wherein said plurality of placement lines are arranged concentrically.

5. The semiconductor device according to claim 4 , wherein said plurality of placement lines are circular or elliptical.

6. 6. The semiconductor device according to claim 2, wherein said plurality of layout lines include a straight layout line.

7. The first surface has a shape whose longitudinal direction is a first direction perpendicular to the thickness direction, The semiconductor device according to claim 6 , wherein the plurality of arrangement lines include straight arrangement lines extending along the thickness direction and a second direction intersecting the first direction.

8. 6. The semiconductor device according to claim 1, wherein the uneven area is provided on the entire surface of the first surface.

9. 6. The semiconductor device according to claim 1, wherein the uneven region has an average line that is recessed toward the first side in the thickness direction or that bulges toward the second side.

10. 6. The semiconductor device according to claim 1, wherein the support includes a first metal layer constituting the first surface.

11. The semiconductor device according to claim 10 , wherein the first metal layer is mainly composed of Cu.

12. The semiconductor device according to claim 11 , wherein the support includes an insulating layer disposed on the first side in the thickness direction with respect to the first metal layer.

13. The semiconductor device according to claim 12 , wherein the support includes a second metal layer disposed on the first side in the thickness direction with respect to the insulating layer.

14. The semiconductor device according to claim 13 , wherein the semiconductor element is mounted on the second metal layer.

15. A plurality of the semiconductor elements are provided, the second metal layer includes a first region and a second region spaced apart in a direction intersecting the thickness direction, 15. The semiconductor device according to claim 14, wherein the plurality of semiconductor elements include a first semiconductor element mounted in the first region and a second semiconductor element mounted in the second region.

16. The semiconductor device according to claim 15 , wherein the first semiconductor element and the second semiconductor element are switching elements.

17. 17. The semiconductor device according to claim 16, further comprising a half-bridge circuit including an upper arm circuit constituted by said first semiconductor element and a lower arm circuit constituted by said second semiconductor element.

18. A support; A semiconductor element disposed on a first side in a thickness direction of the support; a sealing body that covers a part of the support and the semiconductor element, a first surface of the support body facing a second side in the thickness direction and exposed from the sealing body, A method for manufacturing a semiconductor device, comprising: irradiating the first surface with a pulsed laser to form a concave-convex region composed of a plurality of overlapping dot-shaped concave portions.