Semiconductor device

Abstract

This semiconductor device is provided with: a main substrate which has a first main metal layer; a first semiconductor element supported by the main substrate; a first sub-substrate supported by the main substrate; and a sealing resin which covers the first semiconductor element. The first sub-substrate has: a sub insulating layer; and a first sub metal layer and a second sub metal layer with the sub insulating layer interposed therebetween in the thickness direction. The second sub metal layer is conductively bonded to the first main metal layer. The first sub metal layer includes a region. The first sub-substrate further has a connection conductive part which electrically connects the region and the second sub metal layer to each other.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Conventionally, semiconductor devices including power switching elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) have been known. Such semiconductor devices are installed in a wide variety of electronic devices, from industrial equipment to home appliances, information terminals, and automotive equipment. Patent Document 1 (Patent Document 1) discloses a conventional semiconductor device (power module). The semiconductor device disclosed in Patent Document 1 includes a semiconductor element, a main substrate, and a substrate. The main substrate has a metal layer. The semiconductor element is conductively bonded to the metal layer. The sub-substrate is supported by the main substrate. The semiconductor device disclosed in Patent Document 1 also includes a support substrate (ceramic substrate). The support substrate supports the semiconductor element. The support substrate includes an insulating base material and conductor layers laminated on both sides of the base material. The base material is made of, for example, ceramic. Each conductor layer is made of, for example, Cu (copper), and a semiconductor element is bonded to one of the conductor layers. Wires made of, for example, Al are used to electrically connect the semiconductor element and the conductor layers.

[0003] Japanese Patent Application Laid-Open No. 2021-190505

[0004] When monitoring the potential of the metal layer of the main board from the outside, the configuration of the conduction path is limited, for example, by connecting a wire to the metal layer, etc. Furthermore, when a wire is used, there is a possibility that an unintended phenomenon may occur at the junction interface of different metals, such as between a conductor layer made of Cu and a wire made of Al.

[0005] The present disclosure was conceived in light of the above-mentioned circumstances, and has as its object to provide an improved semiconductor device compared to conventional devices. In particular, the present disclosure has as its object to provide a semiconductor device and a vehicle that allow for more diverse configurations of conduction paths to the main board. Another object of the present disclosure is to provide a semiconductor device that can suppress unintended phenomena occurring between dissimilar metals.

[0006] A semiconductor device provided by a first aspect of the present disclosure comprises a main substrate having a first main metal layer, a first semiconductor element supported on the main substrate, a first sub-substrate supported on the main substrate, and a sealing resin covering the first semiconductor element, wherein the first sub-substrate has a sub-insulating layer, and a first sub-metal layer and a second sub-metal layer arranged on either side of the sub-insulating layer in the thickness direction, the second sub-metal layer is conductively joined to the first main metal layer, the first sub-metal layer includes a region, and the first sub-substrate further has a connecting conductive portion that connects the region and the second sub-metal layer.

[0007] A vehicle provided by a second aspect of the present disclosure includes a drive source and the semiconductor device provided by the first aspect of the present disclosure, the semiconductor device being electrically connected to the drive source.

[0008] A semiconductor device provided by a third aspect of the present disclosure comprises a first conductive member including a first metal, a second conductive member including a second metal, and a first block including a third metal, wherein the first metal, the second metal, and the third metal are different from one another, and the first block is disposed between the first conductive member and the second conductive member.

[0009] According to the above configuration, it is possible to set a more diverse range of conductive paths to the main board, and also to suppress unintended phenomena between dissimilar metals.

[0010] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0011] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a partial perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 3 is a partial perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 4 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 5 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 6 is a partial side view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 7 is a partial enlarged plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 8 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 9 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 10 is a side view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 11 is a bottom view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 5. FIG. 13 is a partial enlarged cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 14 is a partial enlarged cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 5. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 5 . FIG. 17 is a partially enlarged plan view showing a semiconductor device according to the first embodiment of the present disclosure. FIG. 18 is a partially enlarged plan view showing a semiconductor device according to the first embodiment of the present disclosure. FIG. 19 is a partially enlarged cross-sectional view taken along line XIX-XIX in FIG. 17 . FIG. 20 is a configuration diagram showing a vehicle according to the first embodiment of the present disclosure. FIG. 21 is a partially enlarged cross-sectional view showing a first modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 22 is a partially enlarged cross-sectional view showing a second modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 23 is a partially enlarged cross-sectional view showing a third modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 24 is a partially enlarged plan view showing a fourth modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 25 is a partially enlarged plan view showing a semiconductor device according to the second embodiment of the present disclosure. FIG. 26 is a partially enlarged cross-sectional view taken along line XXVI-XXVI in FIG. 25 . FIG. 27 is a partially enlarged cross-sectional view showing a first modified example of the semiconductor device according to the second embodiment of the present disclosure. FIG. 28 is a partially enlarged cross-sectional view showing a second modification of the semiconductor device according to the second embodiment of the present disclosure.FIG. 29 is a partially enlarged cross-sectional view showing a third modified example of the semiconductor device according to the second embodiment of the present disclosure. FIG. 30 is a partially enlarged plan view showing a fourth modified example of the semiconductor device according to the second embodiment of the present disclosure. FIG. 31 is a partially enlarged cross-sectional view showing a semiconductor device according to the third embodiment of the present disclosure. FIG. 32 is a partially enlarged plan view showing a first modified example of the semiconductor device according to the third embodiment of the present disclosure. FIG. 33 is a partially enlarged cross-sectional view taken along line XXXIII-XXXIII of FIG. 32. FIG. 34 is a perspective view showing a semiconductor device according to a fourth embodiment of the present disclosure. FIG. 35 is a partial perspective view showing a semiconductor device according to the fourth embodiment of the present disclosure. FIG. 36 is a partial perspective view showing a semiconductor device according to the fourth embodiment of the present disclosure. FIG. 37 is a plan view showing a semiconductor device according to the fourth embodiment of the present disclosure. FIG. 38 is a partial plan view showing a semiconductor device according to the fourth embodiment of the present disclosure. FIG. 39 is a partial side view showing a semiconductor device according to the fourth embodiment of the present disclosure. FIG. 40 is a partially enlarged plan view showing a semiconductor device according to the fourth embodiment of the present disclosure. FIG. 41 is a partial plan view showing a semiconductor device according to the fourth embodiment of the present disclosure. FIG. 42 is a partial plan view showing a semiconductor device according to the fourth embodiment of the present disclosure. FIG. 43 is a side view showing a semiconductor device according to the fourth embodiment of the present disclosure. FIG. 44 is a bottom view showing a semiconductor device according to the fourth embodiment of the present disclosure. FIG. 45 is a cross-sectional view taken along line XLV-XLV in FIG. 38. FIG. 46 is a cross-sectional view taken along line XLVI-XLVI in FIG. 38. FIG. 47 is a partially enlarged cross-sectional view showing a semiconductor device according to the fourth embodiment of the present disclosure. FIG. 48 is a partially enlarged cross-sectional view showing a semiconductor device according to the fourth embodiment of the present disclosure. FIG. 49 is a cross-sectional view taken along line XLIX-XLIX in FIG. 38. FIG. 50 is a cross-sectional view taken along line L-L in FIG. 38. FIG. 51 is a cross-sectional view taken along line LI-LI in FIG. 38. FIG. 52 is a cross-sectional view taken along line LII-LIII in FIG. 38. FIG. 53 is a cross-sectional view taken along line LIII-LIII in FIG. 38. FIG. 54 is a cross-sectional view taken along line LIV-LIV in FIG. 42. Fig. 55 is a partially enlarged cross-sectional view taken along the line LV-LV in Fig. 54. Fig. 56 is a partially enlarged cross-sectional view showing a third conductive component of a first modified example of the semiconductor device according to the fourth embodiment of the present disclosure. Fig. 57 is a partially enlarged cross-sectional view showing a third conductive component of a second modified example of the semiconductor device according to the fourth embodiment of the present disclosure.FIG. 58 is a partially enlarged cross-sectional view showing a third conductive component of a third modified example of the semiconductor device according to the fourth embodiment of the present disclosure. FIG. 59 is a partially enlarged cross-sectional view taken along line LIX-LIX in FIG. 58. FIG. 60 is a partial plan view showing a semiconductor device according to the fifth embodiment of the present disclosure. FIG. 61 is a partially cross-sectional view taken along line LXI-LXI in FIG. 60. FIG. 62 is a partially cross-sectional view taken along line LXII-LXII in FIG. 60. FIG. 63 is a partially cross-sectional view taken along line LXIII-LXIII in FIG. 60. FIG. 64 is a partially cross-sectional view taken along line LXIV-LXIV in FIG. 60. FIG. 65 is a partial plan view showing a semiconductor device according to the sixth embodiment of the present disclosure. FIG. 66 is a partially cross-sectional view taken along line LXVI-LXVI in FIG. 65. FIG. 67 is a partially cross-sectional view taken along line LXVII-LXVII in FIG. 65.

[0012] Preferred embodiments of the present disclosure will be specifically described below with reference to the drawings. Note that the reference numerals used in Figures 1 to 33 (first to third embodiments) and the reference numerals used in Figures 34 to 67 (fourth to sixth embodiments) are independent of each other. For example, the same reference numeral may be used for different members (elements, etc.), or different reference numerals may be used for the same (or similar) members (elements, etc.).

[0013] The terms "first," "second," "third," etc. in this disclosure are used for identification purposes only and are not intended to impose any ranking on their objects.

[0014] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, in the present disclosure, "a surface A faces in (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0015] 1 to 20 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A1 of this embodiment includes a plurality of first semiconductor elements 10A, a plurality of second semiconductor elements 10B, a main substrate 3, a first terminal 41, a second terminal 42, a plurality of third terminals 43, a fourth terminal 44, a plurality of control terminals 45, a first sub-substrate 48A, a second sub-substrate 48B, a first conductive member 5, a second conductive member 6, and a sealing resin 8.

[0016] FIG. 1 is a perspective view showing the semiconductor device A1. FIG. 2 is a partial perspective view showing the semiconductor device A1. FIG. 3 is a partial perspective view showing the semiconductor device A1. FIG. 4 is a plan view showing the semiconductor device A1. FIG. 5 is a partial plan view showing the semiconductor device A1. FIG. 6 is a partial side view showing the semiconductor device A1. FIG. 7 is a partial enlarged plan view showing the semiconductor device A1. FIG. 8 is a partial plan view showing the semiconductor device A1. FIG. 9 is a partial plan view showing the semiconductor device A1. FIG. 10 is a side view showing the semiconductor device A1. FIG. 11 is a bottom view showing the semiconductor device A1. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 5. FIG. 13 is a partial enlarged cross-sectional view showing the semiconductor device A1. FIG. 14 is a partial enlarged cross-sectional view showing the semiconductor device A1. FIG. 15 is a cross-sectional view taken along line XVIII-XVIII in FIG. 5. FIG. 16 is a cross-sectional view taken along line XX-XX in FIG. 5. FIG. 17 is a partial enlarged plan view showing the semiconductor device A1. FIG. 18 is a partial enlarged plan view showing the semiconductor device A1. Fig. 19 is a partially enlarged cross-sectional view taken along line XIX-XIX in Fig. 17. Fig. 20 is a configuration diagram showing a vehicle according to the first embodiment of the present disclosure. For ease of understanding, sealing resin 8 is omitted from Fig. 19.

[0017] 1 to 20, the thickness direction z is the thickness direction of the present disclosure. The first direction x is a direction perpendicular to the thickness direction z. The second direction y is a direction perpendicular to the thickness direction z and the first direction x. One side of the first direction x is referred to as the x1 side of the first direction x, and the other side of the first direction x is referred to as the x2 side of the first direction x. One side of the second direction y is referred to as the y1 side of the second direction y, and the other side of the second direction y is referred to as the y2 side of the second direction y. One side of the thickness direction z is referred to as the z1 side of the thickness direction z, and the other side of the thickness direction z is referred to as the z2 side of the thickness direction z.

[0018] First semiconductor element 10A, second semiconductor element 10B: The first semiconductor elements 10A and the second semiconductor elements 10B are electronic components that are the core of the semiconductor device A1's functionality. The first semiconductor elements 10A and the second semiconductor elements 10B are made of a semiconductor material primarily composed of, for example, silicon carbide (SiC). This semiconductor material is not limited to silicon carbide (SiC) and may be silicon (Si), gallium nitride (GaN), diamond (C), or other materials. Each of the first semiconductor elements 10A and the second semiconductor elements 10B is a power semiconductor chip with switching functionality, such as a metal oxide semiconductor field effect transistor (MOSFET). While this embodiment illustrates a case in which the first semiconductor elements 10A and the second semiconductor elements 10B are MOSFETs, other transistors, such as insulated gate bipolar transistors (IGBTs), may also be used. The first semiconductor elements 10A and the second semiconductor elements 10B may have different configurations or may have the same configuration. In the following description, the first semiconductor elements 10A and the second semiconductor elements 10B are all the same element. Each of the first semiconductor elements 10A and the second semiconductor elements 10B is, for example, an n-channel MOSFET, but may also be a p-channel MOSFET.

[0019] 13 and 14 , the first semiconductor element 10A and the second semiconductor element 10B each have an element main surface 101 and an element back surface 102. In each of the first semiconductor elements 10A and the second semiconductor elements 10B, the element main surface 101 and the element back surface 102 are spaced apart in the thickness direction z. The element main surface 101 faces the z1 side in the thickness direction z, and the element back surface 102 faces the z2 side in the thickness direction z.

[0020] The number of first semiconductor elements 10A and the number of second semiconductor elements 10B are changed as appropriate depending on the required performance, such as the current capacity handled by the semiconductor device A1. In this embodiment, as shown in Figures 8 and 9, four first semiconductor elements 10A and four second semiconductor elements 10B are arranged. The number of first semiconductor elements 10A and four second semiconductor elements 10B may be two or three, or five or more. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B may be equal to or different from each other.

[0021] The semiconductor device A1 is configured, for example, as a half-bridge switching circuit. In this case, a plurality of first semiconductor elements 10A form an upper arm circuit of the semiconductor device A1, and a plurality of second semiconductor elements 10B form a lower arm circuit. In the upper arm circuit, the plurality of first semiconductor elements 10A are connected in parallel with each other, and in the lower arm circuit, the plurality of second semiconductor elements 10B are connected in parallel with each other. The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are connected in series to form a bridge layer.

[0022] As shown in Figures 8, 9, and 16, each of the multiple first semiconductor elements 10A is mounted on a first conductive portion 32A of the main substrate 3, which will be described later. In the example shown in Figures 8 and 9, the multiple first semiconductor elements 10A are lined up, for example, in the second direction y and spaced apart from one another. Each first semiconductor element 10A is conductively bonded to the first conductive portion 32A via a first conductive bonding material 19A. The element back surface 102 faces the first conductive portion 32A.

[0023] As shown in Figures 8, 9, and 15, each of the multiple second semiconductor elements 10B is mounted on a second conductive portion 32B of the main substrate 3 (described later). In the example shown in Figures 8 and 9, the multiple second semiconductor elements 10B are aligned, for example, in the second direction y and spaced apart from one another. Each second semiconductor element 10B is conductively bonded to the second conductive portion 32B via a second conductive bonding material 19B. The element back surface 102 faces the second conductive portion 32B. As can be seen from Figure 9, the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B overlap when viewed in the first direction x, but they do not necessarily have to overlap.

[0024] The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B each have a first principal surface electrode 11, a second principal surface electrode 12, a third principal surface electrode 13, and a back surface electrode 15. The configurations of the first principal surface electrode 11, the second principal surface electrode 12, the third principal surface electrode 13, and the back surface electrode 15 described below are common to each of the first semiconductor elements 10A and each of the second semiconductor elements 10B. The first principal surface electrode 11, the second principal surface electrode 12, and the third principal surface electrode 13 are provided on the element main surface 101. The first principal surface electrode 11, the second principal surface electrode 12, and the third principal surface electrode 13 are insulated by an insulating film (not shown). The back surface electrode 15 is provided on the element back surface 102.

[0025] The first principal surface electrode 11 is, for example, a gate electrode, to which a drive signal (for example, a gate voltage) for driving the first semiconductor element 10A (second semiconductor element 10B) is input. In the first semiconductor element 10A (second semiconductor element 10B), the second principal surface electrode 12 is, for example, a source electrode, through which a source current flows. The third principal surface electrode 13 is, for example, a source sense electrode, through which a source current flows. The back surface electrode 15 is, for example, a drain electrode, through which a drain current flows. The back surface electrode 15 covers substantially the entire area of ​​the element back surface 102. The back surface electrode 15 is, for example, formed by Ag (silver) plating.

[0026] When a drive signal (gate voltage) is input to the first principal surface electrode 11 (gate electrode), each first semiconductor element 10A (each second semiconductor element 10B) switches between a conductive state and a non-conductive state in response to the drive signal. In the conductive state, current flows from the back surface electrode 15 (drain electrode) to the second principal surface electrode 12 (source electrode), and in the non-conductive state, current does not flow. In other words, each first semiconductor element 10A (each second semiconductor element 10B) performs a switching operation. The semiconductor device A1 converts a DC voltage input between the single fourth terminal 44 and the two first and second terminals 41 and 42 into, for example, an AC voltage, and outputs the AC voltage from the third terminal 43, using the switching functions of the multiple first semiconductor elements 10A and multiple second semiconductor elements 10B.

[0027] Main substrate 3: The main substrate 3 supports a plurality of first semiconductor elements 10A and a plurality of second semiconductor elements 10B. The specific configuration of the main substrate 3 is not limited, and may be, for example, a DBC (Direct Bonded Copper) substrate or an AMB (Active Metal Brazing) substrate. The main substrate 3 includes a main insulating layer 31, a first main metal layer 32, and a second main metal layer 33. The first main metal layer 32 includes a first conductive portion 32A and a second conductive portion 32B. The dimension of the main substrate 3 in the thickness direction z is not limited, and may be, for example, 0.4 mm or more and 3.0 mm or less. In the illustrated example, the first main metal layer 32 is not provided with a plating layer or the like and is composed of a single layer.

[0028] The constituent material of the main insulating layer 31 includes, for example, ceramics with excellent thermal conductivity. Examples of such ceramics include SiN (silicon nitride). The constituent material of the main insulating layer 31 is not limited to ceramics and may be an insulating resin sheet or the like. The main insulating layer 31 has, for example, a rectangular shape in a plan view. The dimension of the main insulating layer 31 in the thickness direction z is not limited in any way and is, for example, 0.05 mm to 1.0 mm.

[0029] As shown in FIGS. 8, 9, and 12, the first conductive portion 32A supports a plurality of first semiconductor elements 10A, and the second conductive portion 32B supports a plurality of second semiconductor elements 10B. The first conductive portion 32A and the second conductive portion 32B are formed on the upper surface (the surface facing the z1 side in the thickness direction z) of the main insulating layer 31. The constituent material of the first conductive portion 32A and the second conductive portion 32B includes, for example, Cu (copper). The constituent material may include, for example, Al (aluminum) other than Cu (copper). The first conductive portion 32A and the second conductive portion 32B are spaced apart in the first direction x. The first conductive portion 32A is located on the x1 side of the second conductive portion 32B in the first direction x. The first conductive portion 32A and the second conductive portion 32B each have, for example, a rectangular shape in a plan view. The first conductive portion 32A and the second conductive portion 32B, together with the first conductive member 5 and the second conductive member 6, constitute a path of the main circuit current switched by the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B.

[0030] The first conductive portion 32A has a first main surface 301A. The first main surface 301A is a flat surface facing the z1 side in the thickness direction z. A plurality of first semiconductor elements 10A are bonded to the first main surface 301A of the first conductive portion 32A via first conductive bonding materials 19A. The second conductive portion 32B has a second main surface 301B. The second main surface 301B is a flat surface facing the z1 side in the thickness direction z. A plurality of second semiconductor elements 10B are bonded to the second main surface 301B of the second conductive portion 32B via second conductive bonding materials 19B. The constituent materials of the first conductive bonding material 19A and the second conductive bonding material 19B are not particularly limited and may be, for example, solder, a metal paste material containing a metal such as Ag (silver), or a sintered metal containing a metal such as Ag (silver). The dimensions of first conductive portion 32A and second conductive portion 32B in thickness direction z are not limited in any way and may be, for example, 0.1 mm or more and 1.5 mm or less.

[0031] The second main metal layer 33 is formed on the lower surface (surface facing the z2 side in the thickness direction z) of the main insulating layer 31. The constituent material of the second main metal layer 33 is, for example, the same as the constituent material of the first main metal layer 32. The second main metal layer 33 has a back surface 302. The back surface 302 is a flat surface facing the z2 side in the thickness direction z. In the example shown in FIG. 11 , the back surface 302 is exposed from the sealing resin 8, for example. A heat dissipation member (e.g., a heat sink) (not shown) can be attached to the back surface 302. The back surface 302 may not be exposed from the sealing resin 8 and may be covered by the sealing resin 8. The second main metal layer 33 overlaps both the first conductive portion 32A and the second conductive portion 32B in a plan view.

[0032] First terminal 41, second terminal 42, third terminal 43, fourth terminal 44: The specific configurations of the first terminal 41, second terminal 42, the plurality of third terminals 43, and fourth terminal 44 are not limited in any way, and in this embodiment, they are made of a plate-shaped metal plate. This metal plate contains, for example, Cu (copper) or a Cu (copper) alloy. In the example shown in Figures 1 to 6, 8, 9, and 11, the semiconductor device A1 includes one each of the first terminal 41, second terminal 42, and fourth terminal 44, and two third terminals 43, but the number of each terminal is not limited in any way.

[0033] A DC voltage to be converted into power is input to the first terminal 41, the second terminal 42, and the fourth terminal 44. For example, the fourth terminal 44 is a positive electrode (P terminal), and the first terminal 41 and the second terminal 42 are each a negative electrode (N terminal). An AC voltage converted into power by the first semiconductor element 10A and the second semiconductor element 10B is output from the plurality of third terminals 43. The first terminal 41, the second terminal 42, the plurality of third terminals 43, and the fourth terminal 44 each include a portion covered with the sealing resin 8 and a portion exposed from the sealing resin 8.

[0034] As shown in FIG. 12 , the fourth terminal 44 is conductively bonded to the first conductive portion 32A. The conductive bonding method is not limited, and methods such as ultrasonic bonding, laser bonding, and welding, or methods using solder, metal paste, silver sintered body, etc., may be appropriately adopted. The fourth terminal 44 may be integrally formed with the first conductive portion 32A. As shown in FIGS. 8 and 9 , the fourth terminal 44 is located on the x1 side in the first direction x with respect to the multiple first semiconductor elements 10A and the first conductive portions 32A. The fourth terminal 44 is conductively connected to the first conductive portion 32A and, via the first conductive portion 32A, to the back surface electrode 15 (drain electrode) of each first semiconductor element 10A.

[0035] As shown in FIG. 5 , the first terminal 41 and the second terminal 42 are conductively joined to the second conductive member 6. The method of conductive joining is not limited, and methods such as ultrasonic bonding, laser bonding, welding, or methods using solder, metal paste, silver sintered body, etc. may be appropriately adopted. The first terminal 41 and the second terminal 42 may be integrally formed with the second conductive member 6. As shown in FIGS. 5 , 8 , etc., the first terminal 41 and the second terminal 42 are each located on the x1 side in the first direction x with respect to the multiple first semiconductor elements 10A and the first conductive portions 32A. The first terminal 41 and the second terminal 42 are each conductively connected to the second conductive member 6 and, via the second conductive member 6, to the second principal surface electrodes 12 (source electrodes) of each second semiconductor element 10B.

[0036] As shown in FIGS. 1 to 5 and 11 , the first terminal 41, the second terminal 42, and the fourth terminal 44 each protrude from the sealing resin 8 toward the x1 side in the first direction x in the semiconductor device A1. The first terminal 41, the second terminal 42, and the fourth terminal 44 are spaced apart from one another. The first terminal 41 and the second terminal 42 are located on opposite sides of the fourth terminal 44 in the second direction y. The first terminal 41 is located on the y1 side of the fourth terminal 44 in the second direction y, and the second terminal 42 is located on the y2 side of the fourth terminal 44 in the second direction y. The first terminal 41, the second terminal 42, and the fourth terminal 44 overlap one another when viewed in the second direction y.

[0037] As can be seen from FIGS. 8 , 9 , and 12 , the two third terminals 43 are each conductively bonded to the second conductive portion 32B. The conductive bonding method is not limited to any particular method, and methods such as ultrasonic bonding, laser bonding, and welding, or methods using solder, metal paste, silver sintered body, etc., may be appropriately employed. As shown in FIG. 8 and other figures, the two third terminals 43 are each located on the x2 side of the second semiconductor elements 10B and the second conductive portions 32B in the first direction x. Each third terminal 43 is conductively connected to the second conductive portion 32B and, via the second conductive portion 32B, to the back electrode 15 (drain electrode) of each second semiconductor element 10B. The number of third terminals 43 is not limited to two and may be, for example, one or three or more. For example, when there is one third terminal 43, it is preferably connected to the center portion of the second conductive portion 32B in the second direction y.

[0038] First sub-substrate 48A, second sub-substrate 48B: The first sub-substrate 48A and the second sub-substrate 48B support a plurality of control terminals 45. The first sub-substrate 48A and the second sub-substrate 48B are interposed between the first main surface 301A and the second main surface 301B and the plurality of control terminals 45 in the thickness direction z. The first sub-substrate 48A and the second sub-substrate 48B may have different configurations or may have the same configuration. The first sub-substrate 48A is disposed on the first conductive portion 32A. The second sub-substrate 48B is disposed on the second conductive portion 32B. In this embodiment, the first sub-substrate 48A and the second sub-substrate 48B have the same configuration and are rotated 180 degrees relative to each other when viewed in the thickness direction z.

[0039] The specific configuration of the first sub-substrate 48A and the second sub-substrate 48B is not limited in any way. Specific examples of the first sub-substrate 48A and the second sub-substrate 48B include an IMS (Insulated Metal Substrate) substrate and a glass epoxy resin substrate. In this embodiment, the first sub-substrate 48A and the second sub-substrate 48B are IMS substrates. The first sub-substrate 48A and the second sub-substrate 48B have a sub-insulation layer 481, a first sub-metal layer 482, and a second sub-metal layer 483 stacked on top of each other.

[0040] The sub-insulating layer 481 is made of, for example, ceramics. The sub-insulating layer 481 has, for example, a rectangular shape in plan view. The thickness of the sub-insulating layer 481 is not particularly limited and is, for example, 0.05 mm to 1.0 mm.

[0041] As shown in FIG. 19 and other figures, the first sub-metal layer 482 is formed on the upper surface (surface facing the z1 side in the thickness direction z) of the sub-insulating layer 481. The first sub-metal layer 482 contains, for example, Cu (copper) or a Cu (copper) alloy. The specific configuration of the first sub-metal layer 482 is not limited, and in this embodiment, it includes a base material layer 4820 and a surface metal layer 4829. The base material layer 4820 is in contact with the sub-insulating layer 481. The base material layer 4820 contains, for example, Cu (copper) or a Cu (copper) alloy. The thickness of the base material layer 4820 is not limited, and is, for example, 0.035 mm to 2.0 mm. The surface metal layer 4829 is stacked on the side of the base material layer 4820 opposite the sub-insulating layer 481. The surface metal layer 4829 contains a metal different from the constituent material of the base material layer 4820, such as Ni (nickel). Furthermore, the surface metal layer 4829 may have a structure in which a plurality of metal layers are laminated. There are no particular limitations on the thickness of the surface metal layer 4829, and it may be, for example, 1 μm or more and 10 μm or less.

[0042] 17 and 18, the first sub-metal layer 482 includes a plurality of regions 482A, 482B, 482C, 482D, 482E, and 482F. The plurality of regions 482A, 482B, 482C, 482D, 482E, and 482F are separated and insulated from one another.

[0043] The region 482A includes a connection portion 4821A and a terminal portion 4822A. In the first sub-substrate 48A, the connection portion 4821A is located on the x2 side in the first direction x, and the terminal portion 4822A is located on the x1 side in the first direction x. In the second sub-substrate 48B, the connection portion 4821A is located on the x1 side in the first direction x, and the terminal portion 4822A is located on the x2 side in the first direction x. The connection portion 4821A has a shape that extends elongatedly in the second direction y. The terminal portion 4822A has a substantially circular shape.

[0044] A plurality of wires 71 are bonded to the connection portion 4821A. In this embodiment, the wires 71 are bonded to a surface metal layer 4829 of the connection portion 4821A. The constituent material of the wires 71 is not limited in any way and includes, for example, Al (aluminum) or an Al (aluminum) alloy. The region 482A is electrically connected to the first main surface electrodes 11 (gate electrodes) of the plurality of first semiconductor elements 10A (the plurality of second semiconductor elements 10B) via the plurality of wires 71.

[0045] The region 482B includes a connection portion 4821B and a terminal portion 4822B. In the first sub-substrate 48A, the connection portion 4821B is located on the x2 side in the first direction x, and the terminal portion 4822B is located on the x1 side in the first direction x. In the second sub-substrate 48B, the connection portion 4821B is located on the x1 side in the first direction x, and the terminal portion 4822B is located on the x2 side in the first direction x. In the first sub-substrate 48A, the region 482B is located on the x1 side in the first direction x of the connection portion 4821A. In the second sub-substrate 48B, the region 482B is located on the x2 side in the first direction x of the connection portion 4821A. The connection portion 4821B has a shape that extends elongated in the second direction y. The terminal portion 4822B has a substantially semicircular shape. On the first sub-substrate 48A, the terminal portion 4822B is located on the y2 side of the terminal portion 4822A in the second direction y. On the second sub-substrate 48B, the terminal portion 4822B is located on the y1 side of the terminal portion 4822A in the second direction y.

[0046] A plurality of wires 72 are joined to the connection portion 4821B. In this embodiment, the wires 72 are joined to a surface metal layer 4829 of the connection portion 4821B. The constituent material of the wires 72 is not limited in any way and includes, for example, Al (aluminum) or an Al (aluminum) alloy. The region 482B is electrically connected to the third principal surface electrodes 13 (source sense electrodes) of the plurality of first semiconductor elements 10A (the plurality of second semiconductor elements 10B) via the plurality of wires 72.

[0047] The region 482C includes a connection portion 4821C and a terminal portion 4822C. In the first sub-substrate 48A, the connection portion 4821C is located on the y2 side in the second direction y, and the terminal portion 4822C is located on the y1 side in the second direction y. In the second sub-substrate 48B, the connection portion 4821C is located on the y1 side in the second direction y, and the terminal portion 4822C is located on the y2 side in the second direction y. The connection portion 4821C has a bent shape extending in the second direction y. The terminal portion 4822C has a substantially circular shape. In the first sub-substrate 48A, the terminal portion 4822C is located on the x1 side in the first direction x of the connection portion 4821A, and on the y2 side in the second direction y of the terminal portion 4822B. On the second sub-substrate 48B, the connecting portion 4821A is located on the x2 side in the first direction x, and the terminal portion 4822C is located on the y1 side in the second direction y of the terminal portion 4822B.

[0048] The region 482D includes a connection portion 4821D and a terminal portion 4822D. In the first sub-substrate 48A, the connection portion 4821D is located on the y2 side in the second direction y, and the terminal portion 4822D is located on the y1 side in the second direction y. The connection portion 4821D is, for example, rectangular, and the terminal portion 4822D is, for example, approximately circular. In the first sub-substrate 48A, the connection portion 4821D is located on the x1 side in the first direction x of the connection portion 4821C. In the second sub-substrate 48B, the connection portion 4821D is located on the x2 side in the first direction x of the connection portion 4821C. In the first sub-substrate 48A, the terminal portion 4822D is located on the y2 side in the second direction y of the terminal portion 4822C. In the second sub-substrate 48B, the terminal portion 4822D is located on the y1 side in the second direction y of the terminal portion 4822C.

[0049] In the first sub-substrate 48A, the region 482E is located on the y2 side in the second direction y of the connecting portion 4821A, and on the x2 side in the first direction x of the connecting portion 4821C. In the second sub-substrate 48B, the region 482E is located on the y1 side in the second direction y of the connecting portion 4821A, and on the x1 side in the first direction x of the connecting portion 4821C. The region 482E has a shape that extends in the second direction y.

[0050] Region 482E corresponds to the "first region" in this disclosure. Region 482D corresponds to the "second region" in this disclosure. Region 482C corresponds to the "third region" in this disclosure. That is, region 482C is located between region 482E and region 482D in the first direction x.

[0051] The multiple regions 482F are arranged alternately in the second direction y, with the terminal portion 4822A, the terminal portion 4822B, the terminal portion 4822C, and the terminal portion 4822D. The shape of the multiple regions 482F is not limited in any way and may be rectangular, circular, or the like, and is rectangular in the illustrated example.

[0052] 13, 14, 19, etc., the second sub-metal layer 483 is formed on the lower surface (the surface on the z2 side in the thickness direction z) of the sub-insulating layer 481. The constituent material of the second sub-metal layer 483 includes, for example, Cu (copper) or a Cu (copper) alloy. The thickness of the second sub-metal layer 483 is not particularly limited and is, for example, 0.035 mm to 3.0 mm.

[0053] The second sub-metal layer 483 of the first sub-substrate 48A is conductively bonded to the first conductive portion 32A. The second sub-metal layer 483 of the second sub-substrate 48B is conductively bonded to the second conductive portion 32B. The method for conductively bonding the second sub-metal layer 483 to the first conductive portion 32A or the second conductive portion 32B is not limited in any way. Examples of conductive bonding methods include a method using a conductive bonding material, a laser bonding method, an ultrasonic bonding method, and a solid-state bonding method. In this embodiment, the second sub-metal layers 483 of the first sub-substrate 48A and the second sub-substrate 48B are conductively bonded to the first conductive portion 32A and the second conductive portion 32B via a conductive bonding material 49, as shown in FIG. 19 . The conductive bonding material 49 is, for example, solder.

[0054] As shown in FIGS. 17 to 19 , the first sub-substrate 48A and the second sub-substrate 48B have a connecting conductive portion 485. The connecting conductive portion 485 electrically connects the region 482E and the second sub-metal layer 483. The specific configuration of the connecting conductive portion 485 is not limited in any way. In the illustrated example, the connecting conductive portion 485 is formed of a conductive member that penetrates the sub-insulating layer 481 in the thickness direction z. Such a connecting conductive portion 485 includes, for example, a plating material containing Cu (copper), solder, or the like. In the illustrated example, the connecting conductive portion 485 penetrates the sub-insulating layer 481 and the region 482E.

[0055] 17 , in the first sub-substrate 48A, a wire 73 is connected to the region 482E and the connection portion 4821D. In this embodiment, the wire 73 is bonded to the surface metal layer 4829 of each of the region 482E and the connection portion 4821D. The material of the wire 73 is not limited in any way and includes, for example, Al (aluminum) or an Al (aluminum) alloy. This provides electrical continuity between the region 482D and the first conductive portion 32A.

[0056] 18 , on the second sub-substrate 48B, a thermistor 17 is connected to the connection portion 4821C and the connection portion 4821D. The thermistor 17 is used as a temperature detection sensor. The semiconductor device A1 may be configured to include, in addition to the thermistor 17, a temperature-sensitive diode, for example, or may not be configured to include the thermistor 17.

[0057] The wires 71, 72, and 73 are not connected to the first main metal layer 32. In other words, the first main metal layer 32 is separated from the plurality of wires 71, 72, and 73.

[0058] Control terminals 45: The multiple control terminals 45 are terminals for controlling each of the first semiconductor elements 10A and each of the second semiconductor elements 10B. The multiple control terminals 45 include multiple control terminals 46A, 46B, 46E and multiple control terminals 47A to 47D. The multiple control terminals 46A, 46B, 46E are used to control each of the first semiconductor elements 10A, etc. The multiple control terminals 47A to 47D are used to control each of the second semiconductor elements 10B, etc.

[0059] The control terminals 46A, 46B, and 46E are arranged at intervals in the second direction y. As shown in Figures 2, 3, 5, 6, 8, and 17, the control terminals 46A, 46B, and 46E are supported by the first conductive portion 32A via the first sub-substrate 48A. As shown in Figure 5, the control terminals 46A, 46B, and 46E are located between the first semiconductor elements 10A and the first terminal 41, the second terminal 42, and the fourth terminal 44 in the first direction x.

[0060] 17 , the control terminal 46A is disposed on the terminal portion 4822A. The control terminal 46A is a terminal (gate terminal) for inputting drive signals to the plurality of first semiconductor elements 10A. A drive signal for driving the plurality of first semiconductor elements 10A is input to the control terminal 46A (for example, a gate voltage is applied).

[0061] The control terminal 46B is disposed on the terminal portion 4822B. The control terminal 46B is a terminal (source sense terminal) for detecting source signals of the multiple first semiconductor elements 10A. The control terminal 46B detects a voltage (a voltage corresponding to a source current) applied to each second main surface electrode 12 (source electrode) of the multiple first semiconductor elements 10A.

[0062] The control terminal 46E is disposed on the terminal portion 4822D. The control terminal 46E is a terminal (drain sense terminal) for detecting drain signals of the multiple first semiconductor elements 10A. The control terminal 46E detects the voltage (voltage corresponding to the drain current) applied to each back electrode 15 (drain electrode) of the multiple first semiconductor elements 10A. The control terminal 46E corresponds to the "first control terminal" in this disclosure.

[0063] The control terminals 47A to 47D are arranged at intervals in the second direction y. As shown in Figures 2, 3, 5, 6, 8, 18, etc., the control terminals 47A to 47D are supported by the second conductive portion 32B via the second sub-substrate 48B. As shown in Figure 5, the control terminals 47A to 47D are located between the second semiconductor elements 10B and the third terminals 43 in the first direction x.

[0064] 18 , the control terminal 47A is disposed on the terminal portion 4822A. The control terminal 47A is a terminal (gate terminal) for inputting drive signals to the plurality of second semiconductor elements 10B. A drive signal for driving the plurality of second semiconductor elements 10B is input to the control terminal 47A (for example, a gate voltage is applied).

[0065] The control terminal 46B is disposed on the terminal portion 4822B. The control terminal 46B is a terminal (source sense terminal) for detecting source signals of the plurality of second semiconductor elements 10B. The control terminal 46B detects a voltage (a voltage corresponding to a source current) applied to each second main surface electrode 12 (source electrode) of the plurality of second semiconductor elements 10B.

[0066] The control terminal 47C is disposed on the terminal portion 4822C. The control terminal 47D is disposed on the terminal portion 4822D. The control terminals 47C and 47D are terminals that are electrically connected to the thermistor 17.

[0067] As shown in FIGS. 12, 17 and 18, each of the plurality of control terminals 45 (the plurality of control terminals 46A, 46B, 46E and the plurality of control terminals 47A to 47D) includes a holder 451 and a metal pin 452.

[0068] The holder 451 is made of a conductive material. As shown in FIGS. 13 and 14 , the holder 451 is bonded to the first sub-metal layer 482 via a conductive bonding material (not shown). The holder 451 includes a cylindrical portion, an upper flange, and a lower flange. The upper flange is connected to the upper part of the cylindrical portion, and the lower flange is connected to the lower part of the cylindrical portion. A metal pin 452 is inserted through at least the upper flange and the cylindrical portion of the holder 451. The holder 451 is covered with a sealing resin 8.

[0069] The metal pin 452 is a rod-shaped member extending in the thickness direction z. The metal pin 452 is supported by being press-fitted into the holder 451. The metal pin 452 is electrically connected to the first sub-metal layer 482 at least via the holder 451. As shown in FIGS. 1 and 12 , the metal pin 452 protrudes from the sealing resin 8 to the z1 side in the thickness direction z.

[0070] First conductive member 5, second conductive member 6: The first conductive member 5 and second conductive member 6, together with the first conductive portion 32A and the second conductive portion 32B, form a path for a main circuit current switched by the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B. The first conductive member 5 and second conductive member 6 are spaced apart from the first main surface 301A and the second main surface 301B on the z1 side in the thickness direction z and overlap the first main surface 301A and the second main surface 301B in a plan view. In this embodiment, the first conductive member 5 and second conductive member 6 are each made of a metal plate material. The metal includes, for example, Cu (copper) or a Cu (copper) alloy. Specifically, the first conductive member 5 and second conductive member 6 are made of an appropriately bent metal plate material.

[0071] The first conductive member 5 is connected to the second principal surface electrode 12 (source electrode) of each first semiconductor element 10A and the second conductive portion 32B, thereby electrically connecting the second principal surface electrode 12 of each first semiconductor element 10A and the second conductive portion 32B. The first conductive member 5 forms a path for a main circuit current switched by the multiple first semiconductor elements 10A. As shown in FIGS. 7 and 8 , the first conductive member 5 includes a main portion 51, multiple first bonding portions 52, and multiple second bonding portions 53.

[0072] The main portion 51 is located between the plurality of first semiconductor elements 10A and the second conductive portion 32B in the first direction x and is a strip-shaped portion extending in the second direction y in a plan view. The main portion 51 overlaps both the first conductive portion 32A and the second conductive portion 32B in a plan view and is spaced apart in the thickness direction z from the first main surface 301A and the second main surface 301B on the z1 side in the thickness direction z. As shown in FIG. 16 and other figures, the main portion 51 is located on the z2 side in the thickness direction z with respect to a third path portion 66 and a fourth path portion 67 of the second conductive member 6 described later and is closer to the first main surface 301A and the second main surface 301B than the third path portion 66 and the fourth path portion 67.

[0073] In this embodiment, the main portion 51 is disposed parallel to the first main surface 301A and the second main surface 301B.

[0074] As shown in FIG. 8 and other figures, the main portion 51 extends continuously in the second direction y to correspond to the region in which the multiple first semiconductor elements 10A are arranged. In this embodiment, as shown in FIGS. 7 , 8 , 12 , and other figures, multiple first openings 514 are formed in the main portion 51. Each of the multiple first openings 514 is, for example, a through hole penetrating in the thickness direction z (the plate thickness direction of the main portion 51). The multiple first openings 514 are arranged at intervals in the second direction y. The multiple first openings 514 are provided corresponding to each of the multiple first semiconductor elements 10A. In this embodiment, four first openings 514 are provided in the main portion 51, and these first openings 514 and the multiple (four) first semiconductor elements 10A are positioned at the same position in the second direction y.

[0075] 8, 12, etc., in the present embodiment, each first opening 514 overlaps with a gap between the first conductive portion 32A and the second conductive portion 32B in a plan view. The multiple first openings 514 are formed to facilitate the flow of the resin material between the upper side (the z1 side in the thickness direction z) and the lower side (the z2 side in the thickness direction z) near the main portion 51 (first conductive member 5) when injecting the flowable resin material to form the sealing resin 8.

[0076] As shown in FIG. 8 and other figures, the multiple first bonding portions 52 and the multiple second bonding portions 53 are connected to the main portion 51 and are arranged corresponding to the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B. Specifically, each first bonding portion 52 is located on the x1 side of the main portion 51 in the first direction x. Each second bonding portion 53 is located on the x2 side of the main portion 51 in the first direction x. As shown in FIG. 13 , the multiple first bonding portions 52 are individually bonded to the second principal surface electrodes 12 of the multiple first semiconductor elements 10A via conductive bonding materials 59. The multiple second bonding portions 53 and the second conductive portion 32B are bonded to each other via the conductive bonding material 59. The material of the conductive bonding material 59 is not particularly limited and may be, for example, solder, a metal paste material, or a sintered metal. In this embodiment, the first bonding portion 52 has two portions spaced apart in the second direction y.

[0077] The second conductive member 6 electrically connects the second main surface electrode 12 (source electrode) of each second semiconductor element 10B to the first terminal 41 and the second terminal 42. The second conductive member 6 is formed integrally with the first terminal 41 and the second terminal 42. The second conductive member 6 constitutes a path for a main circuit current switched by the plurality of second semiconductor elements 10B. As shown in FIGS. 2 and 5 to 7 , the second conductive member 6 includes a plurality of third joint portions 61, a first path portion 64, a second path portion 65, a plurality of third path portions 66, and a fourth path portion 67.

[0078] The multiple third bonding portions 61 are portions that are individually bonded to the multiple second semiconductor elements 10B. Each third bonding portion 61 and the second main surface electrode 12 of each second semiconductor element 10B are bonded via a conductive bonding material 69. The material of the conductive bonding material 69 is not particularly limited and may be, for example, solder, a metal paste material, or a sintered metal. In this embodiment, the third bonding portion 61 has two flat portions 611 and two first inclined portions 612.

[0079] The two flat portions 611 are aligned in the second direction y. The two flat portions 611 are spaced apart from each other in the second direction y. The shape of the flat portions 611 is not limited in any way, and in the illustrated example, they are rectangular. The two flat portions are joined to the second principal surface electrode 12 on both sides in the second direction y.

[0080] The two first inclined portions 612 are connected to the outside of the two flat portions 611 in the second direction y. That is, the first inclined portion 612 located on the y1 side in the second direction y is connected to the y1 side in the second direction y of the flat portion 611 located on the y1 side in the second direction y. Furthermore, the first inclined portion 612 located on the y2 side in the second direction y is connected to the y2 side in the second direction y of the flat portion 611 located on the y2 side in the second direction y. The first inclined portion 612 is inclined so that the farther it is from the flat portion 611 in the second direction y, the closer it is to the z1 side in the thickness direction z.

[0081] The first path portion 64 is interposed between the plurality of third joint portions 61 and the first terminal 41. In the illustrated example, the first path portion 64 is connected to the first terminal 41 via a first step portion 602. The first path portion 64 overlaps the first conductive portion 32A in a plan view. The first path portion 64 has a shape that extends as a whole in the first direction x.

[0082] The first path portion 64 includes a first band portion 641 and a first extending portion 643. The first band portion 641 is located on the x2 side in the first direction x with respect to the first terminal 41, and is substantially parallel to the first main surface 301A. The first band portion 641 has a shape that extends in the first direction x as a whole.

[0083] The first extending portion 643 extends from the side end of the first strip portion 641 on the y1 side in the second direction y to the z2 side in the thickness direction z. The first extending portion 643 is spaced apart from the first conductive portion 32A. In the illustrated example, the first extending portion 643 is shaped along the thickness direction z and has an elongated rectangular shape with the first direction x as the longitudinal direction. Note that the first path portion 64 may not have the first extending portion 643.

[0084] The second path portion 65 is interposed between the plurality of third joint portions 61 and the second terminal 42. In the illustrated example, the second path portion 65 is connected to the second terminal 42 via the second step portion 603. The second path portion 65 overlaps the first conductive portion 32A in a plan view. The second path portion 65 has a shape that extends as a whole in the first direction x.

[0085] The second path portion 65 includes a second band portion 651 and a second extending portion 653. The second band portion 651 is located on the x2 side in the first direction x with respect to the second terminal 42 and is substantially parallel to the first main surface 301A. The second band portion 651 has a shape that extends in the first direction x as a whole.

[0086] The second extending portion 653 extends from the side end of the second strip portion 651 on the y2 side in the second direction y to the z2 side in the thickness direction z. The second extending portion 653 is spaced apart from the first conductive portion 32A. In the example shown, the second extending portion 653 is shaped along the thickness direction z and has an elongated rectangular shape with the first direction x as the longitudinal direction. Note that the second path portion 65 may not have the second extending portion 653.

[0087] The multiple third path portions 66 are individually connected to the multiple third joint portions 61. Each third path portion 66 has a shape extending in the first direction x and is arranged at a distance from one another in the second direction y. There is no limitation on the number of multiple third path portions 66, and in the example shown, five third path portions 66 are arranged. Each third path portion 66 is arranged so as to be located between the multiple second semiconductor elements 10B in the second direction y or to be located outward of the multiple second semiconductor elements 10B in the second direction y.

[0088] In the present embodiment, one third joint 61 is disposed between two third path portions 66 adjacent to each other in the second direction y. In one third joint 61, the first inclined portion 612 located on the y1 side in the second direction y is connected to the third path portion 66 located on the y1 side in the second direction y, of the two third path portions 66 adjacent to each other in the second direction y. In one third joint 61, the first inclined portion 612 located on the y2 side in the second direction y is connected to the third path portion 66 located on the y2 side in the second direction y, of the two third path portions 66 adjacent to each other in the second direction y.

[0089] The fourth path portion 67 is connected to the ends of the plurality of third path portions 66 on the x1 side in the first direction x. The fourth path portion 67 has a shape that extends elongatedly in the second direction y. The fourth path portion 67 is connected to the ends of the first band portion 641 of the first path portion 64 and the second band portion 651 of the second path portion 65 on the x2 side in the first direction x. In the example shown, the first path portion 64 is connected to the end of the fourth path portion 67 on the y1 side in the second direction y. Furthermore, the second path portion 65 is connected to the end of the fourth path portion 67 on the y2 side in the second direction y.

[0090] Sealing resin 8: The sealing resin 8 covers the multiple first semiconductor elements 10A, the multiple second semiconductor elements 10B, the main substrate 3 (excluding the back surface 302), portions of the first terminal 41, the second terminal 42, the multiple third terminals 43, and the fourth terminal 44, portions of the multiple control terminals 45, the first sub-substrate 48A and the second sub-substrate 48B, the first conductive member 5, the second conductive member 6, and the multiple wires 71 to 73. The sealing resin 8 is made of, for example, black epoxy resin. The sealing resin 8 is formed, for example, by molding. The size of the sealing resin 8 is not limited in any way, and may be, for example, approximately 35 mm to 60 mm in the first direction x, approximately 35 mm to 50 mm in the second direction y, and approximately 4 mm to 15 mm in the thickness direction z. These dimensions are the sizes of the largest portions along each direction. The sealing resin 8 has a resin main surface 81, a resin back surface 82, and a plurality of resin side surfaces 831 to 834.

[0091] As shown in Figures 10, 12, and 15, the resin main surface 81 and the resin back surface 82 are spaced apart in the thickness direction z. The resin main surface 81 faces the z1 side in the thickness direction z, and the resin back surface 82 faces the z2 side in the thickness direction z. A plurality of control terminals 45 (a plurality of control terminals 46A, 46B, and 46E and a plurality of control terminals 47A to 47D) protrude from the resin main surface 81. As shown in Figure 11, the resin back surface 82 has a frame shape that surrounds the back surface 302 (the lower surface of the second main metal layer 33) of the main substrate 3 in a plan view. The back surface 302 of the main substrate 3 is exposed from the resin back surface 82 and is, for example, flush with the resin back surface 82.

[0092] Each of the multiple resin side surfaces 831 to 834 is connected to both the resin main surface 81 and the resin back surface 82 and is sandwiched between them in the thickness direction z. As shown in FIG. 4 and other figures, the resin side surface 831 and the resin side surface 832 are spaced apart in the first direction x. The resin side surface 831 faces the x2 side of the first direction x, and the resin side surface 832 faces the x1 side of the first direction x. Two third terminals 43 protrude from the resin side surface 831, and the first terminal 41, the second terminal 42, and the fourth terminal 44 protrude from the resin side surface 832. As shown in FIG. 4 and other figures, the resin side surface 833 and the resin side surface 834 are spaced apart in the second direction y. The resin side surface 833 faces the y2 side of the second direction y, and the resin side surface 834 faces the y1 side of the second direction y.

[0093] As shown in FIG. 4 , a plurality of recesses 832a are formed in the resin side surface 832. Each recess 832a is a portion recessed in the first direction x in a plan view. The plurality of recesses 832a include those formed between the first terminal 41 and the fourth terminal 44 and those formed between the second terminal 42 and the fourth terminal 44 in a plan view. The plurality of recesses 832a are provided to increase the creepage distance along the resin side surface 832 between the first terminal 41 and the fourth terminal 44 and the creepage distance along the resin side surface 832 between the second terminal 42 and the fourth terminal 44.

[0094] Next, a vehicle B1 equipped with the semiconductor device A1 will be described with reference to Fig. 20. The vehicle B1 is, for example, an electric vehicle (EV).

[0095] As shown in Fig. 20, vehicle B1 includes an on-board charger 91, a storage battery 92, and a drive system 93. Power is supplied to the on-board charger 91 wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power may be supplied from the power supply facility to the on-board charger 91 via a wired connection. The on-board charger 91 is configured with a step-up DC-DC converter. The voltage of the power supplied to the on-board charger 91 is stepped up by the converter and then supplied to the storage battery 92. The stepped-up voltage is, for example, 600 V.

[0096] The drive system 93 drives the vehicle B1. The drive system 93 has an inverter 931 and a drive source 932. The semiconductor device A1 constitutes part of the inverter 931. Power stored in the storage battery 92 is supplied to the inverter 931. The power supplied from the storage battery 92 to the inverter 931 is DC power. In addition, unlike the power system shown in FIG. 20 , a step-up DC-DC converter may be further provided between the storage battery 92 and the inverter 931. The inverter 931 converts DC power into AC power. The inverter 931 including the semiconductor device A1 is electrically connected to the drive source 932.

[0097] The drive source 932 includes an AC motor and a transmission. When AC power converted by the inverter 931 is supplied to the drive source 932, the AC motor rotates and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotation speed transmitted from the AC motor and then rotates the drive shaft of the vehicle B1. This drives the vehicle B1. To drive the vehicle B1, it is necessary to freely control the rotation speed of the AC motor based on information such as the amount of fluctuation in the accelerator pedal. The semiconductor device A1 in the inverter 931 is required to output AC power whose frequency has been appropriately changed to correspond to the required rotation speed of the AC motor.

[0098] Next, the operation of the semiconductor device A1 will be described.

[0099] 9, the region 482E of the first sub-substrate 48A is electrically connected to the first conductive portion 32A via the connecting conductive portion 485 and the second sub-metal layer 483. Therefore, to electrically connect the control terminal 46E and the first conductive portion 32A shown in FIG. 17, it is sufficient to electrically connect the region 482D and the region 482E, and it is not necessary to connect another conductive member to the first conductive portion 32A. Therefore, a wider variety of conductive paths to the main substrate 3 can be set.

[0100] The first sub-metal layer 482 has a surface metal layer 4829. The plurality of wires 71, 72, and 73 are connected to the surface metal layer 4829. This makes it possible to prevent the Kirkendall void phenomenon from occurring at the connection portions between the plurality of wires 71, 72, and 73 and the base material layer 4820. When the plurality of wires 71, 72, and 73 contain Al (aluminum) and the base material layer 4820 contains Cu (copper), the Kirkendall void phenomenon can be more reliably suppressed by providing the surface metal layer 4829 containing Ni (nickel).

[0101] Furthermore, since the control terminal 46E is used to detect the potential at the first conductive portion 32A, there is no need to connect a wire or the like to the first conductive portion 32A. Therefore, there is no need to provide a metal layer or the like in the first conductive portion 32A to suppress the Kirkendall void phenomenon. This is advantageous for reducing the cost of the semiconductor device A1.

[0102] As shown in Figures 17 and 18, the first sub-substrate 48A and the second sub-substrate 48B have a common configuration. As shown in Figure 17, in the first sub-substrate 48A, region 482E and connection portion 4821D are connected by wire 73, making it possible to detect the potential of the first conductive portion 32A using control terminal 46E. On the other hand, as shown in Figure 18, temperature monitoring is possible using control terminal 47C and control terminal 47D by connecting thermistor 17 to connection portion 4821C and connection portion 4821D. In this way, two sub-substrates, namely, the first sub-substrate 48A and the second sub-substrate 48B, which have different functions, can be realized using a single type of sub-substrate, which is advantageous for reducing the cost of the semiconductor device A1.

[0103] 21 to 33 show other modified embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are given the same reference numerals. Furthermore, the configurations of the various parts in each modified embodiment and each embodiment can be combined as appropriate to the extent that no technical contradictions arise. Furthermore, in the following modified embodiments and embodiments, unless otherwise specified, the following will be described as matters common to the first sub-substrate 48A and the second sub-substrate 48B.

[0104] First Modification of First Embodiment: FIG. 21 shows a first modification of the semiconductor device A1. The semiconductor device A11 of this modification differs from the above-described example in the configuration of the linking conductive portion 485. In this modification, the linking conductive portion 485 penetrates the first sub-metal layer 482 (region 482E) and the sub-insulating layer 481 and further penetrates into a portion of the second sub-metal layer 483. For example, when processing the first sub-metal layer 482 and the sub-insulating layer 481 to form the linking conductive portion 485, the first sub-metal layer 482 is removed from the z1 side to the z2 side in the thickness direction z, and a portion of the second sub-metal layer 483 is removed beyond the first sub-metal layer 482 and the sub-insulating layer 481. This removal process may be, for example, mechanical processing or chemical processing such as etching.

[0105] This modification also makes it possible to set a wider variety of conductive paths to the main substrate 3. Furthermore, in the removal process for forming the connecting conductive portion 485, a through-hole is formed that completely penetrates the sub-insulating layer 481. This ensures that the connecting conductive portion 485 is electrically connected to the second sub-metal layer 483.

[0106] 22 shows a second modification of the semiconductor device A1. In the semiconductor device A12 of this modification, the linking conductive portion 485 penetrates the second sub-metal layer 483 and the sub-insulating layer 481 and contacts the first sub-metal layer 482 (region 482E).

[0107] This modification also makes it possible to set a wider variety of conductive paths leading to the main substrate 3. Furthermore, as can be understood from this modification, the connecting conductive portion 485 may be configured to penetrate the first sub-metal layer 482 or the second sub-metal layer 483.

[0108] 23 shows a third modification of the semiconductor device A1. In the semiconductor device A13 of this modification, the linking conductive portion 485 penetrates the first sub-metal layer 482 (region 482E), the sub-insulating layer 481, and the second sub-metal layer 483.

[0109] This modification also makes it possible to set a wider variety of conductive paths leading to the main board 3. Furthermore, as can be understood from this modification, the connecting conductive portion 485 may be configured to penetrate the entire first sub-board 48A and the second sub-board 48B in the thickness direction z.

[0110] Fourth Modification of First Embodiment: FIG. 24 shows a fourth modification of the semiconductor device A1. In the semiconductor device A14 of this modification, the first sub-substrate 48A has a plurality of connecting conductive portions 485. In the illustrated example, the first sub-substrate 48A has three connecting conductive portions 485. One connecting conductive portion 485 provides electrical continuity between the region 482E and the second sub-metal layer 483. Two connecting conductive portions 485 provide electrical continuity between two regions 482F and the second sub-metal layer 483. One of the two regions 482F is the one of the multiple regions 482F arranged closest to the y1 side in the second direction y, and the other is the third region 482F of the multiple regions 482F counting from the y1 side in the second direction y.

[0111] This modification also allows for a wider variety of conductive paths to be set up to the main substrate 3. Furthermore, as can be seen from this modification, there is no limitation on the number of connecting conductive portions 485. The region 482F is not connected to the wires 71 to 73 or the control terminal 45. Therefore, even if the region 482F is electrically connected to the second sub-metal layer 483 by the connecting conductive portion 485, the electrical function of the semiconductor device A14 is achieved.

[0112] 25 and 26 show a semiconductor device according to a second embodiment of the present disclosure. The semiconductor device A2 of this embodiment differs from the above-described embodiments in the method of electrically connecting the second sub-metal layer 483 of the first sub-substrate 48A to the first conductive portion 32A. In this embodiment, laser bonding is used to electrically connect the second sub-metal layer 483 of the first sub-substrate 48A to the first conductive portion 32A.

[0113] An opening 4811 is provided in the sub-insulating layer 481. The opening 4811 penetrates the sub-insulating layer 481 in the thickness direction z, exposing the second sub-metal layer 483 on the z1 side in the thickness direction z. A bonding portion 4839 is formed in the second sub-metal layer 483.

[0114] The joint 4839 is formed, for example, by irradiating a laser beam onto a portion of the second sub-metal layer 483 that is exposed from the opening 4811 while the first sub-substrate 48A is placed on the first conductive portion 32A. The laser beam causes a portion of the second sub-metal layer 483 and a portion of the first conductive portion 32A to fuse together, thereby forming the joint 4839 as shown in the figure.

[0115] In the illustrated example, the sub-insulating layer 481 has three openings 4811. The control terminal support 48 (second sub-metal layer 483) also has three joints 4839. The three openings 4811 and the three joints 4839 are spaced apart from one another in the second direction y. Two openings 4811 and two joints 4839 are formed at both ends of the first sub-substrate 48A in the second direction y. One opening 4811 and one joint 4839 are formed between the terminal portion 4822B and the terminal portion 4822C in the second direction y, and are formed approximately in the center of the first sub-substrate 48A in the second direction y.

[0116] This embodiment also makes it possible to set a wider variety of conductive paths to the main substrate 3. Furthermore, laser bonding makes it possible to reduce the amount of heat applied to the first sub-substrate 48A and the first conductive portion 32A when bonding the first sub-substrate 48A to the first conductive portion 32A. This is suitable for suppressing unintended thermal deformation of the first sub-substrate 48A, etc.

[0117] 27 shows a first modification of the semiconductor device A2. In the semiconductor device A21 of this modification, a recess 48313 is formed in the second sub-metal layer 483.

[0118] For example, in the removal process for forming the opening 4811, after the sub-insulating layer 481 is penetrated, a part of the sub-insulating layer 481 is removed to form the recess 4831. A laser beam is irradiated onto the bottom of the recess 4831 to form the bonding portion 4839.

[0119] This modification also allows for a wider variety of conductive paths to be set up to the main substrate 3. Furthermore, in this modification, the formation of the recess 4831 makes it possible to more reliably form the opening 4811 penetrating the sub-insulating layer 481. Therefore, it is possible to avoid a situation in which the formation of the joint 4839 is insufficient due to a portion of the sub-insulating layer 481 unintentionally remaining during laser bonding to form the joint 4839.

[0120] 28 shows a second modification of the semiconductor device A2. In the semiconductor device A22 of this modification, the first sub-metal layer 482 has an opening 4825.

[0121] The opening 4825 penetrates the first sub-metal layer 482 in the thickness direction z. The opening 4825 is substantially aligned with the opening 4811 when viewed in the thickness direction z.

[0122] This modification also makes it possible to set a wider variety of conduction paths leading to the main substrate 3. Furthermore, as can be understood from this modification, in the laser bonding to form the bonding portion 4839, laser light may be irradiated onto the first sub-metal layer 482 through the openings 4825 and 4811.

[0123] 29 shows a third modification of the semiconductor device A2. In this modification, the sub-insulation layer 481 has an opening 4811, the first sub-metal layer 482 has an opening 4825, and the second sub-metal layer 483 has a recess 4831.

[0124] This modification also makes it possible to set a wider variety of conduction paths to the main substrate 3. Furthermore, by forming the recess 4831, the portion of the second sub-metal layer 483 that is irradiated with laser light during laser bonding to form the bonding portion 4839 is spaced further away from the first sub-metal layer 482 on the z2 side in the thickness direction z. This makes it possible to prevent the heat of the laser bonding from reaching the first sub-metal layer 482.

[0125] Fourth Modification of Second Embodiment: Figure 30 shows a fourth modification of the semiconductor device A2. The semiconductor device A24 of this modification differs from the above-described example in the configuration of the two openings 4811 formed at both ends of the first sub-substrate 48A in the second direction y. In this modification, the two openings 4811 formed at both ends of the first sub-substrate 48A in the second direction y are connected to both edges of the openings 4811 in the second direction y. In other words, these openings 4811 are not closed when viewed in the thickness direction z, but are open to the outside of the sub-insulating layer 481.

[0126] This modification also makes it possible to set a wider variety of conduction paths to the main substrate 3. Furthermore, as can be seen from this modification, there are no limitations on the shape and arrangement of the openings 4811. According to this modification, the dimension of the first sub-substrate 48A in the second direction y can be reduced compared to, for example, the semiconductor device A2.

[0127] 31 shows a semiconductor device according to a third embodiment of the present disclosure. A semiconductor device A3 of this embodiment differs from the above-described embodiments in the configurations of a first sub-substrate 48A and a second sub-substrate 48B.

[0128] In this embodiment, the first sub-substrate 48A and the second sub-substrate 48B are formed of glass epoxy resin substrates. The sub-insulating layer 481 is a layer made of glass epoxy resin. The first sub-metal layer 482 and the second sub-metal layer 483 are, for example, metal plating layers formed on both sides of the sub-insulating layer 481 and contain, for example, Cu (copper). The shape of the first sub-metal layer 482 as viewed in the thickness direction z is similar to, for example, the first sub-metal layer 482 of the semiconductor device A1. The second sub-metal layer 483 is conductively joined to the first conductive portion 32A or the second conductive portion 32B by, for example, a conductive bonding material 49.

[0129] The connecting conductive portion 485 of this embodiment has a configuration known as a through-hole conductive portion, in which a through-hole is formed penetrating the sub-insulating layer 481, the first sub-metal layer 482, and the second sub-metal layer 483, and the connecting conductive portion 485 is made of a metal plating layer formed on the inner surface of the through-hole.

[0130] This embodiment also makes it possible to set a wider variety of conductive paths to the main substrate 3. Furthermore, as can be understood from this embodiment, there are no limitations on the specific configurations of the first sub-substrate 48A and the second sub-substrate 48B. The first sub-substrate 48A and the second sub-substrate 48B made of a glass epoxy resin substrate are suitable for finishing the first sub-metal layer 482 into a finer shape, for example.

[0131] 32 and 33 show a first modification of the semiconductor device A3. The semiconductor device A31 of this modification has a different configuration of the linking conductive portion 485 from the above-described embodiment.

[0132] In this modification, a concave groove extending in the thickness direction z is formed at the end on the y1 side in the second direction y of the sub-insulating layer 481. The connecting conductive portion 485 is formed to cover the groove and provides electrical continuity between the first sub-metal layer 482 and the second sub-metal layer 483.

[0133] This modification also allows for a wider variety of conductive paths to be set up to the main substrate 3. Furthermore, as can be seen from this modification, the specific configuration of the connecting conductive portion 485 is not limited in any way. According to this modification, as shown in Fig. 33, it is expected that the conductive bonding material 49 will adhere along the connecting conductive portion 485. This is suitable for increasing the bonding strength between the first sub-substrate 48A and the first conductive portion 32A.

[0134] The semiconductor device and vehicle according to the present disclosure are not limited to the above-described embodiments. The specific configurations of each part of the semiconductor device and vehicle according to the present disclosure can be freely designed and modified. Supplementary Note 1A: A semiconductor device comprising: a main substrate having a first main metal layer; a first semiconductor element supported on the main substrate; a first sub-substrate supported on the main substrate; and a sealing resin covering the first semiconductor element, wherein the first sub-substrate has a sub-insulating layer and a first sub-metal layer and a second sub-metal layer disposed on either side of the sub-insulating layer in the thickness direction, the second sub-metal layer being conductively bonded to the first main metal layer, the first sub-metal layer including a first region, and the first sub-substrate further having a connecting conductive portion connecting the first region and the second sub-metal layer. Supplementary Note 2A: The semiconductor device according to Supplementary Note 1A, wherein the first semiconductor element is conductively bonded to the first main metal layer. Appendix 3A The semiconductor device according to Appendix 1A or 2A, further comprising a first control terminal electrically connected to the first region and protruding from the sealing resin. Appendix 4A The semiconductor device according to Appendix 3A, wherein the first sub-metal layer further includes a second region spaced apart from the first region. Appendix 5A The semiconductor device according to Appendix 4A, wherein the first control terminal is supported by the second region. Appendix 6A The semiconductor device according to Appendix 5A, further comprising a first wire connected to the first region and the second region. Appendix 7A The semiconductor device according to Appendix 6A, wherein the first sub-metal layer further includes a third region spaced apart from the first region and the second region and located between the first region and the second region. Appendix 8A The semiconductor device according to Appendix 6A or 7A, wherein the first sub-metal layer includes a base material layer and a surface metal layer. Appendix 9A The semiconductor device according to Appendix 8A, wherein the base material layer includes Cu. Appendix 10A The semiconductor device according to Appendix 9A, wherein the surface metal layer contains Ni. Appendix 11A The semiconductor device according to Appendix 10A, wherein the first sub-metal layer contains Cu. Appendix 12A The semiconductor device according to Appendix 11A, wherein the first wire contains Al. Appendix 13A The semiconductor device according to any one of Appendixes 1A to 12A, wherein the second sub-metal layer is conductively joined to the first main metal layer by a conductive bonding material.Appendix 14A The semiconductor device according to any one of Appendixes 1A to 12A, wherein the second sub-metal layer is conductively bonded to the first main metal layer by laser bonding. Appendix 15A The semiconductor device according to Appendix 14A, wherein the second sub-metal layer has a bonding portion formed by laser bonding, and the second sub-metal layer has an opening that contains the bonding portion when viewed in the thickness direction. Appendix 16A The semiconductor device according to any one of Appendixes 1A to 15A, wherein the sub-insulating layer includes ceramics. Appendix 17A The semiconductor device according to any one of Appendixes 1A to 15A, wherein the sub-insulating layer includes glass epoxy resin. Appendix 18A A vehicle comprising: a drive source; and the semiconductor device according to any one of Appendixes 1A to 17A, wherein the semiconductor device is conductive to the drive source.

[0135] Next, fourth to sixth embodiments of the present disclosure will be described with reference to Figures 34 to 67. Figures 34 to 55 show a semiconductor device according to the fourth embodiment of the present disclosure. A semiconductor device A1 of this embodiment includes a plurality of first semiconductor elements 10A, a plurality of second semiconductor elements 10B, a thermistor 17, a support substrate 3, a first terminal 41, a second terminal 42, a plurality of third terminals 43, a fourth terminal 44, a plurality of control terminals 45, a control terminal support 48, a third conductive component 38, wires 71 to 74, a first conductive member 5, a second conductive member 6, and a sealing resin 8.

[0136] FIG. 34 is a perspective view showing the semiconductor device A1. FIGS. 35 and 36 are partial perspective views showing the semiconductor device A1. FIG. 37 is a plan view showing the semiconductor device A1. FIG. 38 is a partial plan view showing the semiconductor device A1. FIG. 39 is a partial side view showing the semiconductor device A1. FIG. 40 is a partial enlarged plan view showing the semiconductor device A1. FIGS. 41 and 42 are partial plan views showing the semiconductor device A1. FIG. 43 is a side view showing the semiconductor device A1. FIG. 44 is a bottom view showing the semiconductor device A1. FIG. 45 is a cross-sectional view taken along line XLV-XLV in FIG. 38. FIG. 46 is a cross-sectional view taken along line XLVI-XLVI in FIG. 38. FIGS. 47 and 48 are partial enlarged cross-sectional views showing the semiconductor device A1. FIG. 49 is a cross-sectional view taken along line XLIX-XLIX in FIG. 38. FIG. 50 is a cross-sectional view taken along line LL in FIG. 38. FIG. 51 is a cross-sectional view taken along line LI-LI in FIG. 38. Fig. 52 is a cross-sectional view taken along line LII-LII in Fig. 38. Fig. 53 is a cross-sectional view taken along line LIII-LIII in Fig. 38. Fig. 54 is a cross-sectional view taken along line LIV-LIV in Fig. 42. Fig. 55 is a cross-sectional view of the third conductive component 38.

[0137] 34 to 55, the thickness direction z is the thickness direction of the present disclosure, the first direction x is the first direction of the present disclosure, and the second direction y is the second direction of the present disclosure. Furthermore, one side of the first direction x is referred to as the x1 side of the first direction x, and the other side of the first direction x is referred to as the x2 side of the first direction x. Furthermore, one side of the second direction y is referred to as the y1 side of the second direction y, and the other side of the second direction y is referred to as the y2 side of the second direction y. Furthermore, one side of the thickness direction z is referred to as the z1 side of the thickness direction z, and the other side of the thickness direction z is referred to as the z2 side of the thickness direction z.

[0138] The multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B are electronic components that are central to the functionality of the semiconductor device A1. The constituent material of each of the first semiconductor elements 10A and each of the second semiconductor elements 10B is a semiconductor material primarily composed of, for example, silicon carbide (SiC). This semiconductor material is not limited to SiC and may be silicon (Si), gallium nitride (GaN), diamond (C), or the like. Each of the first semiconductor elements 10A and each of the second semiconductor elements 10B is, for example, a power semiconductor chip with switching function, such as a metal oxide semiconductor field effect transistor (MOSFET). In this embodiment, the first semiconductor elements 10A and the second semiconductor elements 10B are MOSFETs, but are not limited thereto and may be other transistors such as insulated gate bipolar transistors (IGBTs). Each of the first semiconductor elements 10A and each of the second semiconductor elements 10B is the same element. Each of the first semiconductor elements 10A and each of the second semiconductor elements 10B is, for example, an n-channel MOSFET, but may also be a p-channel MOSFET.

[0139] 47 and 48 , the first semiconductor element 10A and the second semiconductor element 10B each have an element main surface 101 and an element back surface 102. In each of the first semiconductor elements 10A and the second semiconductor elements 10B, the element main surface 101 and the element back surface 102 are spaced apart in the thickness direction z. The element main surface 101 faces the z1 side in the thickness direction z, and the element back surface 102 faces the z2 side in the thickness direction z.

[0140] In this embodiment, the semiconductor device A1 includes four first semiconductor elements 10A and four second semiconductor elements 10B. However, the number of first semiconductor elements 10A and the number of second semiconductor elements 10B are not limited to this configuration and may be changed as appropriate depending on the performance required of the semiconductor device A1. In the example shown in FIGS. 41 and 42 , four first semiconductor elements 10A and four second semiconductor elements 10B are arranged. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B may be two, three, or five or more. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B may be equal to or different from each other. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B is determined by the current capacity handled by the semiconductor device A1.

[0141] The semiconductor device A1 is configured, for example, as a half-bridge switching circuit. In this case, a plurality of first semiconductor elements 10A form an upper arm circuit of the semiconductor device A1, and a plurality of second semiconductor elements 10B form a lower arm circuit. In the upper arm circuit, the plurality of first semiconductor elements 10A are connected in parallel with each other, and in the lower arm circuit, the plurality of second semiconductor elements 10B are connected in parallel with each other. Each first semiconductor element 10A and each second semiconductor element 10B are connected in series to form a bridge layer.

[0142] As shown in FIGS. 41 , 42 , and 52 , each of the multiple first semiconductor elements 10A is mounted on a first conductive portion 32A of a support substrate 3 (described later). In the example shown in FIGS. 41 and 42 , the multiple first semiconductor elements 10A are aligned, for example, in the second direction y and spaced apart from one another. Each first semiconductor element 10A is conductively bonded to the first conductive portion 32A via a first conductive bonding material 19A. When each first semiconductor element 10A is bonded to the first conductive portion 32A, the element back surface 102 faces the first conductive portion 32A. Unlike the present embodiment, the multiple first semiconductor elements 10A may be mounted on a metal member other than a part of the DBC substrate, etc. In this case, the metal member corresponds to the first conductive portion in the present disclosure. This metal member may be supported by, for example, the first conductive portion 32A.

[0143] As shown in FIGS. 41 , 42 , and 51 , each of the multiple second semiconductor elements 10B is mounted on a second conductive portion 32B of a support substrate 3 (described later). In the example shown in FIGS. 41 and 42 , the multiple second semiconductor elements 10B are aligned, for example, in the second direction y and spaced apart from one another. Each second semiconductor element 10B is conductively bonded to the second conductive portion 32B via a second conductive bonding material 19B. When each second semiconductor element 10B is bonded to the second conductive portion 32B, the element back surface 102 faces the second conductive portion 32B. As can be seen from FIG. 42 , the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B overlap when viewed in the first direction x, but they do not necessarily need to overlap. Note that, unlike the present embodiment, the multiple second semiconductor elements 10B may be mounted on a metal member other than a part of the DBC substrate, etc. In this case, the metal member corresponds to the second conductive portion in this disclosure. This metal member may be supported by, for example, the second conductive portion 32B.

[0144] The first semiconductor elements 10A and the second semiconductor elements 10B each have a first principal surface electrode 11, a second principal surface electrode 12, a third principal surface electrode 13, and a back surface electrode 15. The configurations of the first principal surface electrode 11, the second principal surface electrode 12, the third principal surface electrode 13, and the back surface electrode 15 described below are common to the first semiconductor elements 10A and the second semiconductor elements 10B. The first principal surface electrode 11, the second principal surface electrode 12, and the third principal surface electrode 13 are provided on the element main surface 101. The first principal surface electrode 11, the second principal surface electrode 12, and the third principal surface electrode 13 are insulated by an insulating film (not shown). The back surface electrode 15 is provided on the element back surface 102. The first principal surface electrode 11 is, for example, a gate electrode, to which a drive signal (e.g., a gate voltage) for driving the first semiconductor element 10A (second semiconductor element 10B) is input. In the first semiconductor element 10A (second semiconductor element 10B), the second principal surface electrode 12 is, for example, a source electrode through which a source current flows. The second principal surface electrode 12 of this embodiment has a gate finger 121. The gate finger 121 is, for example, made of a linear insulator extending in the first direction x, and divides the second principal surface electrode 12 into two parts in the second direction y. The third principal surface electrode 13 is, for example, a source sense electrode through which a source current flows. The back surface electrode 15 is, for example, a drain electrode through which a drain current flows. The back surface electrode 15 covers substantially the entire area of ​​the back surface 102 of the element. The back surface electrode 15 is, for example, formed by Ag (silver) plating.

[0145] When a drive signal (gate voltage) is input to the first principal surface electrode 11 (gate electrode), each first semiconductor element 10A (each second semiconductor element 10B) switches between a conductive state and a non-conductive state in response to the drive signal. In the conductive state, current flows from the back surface electrode 15 (drain electrode) to the second principal surface electrode 12 (source electrode), and in the non-conductive state, current does not flow. In other words, each first semiconductor element 10A (each second semiconductor element 10B) performs a switching operation. The semiconductor device A1 converts a DC voltage input between the single fourth terminal 44 and the two first and second terminals 41 and 42 into, for example, an AC voltage, and outputs the AC voltage from the third terminal 43, using the switching functions of the multiple first semiconductor elements 10A and multiple second semiconductor elements 10B.

[0146] The thermistor 17 is used as a temperature detection sensor. The semiconductor device A1 may be configured to include, for example, a temperature-sensitive diode in addition to the thermistor 17, or may be configured without the thermistor 17 or the like.

[0147] The support substrate 3 supports a plurality of first semiconductor elements 10A and a plurality of second semiconductor elements 10B. The specific configuration of the support substrate 3 is not limited, and may be, for example, a DBC (Direct Bonded Copper) substrate or an AMB (Active Metal Brazing) substrate. The support substrate 3 includes an insulating layer 31, a front metal layer 32, and a back metal layer 33. The front metal layer 32 includes a first conductive portion 32A and a second conductive portion 32B. Here, the first conductive portion 32A corresponds to the first conductive component of the present disclosure. The dimension of the support substrate 3 in the thickness direction z is, for example, 0.4 mm or more and 3.0 mm or less.

[0148] The insulating layer 31 is made of, for example, ceramics with excellent thermal conductivity. Examples of such ceramics include SiN (silicon nitride). The insulating layer 31 is not limited to ceramics and may be an insulating resin sheet or the like. The insulating layer 31 has, for example, a rectangular shape in a plan view. The dimension of the insulating layer 31 in the thickness direction z is, for example, 0.05 mm or more and 1.0 mm or less.

[0149] The first conductive portion 32A supports a plurality of first semiconductor elements 10A, and the second conductive portion 32B supports a plurality of second semiconductor elements 10B. The first conductive portion 32A and the second conductive portion 32B are formed on the upper surface of the insulating layer 31 (the surface facing the z1 side in the thickness direction z). The constituent material of the first conductive portion 32A and the second conductive portion 32B includes, for example, Cu (copper). The constituent material may include, for example, Al (aluminum) other than Cu (copper). The first conductive portion 32A and the second conductive portion 32B are spaced apart in the first direction x. The first conductive portion 32A is located on the x1 side of the second conductive portion 32B in the first direction x. The first conductive portion 32A and the second conductive portion 32B each have, for example, a rectangular shape in a plan view. The first conductive portion 32A and the second conductive portion 32B, together with the first conductive member 5 and the second conductive member 6, constitute a path of the main circuit current switched by the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B.

[0150] The first conductive portion 32A has a first main surface 301A. The first main surface 301A is a flat surface facing the z1 side in the thickness direction z. A plurality of first semiconductor elements 10A are bonded to the first main surface 301A of the first conductive portion 32A via first conductive bonding materials 19A. The second conductive portion 32B has a second main surface 301B. The second main surface 301B is a flat surface facing the z1 side in the thickness direction z. A plurality of second semiconductor elements 10B are bonded to the second main surface 301B of the second conductive portion 32B via second conductive bonding materials 19B. The constituent materials of the first conductive bonding material 19A and the second conductive bonding material 19B are not particularly limited and may be, for example, solder, a metal paste material containing a metal such as Ag (silver), or a sintered metal containing a metal such as Ag (silver). The dimension of first conductive portion 32A and second conductive portion 32B in thickness direction z is, for example, not less than 0.1 mm and not more than 1.5 mm.

[0151] The back surface metal layer 33 is formed on the lower surface (surface facing the z2 side in the thickness direction z) of the insulating layer 31. The constituent material of the back surface metal layer 33 is the same as the constituent material of the front surface metal layer 32. The back surface metal layer 33 has a back surface 302. The back surface 302 is a flat surface facing the z2 side in the thickness direction z. In the example shown in FIG. 44 , the back surface 302 is exposed from the sealing resin 8, for example. A heat dissipation member (for example, a heat sink) (not shown) can be attached to the back surface 302. The back surface 302 may not be exposed from the sealing resin 8 and may be covered by the sealing resin 8. The back surface metal layer 33 overlaps both the first conductive portion 32A and the second conductive portion 32B in a plan view.

[0152] The first terminal 41, the second terminal 42, the plurality of third terminals 43, and the fourth terminal 44 are each made of a plate-shaped metal plate. This metal plate contains, for example, Cu (copper) or a Cu (copper) alloy. In the examples shown in Figures 34 to 38, 41, 42, and 44, the semiconductor device A1 includes one each of the first terminal 41, the second terminal 42, and the fourth terminal 44, and two third terminals 43, but the number of each terminal is not limited in any way.

[0153] A DC voltage to be converted into power is input to the first terminal 41, the second terminal 42, and the fourth terminal 44. The fourth terminal 44 is a positive electrode (P terminal), and the first terminal 41 and the second terminal 42 are each a negative electrode (N terminal). An AC voltage converted into power by the first semiconductor element 10A and the second semiconductor element 10B is output from the plurality of third terminals 43. The first terminal 41, the second terminal 42, the plurality of third terminals 43, and the fourth terminal 44 each include a portion covered with the sealing resin 8 and a portion exposed from the sealing resin 8.

[0154] As shown in FIG. 46 , the fourth terminal 44 is conductively bonded to the first conductive portion 32A. The method of conductive bonding is not limited, and methods such as ultrasonic bonding, laser bonding, welding, or methods using solder, metal paste, sintered silver, etc. may be appropriately adopted. As shown in FIGS. 41 and 42 , the fourth terminal 44 is located on the x1 side in the first direction x with respect to the multiple first semiconductor elements 10A and the first conductive portions 32A. The fourth terminal 44 is conductively connected to the first conductive portion 32A and, via the first conductive portion 32A, to the back surface electrode 15 (drain electrode) of each first semiconductor element 10A.

[0155] The first terminal 41 and the second terminal 42 are electrically connected to the second conductive member 6. In this embodiment, the first terminal 41 and the second conductive member 6 are integrally formed. The term "integrally formed" refers to a configuration in which the first terminal 41 and the second conductive member 6 are formed, for example, by cutting and bending a single metal plate material, without using any bonding material to join them. Furthermore, in this embodiment, the second terminal 42 and the second conductive member 6 are integrally formed. Note that the first terminal 41 and the second terminal 42 may be configured to be electrically connected to the second conductive member 6, and may have a bonding portion to join them, unlike this embodiment. As shown in FIGS. 35 and 38 , the first terminal 41 and the second terminal 42 are each located on the x1 side in the first direction x with respect to the multiple first semiconductor elements 10A and the first conductive portion 32A. The first terminal 41 and the second terminal 42 are each electrically connected to the second conductive member 6 and, via the second conductive member 6, to the second principal surface electrode 12 (source electrode) of each second semiconductor element 10B.

[0156] As shown in Figures 34 to 38 and 44, in the semiconductor device A1, the first terminal 41, the second terminal 42, and the fourth terminal 44 each protrude from the sealing resin 8 toward the x1 side in the first direction x. The first terminal 41, the second terminal 42, and the fourth terminal 44 are spaced apart from one another. The first terminal 41 and the second terminal 42 are located on opposite sides of the fourth terminal 44 in the second direction y. The first terminal 41 is located on the y1 side of the fourth terminal 44 in the second direction y, and the second terminal 42 is located on the y2 side of the fourth terminal 44 in the second direction y. The first terminal 41, the second terminal 42, and the fourth terminal 44 overlap one another when viewed in the second direction y.

[0157] As can be seen from FIGS. 41 , 42 , and 45 , the two third terminals 43 are each conductively bonded to the second conductive portion 32B. The conductive bonding method is not limited to any particular method, and methods such as ultrasonic bonding, laser bonding, and welding, or methods using solder, metal paste, silver sintered body, etc., may be appropriately employed. As shown in FIG. 41 and other figures, the two third terminals 43 are each located on the x2 side of the second semiconductor elements 10B and the second conductive portions 32B in the first direction x. Each third terminal 43 is conductively connected to the second conductive portion 32B and, via the second conductive portion 32B, to the back electrode 15 (drain electrode) of each second semiconductor element 10B. The number of third terminals 43 is not limited to two and may be, for example, one or three or more. For example, when there is one third terminal 43, it is preferably connected to the center portion of the second conductive portion 32B in the second direction y.

[0158] The plurality of control terminals 45 are pin-shaped terminals for controlling each of the first semiconductor elements 10A and each of the second semiconductor elements 10B. The plurality of control terminals 45 include a plurality of first control terminals 46A to 46E and a plurality of second control terminals 47A to 47D. The plurality of first control terminals 46A to 46E are used to control each of the first semiconductor elements 10A, etc. The plurality of second control terminals 47A to 47D are used to control each of the second semiconductor elements 10B, etc.

[0159] The multiple first control terminals 46A-46E are arranged at intervals in the second direction y. As shown in FIGS. 41 , 46 , 53 , etc., each of the first control terminals 46A-46E is supported by the first conductive portion 32A via a control terminal support body 48 (a first support portion 48A described below). As shown in FIGS. 38 and 41 , each of the first control terminals 46A-46E is located in the first direction x between the multiple first semiconductor elements 10A and the first terminal 41, the second terminal 42, and the fourth terminal 44.

[0160] The first control terminal 46A is a terminal (gate terminal) for inputting a drive signal for the plurality of first semiconductor elements 10A. A drive signal for driving the plurality of first semiconductor elements 10A is input to the first control terminal 46A (for example, a gate voltage is applied).

[0161] The first control terminal 46B is a terminal (source sense terminal) for detecting source signals of the multiple first semiconductor elements 10A. The first control terminal 46B detects a voltage (a voltage corresponding to a source current) applied to each second principal surface electrode 12 (source electrode) of the multiple first semiconductor elements 10A.

[0162] The first control terminal 46C and the first control terminal 46D are terminals that are electrically connected to the thermistor 17.

[0163] The first control terminal 46E is a terminal (drain sense terminal) for detecting drain signals of the multiple first semiconductor elements 10A. The first control terminal 46E detects a voltage (a voltage corresponding to a drain current) applied to each back electrode 15 (drain electrode) of the multiple first semiconductor elements 10A.

[0164] The second control terminals 47A to 47D are arranged at intervals in the second direction y. As shown in Figures 41 and 46, each of the second control terminals 47A to 47D is supported by the second conductive portion 32B via a control terminal support 48 (a second support portion 48B described below). As shown in Figures 38 and 41, each of the second control terminals 47A to 47D is located between the second semiconductor elements 10B and two third terminals 43 in the first direction x.

[0165] The second control terminal 47A is a terminal (gate terminal) for inputting drive signals for the multiple second semiconductor elements 10B. A drive signal for driving the multiple second semiconductor elements 10B is input to the second control terminal 47A (for example, a gate voltage is applied). The second control terminal 47B is a terminal (source sense terminal) for detecting source signals for the multiple second semiconductor elements 10B. The second control terminal 47B detects a voltage (a voltage corresponding to a source current) applied to each second main surface electrode 12 (source electrode) of the multiple second semiconductor elements 10B. The second control terminal 47C and the second control terminal 47D are terminals that are electrically connected to the thermistor 17.

[0166] Each of the plurality of control terminals 45 (the plurality of first control terminals 46A to 46E and the plurality of second control terminals 47A to 47D) includes a holder 451 and a metal pin 452.

[0167] The holder 451 is made of a conductive material. As shown in FIGS. 47 and 48 , the holder 451 is bonded to the control terminal support 48 (first metal layer 482 described below) via a conductive bonding material 459. The holder 451 includes a cylindrical portion, an upper flange, and a lower flange. The upper flange is connected to the upper part of the cylindrical portion, and the lower flange is connected to the lower part of the cylindrical portion. A metal pin 452 is inserted through at least the upper flange and the cylindrical portion of the holder 451. The holder 451 is covered with sealing resin 8 (second protrusion 852 described below).

[0168] The metal pin 452 is a rod-shaped member extending in the thickness direction z. The metal pin 452 is supported by being press-fitted into the holder 451. The metal pin 452 is electrically connected to the control terminal support body 48 (a first metal layer 482 described below) at least via the holder 451. As in the examples shown in FIGS. 47 and 48 , when the lower end (the end on the z2 side in the thickness direction z) of the metal pin 452 is in contact with the conductive bonding material 459 inside the insertion hole of the holder 451, the metal pin 452 is electrically connected to the control terminal support body 48 via the conductive bonding material 459.

[0169] The control terminal support body 48 supports the plurality of control terminals 45. The control terminal support body 48 is interposed between the first main surface 301A and the second main surface 301B and the plurality of control terminals 45 in the thickness direction z.

[0170] The control terminal support 48 includes a first support portion 48A and a second support portion 48B. The first support portion 48A is disposed on the first conductive portion 32A and supports a plurality of first control terminals 46A to 46E among the plurality of control terminals 45. As shown in FIG. 47 , the first support portion 48A is bonded to the first conductive portion 32A via a bonding material 49. The bonding material 49 may be conductive or insulating, and is, for example, solder. The second support portion 48B is disposed on the second conductive portion 32B and supports a plurality of second control terminals 47A to 47D among the plurality of control terminals 45. As shown in FIG. 48 , the second support portion 48B is bonded to the second conductive portion 32B via the bonding material 49.

[0171] The control terminal support 48 (each of the first support portion 48A and the second support portion 48B) is made of, for example, a direct bonded copper (DBC) substrate and includes an insulating layer 481, a first metal layer 482, and a second metal layer 483 stacked on top of each other.

[0172] The insulating layer 481 is made of, for example, ceramics and has, for example, a rectangular shape in plan view.

[0173] As shown in Figures 47 and 48, the first metal layer 482 is formed on the upper surface of the insulating layer 481. Each control terminal 45 is provided upright on the first metal layer 482. The first metal layer 482 includes, for example, Cu (copper) or a Cu (copper) alloy. As shown in Figure 41, the first metal layer 482 includes a first portion 482A, a second portion 482B, a third portion 482C, a fourth portion 482D, a fifth portion 482E, and a sixth portion 482F. The first portion 482A, the second portion 482B, the third portion 482C, the fourth portion 482D, the fifth portion 482E, and the sixth portion 482F are separated and insulated from one another.

[0174] A plurality of wires 71 are bonded to the first portion 482A, and the first portion 482A is electrically connected to the first principal surface electrodes 11 (gate electrodes) of the first semiconductor elements 10A (second semiconductor elements 10B) via the wires 71. A plurality of wires 73 are connected between the first portion 482A and the sixth portion 482F. As a result, the sixth portion 482F is electrically connected to the first principal surface electrodes 11 (gate electrodes) of the first semiconductor elements 10A (second semiconductor elements 10B) via the wires 73 and 71. As shown in FIG. 41 , the first control terminal 46A is bonded to the sixth portion 482F of the first support portion 48A, and the second control terminal 47A is bonded to the sixth portion 482F of the second support portion 48B.

[0175] A plurality of wires 72 are bonded to the second portion 482B. The second portion 482B is electrically connected to the third principal surface electrode 13 (source sense electrode) of each first semiconductor element 10A (each second semiconductor element 10B) via each wire 72. As shown in FIG. 41 , a first control terminal 46B is bonded to the second portion 482B of the first support portion 48A, and a second control terminal 47B is bonded to the second portion 482B of the second support portion 48B.

[0176] The thermistor 17 is joined to the third portion 482C and the fourth portion 482D. As shown in Fig. 41 , the first control terminals 46C and 46D are joined to the third portion 482C and the fourth portion 482D of the first support portion 48A, and the second control terminals 47C and 47D are joined to the third portion 482C and the fourth portion 482D of the second support portion 48B.

[0177] The fifth portion 482E is electrically connected to the first conductive portion 32A via the wire 74. As shown in FIG. 41 , the first control terminal 46E is joined to the fifth portion 482E of the first support portion 48A. The fifth portion 482E of the second support portion 48B is not electrically connected to other components. The surface of the fifth portion 482E is plated with Ni (nickel), not shown. The wires 71 to 74 are made of a material that includes, for example, Au (gold), Al (aluminum), or Cu (copper).

[0178] As shown in Figures 47 and 48, the second metal layer 483 is formed on the lower surface of the insulating layer 481. As shown in Figure 47, the second metal layer 483 of the first support portion 48A is joined to the first conductive portion 32A via a bonding material 49. As shown in Figure 48, the second metal layer 483 of the second support portion 48B is joined to the second conductive portion 32B via a bonding material 49.

[0179] The wire 74 electrically connects the first conductive portion 32A and the fifth portion 482E. The wire 74 corresponds to the second conductive component of the present disclosure. The wire 74 includes a second metal, and in this embodiment, the second metal is the main component. The second metal is, for example, aluminum (Al).

[0180] As shown in FIGS. 41 , 42 , and 45 , the third conductive component 38 is disposed between the surface metal layer 32 and the wire 74. The surface metal layer 32 includes a first metal, and in this embodiment, the first metal is the main component. The first metal is, for example, Cu (copper). As shown in FIG. 42 , the third conductive component 38 is located on the y2 side in the y direction with respect to the first support portion 48A. The shape of the third conductive component 38 is not limited in any way, and in the illustrated example, it is rectangular when viewed in the z direction. The specific method for disposing the third conductive component 38 on the surface metal layer 32 is not limited in any way. In this embodiment, the third conductive component 38 is conductively bonded to the surface metal layer 32 by, for example, a conductive bonding material 39.

[0181] The specific configuration of the third conductive component 38 is not limited in any way. In the illustrated example, as shown in FIGS. 54 and 55 , the third conductive component 38 has a core material 381 and a first layer 382. The core material 381 is primarily composed of a first metal. The core material 381 is conductively bonded to the surface metal layer 32 by a conductive bonding material 39. The first layer 382 is stacked on the z1 side of the core material 381 in the z direction. The first layer 382 is primarily composed of a third metal. The third metal is, for example, Ni (nickel). The first layer 382 and the wire 74 are directly bonded. The first layer 382 is formed on the surface of the core material 381 by, for example, plating. In this case, the thickness of the first layer 382 in the z direction is thinner than the thickness of the core material 381 in the z direction.

[0182] The first conductive member 5 and the second conductive member 6, together with the first conductive portion 32A and the second conductive portion 32B, form a path for a main circuit current switched by the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B. The first conductive member 5 and the second conductive member 6 are spaced apart from the first main surface 301A and the second main surface 301B on the z1 side in the thickness direction z and overlap the first main surface 301A and the second main surface 301B in a plan view. In this embodiment, the first conductive member 5 and the second conductive member 6 are each made of a metal plate material. The metal includes, for example, Cu (copper) or a Cu (copper) alloy. Specifically, the first conductive member 5 and the second conductive member 6 are made of an appropriately bent metal plate material.

[0183] The first conductive member 5 is connected to the second principal surface electrode 12 (source electrode) of each first semiconductor element 10A and the second conductive portion 32B, and provides electrical continuity between the second principal surface electrode 12 of each first semiconductor element 10A and the second conductive portion 32B. The first conductive member 5 forms a path for a main circuit current switched by the multiple first semiconductor elements 10A. As shown in FIGS. 40 and 41 , the first conductive member 5 includes a main portion 51, multiple first bonding portions 52, and multiple second bonding portions 53.

[0184] The main portion 51 is located between the plurality of first semiconductor elements 10A and the second conductive portion 32B in the first direction x and is a strip-shaped portion extending in the second direction y in a plan view. The main portion 51 overlaps both the first conductive portion 32A and the second conductive portion 32B in a plan view and is spaced apart in the thickness direction z from the first main surface 301A and the second main surface 301B on the z1 side in the thickness direction z. As shown in FIG. 49 and other figures, the main portion 51 is located on the z2 side in the thickness direction z with respect to a third path portion 66 and a fourth path portion 67 of the second conductive member 6 described later and is closer to the first main surface 301A and the second main surface 301B than the third path portion 66 and the fourth path portion 67.

[0185] In this embodiment, the main portion 51 is disposed parallel to the first main surface 301A and the second main surface 301B.

[0186] As shown in FIG. 41 and other figures, the main portion 51 extends continuously in the second direction y to correspond to the region in which the multiple first semiconductor elements 10A are arranged. In this embodiment, as shown in FIGS. 40 , 41 , 46 , and other figures, multiple first openings 514 are formed in the main portion 51. Each of the multiple first openings 514 is, for example, a through-hole penetrating in the thickness direction z (the plate thickness direction of the main portion 51). The multiple first openings 514 are arranged at intervals in the second direction y. The multiple first openings 514 are provided corresponding to each of the multiple first semiconductor elements 10A. In this embodiment, four first openings 514 are provided in the main portion 51, and these first openings 514 and the multiple (four) first semiconductor elements 10A are positioned at the same position in the second direction y.

[0187] 41 , 46 , etc., in the present embodiment, each first opening 514 overlaps with a gap between the first conductive portion 32A and the second conductive portion 32B in a plan view. The multiple first openings 514 are formed to facilitate the flow of the resin material between the upper side (the z1 side in the thickness direction z) and the lower side (the z2 side in the thickness direction z) near the main portion 51 (first conductive member 5) when injecting the flowable resin material to form the sealing resin 8.

[0188] As shown in FIG. 41 and other figures, the multiple first bonding portions 52 and the multiple second bonding portions 53 are each connected to the main portion 51 and are arranged to correspond to the multiple first semiconductor elements 10A. Specifically, each first bonding portion 52 is located on the x1 side of the main portion 51 in the first direction x. Each second bonding portion 53 is located on the x2 side of the main portion 51 in the first direction x. As shown in FIG. 47 , each first bonding portion 52 is bonded to the corresponding second principal surface electrode 12 of one of the first semiconductor elements 10A via a conductive bonding material 59. Each second bonding portion 53 is bonded to the second conductive portion 32B via the conductive bonding material 59. The material of the conductive bonding material 59 is not particularly limited and may be, for example, solder, a metal paste material, or a sintered metal. In this embodiment, the first bonding portion 52 has two portions spaced apart in the second direction y. These two portions are joined to the second principal surface electrode 12 on both sides in the second direction y, with the gate finger 121 of the second principal surface electrode 12 of the first semiconductor element 10A sandwiched therebetween.

[0189] The second conductive member 6 electrically connects the second main surface electrode 12 (source electrode) of each second semiconductor element 10B to the first terminal 41 and the second terminal 42. The second conductive member 6 is integrally formed with the first terminal 41 and the second terminal 42. The second conductive member 6 forms a path for a main circuit current switched by the plurality of second semiconductor elements 10B. As shown in FIG. 40 , the second conductive member 6 includes a plurality of third joint portions 61, a first path portion 64, a second path portion 65, a plurality of third path portions 66, and a fourth path portion 67. In the illustrated example, the second conductive member 6 also includes a first step portion 602 and a second step portion 603.

[0190] The multiple third bonding portions 61 are portions that are individually bonded to the multiple second semiconductor elements 10B. Each third bonding portion 61 and the second main surface electrode 12 of each second semiconductor element 10B are bonded via a conductive bonding material 69. The material of the conductive bonding material 69 is not particularly limited and may be, for example, solder, a metal paste material, or a sintered metal. In this embodiment, the third bonding portion 61 has two flat portions 611 and two first inclined portions 612.

[0191] The two flat portions 611 are aligned in the second direction y. The two flat portions 611 are spaced apart from each other in the second direction y. The shape of the flat portions 611 is not limited in any way, and in the illustrated example, they are rectangular. The two flat portions 611 are joined to the second principal surface electrode 12 on both sides in the second direction y, sandwiching the gate finger 121 of the second principal surface electrode 12 of the second semiconductor element 10B therebetween.

[0192] The two first inclined portions 612 are connected to the outside of the two flat portions 611 in the second direction y. That is, the first inclined portion 612 located on the y1 side in the second direction y is connected to the y1 side in the second direction y of the flat portion 611 located on the y1 side in the second direction y. Furthermore, the first inclined portion 612 located on the y2 side in the second direction y is connected to the y2 side in the second direction y of the flat portion 611 located on the y2 side in the second direction y. The first inclined portion 612 is inclined so that the farther it is from the flat portion 611 in the second direction y, the closer it is to the z1 side in the thickness direction z.

[0193] The first path portion 64 is interposed between the plurality of third joint portions 61 and the first terminal 41. In the illustrated example, the first path portion 64 is connected to the first terminal 41 via a first step portion 602. The first path portion 64 overlaps the first conductive portion 32A in a plan view. The first path portion 64 has a shape that extends as a whole in the first direction x.

[0194] The first path portion 64 includes a first band-shaped portion 641 and a first extending portion 643. The first band-shaped portion 641 is located on the x2 side in the first direction x with respect to the first terminal 41, and is substantially parallel to the first main surface 301A. The first band-shaped portion 641 has a shape that extends in the first direction x as a whole. In the illustrated example, the first band-shaped portion 641 has a recess 649. The recess 649 is a portion of the first band-shaped portion 641 that is recessed toward the y1 side in the second direction y.

[0195] The first extending portion 643 extends from the side end of the first strip portion 641 on the y1 side in the second direction y to the z2 side in the thickness direction z. The first extending portion 643 is spaced apart from the first conductive portion 32A. In the illustrated example, the first extending portion 643 is shaped along the thickness direction z and has an elongated rectangular shape with the first direction x as the longitudinal direction. Note that the first path portion 64 may also be configured without the first extending portion 643.

[0196] The second path portion 65 is interposed between the plurality of third joint portions 61 and the second terminal 42. In the illustrated example, the second path portion 65 is connected to the second terminal 42 via the second step portion 603. The second path portion 65 overlaps the first conductive portion 32A in a plan view. The second path portion 65 has a shape that extends as a whole in the first direction x.

[0197] The second path portion 65 includes a second band-shaped portion 651 and a second extending portion 653. The second band-shaped portion 651 is located on the x2 side in the first direction x with respect to the second terminal 42 and is substantially parallel to the first main surface 301A. The second band-shaped portion 651 has a shape that extends in the first direction x as a whole. In the illustrated example, the second band-shaped portion 651 has a recess 659. The recess 659 is a portion of the second band-shaped portion 651 that is recessed toward the y2 side in the second direction y.

[0198] The second extending portion 653 extends from the side end of the second strip portion 651 on the y2 side in the second direction y to the z2 side in the thickness direction z. The second extending portion 653 is spaced apart from the first conductive portion 32A. In the example shown, the second extending portion 653 is shaped along the thickness direction z and has an elongated rectangular shape with the first direction x as the longitudinal direction. Note that the second path portion 65 may not have the second extending portion 653.

[0199] In the following description, when describing modified examples or other embodiments of the first path portion 64, the configuration of the first path portion 64 can also be appropriately adopted for the second path portion 65, for example, in a relationship where it is linearly symmetrical about a center line extending in the first direction x.

[0200] The multiple third path portions 66 are individually connected to the multiple third joint portions 61. Each third path portion 66 has a shape extending in the first direction x and is arranged at a distance from one another in the second direction y. There is no limitation on the number of multiple third path portions 66, and in the example shown, five third path portions 66 are arranged. Each third path portion 66 is arranged so as to be located between the multiple second semiconductor elements 10B in the second direction y or to be located outward of the multiple second semiconductor elements 10B in the second direction y.

[0201] Recesses 669 are formed in the two third path portions 66 located on both outer sides in the second direction y. The recesses 669 are recessed from the inside toward the outside in the second direction y. In the illustrated example, one recess 669 is formed in each of the two third path portions 66. In FIG. 38 , the second conductive portion 32B appears through these recesses 669.

[0202] In the present embodiment, one third joint 61 is disposed between two third path portions 66 adjacent to each other in the second direction y. In one third joint 61, the first inclined portion 612 located on the y1 side in the second direction y is connected to the third path portion 66 located on the y1 side in the second direction y, of the two third path portions 66 adjacent to each other in the second direction y. In one third joint 61, the first inclined portion 612 located on the y2 side in the second direction y is connected to the third path portion 66 located on the y2 side in the second direction y, of the two third path portions 66 adjacent to each other in the second direction y.

[0203] The fourth path portion 67 is connected to the ends of the plurality of third path portions 66 on the x1 side in the first direction x. The fourth path portion 67 has a shape that extends elongatedly in the second direction y. The fourth path portion 67 is connected to the ends of the first band portion 641 of the first path portion 64 and the second band portion 651 of the second path portion 65 on the x2 side in the first direction x. In the example shown, the first path portion 64 is connected to the end of the fourth path portion 67 on the y1 side in the second direction y. Furthermore, the second path portion 65 is connected to the end of the fourth path portion 67 on the y2 side in the second direction y.

[0204] The sealing resin 8 covers the plurality of first semiconductor elements 10A, the plurality of second semiconductor elements 10B, the support substrate 3 (excluding the back surface 302), portions of the first terminal 41, the second terminal 42, the plurality of third terminals 43, and the fourth terminal 44, portions of the plurality of control terminals 45, the control terminal support 48, the first conductive member 5, the second conductive member 6, and the plurality of wires 71 to 74. The sealing resin 8 is made of, for example, black epoxy resin. The sealing resin 8 is formed, for example, by molding. The sealing resin 8 has, for example, a dimension in the first direction x of approximately 35 mm to 60 mm, a dimension in the second direction y of approximately 35 mm to 50 mm, and a dimension in the thickness direction z of approximately 4 mm to 15 mm. These dimensions are the sizes of the largest portions along each direction. The sealing resin 8 has a resin main surface 81, a resin back surface 82, and multiple resin side surfaces 831 to 834.

[0205] As shown in Figures 43, 45, and 51, the resin main surface 81 and the resin back surface 82 are spaced apart in the thickness direction z. The resin main surface 81 faces the z1 side in the thickness direction z, and the resin back surface 82 faces the z2 side in the thickness direction z. A plurality of control terminals 45 (a plurality of first control terminals 46A to 46E and a plurality of second control terminals 47A to 47D) protrude from the resin main surface 81. As shown in Figure 44, the resin back surface 82 has a frame shape surrounding the back surface 302 (the lower surface of the back surface metal layer 33) of the support substrate 3 in a plan view. The back surface 302 of the support substrate 3 is exposed from the resin back surface 82 and is, for example, flush with the resin back surface 82. Each of the plurality of resin side surfaces 831 to 834 is connected to both the resin main surface 81 and the resin back surface 82 and is sandwiched between them in the thickness direction z. As shown in Figure 37 and other figures, the resin side surface 831 and the resin side surface 832 are spaced apart in the first direction x. The resin side surface 831 faces the x2 side in the first direction x, and the resin side surface 832 faces the x1 side in the first direction x. Two third terminals 43 protrude from the resin side surface 831, and the first terminal 41, the second terminal 42, and the fourth terminal 44 protrude from the resin side surface 832. As shown in Figure 37 and other figures, the resin side surface 833 and the resin side surface 834 are spaced apart in the second direction y. The resin side surface 833 faces the y2 side in the second direction y, and the resin side surface 834 faces the y1 side in the second direction y.

[0206] 37 , a plurality of recesses 832a are formed on the resin side surface 832. Each recess 832a is a portion recessed in the first direction x in a plan view. The plurality of recesses 832a include those formed between the first terminal 41 and the fourth terminal 44 and those formed between the second terminal 42 and the fourth terminal 44 in a plan view. The plurality of recesses 832a are provided to increase the creepage distance along the resin side surface 832 between the first terminal 41 and the fourth terminal 44 and the creepage distance along the resin side surface 832 between the second terminal 42 and the fourth terminal 44.

[0207] As shown in FIGS. 45 and 46 , the sealing resin 8 has a plurality of first protrusions 851 , a plurality of second protrusions 852 , and a resin gap 86 .

[0208] Each of the multiple first protrusions 851 protrudes from the resin main surface 81 in the thickness direction z. The multiple first protrusions 851 are arranged near the four corners of the sealing resin 8 in a plan view. A first protrusion end surface 851a is formed at the tip (the end on the z1 side in the thickness direction z) of each of the first protrusions 851. Each of the multiple first protrusions 851 has a bottomed, hollow truncated cone shape, for example. The multiple first protrusions 851 are used as spacers when the semiconductor device A1 is mounted on a control circuit board or other device that uses power generated by the semiconductor device A1. Each of the multiple first protrusions 851 has a recess 851b and an inner wall surface 851c formed in the recess 851b. The shape of each first protrusion 851 may be columnar, and is preferably cylindrical. The shape of the recess 851b is preferably cylindrical, and the inner wall surface 851c is preferably a single perfect circle in plan view.

[0209] The semiconductor device A1 may be mechanically fixed to a control circuit board or the like by a method such as screwing. In this case, a female screw thread may be formed on the inner wall surfaces 851c of the recesses 851b of the first protrusions 851. Insert nuts may be embedded in the recesses 851b of the first protrusions 851.

[0210] As shown in FIG. 46 and other figures, the multiple second protrusions 852 protrude from the resin main surface 81 in the thickness direction z. The multiple second protrusions 852 overlap the multiple control terminals 45 in a plan view. Each metal pin 452 of the multiple control terminals 45 protrudes from the corresponding second protrusion 852. Each second protrusion 852 has a truncated cone shape. In each control terminal 45, the second protrusion 852 covers the holder 451 and a portion of the metal pin 452.

[0211] Next, the operation of this embodiment will be described.

[0212] When the surface metal layer 32 is primarily composed of a first metal and the wire 74 is primarily composed of a second metal, directly joining the wire 74 to the surface metal layer 32 may result in unintended phenomena. In this embodiment, a third conductive component 38 is disposed between the surface metal layer 32 and the wire 74. The third conductive component 38 contains a third metal that is different from the first metal and the second metal. This prevents direct contact between a member made of the first metal and a member made of the second metal, thereby preventing unintended phenomena from occurring.

[0213] When the first metal is Cu (copper) and the second metal is Al (aluminum), for example, Kirkendall phenomenon may occur when the electrode is left at high temperatures. Therefore, by using Ni (nickel) as the third metal, the Kirkendall phenomenon can be suppressed.

[0214] The third conductive component 38 may be divided into a core material and a first layer 382, ​​and the first layer 382 containing the third metal as a main component may be formed on the surface that contacts the wire 74. This is because, in order to suppress the Kirkendall phenomenon, it is sufficient to form only the surface that contacts the wire 74 from a material containing the third metal as a main component. This reduces the cost of forming the third conductive component 38.

[0215] The third conductive component 38 is joined to the surface metal layer 32 via a conductive bonding material 39. A second layer mainly composed of a third metal is formed on the surface of the third conductive component 38 that contacts the conductive bonding material 39. This makes it possible to suppress the Kirkendall phenomenon between the third conductive component 38 and the conductive bonding material 39.

[0216] The control terminal support 48 has an insulating layer 31 and a first metal layer 482 and a second metal layer 483 on either side of the insulating layer 31. The control terminal support 48 is located on the support substrate 3. In this case, if the thickness T1 of the third conductive component 38 is made smaller than the thickness T2 of the control terminal support 48, it is possible to prevent other components from getting caught on the third conductive component 38 during assembly.

[0217] The first terminal 41 and the second conductive member 6 are integrally formed. This makes it possible to reduce the number of bonding steps in the manufacturing process of the semiconductor device A1 compared to a configuration in which the first terminal 41 and the second conductive member 6 are bonded together. Furthermore, it is possible to prevent cracks, peeling, etc. from occurring at the bonded portion when the semiconductor device A1 is in use. This makes it possible to simplify the manufacturing process of the semiconductor device A1 and improve reliability during use.

[0218] Furthermore, the second terminal 42 and the second conductive member 6 are integrally formed. This makes it possible to reduce the number of bonding steps in the manufacturing process of the semiconductor device A1 compared to a configuration in which the second terminal 42 and the second conductive member 6 are bonded together. It also makes it possible to prevent cracks, peeling, and the like from occurring at the bonded portion when the semiconductor device A1 is in use. This makes it possible to simplify the manufacturing process of the semiconductor device A1 and improve reliability during use.

[0219] The second conductive member 6 has a first step portion 602 connected to the first terminal 41. This can increase the rigidity of the connecting portion between the second conductive member 6 and the first terminal 41.

[0220] The second conductive member 6 has a second step portion 603 that is connected to the second terminal 42. This increases the rigidity of the connecting portion between the second conductive member 6 and the second terminal 42.

[0221] The third bonding portion 61 has two flat portions 611 and two first inclined portions 612. The two first inclined portions 612 are connected to the outside of the two flat portions 611 in the second direction y. Therefore, the current flowing through the second principal surface electrode 12 flows from the second principal surface electrode 12 to both sides in the second direction y via the flat portions 611 and the first inclined portions 612. This makes it possible to prevent the current flowing through the second principal surface electrode 12 from concentrating in one place.

[0222] The two flat portions 611 are spaced apart in the second direction y. This allows current to flow reliably through both the two flat portions 611 and the two first inclined portions 612, which is preferable for suppressing current concentration.

[0223] By separating the two flat portions 611 from each other, the gate finger 121 of the second principal surface electrode 12 can be disposed between them.

[0224] One third joint portion 61 is disposed between two third path portions 66 adjacent to each other in the second direction y. This allows the current flowing through the second main surface electrode 12 of one second semiconductor element 10B to be distributed to the two third path portions 66.

[0225] Next, a first modification of the fourth embodiment will be described. This modification relates to the third conductive component 38. In this modification, as shown in FIG. 56 , the first layer 382 is formed locally only in the portion that contacts the wire 74. That is, the first layer 382 is smaller than the core material 381 when viewed in the z direction. Because the Kirkendall phenomenon occurs at the joint between the wire 74 and the third conductive component 38, the first layer 382 may be formed only in that portion.

[0226] Next, a second modification of the fourth embodiment will be described. In this modification, as shown in Fig. 57, the third conductive component 38 of this modification further includes a second layer 383. The second layer 383 is provided on the opposite side of the core material 381 from the first layer 382, ​​and is formed on the surface that contacts the conductive bonding material 39. In this case, the conductive bonding material 39 and the core material 381 do not come into direct contact with each other, which also prevents the Kirkendall phenomenon from occurring in this area.

[0227] Next, a third modification of the fourth embodiment will be described. As shown in Figures 58 and 59, for ease of manufacturing, the entire surface of the core material 381 may be plated. In this case, the third conductive component 38 further includes a third layer 384, a fourth layer 385, a fifth layer 386, and a sixth layer 387. The third layer 384, the fourth layer 385, the fifth layer 386, and the sixth layer 387 individually cover the four side surfaces of the core material 381.

[0228] 60 to 67 show other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above-described embodiment are given the same reference numerals. Furthermore, the configurations of the various parts in each of the modified examples and embodiments can be combined with each other as appropriate within the scope of not causing technical contradictions.

[0229] 60 to 64 show a fifth embodiment of the present disclosure. In a semiconductor device A2 of this embodiment, the positions and number of third conductive components 38 differ from those in the above-described examples.

[0230] In the fifth embodiment, the control terminal support 48 corresponds to the first conductive component of the present disclosure, and the wires 71 to 74 correspond to the second conductive component of the present disclosure. A plurality of third conductive components 38 are joined to the wires 71 to 74. The plurality of third conductive components 38 are joined to the plurality of control terminal supporters 48 via conductive bonding materials 39.

[0231] 60 and 61 , the wire 71 electrically connects the first principal surface electrode 11 and the first portion 482A. In this embodiment, the third conductive component 38 is disposed between the first portion 482A and the wire 71. The first portion 482A corresponds to the first conductive component of the present disclosure, and the wire 71 corresponds to the second conductive component. The core material 381 is electrically connected to the first portion 482A by the conductive bonding material 39. The first layer 382 and the wire 71 are directly connected.

[0232] 60 and 62 , the wire 72 electrically connects the third principal surface electrode 13 and the second portion 482B. In this embodiment, the third conductive component 38 is disposed between the second portion 482B and the wire 72. The second portion 482B corresponds to the first conductive component of the present disclosure, and the wire 72 corresponds to the second conductive component. The core material 381 is electrically connected to the second portion 482B by the conductive bonding material 39. The first layer 382 and the wire 72 are directly connected.

[0233] 63 shows two third conductive components 38. The wire 73 electrically connects the first portion 482A and the sixth portion 482F. In this embodiment, one third conductive component 38 is disposed between the first portion 482A and the wire 73, and the other third conductive component 38 is disposed between the sixth portion 482F and the wire 73. The first portion 482A and the sixth portion 482F correspond to the first conductive component of the present disclosure, and the wire 73 corresponds to the second conductive component. The core material 381 is electrically connected to the first portion 482A and the sixth portion 482F by the conductive bonding material 39. The first layer 382 and the wire 73 are directly connected.

[0234] 64 shows two third conductive components 38. The wire 74 electrically connects the first portion 482A and the surface metal layer 32. In this embodiment, one third conductive component 38 is disposed between the first portion 482A and the wire 74, and the other third conductive component 38 is disposed between the surface metal layer 32 and the wire 74. The first portion 482A and the surface metal layer 32 correspond to the first conductive component of the present disclosure, and the wire 74 corresponds to the second conductive component. The core material 381 is electrically connected to the first portion 482A and the surface metal layer 32 by the conductive bonding material 39. The first layer 382 and the wire 74, and the surface metal layer 32 and the wire 74 are directly connected.

[0235] According to this embodiment, the Kirkendall phenomenon that may occur between the control terminal support body 48 and the wires 71 to 74 can also be suppressed.

[0236] 65 to 67 show a semiconductor device according to a sixth embodiment of the present disclosure. In the semiconductor device A3 of this embodiment, the position of the third conductive component 38 and the shape of the second conductive member 6 differ from those of the above-described examples. The semiconductor device A3 further includes wires 75 and 76. The number and thickness of the wires 75 and 76 are not limited, but in order to carry a large current, it is desirable to use wires of, for example, about four in number and thicker than the wires 71 to 74.

[0237] 65 and 66 , a wire 75 electrically connects the second conductive portion 32B and the first semiconductor element 10A. In this embodiment, a third conductive component 38 is disposed between the second conductive portion 32B and the wire 75. The second conductive portion 32B corresponds to the first conductive component, and the wire 75 corresponds to the second conductive component. A core material 381 is electrically conductively bonded to the second conductive portion 32B by a conductive bonding material 39. The first layer 382 and the wire 75 are directly bonded.

[0238] As shown in FIGS. 65 and 67 , the shape of the second conductive member 6 differs from that of the fourth embodiment in that the length in the first direction x is shorter. Therefore, the wire 76 electrically connects the second conductive member 6 and the second semiconductor element 10B. In this embodiment, the third conductive component 38 is disposed between the third path portion 66 and the wire 76. An insulator 324 is interposed between the third path portion 66 and the first conductive portion 32A. The insulator 324 is an electrically insulating member. Here, the second conductive member 6 corresponds to the first conductive component of the present disclosure, and the wire 76 corresponds to the second conductive component of the present disclosure. The core material 381 is electrically connected to the second conductive member 6 by the conductive bonding material 39. The first layer 382 and the wire 76 are directly bonded.

[0239] According to this embodiment, the Kirkendall phenomenon that may occur between the second conductive portion 32B and the wire 75 and between the second conductive member 6 and the wire 76 can also be suppressed.

[0240] The semiconductor device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed and modified in various ways. Appendix 1B. A semiconductor device comprising: a first conductive component including a first metal; a second conductive component including a second metal; and a third conductive component including a third metal, wherein the first metal, the second metal, and the third metal are different from one another; and the third conductive component is disposed between the first conductive component and the second conductive component. Appendix 2B. The semiconductor device according to Appendix 1B, wherein the third conductive component has a core material and a first layer, wherein the core material is mainly composed of the first metal, the first layer is mainly composed of the third metal, and the first layer and the second conductive component are directly bonded. Appendix 3B. The semiconductor device according to Appendix 2B, wherein the third conductive component further includes a second layer, the second layer being located opposite the first layer, the second layer being mainly composed of the third metal, and the second layer and the first conductive component being electrically connected. Appendix 4B. The semiconductor device according to any of Appendixes 1B to 3B, wherein the first metal is Cu. Appendix 5B. The semiconductor device according to any of Appendixes 1B to 4B, wherein the first conductive component is mainly composed of the first metal. Appendix 6B. The semiconductor device according to any of Appendixes 1B to 5B, wherein the second metal is Al. Appendix 7B. The semiconductor device according to any of Appendixes 1B to 6B, wherein the second conductive component is mainly composed of the second metal. Appendix 8B. The semiconductor device according to any of Appendixes 1B to 7B, wherein the third metal is Ni. Appendix 9B. The semiconductor device according to any of Appendixes 1B to 8B, wherein the third conductive component is mainly composed of the third metal. Appendix 10B. The semiconductor device according to any one of Supplements 1B to 9B, wherein the first conductive component is plate-shaped.Supplement 11B. The semiconductor device according to any one of Supplements 1B to 10B, wherein the second conductive component is a wire.Supplement 12B. The semiconductor device according to any one of Supplements 1B to 11B, wherein a conductive bonding material is interposed between the first conductive component and the third conductive component.Appendix 13B. The semiconductor device according to any one of Appendixes 1B to 12B, comprising a support substrate having an insulating layer and conductive layers on both sides thereof, one of the conductive layers being the first conductive component, and a semiconductor element being conductively joined to the first conductive component. Appendix 14B. The semiconductor device according to Appendix 13B, further comprising a control terminal support having an insulating layer and conductive first and second metal layers on both sides thereof, the control terminal support being positioned on the support substrate, and the third conductive component having a thickness smaller than that of the control terminal support. Appendix 15B. The semiconductor device according to Appendix 13B or 14B, wherein the control terminal support is directly joined to the second conductive component.

[0241] (Symbols used in FIGS. 1 to 33) A1, A11, A12, A13, A14, A2, A21, A22, A23, A24, A3, A31: semiconductor device B1: vehicle 3: main board 5: first conductive member 6: second conductive member 8: sealing resin 10A: first semiconductor element 10B: second semiconductor element 11: first principal surface electrode 12: second principal surface electrode 13: third principal surface electrode 15: back surface electrode 17: thermistor 19A: first conductive bonding material 19B: second conductive bonding material 31: main insulating layer 32: first main metal layer 32A: first conductive portion 32B: second conductive portion 33: second main metal layer 41: first terminal 42: second terminal 43: third terminal 44: fourth terminal 45, 46A, 46B, 47A, 47B, 47C, 47D: Control terminal 46E: Control terminal (first control terminal) 48: Control terminal support 48A: First sub-board 48B: Second sub-board 49: Conductive bonding material 51: Main portion 52: First joint portion 53: Second joint portion 59: Conductive bonding material 61: Third joint portion 64: First path portion 65: Second path portion 66: Third path portion 67: Fourth path portion 69: Conductive bonding material 71, 72, 73: Wire 81: Resin main surface 82: Resin back surface 91: On-board charger 92: Storage battery 93: Drive system 101: Element main surface 102: Element back surface 301A: First main surface 301B: Second main surface 302: Back surface 451: Holder 452: Metal pin 481: Sub-insulating layer 482: First sub-metal layer 482A, 482B, 482F: Region 482E: Region (first region) 482D: Region (second region) 482C: Region (third region) 483: Second sub-metal layer 485: Connecting conductive portion 514: First opening 602: First step portion 603: Second step portion 611: Flat portion 612: First inclined portion 641: First strip portion 643: First extending portion 651: Second strip portion 653: Second extending portion 831, 832, 833, 834: Resin side surface 832a: Recess 931: Inverter 932: Driving source 4811: Opening 4820: Base material layer 4821A, 4821B, 4821C, 4821D: Connection parts 4822A, 4822B, 4822C,4822D: Terminal portion 4825: Opening 4829: Surface metal layer 4831: Recess 4839: Joint portion 48313: Recess x: First direction y: Second direction z: Thickness direction (Reference symbols used in FIGS. 33 to 67) A1, A2, A3: Semiconductor device 3: Support substrate 5: First conductive member 6: Second conductive member 8: Sealing resin 10A: First semiconductor element 10B: Second semiconductor element 11: First principal surface electrode 12: Second principal surface electrode 13: Third principal surface electrode 15: Back surface electrode 17: Thermistor 19A: First conductive bonding material 19B: Second conductive bonding material 31: Insulating layer 32: Surface metal layer 32A: First conductive portion (first conductive component) 32B: Second conductive portion 33: Back surface metal layer 38: Third conductive component 39: Conductive bonding material 41: First terminal 42: Second terminal 43: Third terminal 44: Fourth terminal 45: Control terminal 46A: First control terminal 46B: First control terminal 46C: First control terminal 46D: First control terminal 46E: First control terminal 47A: Second control terminal 47B: Second control terminal 47C: Second control terminal 47D: Second control terminal 48: Control terminal support 48A: First support portion 48B: Second support portion 49: Bonding material 51: Main portion 52: First joint portion 53: Second joint portion 59: Conductive bonding material 61: Third joint portion 64: First path portion 65: Second path portion 66: Third path portion 67: Fourth path portion 69: Conductive bonding material 71, 72, 73, 74, 75,76: Wire (second conductive component) 81: Resin main surface 82: Resin back surface 86: Resin void 101: Element main surface 102: Element back surface 121: Gate finger 301A: First main surface 301B: Second main surface 302: Back surface 324: Insulator 381: Core material 382: First layer 383: Second layer 384: Third layer 385: Fourth layer 386: Fifth layer 387: Sixth layer 451: Holder 452: Metal pin 459: Conductive bonding material 481: Insulating layer 482: First metal layer 482A: First portion 482B: Second portion 482C: Third portion 482D: Fourth portion 482E: Fifth portion 482F: Sixth portion 483: Second metal layer 514: First opening 602: First step portion 603: Second step portion 611: Flat portion 612: First inclined portion 641: First band-shaped portion 643: First extending portion 649: Recessed portion 651: Second band-shaped portion 653: Second extending portion 659, 669: Recessed portion 831, 832, 833, 834: Resin side surface 832a: Recessed portion 851: First protruding portion 851a: First protruding end surface 851b: Recessed portion 851c: Inner wall surface 852: Second protruding portion T1, T2: Thickness x: First direction y: Second direction z: Thickness direction

Claims

1. a main substrate having a first main metal layer; A first semiconductor element supported by the main substrate; A first sub-substrate supported by the main substrate; a sealing resin that covers the first semiconductor element, The first sub-substrate has a sub-insulation layer, and a first sub-metal layer and a second sub-metal layer disposed on either side of the sub-insulation layer in a thickness direction, the second sub-metal layer is conductively connected to the first main metal layer; the first sub-metal layer includes a first region; The first sub-substrate further includes a connecting conductive portion that electrically connects the first region and the second sub-metal layer.

2. The semiconductor device according to claim 1 , wherein said first semiconductor element is conductively joined to said first main metal layer.

3. 3. The semiconductor device according to claim 1, further comprising a first control terminal that is electrically connected to said first region and protrudes from said sealing resin.

4. The semiconductor device according to claim 3 , wherein said first sub-metal layer further includes a second region separate from said first region.

5. The semiconductor device according to claim 4 , wherein the first control terminal is supported by the second region.

6. The semiconductor device according to claim 5 , further comprising a first wire connected to said first region and said second region.

7. 7. The semiconductor device according to claim 6, wherein said first sub-metal layer further includes a third region spaced apart from said first region and said second region and located between said first region and said second region.

8. The semiconductor device according to claim 6 , wherein the first sub-metal layer includes a base material layer and a surface metal layer.

9. The semiconductor device according to claim 8 , wherein the base material layer contains Cu.

10. The semiconductor device according to claim 9 , wherein the surface metal layer contains Ni.

11. The semiconductor device according to claim 10 , wherein the first sub-metal layer includes Cu.

12. The semiconductor device according to claim 11 , wherein the first wire contains Al.

13. 2. The semiconductor device according to claim 1, wherein said second sub-metal layer is conductively joined to said first main metal layer by a conductive bonding material.

14. 2. The semiconductor device according to claim 1, wherein said second sub-metal layer is electrically connected to said first main metal layer by laser bonding.

15. 15 . The semiconductor device according to claim 14 , wherein the second sub-metal layer has a bonding portion formed by laser bonding, and the second sub-metal layer has an opening that includes the bonding portion when viewed in the thickness direction.

16. The semiconductor device according to claim 1 , wherein the sub-insulating layer includes a ceramic.

17. The semiconductor device according to claim 1 , wherein the sub-insulating layer includes a glass epoxy resin.

18. A driving source; The semiconductor device according to claim 1, The semiconductor device is electrically connected to the drive source.