Semiconductor memory device

Abstract

A semiconductor memory device (1) comprises: a first pull-down N-channel MOS transistor (21) having a drain connected to a word line (20), a source connected to a ground line, and a gate connected to a first node (91); a first series-connected N-channel MOS transistor (22) having a drain connected to a power supply line, and a source connected to the first node (91); and a second series-connected N-channel MOS transistor (23) having drain connected to the first node (91), and a source connected to the ground line. A signal that is an inverted logic of a signal input to the gate of the second series-connected N-channel MOS transistor (23) is inputted to the gate of the first series-connected N-channel MOS transistor (22).

Description

semiconductor memory device

[0001] The present invention relates to semiconductor memory devices, and in particular to SRAMs (Static Random Access Memories).

[0002] A conventional technique for improving the static noise margin (SNM) in an SRAM is to pull down the voltage of a word line in an active state.

[0003] Japanese Patent Application Laid-Open No. 2008-262637

[0004] In an SRAM, if the voltage of an active word line is lowered to improve SNM, the ability to write to and read from a memory cell (hereinafter also referred to as "write / read ability") will decrease.

[0005] Therefore, an object of the present disclosure is to provide a semiconductor memory device that can suppress a decrease in write / read performance and realizes a voltage drop on word lines to improve SNM.

[0006] A semiconductor memory device according to one aspect of the present disclosure includes a first pull-down N-channel MOS (Metal Oxide Semiconductor) transistor having a drain connected to a first word line connected to one or more first memory cells, a source connected to a ground line that supplies a ground voltage, and a gate connected to a first node; a first series-connected N-channel MOS transistor having a drain connected to a power supply line that supplies a power supply voltage and a source connected to the first node; and a second series-connected N-channel MOS transistor having a drain connected to the first node and a source connected to the ground line, wherein a signal having an inverted logic of a signal input to a gate of the second series-connected N-channel MOS transistor is input to a gate of the first series-connected N-channel MOS transistor.

[0007] A semiconductor memory device according to one aspect of the present disclosure includes: a first pull-down N-channel MOS transistor having a drain connected to a first word line connected to one or more first memory cells, a source connected to a ground line that supplies a ground voltage, and a gate connected to a first node; a first P-channel MOS transistor having a source connected to a power supply line that supplies a power supply voltage and a drain connected to a second node; a first series-connected N-channel MOS transistor having a drain connected to the second node, a source connected to the first node, and a gate connected to a first control signal input terminal that receives a first control signal; and a second series-connected N-channel MOS transistor having a drain connected to the first node and a source connected to the ground line, wherein a signal having the same logic as a signal input to the gate of the second series-connected N-channel MOS transistor is input to the gate of the first P-channel MOS transistor.

[0008] According to one aspect of the present disclosure, a semiconductor memory device is provided that can suppress a decrease in write / read performance and realizes a voltage drop on word lines to improve SNM.

[0009] FIG. 1 is a block diagram showing the configuration of a semiconductor memory device according to a first embodiment. FIG. 2 is a circuit diagram showing the configuration of a memory cell according to the first embodiment. FIG. 3 is a circuit diagram showing the configuration of an assist circuit according to the first embodiment. FIG. 4 is a schematic diagram showing how the assist circuit according to the first embodiment pulls down the voltage of an active word line. FIG. 5 is a block diagram showing the configuration of a semiconductor memory device according to a second embodiment. FIG. 6 is a circuit diagram showing the configuration of an assist circuit according to the second embodiment. FIG. 7 is a block diagram showing the configuration of a semiconductor memory device according to a third embodiment. FIG. 8 is a circuit diagram showing the configuration of an assist circuit according to the third embodiment. FIG. 9 is a block diagram showing the configuration of a semiconductor memory device according to a fourth embodiment. FIG. 10 is a circuit diagram showing the configuration of an assist circuit according to the fourth embodiment. FIG. 11 is a block diagram showing the configuration of a semiconductor memory device according to a fifth embodiment. FIG. 12 is a circuit diagram showing the configuration of an assist circuit according to the fifth embodiment. FIG. 13 is a block diagram showing the configuration of a semiconductor memory device according to a sixth embodiment. FIG. 14 is a circuit diagram showing the configuration of an assist circuit according to the sixth embodiment. FIG. 15 is a block diagram showing the configuration of a semiconductor memory device according to a seventh embodiment. FIG. 16 is a circuit diagram showing the configuration of an assist circuit according to the seventh embodiment. FIG. 17 is a schematic diagram showing the relationship between process variation conditions and voltage drop amounts. FIG. 18 is a block diagram showing the configuration of a semiconductor memory device according to an eighth embodiment. FIG. 19 is a circuit diagram showing the configuration of an assist circuit according to the eighth embodiment. FIG. 20 is a block diagram showing the configuration of a semiconductor memory device according to a ninth embodiment. FIG. 21 is a circuit diagram showing the configuration of an assist circuit according to the ninth embodiment. FIG. 22 is a block diagram showing the configuration of a semiconductor memory device according to a tenth embodiment. FIG. 23 is a circuit diagram showing the configuration of an assist circuit according to the tenth embodiment. FIG. 24 is a block diagram showing the configuration of a semiconductor memory device according to an eleventh embodiment. FIG. 25 is a circuit diagram showing the configuration of an assist circuit according to the eleventh embodiment. FIG. 26 is a schematic diagram showing the relationship between process variation conditions and voltage drop amounts. FIG. 27 is a block diagram showing the configuration of a semiconductor memory device according to a twelfth embodiment. FIG. 28 is a circuit diagram showing the configuration of an assist circuit according to the twelfth embodiment.29 is a block diagram showing the configuration of a semiconductor memory device according to embodiment 13. FIG. 30 is a circuit diagram showing the configuration of an assist circuit according to embodiment 13.

[0010] (How one aspect of the present disclosure was achieved) Generally, SNM is small when the temperature condition is a high temperature condition and when the process variation condition is an N-channel MOS (Metal Oxide Semiconductor) transistor fast condition (the threshold voltage of the N-channel MOS transistor is low).

[0011] Generally, when the temperature condition is a low temperature condition and when the process variation condition is a slow N-channel MOS transistor (the threshold voltage of the N-channel MOS transistor is high), the write / read capability is reduced.

[0012] Based on these findings, the inventors considered that if it were possible to control the amount of voltage drop on the word line in an SRAM so that when the temperature condition is a low temperature condition, the amount of voltage drop on the word line in the active state is smaller than when the temperature condition is a high temperature condition, and so that when the process variation condition is an N-channel MOS transistor slow condition, the amount of voltage drop on the word line in the active state is smaller than when the process variation condition is an N-channel MOS transistor fast condition, then it might be possible to suppress a decrease in write and read capabilities without reducing the SNM.

[0013] Based on the above idea, the inventors have conducted extensive experiments and studies on a semiconductor memory device that can suppress a decrease in write / read capability and achieves a voltage drop on the word line to improve SNM.

[0014] As a result, the inventors have come up with the following semiconductor memory device according to the present disclosure.

[0015] A semiconductor memory device according to one aspect of the present disclosure includes a first pull-down N-channel MOS (Metal Oxide Semiconductor) transistor having a drain connected to a first word line connected to one or more first memory cells, a source connected to a ground line that supplies a ground voltage, and a gate connected to a first node; a first series-connected N-channel MOS transistor having a drain connected to a power supply line that supplies a power supply voltage and a source connected to the first node; and a second series-connected N-channel MOS transistor having a drain connected to the first node and a source connected to the ground line, wherein a signal having an inverted logic of a signal input to a gate of the second series-connected N-channel MOS transistor is input to a gate of the first series-connected N-channel MOS transistor.

[0016] In the semiconductor memory device having the above configuration, the voltage of the first node, i.e., the gate voltage of the first pull-down N-channel MOS transistor, becomes a voltage (VDD-Vtn) that is lower than the power supply voltage (hereinafter also referred to as "VDD") by the threshold voltage (hereinafter also referred to as "Vtn") of the N-channel MOS transistor.

[0017] In general, Vtn is larger under low temperature conditions than under high temperature conditions, and is larger under N-channel MOS transistor slow conditions than under N-channel MOS transistor fast conditions.

[0018] Therefore, the gate voltage of the first pull-down N-channel MOS transistor is lower when the temperature condition is a low temperature condition than when the temperature condition is a high temperature condition, and is lower when the process variation condition is an N-channel MOS transistor slow condition than when the process variation condition is an N-channel MOS transistor fast condition.

[0019] In the semiconductor memory device having the above configuration, the first pull-down N-channel MOS transistor pulls down the voltage of the first word line in an active state in accordance with its gate voltage, such that the lower the gate voltage, the smaller the pull-down voltage amount of the first word line in an active state.

[0020] Therefore, in the semiconductor memory device having the above configuration, the amount of voltage drop on the first word line in the active state is controlled so that when the temperature condition is a low temperature condition, the amount of voltage drop on the first word line is smaller than when the temperature condition is a high temperature condition, and when the process variation condition is an N-channel MOS transistor slow condition, the amount of voltage drop on the first word line is smaller than when the process variation condition is an N-channel MOS transistor fast condition.

[0021] As a result, according to the semiconductor memory device having the above configuration, it is possible to provide a semiconductor memory device that can suppress a decrease in write / read performance and realizes a voltage drop on the word line to improve SNM.

[0022] Furthermore, the power supply may further include a first P-channel MOS transistor having a drain connected to the drain of the first series-connected N-channel MOS transistor, a source connected to the power supply line, and a gate connected to a first control signal input terminal to which a first control signal is input, and the drain of the first series-connected N-channel MOS transistor may be connected to the power supply line via the first P-channel MOS transistor.

[0023] Thus, by controlling the first control signal, it is possible to control whether or not the voltage of the first word line is pulled down by the first pull-down N-channel MOS transistor.

[0024] Furthermore, the memory cell may further include a second pull-down N-channel MOS transistor having a drain connected to a second word line connected to one or more second memory cells, a source connected to the ground line, and a gate connected to a second node; a third series-connected N-channel MOS transistor having a drain connected to the drain of the first P-channel MOS transistor and a source connected to the second node; and a fourth series-connected N-channel MOS transistor having a drain connected to the second node and a source connected to the ground line, wherein a signal having an inverted logic of a signal input to the gate of the fourth series-connected N-channel MOS transistor is input to the gate of the third series-connected N-channel MOS transistor.

[0025] According to the semiconductor memory device having the above configuration, the P-channel MOS transistor located in the current path from the power supply wiring to the first node and the P-channel MOS transistor located in the current path from the power supply wiring to the second node can be made into a single common first P-channel MOS transistor.

[0026] This makes it possible to reduce the area required to form the P-channel MOS transistors compared to when the P-channel MOS transistor located in the current path from the power supply wiring to the first node and the P-channel MOS transistor located in the current path from the power supply wiring to the second node are formed separately.

[0027] Furthermore, there is a second pull-down N-channel MOS transistor having a drain connected to a second word line connected to one or more second memory cells, a source connected to the ground line, and a gate connected to the first node; a third pull-down N-channel MOS transistor having a drain connected to a third word line connected to one or more third memory cells, a source connected to the ground line, and a gate connected to the second node; a fourth pull-down N-channel MOS transistor having a drain connected to a fourth word line connected to one or more fourth memory cells, a source connected to the ground line, and a gate connected to the second node; and a fourth pull-down N-channel MOS transistor having a drain connected to the drain of the first P-channel MOS transistor, and a source connected to the second node. and a fourth series-connected N-channel MOS transistor having a drain connected to the second node and a source connected to the ground line, wherein when the first word line and / or the second word line are active, a signal having an inverted logic of a signal input to the gate of the second series-connected N-channel MOS transistor is input to the gate of the first series-connected N-channel MOS transistor, and when the third word line and / or the fourth word line are active, a signal having an inverted logic of a signal input to the gate of the fourth series-connected N-channel MOS transistor is input to the gate of the third series-connected N-channel MOS transistor.

[0028] According to the semiconductor memory device having the above configuration, the P-channel MOS transistor located in the current path from the power supply wiring to the first node and the P-channel MOS transistor located in the current path from the power supply wiring to the second node can be made into a single common first P-channel MOS transistor.

[0029] This makes it possible to reduce the area required to form the P-channel MOS transistors compared to when the P-channel MOS transistor located in the current path from the power supply wiring to the first node and the P-channel MOS transistor located in the current path from the power supply wiring to the second node are formed separately.

[0030] Furthermore, in the semiconductor memory device having the above configuration, the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the first pull-down N-channel MOS transistor and the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the second pull-down N-channel MOS transistor can be formed into a single common first series-connected N-channel MOS transistor, and the N-channel MOS transistor located in the current path from the gate of the first pull-down N-channel MOS transistor to the ground wiring and the N-channel MOS transistor located in the current path from the gate of the second pull-down N-channel MOS transistor to the ground wiring can be formed into a single common second series-connected N-channel MOS transistor.

[0031] This makes it possible to reduce the area required to form the N-channel MOS transistors compared to when an N-channel MOS transistor located in the current path from the power supply wiring to the gate of the first pull-down N-channel MOS transistor and an N-channel MOS transistor located in the current path from the power supply wiring to the gate of the second pull-down N-channel MOS transistor are separately formed, and / or when an N-channel MOS transistor located in the current path from the gate of the first pull-down N-channel MOS transistor to the ground wiring and an N-channel MOS transistor located in the current path from the gate of the second pull-down N-channel MOS transistor to the ground wiring are separately formed.

[0032] Furthermore, in the semiconductor memory device having the above configuration, the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the third pull-down N-channel MOS transistor and the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the fourth pull-down N-channel MOS transistor can be formed as a single common third series-connected N-channel MOS transistor, and the N-channel MOS transistor located in the current path from the gate of the third pull-down N-channel MOS transistor to the ground wiring and the N-channel MOS transistor located in the current path from the gate of the fourth pull-down N-channel MOS transistor to the ground wiring can be formed as a single common fourth series-connected N-channel MOS transistor.

[0033] This makes it possible to reduce the area required to form the N-channel MOS transistors compared to when an N-channel MOS transistor located in the current path from the power supply wiring to the gate of the third pull-down N-channel MOS transistor and an N-channel MOS transistor located in the current path from the power supply wiring to the gate of the fourth pull-down N-channel MOS transistor are separately formed, and / or when an N-channel MOS transistor located in the current path from the gate of the third pull-down N-channel MOS transistor to the ground wiring and an N-channel MOS transistor located in the current path from the gate of the fourth pull-down N-channel MOS transistor to the ground wiring are separately formed.

[0034] Furthermore, the input / output terminal may further include a second pull-down N-channel MOS transistor having a drain connected to the first word line, a source connected to the ground line, and a gate connected to a second node; a second P-channel MOS transistor having a drain connected to a third node, a source connected to the power supply line, and a gate connected to a second control signal input terminal to which a second control signal is input; a third series-connected N-channel MOS transistor having a drain connected to the third node and a source connected to the second node; and a fourth series-connected N-channel MOS transistor having a drain connected to the second node and a source connected to the ground line, wherein a signal having the same logic as a signal input to a gate of the third series-connected N-channel MOS transistor is input to a gate of the first series-connected N-channel MOS transistor, and a signal having the same logic as a signal input to a gate of the fourth series-connected N-channel MOS transistor is input to a gate of the second series-connected N-channel MOS transistor.

[0035] This makes it possible to select whether to pull down the first word line using the first pull-down N-channel MOS transistor, to pull down the first word line using the second pull-down N-channel MOS transistor, to pull down the first word line using the first pull-down N-channel MOS transistor and the second pull-down N-channel MOS transistor, or not to pull down the first word line.

[0036] A semiconductor memory device according to one aspect of the present disclosure includes: a first pull-down N-channel MOS transistor having a drain connected to a first word line connected to one or more first memory cells, a source connected to a ground line that supplies a ground voltage, and a gate connected to a first node; a first P-channel MOS transistor having a source connected to a power supply line that supplies a power supply voltage and a drain connected to a second node; a first series-connected N-channel MOS transistor having a drain connected to the second node, a source connected to the first node, and a gate connected to a first control signal input terminal that receives a first control signal; and a second series-connected N-channel MOS transistor having a drain connected to the first node and a source connected to the ground line, wherein a signal having the same logic as a signal input to the gate of the second series-connected N-channel MOS transistor is input to the gate of the first P-channel MOS transistor.

[0037] In the semiconductor memory device configured as described above, the voltage at the first node when the first P-channel MOS transistor is in a conductive state, that is, the gate voltage of the first pull-down N-channel MOS transistor, is VDD-Vtn.

[0038] In general, Vtn is larger under low temperature conditions than under high temperature conditions, and is larger under N-channel MOS transistor slow conditions than under N-channel MOS transistor fast conditions.

[0039] Therefore, the gate voltage of the first pull-down N-channel MOS transistor is lower when the temperature condition is a low temperature condition than when the temperature condition is a high temperature condition, and is lower when the process variation condition is an N-channel MOS transistor slow condition than when the process variation condition is an N-channel MOS transistor fast condition.

[0040] In the semiconductor memory device having the above configuration, the first pull-down N-channel MOS transistor pulls down the voltage of the first word line in an active state in accordance with its gate voltage, such that the lower the gate voltage, the smaller the pull-down voltage amount of the first word line in an active state.

[0041] Therefore, in the semiconductor memory device having the above configuration, the amount of voltage drop on the first word line in the active state is controlled so that when the temperature condition is a low temperature condition, the amount of voltage drop on the first word line is smaller than when the temperature condition is a high temperature condition, and when the process variation condition is an N-channel MOS transistor slow condition, the amount of voltage drop on the first word line is smaller than when the process variation condition is an N-channel MOS transistor fast condition.

[0042] As a result, according to the semiconductor memory device having the above configuration, it is possible to provide a semiconductor memory device that can suppress a decrease in write / read performance and realizes a voltage drop on the word line to improve SNM.

[0043] Furthermore, in the semiconductor memory device configured as described above, by controlling the first control signal, it is possible to control whether or not the voltage of the first word line is pulled down by the first pull-down N-channel MOS transistor.

[0044] Furthermore, the memory cell may further include a second pull-down N-channel MOS transistor having a drain connected to a second word line connected to one or more second memory cells, a source connected to the ground line, and a gate connected to the first node.

[0045] In the semiconductor memory device having the above configuration, the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the first pull-down N-channel MOS transistor and the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the second pull-down N-channel MOS transistor can be formed as a single common first series-connected N-channel MOS transistor, and the N-channel MOS transistor located in the current path from the gate of the first pull-down N-channel MOS transistor to the ground wiring and the N-channel MOS transistor located in the current path from the gate of the second pull-down N-channel MOS transistor to the ground wiring can be formed as a single common second series-connected N-channel MOS transistor.

[0046] Therefore, the size of the first series-connected N-channel MOS transistor can be made larger than when the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the first pull-down N-channel MOS transistor and the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the second pull-down N-channel MOS transistor are formed separately.

[0047] This makes it possible to suppress variations in Vtn of the first series-connected N-channel MOS transistors.

[0048] Furthermore, the memory cell may further include a second pull-down N-channel MOS transistor having a drain connected to the first word line, a source connected to the ground line, and a gate connected to the power supply line.

[0049] In the semiconductor memory device having the above configuration, the voltage of the first word line is pulled down by the first pull-down N-channel MOS transistor whose gate voltage is VDD-Vtn and the second pull-down N-channel MOS transistor whose gate voltage is VDD.

[0050] This allows the voltage drop amount of the first word line to be controlled more sensitively.

[0051] The first series-connected N-channel MOS transistor may have a lower threshold than the first pull-down N-channel MOS transistor and the second series-connected N-channel MOS transistor.

[0052] In the semiconductor memory device having the above configuration, when the power supply voltage is lowered, the gate voltage of the first pull-down N-channel MOS transistor becomes lower than the threshold voltage of the first pull-down N-channel MOS transistor, which results in the first pull-down N-channel MOS transistor being unable to pull down the first word line. This prevents this problem.

[0053] This makes it possible to expand the low voltage operating range for the pull-down operation of the first word line.

[0054] Furthermore, the input / output terminal may further include a second pull-down N-channel MOS transistor having a drain connected to the first word line, a source connected to the ground line, and a gate connected to a third node; a second P-channel MOS transistor having a source connected to the power supply line and a drain connected to a fourth node; a third series-connected N-channel MOS transistor having a drain connected to the fourth node, a source connected to the third node, and a gate connected to a second control signal input terminal to which a second control signal is input; and a fourth series-connected N-channel MOS transistor having a drain connected to the third node and a source connected to the ground line, wherein a signal having the same logic as the signal input to the gate of the second series-connected N-channel MOS transistor is input to the gate of the second P-channel MOS transistor and the gate of the fourth series-connected N-channel MOS transistor.

[0055] This makes it possible to select whether to pull down the first word line using the first pull-down N-channel MOS transistor, to pull down the first word line using the second pull-down N-channel MOS transistor, to pull down the first word line using the first pull-down N-channel MOS transistor and the second pull-down N-channel MOS transistor, or not to pull down the first word line.

[0056] Specific examples of semiconductor memory devices according to an embodiment of the present disclosure will be described below with reference to the drawings. Each embodiment shown here illustrates a specific example of the present disclosure. Therefore, the numerical values, shapes, components, component arrangements and connection configurations, steps (processes), and step sequences shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. In each figure, substantially identical components are assigned the same reference numerals, and redundant explanations are omitted or simplified.

[0057] First Embodiment A semiconductor memory device according to the first embodiment will be described below. The semiconductor memory device according to the first embodiment is an SRAM having word lines, and in order to improve SNM, the voltage of the word lines in an active state is pulled down to reduce the voltage.

[0058] <Configuration> FIG. 1 is a block diagram showing the configuration of a semiconductor memory device 1 according to the first embodiment.

[0059] As shown in FIG. 1, the semiconductor memory device 1 includes a memory cell array 50, a row decoder 60, an I / O circuit 70, a control unit 80, a plurality of word lines 20, and a plurality of assist circuits 10.

[0060] The memory cell array 50 is configured by arranging a plurality of memory cells 40 in a matrix.

[0061] The plurality of memory cells 40 constituting the memory cell array 50 are connected for each row to one common word line 20. That is, the semiconductor memory device 1 includes as many word lines 20 as there are rows of the memory cell array 50.

[0062] The memory cell array 50 further includes, for each column, a pair of bit line 28 and inverted bit line 29. The plurality of memory cells 40 constituting the memory cell array 50 are connected for each column to a common pair of bit line 28 and inverted bit line 29. That is, the memory cell array 50 includes the same number of pairs of bit line 28 and inverted bit line 29 as the number of columns of the memory cell array 50.

[0063] FIG. 2 is a circuit diagram showing the configuration of the memory cell 40. As shown in FIG.

[0064] As shown in FIG. 2, the memory cell 40 is connected to the word line 20, the bit line 28, and the inverted bit line 29, and is composed of six transistors: an access transistor 41 which is an N-channel MOS transistor, an access transistor 42 which is an N-channel MOS transistor, a load transistor 43 which is a P-channel MOS transistor, a load transistor 44 which is a P-channel MOS transistor, a drive transistor 45 which is an N-channel MOS transistor, and a drive transistor 46 which is an N-channel MOS transistor.

[0065] Returning to FIG. 1 again, the description of the semiconductor memory device 1 will continue.

[0066] Each of the plurality of word lines 20 is connected to one or more memory cells 40 that form one row of the memory cell array 50 .

[0067] The row decoder 60 selects a row of the memory cell array 50. More specifically, the row decoder 60 includes a plurality of word line drivers 30 that drive a plurality of word lines 20 in a one-to-one relationship, and one of the plurality of word line drivers 30 drives one of the plurality of word lines 20 to an active state, thereby selecting a row made up of one or more memory cells 40 connected to the one word line 20 that has been activated.

[0068] The I / O circuit 70 writes data to the memory cell array 50 and reads data held by the memory cell array 50 .

[0069] The control unit 80 controls the memory cell array 50 , the row decoder 60 , the I / O circuit 70 , and the plurality of assist circuits 10 .

[0070] The assist circuit 10 pulls down the voltage of the word line 20 in the active state.

[0071] Each of the plurality of assist circuits 10 is connected one-to-one to each of the plurality of word lines 20. That is, the semiconductor memory device 1 includes as many assist circuits 10 as there are word lines 20.

[0072] FIG. 3 is a circuit diagram showing the configuration of the assist circuit 10. As shown in FIG.

[0073] As shown in FIG. 3, the assist circuit 10 includes a first pull-down N-channel MOS transistor 21 having a drain connected to the word line 20, a source connected to a ground line that supplies a ground voltage (VSS), and a gate connected to a first node 91, a first series-connected N-channel MOS transistor 22 having a drain connected to a power supply line that supplies a power supply voltage (VDD) and a source connected to the first node 91, and a second series-connected N-channel MOS transistor 23 having a drain connected to the first node 91 and a source connected to the ground line.

[0074] The assist circuit 10 further includes an inverter 24 connected to the gate of the first series-connected N-channel MOS transistor 22 so that a signal having the inverted logic of the signal input to the gate of the second series-connected N-channel MOS transistor 23 is input to the gate of the first series-connected N-channel MOS transistor 22.

[0075] <Consideration> FIG. 4 is a schematic diagram showing how the assist circuit 10 pulls down the voltage of the word line 20 in the active state.

[0076] In the assist circuit 10, when a logical value of 0 is input to the terminal c0, that is, when the voltage of the terminal c0 becomes VSS, the first series-connected N-channel MOS transistor 22 becomes conductive and the second series-connected N-channel MOS transistor 23 becomes non-conductive.

[0077] As a result, the voltage of the first node 91, that is, the gate voltage of the first pull-down N-channel MOS transistor 21, becomes VDD-Vtn.

[0078] In general, Vtn is larger under low temperature conditions than under high temperature conditions, and is larger under N-channel MOS transistor slow conditions than under N-channel MOS transistor fast conditions.

[0079] Therefore, as shown in FIG. 4, the voltage VDD-Vtn of the first node 91, i.e., the gate voltage VDD-Vtn of the first pull-down N-channel MOS transistor 21, is lower when the temperature condition is a low temperature condition than when the temperature condition is a high temperature condition, and is lower when the process variation condition is an N-channel MOS transistor slow condition than when the process variation condition is an N-channel MOS transistor fast condition.

[0080] In the assist circuit 10, the first pull-down N-channel MOS transistor 21 pulls down the voltage of the active word line 20 in accordance with its gate voltage, so that the lower the gate voltage, the smaller the pull-down voltage amount Vpd of the active word line 20 becomes.

[0081] Therefore, as shown in FIG. 4, in the semiconductor memory device 1, the voltage drop amount Vpd of the word line 20 in the active state is controlled so that when the temperature condition is a low temperature condition, the voltage drop amount Vpd of the word line 20 is smaller than when the temperature condition is a high temperature condition, and when the process variation condition is an N-channel MOS transistor slow condition, the voltage drop amount Vpd of the word line 20 is smaller than when the process variation condition is an N-channel MOS transistor fast condition.

[0082] As a result, the semiconductor memory device 1 having the above configuration can suppress a decrease in write / read performance and can realize a voltage drop on the word line to improve SNM.

[0083] Second Embodiment Hereinafter, a semiconductor memory device according to a second embodiment will be described, which is configured by partially modifying the configuration of the semiconductor memory device 1 according to the first embodiment.

[0084] Here, for the semiconductor memory device of embodiment 2, the components that are similar to those of semiconductor memory device 1 have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from semiconductor memory device 1.

[0085] <Configuration> FIG. 5 is a block diagram showing the configuration of a semiconductor memory device 1A according to the second embodiment.

[0086] As shown in FIG. 5, the semiconductor memory device 1A is configured by adding a first control signal input terminal CNT0 to the semiconductor memory device 1 according to the first embodiment and changing the assist circuit 10 to an assist circuit 10A.

[0087] The first control signal input terminal CNT0 is a terminal to which a first control signal is input from outside the semiconductor memory device 1 A. The first control signal input terminal CNT0 is connected to all of the gates of first P-channel MOS transistors 25 (described later) (see FIG. 6 described later) included in each of the multiple assist circuits 10 A.

[0088] FIG. 6 is a circuit diagram showing the configuration of the assist circuit 10A.

[0089] 6, the assist circuit 10A is configured by adding a first P-channel MOS transistor 25 between the power supply line and the drain of the first series-connected N-channel MOS transistor 22 to the assist circuit 10 according to embodiment 1. More specifically, the assist circuit 10A is configured by adding a first P-channel MOS transistor 25 whose drain is connected to the drain of the first series-connected N-channel MOS transistor 22 and whose source is connected to the power supply line.

[0090] The gate of the first P-channel MOS transistor 25 is connected to the first control signal input terminal CNT0 via the terminal sel0.

[0091] <Consideration> In the assist circuit 10A configured as described above, the drain of the first series-connected N-channel MOS transistor 22 is connected to the power supply line via the first P-channel MOS transistor 25 .

[0092] Therefore, when a first control signal with a logical value of 0 is input from the first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VSS, the first P-channel MOS transistor 25 becomes conductive. Therefore, similar to the assist circuit 10 of embodiment 1, in the assist circuit 10A, when a logical value of 0 is input to terminal c0, that is, when the voltage of terminal c0 becomes VSS, the first series-connected N-channel MOS transistor 22 becomes conductive and the second series-connected N-channel MOS transistor 23 becomes non-conductive.

[0093] As a result, the voltage of the first node 91, that is, the gate voltage of the first pull-down N-channel MOS transistor 21, becomes VDD-Vtn.

[0094] On the other hand, when a first control signal with a logical value of 1 is input from the first control signal input terminal CNT0, that is, when the voltage of the terminal sel0 is VDD, the first P-channel MOS transistor 25 is in a non-conductive state.

[0095] Therefore, in the assist circuit 10A, once a logical value of 1 is input to the terminal c0, that is, once the voltage of the terminal c0 becomes VDD, the second series-connected N-channel MOS transistor 23 becomes conductive and the voltage of the first node 91 is reset (becomes VSS), and thereafter the voltage of the first node 91 will never become higher than VSS, that is, the first pull-down N-channel MOS transistor 21 will not pull down and reduce the voltage of the word line 20 in the active state.

[0096] Thus, with the semiconductor memory device 1A having the above configuration, by controlling the first control signal, it is possible to control whether or not to enable the function of lowering the voltage of the active word line 20 (hereinafter also referred to as the "assist function").

[0097] This allows the user of the semiconductor memory device 1A to evaluate the characteristics of the memory cell 40 in a state where the assist function is not enabled.

[0098] This also allows users of the semiconductor memory device 1A to disable the assist function when using the semiconductor memory device 1A in a state where it has relatively high write / read capabilities, such as when using the semiconductor memory device 1A with a relatively high power supply voltage.

[0099] This also makes it possible to relatively easily realize power cutoff control for suppressing leakage current.

[0100] Third Embodiment A semiconductor memory device according to a third embodiment, which is configured by partially modifying the configuration of the semiconductor memory device 1A according to the second embodiment, will be described below.

[0101] Here, for the semiconductor memory device of embodiment 3, components that are similar to those of semiconductor memory device 1A have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from semiconductor memory device 1A.

[0102] <Configuration> FIG. 7 is a block diagram showing the configuration of a semiconductor memory device 1B according to the third embodiment.

[0103] As shown in FIG. 7, the semiconductor memory device 1B is configured by changing the assist circuit 10A of the semiconductor memory device 1A according to the second embodiment to an assist circuit 10B.

[0104] Here, the first control signal input terminal CNT0 is connected to all of the gates of first series-connected N-channel MOS transistors 22B (see FIG. 8, described later) included in each of the plurality of assist circuits 10B.

[0105] FIG. 8 is a circuit diagram showing the configuration of the assist circuit 10B.

[0106] As shown in FIG. 8, the assist circuit 10B is configured by deleting the inverter 24 from the assist circuit 10 according to the first embodiment, changing the first series-connected N-channel MOS transistor 22 to a first series-connected N-channel MOS transistor 22B, and changing the first P-channel MOS transistor 25 to a first P-channel MOS transistor 25B.

[0107] A signal of the same logic as the signal input to the gate of the second series-connected N-channel MOS transistor 23 (here, the same signal) is input to the gate of the first series-connected N-channel MOS transistor 22B.

[0108] The gate of the first series-connected N-channel MOS transistor 22B is connected to the first control signal input terminal CNT0 via the terminal sel0.

[0109] <Consideration> In the assist circuit 10B configured as described above, the drain of the first series-connected N-channel MOS transistor 22B (that is, the second node 92B) is connected to the power supply line via the first P-channel MOS transistor 25B.

[0110] Therefore, when a first control signal with a logical value of 1 is input from the first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VDD, the first series-connected N-channel MOS transistor 22B is in a conductive state. Therefore, in the assist circuit 10B, when a logical value of 0 is input to terminal c0, that is, when the voltage of terminal c0 becomes VSS, the first P-channel MOS transistor 25B is in a conductive state and the second series-connected N-channel MOS transistor 23 is in a non-conductive state.

[0111] As a result, the voltage of the first node 91, that is, the gate voltage of the first pull-down N-channel MOS transistor 21, becomes VDD-Vtn.

[0112] On the other hand, when a first control signal with a logical value of 0 is input from the first control signal input terminal CNT0, that is, when the voltage of the terminal sel0 is VSS, the first series-connected N-channel MOS transistor 22B is in a non-conductive state.

[0113] Therefore, in the assist circuit 10B, once a logical value of 1 is input to the terminal c0, that is, once the voltage of the terminal c0 becomes VDD, the second series-connected N-channel MOS transistor 23 becomes conductive and the voltage of the first node 91 is reset (becomes VSS), and thereafter the voltage of the first node 91 will never become higher than VSS, that is, the first pull-down N-channel MOS transistor 21 will not pull down and reduce the voltage of the word line 20 in the active state.

[0114] Thus, according to the semiconductor memory device 1B having the above configuration, similar to the semiconductor memory device 1A according to the second embodiment, it is possible to control whether or not to enable the assist function by controlling the first control signal.

[0115] Fourth Embodiment A semiconductor memory device according to a fourth embodiment, which is configured by partially modifying the configuration of the semiconductor memory device 1A according to the second embodiment, will be described below.

[0116] Here, for the semiconductor memory device of embodiment 4, components that are similar to those of semiconductor memory device 1A have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from semiconductor memory device 1A.

[0117] <Configuration> FIG. 9 is a block diagram showing the configuration of a semiconductor memory device 1C according to the fourth embodiment.

[0118] As shown in FIG. 9, the semiconductor memory device 1C is configured by replacing the two assist circuits 10A of the semiconductor memory device 1A according to the second embodiment with one assist circuit 10C.

[0119] That is, each of the plurality of assist circuits 10C is connected to two word lines 20. Therefore, the semiconductor memory device 1C includes half the number of assist circuits 10C as the number of word lines 20.

[0120] Here, the first control signal input terminal CNT0 is connected to all of the gates of the first P-channel MOS transistors 25 (see FIG. 10 described later) included in each of the plurality of assist circuits 10C.

[0121] 10 is a circuit diagram showing the configuration of the assist circuit 10C. Here, one of the two word lines 20 connected to the assist circuit 10C is referred to as word line 20WL0, and the other is referred to as word line 20WL1. That is, of the two word lines 20 connected to the assist circuit 10C, the word line 20 connected to one or more memory cells 40 forming a certain row (e.g., row 0) of the memory cell array 50 is referred to as word line 20WL0, and the word line 20 connected to one or more memory cells 40 forming another certain row (e.g., row 1) of the memory cell array 50 is referred to as word line 20WL1.

[0122] As shown in FIG. 10 , the assist circuit 10C is configured by adding to the assist circuit 10A according to the second embodiment: a second pull-down N-channel MOS transistor 21C having a drain connected to the word line 20 (here, the word line 20WL1), a source connected to a ground line, and a gate connected to a second node 91C; a third series-connected N-channel MOS transistor 22C having a drain connected to the drain of the first P-channel MOS transistor 25 and a source connected to the second node 91C; and a fourth series-connected N-channel MOS transistor 23C having a drain connected to the second node 91C and a source connected to the ground line.

[0123] The assist circuit 10C is further configured by adding an inverter 24C to the gate of the third series-connected N-channel MOS transistor 22C of the assist circuit 10A, which is connected so that a signal with the inverted logic of the signal input to the gate of the fourth series-connected N-channel MOS transistor 23C is input to the gate of the third series-connected N-channel MOS transistor 22C.

[0124] <Consideration> In the assist circuit 10C configured as described above, the drain of the third series-connected N-channel MOS transistor 22C is connected to the power supply line via the first P-channel MOS transistor 25.

[0125] Therefore, when a first control signal with a logical value of 0 is input from the first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VSS, the first P-channel MOS transistor 25 is in a conductive state. Therefore, in the assist circuit 10C, when a logical value of 0 is input to terminal c0, that is, when the voltage of terminal c0 becomes VSS, the third series-connected N-channel MOS transistor 22C is in a conductive state and the fourth series-connected N-channel MOS transistor 23C is in a non-conductive state.

[0126] As a result, the voltage of the second node 91C, that is, the gate voltage of the second pull-down N-channel MOS transistor 21C, becomes VDD-Vtn.

[0127] On the other hand, when a first control signal with a logical value of 1 is input from the first control signal input terminal CNT0, that is, when the voltage of the terminal sel0 is VDD, the first P-channel MOS transistor 25 is in a non-conductive state.

[0128] Therefore, in the assist circuit 10C, once a logical value of 1 is input to terminal c0, that is, once the voltage of terminal c0 becomes VDD, the fourth series-connected N-channel MOS transistor 23C becomes conductive and the voltage of the second node 91C is reset (becomes VSS), and thereafter the voltage of the second node 91C will never become higher than VSS, that is, the second pull-down N-channel MOS transistor 21C will never pull down and reduce the voltage of the active word line 20WL1.

[0129] In this way, according to the semiconductor memory device 1C having the above configuration, it is possible to control whether or not the assist function of the active word line 20 is enabled by controlling the first control signal.

[0130] In the assist circuit 10C having the above configuration, the P-channel MOS transistor located in the current path from the power supply wiring to the first node 91 and the P-channel MOS transistor located in the current path from the power supply wiring to the second node 91C can be made into a single common first P-channel MOS transistor 25.

[0131] This allows the area required to form the P-channel MOS transistors to be reduced compared to when the P-channel MOS transistor located in the current path from the power supply wiring to the first node 91 and the P-channel MOS transistor located in the current path from the power supply wiring to the second node 91C are formed separately.

[0132] In the fourth embodiment, the assist circuit 10C is configured by adding one circuit group consisting of a second pull-down N-channel MOS transistor 21C, a third series-connected N-channel MOS transistor 22C, a fourth series-connected N-channel MOS transistor 23C, and an inverter 24C to the assist circuit 10A of the second embodiment, and has been described as being able to control whether or not to enable the assist function of two active word lines 20 (word line 20WL0 and word line 20WL1).

[0133] In contrast to this, as another configuration example, the assist circuit 10C may be configured, for example, by adding N (N is an integer greater than or equal to 2) of the above-mentioned circuit groups to the assist circuit 10A of embodiment 2, and may be capable of controlling whether or not to enable the assist function of N+1 or more word lines 20 in an active state.

[0134] In this case, the semiconductor memory device 1C includes 1 / (N+1) the number of assist circuits 10C of the word lines 20.

[0135] Fifth Embodiment A semiconductor memory device according to a fifth embodiment, which is configured by partially modifying the configuration of the semiconductor memory device 1A according to the second embodiment, will be described below.

[0136] Here, for the semiconductor memory device of embodiment 5, components that are similar to those of semiconductor memory device 1A have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from semiconductor memory device 1A.

[0137] <Configuration> FIG. 11 is a block diagram showing the configuration of a semiconductor memory device 1D according to the fifth embodiment.

[0138] As shown in FIG. 11, the semiconductor memory device 1D is configured by replacing the eight assist circuits 10A of the semiconductor memory device 1A according to the second embodiment with one assist circuit 10D.

[0139] That is, each of the plurality of assist circuits 10D is connected to eight word lines 20. Therefore, the semiconductor memory device 1D includes one-eighth the number of assist circuits 10D as the number of word lines 20.

[0140] Here, the first control signal input terminal CNT0 is connected to all of the gates of the first P-channel MOS transistors 25 (see FIG. 12, which will be described later) included in each of the plurality of assist circuits 10D.

[0141] 12 is a circuit diagram showing the configuration of the assist circuit 10 D. Here, the eight word lines 20 connected to the assist circuit 10 D are referred to as word line 20WL0, word line 20WL1, word line 20WL2, word line 20WL3, word line 20WL4, word line 20WL5, word line 20WL6, and word line 20WL7, respectively. That is, of the eight word lines 20 connected to the assist circuit 10D, the word line 20 connected to one or more memory cells 40 forming a certain row (e.g., row 0) of the memory cell array 50 is referred to as word line 20WL0, the word line 20 connected to one or more memory cells 40 forming another certain row (e.g., row 1) of the memory cell array 50 is referred to as word line 20WL1, the word line 20 connected to one or more memory cells 40 forming yet another certain row (e.g., row 2) of the memory cell array 50 is referred to as word line 20WL2, and the word line 20 connected to one or more memory cells 40 forming yet another certain row (e.g., row 3) of the memory cell array 50 is referred to as word line 20WL3. A word line 20 connected to one or more memory cells 40 forming another row (e.g., the fourth row) of the memory cell array 50 is referred to as word line 20WL3, a word line 20 connected to one or more memory cells 40 forming another row (e.g., the fifth row) of the memory cell array 50 is referred to as word line 20WL5, a word line 20 connected to one or more memory cells 40 forming another row (e.g., the sixth row) of the memory cell array 50 is referred to as word line 20WL6, and a word line 20 connected to one or more memory cells 40 forming another row (e.g., the seventh row) of the memory cell array 50 is referred to as word line 20WL7.

[0142] 12, the assist circuit 10D is connected to the assist circuit 10A according to the second embodiment by a second pull-down N-channel MOS transistor 21D1 having a drain connected to the word line 20 (here, the word line 20WL1), a source connected to a ground line, and a gate connected to the first node 91; and a third pull-down N-channel MOS transistor 21D2 having a drain connected to the word line 20 (here, the word line 20WL2), a source connected to the ground line, and a gate connected to the first node 91. a fourth pull-down N-channel MOS transistor 21D3 having a drain connected to the word line 20 (here, word line 20WL3), a source connected to the ground line, and a gate connected to the first node 91; a fifth pull-down N-channel MOS transistor 21D4 having a drain connected to the word line 20 (here, word line 20WL4), a source connected to the ground line, and a gate connected to the second node 91D; a sixth pull-down N-channel MOS transistor 21D5 having a drain connected to the word line 20 (here, word line 20WL5), a source connected to the ground line, and a gate connected to the second node 91D; a seventh pull-down N-channel MOS transistor 21D6 having a drain connected to the word line 20 (here, word line 20WL6), a source connected to the ground line, and a gate connected to the second node 91D; an eighth pull-down N-channel MOS transistor 21D7 having a drain connected to the word line 20 (here, word line 20WL7), a source connected to the ground line, and a gate connected to the second node 91D; a third series-connected N-channel MOS transistor 22D having a drain connected to the drain of the first P-channel MOS transistor 25 and a source connected to the second node 91D; and a fourth series-connected N-channel MOS transistor 23D having a drain connected to the second node 91D and a source connected to the ground line.

[0143] The assist circuit 10D further differs from the assist circuit 10A in that the inverter 24 is removed, and a NAND circuit 26 is added to the gate of the first series-connected N-channel MOS transistor 22 so that a signal with the inverted logic of the signal input to the gate of the second series-connected N-channel MOS transistor 23 is input when word line 20WL0, word line 20WL1, word line 20WL2, and / or word line WL3 is active (here, when a signal with a logical value of 1 is input to terminal Rdec0), and a NAND circuit 26D is added to the gate of the third series-connected N-channel MOS transistor 22D so that a signal with the inverted logic of the signal input to the gate of the fourth series-connected N-channel MOS transistor 23D is input when word line 20WL4, word line 20WL5, word line 20WL6, and / or word line WL7 is active (here, when a signal with a logical value of 1 is input to terminal Rdec1).

[0144] <Consideration> In the assist circuit 10D configured as described above, the drain of the first series-connected N-channel MOS transistor 22 is connected to the power supply line via the first P-channel MOS transistor 25 .

[0145] Therefore, when a signal with a logical value of 0 is input from terminal Rdec0, i.e., when the voltage of terminal Rdec0 is VSS, and a first control signal with a logical value of 0 is input from first control signal input terminal CNT0, i.e., when the voltage of terminal sel0 is VSS, the first P-channel MOS transistor 25 becomes conductive. Therefore, in the assist circuit 10D, when a logical value of 0 is input to terminal c0, i.e., when the voltage of terminal c0 becomes VSS, the first series-connected N-channel MOS transistor 22 becomes conductive and the second series-connected N-channel MOS transistor 23 becomes non-conductive.

[0146] As a result, the voltage of the first node 91, that is, the gate voltages of the first pull-down N-channel MOS transistor 21, the second pull-down N-channel MOS transistor 21D1, the third pull-down N-channel MOS transistor 21D2, and the fourth pull-down N-channel MOS transistor 21D3, becomes VDD-Vtn.

[0147] On the other hand, when a first control signal with a logical value of 1 is input from the first control signal input terminal CNT0, that is, when the voltage of the terminal sel0 is VDD, the first P-channel MOS transistor 25 is in a non-conductive state.

[0148] Therefore, in the assist circuit 10D, once a logical value of 1 is input to the terminal c0, that is, once the voltage of the terminal c0 becomes VDD, the second series-connected N-channel MOS transistor 23 becomes conductive and the voltage of the first node 91 is reset (becomes VSS), and thereafter the voltage of the first node 91 will not become higher than VSS; that is, the first pull-down N-channel MOS transistor 21, the second pull-down N-channel MOS transistor 21D1, the third pull-down N-channel MOS transistor 21D2, and the fourth pull-down N-channel MOS transistor 21D3 will not pull down and reduce the voltages of the active word lines 20WL0, 20WL1, 20WL2, and 20WL3, respectively.

[0149] Furthermore, when a signal with a logical value of 0 is input from terminal Rdec1, i.e., when the voltage of terminal Rdec1 is VSS, and a first control signal with a logical value of 0 is input from first control signal input terminal CNT0, i.e., when the voltage of terminal sel0 is VSS, the first P-channel MOS transistor 25 becomes conductive. Therefore, in the assist circuit 10D, when a logical value of 0 is input to terminal c0, i.e., when the voltage of terminal c0 becomes VSS, the third series-connected N-channel MOS transistor 22D becomes conductive and the fourth series-connected N-channel MOS transistor 23D becomes non-conductive.

[0150] As a result, the voltage of the second node 91D, that is, the gate voltages of the fifth pull-down N-channel MOS transistor 21D4, the sixth pull-down N-channel MOS transistor 21D5, the seventh pull-down N-channel MOS transistor 21D6, and the eighth pull-down N-channel MOS transistor 21D7, becomes VDD-Vtn.

[0151] On the other hand, when a first control signal with a logical value of 1 is input from the first control signal input terminal CNT0, that is, when the voltage of the terminal sel0 is VDD, the first P-channel MOS transistor 25 is in a non-conductive state.

[0152] Therefore, in the assist circuit 10D, once a logical value of 1 is input to the terminal c0, that is, once the voltage of the terminal c0 becomes VDD, the fourth series-connected N-channel MOS transistor 23D becomes conductive and the voltage of the second node 91D is reset (becomes VSS), and thereafter the voltage of the second node 91D will never become higher than VSS; that is, the fifth pull-down N-channel MOS transistor 21D4, the sixth pull-down N-channel MOS transistor 21D5, the seventh pull-down N-channel MOS transistor 21D6, and the eighth pull-down N-channel MOS transistor 21D7 will never pull down and reduce the voltages of the word lines 20WL4, 20WL5, 20WL6, and 20WL7, respectively, which are in the active state.

[0153] In this way, according to the semiconductor memory device 1D having the above configuration, it is possible to control whether or not the assist function of the active word line 20 is enabled by controlling the first control signal.

[0154] In the assist circuit 10D having the above configuration, the P-channel MOS transistor located in the current path from the power supply wiring to the first node 91 and the P-channel MOS transistor located in the current path from the power supply wiring to the second node 91D can be made into a single common first P-channel MOS transistor 25.

[0155] This allows the area required to form the P-channel MOS transistors to be reduced compared to when the P-channel MOS transistor located in the current path from the power supply wiring to the first node 91 and the P-channel MOS transistor located in the current path from the power supply wiring to the second node 91D are formed separately.

[0156] Furthermore, in the assist circuit 10D having the above configuration, the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the first pull-down N-channel MOS transistor 21, the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the second pull-down N-channel MOS transistor 21D1, the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the third pull-down N-channel MOS transistor 21D2, and the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the fourth pull-down N-channel MOS transistor 21D3 are all formed as a single first series-connected N-channel MOS transistor 22. and an N-channel MOS transistor located in the current path from the gate of the first pull-down N-channel MOS transistor 21 to the ground wiring, an N-channel MOS transistor located in the current path from the gate of the second pull-down N-channel MOS transistor 21D1 to the ground wiring, an N-channel MOS transistor located in the current path from the gate of the third pull-down N-channel MOS transistor 21D2 to the ground wiring, and an N-channel MOS transistor located in the current path from the gate of the fourth pull-down N-channel MOS transistor 21D3 to the ground wiring can be formed as a single common second series-connected N-channel MOS transistor 23.

[0157] This makes it possible to separately form an N-channel MOS transistor located in the current path from the power supply wiring to the gate of the first pull-down N-channel MOS transistor 21, an N-channel MOS transistor located in the current path from the power supply wiring to the gate of the second pull-down N-channel MOS transistor 21D1, an N-channel MOS transistor located in the current path from the power supply wiring to the gate of the third pull-down N-channel MOS transistor 21D2, and an N-channel MOS transistor located in the current path from the power supply wiring to the gate of the fourth pull-down N-channel MOS transistor 21D3, and / or In this case, the area required for forming the N-channel MOS transistors can be reduced compared to when an N-channel MOS transistor located in the current path from the gate of the third pull-down N-channel MOS transistor 21D2 to the ground wiring, an N-channel MOS transistor located in the current path from the gate of the third pull-down N-channel MOS transistor 21D2 to the ground wiring, and an N-channel MOS transistor located in the current path from the gate of the fourth pull-down N-channel MOS transistor 21D3 are separately formed.

[0158] Furthermore, in the assist circuit 10D having the above configuration, the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the fifth pull-down N-channel MOS transistor 21D4, the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the sixth pull-down N-channel MOS transistor 21D5, the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the seventh pull-down N-channel MOS transistor 21D6, and the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the eighth pull-down N-channel MOS transistor 21D7 are all formed into a single common third series-connected N-channel MOS transistor 22D. and an N-channel MOS transistor located in the current path from the gate of the fifth pull-down N-channel MOS transistor 21D4 to the ground wiring, an N-channel MOS transistor located in the current path from the gate of the sixth pull-down N-channel MOS transistor 21D5 to the ground wiring, an N-channel MOS transistor located in the current path from the gate of the seventh pull-down N-channel MOS transistor 21D6 to the ground wiring, and an N-channel MOS transistor located in the current path from the gate of the eighth pull-down N-channel MOS transistor 21D7 to the ground wiring can be formed as a single common fourth series-connected N-channel MOS transistor 23D.

[0159] This makes it possible to separately form an N-channel MOS transistor located in the current path from the power supply wiring to the gate of fifth pull-down N-channel MOS transistor 21D4, an N-channel MOS transistor located in the current path from the power supply wiring to the gate of sixth pull-down N-channel MOS transistor 21D5, an N-channel MOS transistor located in the current path from the power supply wiring to the gate of seventh pull-down N-channel MOS transistor 21D6, and an N-channel MOS transistor located in the current path from the power supply wiring to the gate of eighth pull-down N-channel MOS transistor 21D7, and / or In this case, the area required for forming the N-channel MOS transistors can be reduced compared to when the N-channel MOS transistor located in the current path from the gate of the sixth pull-down N-channel MOS transistor 21D4 to the ground wiring, the N-channel MOS transistor located in the current path from the gate of the sixth pull-down N-channel MOS transistor 21D5 to the ground wiring, the N-channel MOS transistor located in the current path from the gate of the seventh pull-down N-channel MOS transistor 21D6 to the ground wiring, and the N-channel MOS transistor located in the current path from the gate of the eighth pull-down N-channel MOS transistor 21D7 are separately formed.

[0160] In the fifth embodiment, the assist circuit 10D has been described as having four pull-down N-channel MOS transistors M whose gates are connected to the first node 91 and four N-channel MOS transistors connected to the second node 91D.

[0161] Alternatively, M may be an integer other than 4 that is equal to or greater than 2.

[0162] In this case, the semiconductor memory device 1D includes assist circuits 10D in the number of 1 / 2M, which is the number of word lines 20.

[0163] Sixth Embodiment A semiconductor memory device according to a sixth embodiment, which is configured by partially modifying the configuration of the semiconductor memory device 1A according to the second embodiment, will be described below.

[0164] Here, for the semiconductor memory device of embodiment 6, components that are similar to those of semiconductor memory device 1A have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from semiconductor memory device 1A.

[0165] FIG. 13 is a block diagram showing the configuration of a semiconductor memory device 1E according to the sixth embodiment.

[0166] As shown in FIG. 13, the semiconductor memory device 1E is configured by replacing the four assist circuits 10A of the semiconductor memory device 1A according to the second embodiment with one assist circuit 10E.

[0167] That is, each of the plurality of assist circuits 10E is connected to four word lines 20. Therefore, the semiconductor memory device 1E includes one-fourth the number of the assist circuits 10E as the number of the word lines 20.

[0168] Here, the first control signal input terminal CNT0 is connected to all of the gates of the first P-channel MOS transistors 25 (see FIG. 14 described later) included in each of the plurality of assist circuits 10E.

[0169] 14 is a circuit diagram showing the configuration of the assist circuit 10E. Here, four word lines 20 connected to the assist circuit 10E are referred to as word line 20WL0, word line 20WL1, word line 20WL2, and word line 20WL3. That is, of the four word lines 20 connected to the assist circuit 10E, the word line 20 connected to one or more memory cells 40 forming a certain row (e.g., row 0) of the memory cell array 50 is referred to as word line 20WL0, the word line 20 connected to one or more memory cells 40 forming another certain row (e.g., row 1) of the memory cell array 50 is referred to as word line 20WL1, the word line 20 connected to one or more memory cells 40 forming yet another certain row (e.g., row 2) of the memory cell array 50 is referred to as word line 20WL2, and the word line 20 connected to one or more memory cells 40 forming yet another certain row (e.g., row 3) of the memory cell array 50 is referred to as word line 20WL3.

[0170] 14, the assist circuit 10E is configured by adding to the assist circuit 10A according to the second embodiment: a second pull-down N-channel MOS transistor 21E1 having a drain connected to the word line 20 (here, the word line 20WL1), a source connected to a ground line, and a gate connected to the first node 91; a third pull-down N-channel MOS transistor 21E2 having a drain connected to the word line 20 (here, the word line 20WL2), a source connected to the ground line, and a gate connected to the first node 91; and a fourth pull-down N-channel MOS transistor 21E3 having a drain connected to the word line 20 (here, the word line 20WL3), a source connected to the ground line, and a gate connected to the first node 91.

[0171] <Consideration> In the assist circuit 10E configured as described above, the drain of the first series-connected N-channel MOS transistor 22 is connected to the power supply line via the first P-channel MOS transistor 25 .

[0172] Therefore, when a first control signal with a logical value of 0 is input from the first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VSS, the first P-channel MOS transistor 25 is in a conductive state. Therefore, in the assist circuit 10E, when a logical value of 0 is input to terminal c0, that is, when the voltage of terminal c0 becomes VSS, the first series-connected N-channel MOS transistor 22 is in a conductive state and the second series-connected N-channel MOS transistor 23 is in a non-conductive state.

[0173] As a result, the voltage of the first node 91, that is, the gate voltages of the first pull-down N-channel MOS transistor 21, the second pull-down N-channel MOS transistor 21E1, the third pull-down N-channel MOS transistor 21E2, and the fourth pull-down N-channel MOS transistor 21E3, becomes VDD-Vtn.

[0174] On the other hand, when a first control signal with a logical value of 1 is input from the first control signal input terminal CNT0, that is, when the voltage of the terminal sel0 is VDD, the first P-channel MOS transistor 25 is in a non-conductive state.

[0175] Therefore, in the assist circuit 10E, once a logical value of 1 is input to the terminal c0, that is, once the voltage of the terminal c0 becomes VDD, the second series-connected N-channel MOS transistor 23 becomes conductive and the voltage of the first node 91 is reset (becomes VSS), and thereafter the voltage of the first node 91 will not become higher than VSS, that is, the first pull-down N-channel MOS transistor 21, the second pull-down N-channel MOS transistor 21E1, the third pull-down N-channel MOS transistor 21E2, and the fourth pull-down N-channel MOS transistor 21E3 will not pull down and reduce the voltages of the active word lines 20WL0, 20WL1, 20WL2, and 20WL3, respectively.

[0176] In this way, according to the semiconductor memory device 1E having the above configuration, it is possible to control whether or not the assist function of the active word line 20 is enabled by controlling the first control signal.

[0177] In the assist circuit 10E having the above configuration, the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the first pull-down N-channel MOS transistor 21, the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the second pull-down N-channel MOS transistor 21E1, the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the third pull-down N-channel MOS transistor 21E2, and the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the fourth pull-down N-channel MOS transistor 21E3 can be made into a single common first series-connected N-channel MOS transistor 22. Furthermore, the N-channel MOS transistor located in the current path from the gate of the first pull-down N-channel MOS transistor 21 to the ground wiring, the N-channel MOS transistor located in the current path from the gate of the second pull-down N-channel MOS transistor 21E1 to the ground wiring, the N-channel MOS transistor located in the current path from the gate of the third pull-down N-channel MOS transistor 21E2 to the ground wiring, and the N-channel MOS transistor located in the current path from the gate of the fourth pull-down N-channel MOS transistor 21E3 to the ground wiring can be formed as a single common second series-connected N-channel MOS transistor 23.

[0178] Therefore, the size of the first series-connected N-channel MOS transistor 22 can be increased compared to when the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the first pull-down N-channel MOS transistor 21, the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the second pull-down N-channel MOS transistor 21E1, the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the third pull-down N-channel MOS transistor 21E2, and the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the fourth pull-down N-channel MOS transistor 21E3 are formed separately.

[0179] This makes it possible to suppress variations in Vtn of the first series-connected N-channel MOS transistor 22 .

[0180] In the sixth embodiment, the assist circuit 10E has been described assuming that the number M of pull-down N-channel MOS transistors having gates connected to the first node 91 is four.

[0181] Alternatively, M may be an integer other than 4 that is equal to or greater than 2.

[0182] In this case, the semiconductor memory device 1E includes assist circuits 10E in a number 1 / M of the number of word lines 20.

[0183] Seventh Embodiment A semiconductor memory device according to a seventh embodiment, which is configured by partially modifying the configuration of the semiconductor memory device 1A according to the second embodiment, will be described below.

[0184] Here, for the semiconductor memory device of embodiment 7, components that are similar to those of semiconductor memory device 1A have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from semiconductor memory device 1A.

[0185] <Configuration> FIG. 15 is a block diagram showing the configuration of a semiconductor memory device 1F according to the seventh embodiment.

[0186] As shown in FIG. 15, the semiconductor memory device 1F is configured by replacing the assist circuit 10A of the semiconductor memory device 1A according to the second embodiment with an assist circuit 10F.

[0187] Here, the first control signal input terminal CNT0 is connected to all of the gates of the first P-channel MOS transistors 25 (see FIG. 16 described later) included in each of the plurality of assist circuits 10F.

[0188] FIG. 16 is a circuit diagram showing the configuration of the assist circuit 10F.

[0189] As shown in FIG. 16, the assist circuit 10F is configured by adding a second pull-down N-channel MOS transistor 21F to the assist circuit 10A according to the second embodiment, the drain of which is connected to the word line 20, the source of which is connected to the ground line, and the gate of which is connected to the power supply line.

[0190] <Considerations> In the assist circuit 10F configured as described above, the voltage of the word line 20 is pulled down by the first pull-down N-channel MOS transistor 21, whose gate voltage is VDD-Vtn, and the second pull-down N-channel MOS transistor 21F, whose gate voltage is VDD.

[0191] FIG. 17 is a schematic diagram showing the relationship between the process variation conditions of the N-channel MOS transistor and the amount of voltage drop on the word line 20 in the following cases: (1) when the voltage on the word line 20 is pulled down by two transistors, a second pull-down N-channel MOS transistor 21F having a gate voltage of VDD and a first pull-down N-channel MOS transistor 21 having a gate voltage of VDD-Vtn; (2) when the voltage on the word line 20 is pulled down only by the second pull-down N-channel MOS transistor 21F having a gate voltage of VDD; and (3) when the voltage on the word line 20 is pulled down only by the first pull-down N-channel MOS transistor 21 having a gate voltage of VDD-Vtn.

[0192] In FIG. 17, the horizontal axis indicates the degree of fluctuation in the process variation conditions of the N-channel MOS transistor, and the vertical axis indicates the amount of voltage drop in the word line 20.

[0193] As shown in FIG. 17 , (1) when the voltage of the word line 20 is pulled down by two transistors, the second pull-down N-channel MOS transistor 21F having a gate voltage of VDD and the first pull-down N-channel MOS transistor 21 having a gate voltage of VDD-Vtn, the amount of voltage drop on the word line 20 can be controlled more sensitively than (2) when the voltage of the word line 20 is pulled down only by the second pull-down N-channel MOS transistor 21F having a gate voltage of VDD, and (3) when the voltage of the word line 20 is pulled down only by the first pull-down N-channel MOS transistor 21 having a gate voltage of VDD-Vtn.

[0194] In this way, according to the semiconductor memory device 1F having the above configuration, the amount of voltage drop in the word line 20 can be controlled more sensitively.

[0195] Eighth Embodiment A semiconductor memory device according to an eighth embodiment, which is configured by partially modifying the configuration of the semiconductor memory device 1A according to the second embodiment, will be described below.

[0196] Here, for the semiconductor memory device of embodiment 8, components that are similar to those of semiconductor memory device 1A have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from semiconductor memory device 1A.

[0197] <Configuration> FIG. 18 is a block diagram showing the configuration of a semiconductor memory device 1G according to the eighth embodiment.

[0198] As shown in FIG. 18, a semiconductor memory device 1G is configured by changing the assist circuit 10A of the semiconductor memory device 1A according to the second embodiment to an assist circuit 10G.

[0199] Here, the first control signal input terminal CNT0 is connected to all of the gates of the first P-channel MOS transistors 25 (see FIG. 19 described later) included in each of the plurality of assist circuits 10G.

[0200] FIG. 19 is a circuit diagram showing the configuration of the assist circuit 10G.

[0201] As shown in FIG. 19, the assist circuit 10G is configured by changing the first series-connected N-channel MOS transistor 22 of the assist circuit 10A according to the second embodiment to a first series-connected N-channel MOS transistor 22G.

[0202] Here, the first series-connected N-channel MOS transistor 22 G has a lower threshold than the first pull-down N-channel MOS transistor 21 and the second series-connected N-channel MOS transistor 23 .

[0203] <Considerations> In the semiconductor memory device 1G having the above configuration, when the power supply voltage is lowered, the gate voltage of the first pull-down N-channel MOS transistor 21 becomes lower than the threshold voltage of the first pull-down N-channel MOS transistor 21, and as a result, the occurrence of the inconvenience that the first pull-down N-channel MOS transistor 21 cannot pull down the word line 20 is suppressed.

[0204] As a result, the semiconductor memory device 1G having the above configuration can expand the low voltage operating range of the pull-down operation of the word line 20.

[0205] Ninth Embodiment Hereinafter, a semiconductor memory device according to an eighth embodiment will be described, which is configured by partially modifying the configuration of the semiconductor memory device 1A according to the second embodiment.

[0206] Here, for the semiconductor memory device of embodiment 8, components that are similar to those of semiconductor memory device 1A have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from semiconductor memory device 1A.

[0207] <Configuration> FIG. 20 is a block diagram showing the configuration of a semiconductor memory device 1H according to the ninth embodiment.

[0208] As shown in FIG. 20, the semiconductor memory device 1H is configured by adding a second control signal input terminal CNT1 to the semiconductor memory device 1A according to the second embodiment and changing the assist circuit 10A to an assist circuit 10H.

[0209] Here, the first control signal input terminal CNT0 is connected to all of the gates of the first P-channel MOS transistors 25 (see Figure 21 described below) provided in each of the multiple assist circuits 10H, and the second control signal input terminal CNT1 is connected to all of the gates of the second P-channel MOS transistors 25H (see Figure 21 described below) provided in each of the multiple assist circuits 10H.

[0210] FIG. 21 is a circuit diagram showing the configuration of the assist circuit 10H.

[0211] As shown in FIG. 21 , the assist circuit 10H is configured by adding to the assist circuit 10A according to the second embodiment a second pull-down N-channel MOS transistor 21H having a drain connected to the word line 20, a source connected to a ground line, and a gate connected to a second node 91H, a second P-channel MOS transistor 25H having a drain connected to a third node 92H and a source connected to a power supply line, a third series-connected N-channel MOS transistor 22H having a drain connected to the third node 92H and a source connected to the second node 91H, and a fourth series-connected N-channel MOS transistor 23H having a drain connected to the second node 91H and a source connected to the ground line, and further adding to the gate of the third series-connected N-channel MOS transistor 22H an inverter 24H connected so as to input a signal having the inverted logic of a signal input to the gate of the fourth series-connected N-channel MOS transistor 23H.

[0212] The gate of the second P-channel MOS transistor 25H is connected to the second control signal input terminal CNT1 via the terminal sel1.

[0213] <Considerations> According to the semiconductor memory device 1H having the above configuration, it is possible to control whether or not to enable the assist function using the first pull-down N-channel MOS transistor 21 by controlling the first control signal, and it is possible to control whether or not to enable the assist function using the second pull-down N-channel MOS transistor 21H by controlling the second control signal.

[0214] As a result, in the semiconductor memory device 1H having the above configuration, it is possible to select whether to pull down the word line 20 using the first pull-down N-channel MOS transistor 21, to pull down the word line 20 using the second pull-down N-channel MOS transistor 21H, to pull down the word line 20 using the first pull-down N-channel MOS transistor 21 and the second pull-down N-channel MOS transistor 21H, or not to pull down the word line 20.

[0215] Tenth Embodiment Hereinafter, a semiconductor memory device according to a tenth embodiment will be described, which is configured by partially modifying the configuration of the semiconductor memory device 1B according to the third embodiment.

[0216] Here, for the semiconductor memory device of embodiment 10, components that are similar to those of semiconductor memory device 1B have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from semiconductor memory device 1B.

[0217] FIG. 22 is a block diagram showing the configuration of a semiconductor memory device 1J according to the tenth embodiment.

[0218] As shown in FIG. 22, the semiconductor memory device 1J is configured by changing the four assist circuits 10B of the semiconductor memory device 1B according to the third embodiment to one assist circuit 10J.

[0219] That is, each of the plurality of assist circuits 10J is connected to four word lines 20. Therefore, the semiconductor memory device 1J includes one-fourth the number of assist circuits 10J as the number of word lines 20.

[0220] Here, the first control signal input terminal CNT0 is connected to all of the gates of first series-connected N-channel MOS transistors 22B (see FIG. 23 described later) included in each of the plurality of assist circuits 10J.

[0221] 23 is a circuit diagram showing the configuration of the assist circuit 10J. Here, four word lines 20 connected to the assist circuit 10J are referred to as word line 20WL0, word line 20WL1, word line 20WL2, and word line 20WL3, respectively. That is, of the four word lines 20 connected to the assist circuit 10J, the word line 20 connected to one or more memory cells 40 forming a certain row (e.g., row 0) of the memory cell array 50 is referred to as word line 20WL0, the word line 20 connected to one or more memory cells 40 forming another certain row (e.g., row 1) of the memory cell array 50 is referred to as word line 20WL1, the word line 20 connected to one or more memory cells 40 forming yet another certain row (e.g., row 2) of the memory cell array 50 is referred to as word line 20WL2, and the word line 20 connected to one or more memory cells 40 forming yet another certain row (e.g., row 3) of the memory cell array 50 is referred to as word line 20WL3.

[0222] As shown in FIG. 23 , the assist circuit 10J is configured by adding to the assist circuit 10B of embodiment 3 a second pull-down N-channel MOS transistor 21J1 having a drain connected to the word line 20 (here, word line 20WL1), a source connected to a ground line, and a gate connected to a first node 91; a third pull-down N-channel MOS transistor 21J2 having a drain connected to the word line 20 (here, word line 20WL2), a source connected to the ground line, and a gate connected to the first node 91; and a fourth pull-down N-channel MOS transistor 21J3 having a drain connected to the word line 20 (here, word line 20WL3), a source connected to the ground line, and a gate connected to the first node 91.

[0223] <Consideration> In the assist circuit 10J configured as described above, the drain of the first series-connected N-channel MOS transistor 22B (that is, the second node 92B) is connected to the power supply line via the first P-channel MOS transistor 25B.

[0224] Therefore, when a first control signal with a logical value of 1 is input from the first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VDD, the first series-connected N-channel MOS transistor 22B is in a conductive state. Therefore, in the assist circuit 10J, when a logical value of 0 is input to terminal c0, that is, when the voltage of terminal c0 becomes VSS, the first P-channel MOS transistor 25B is in a conductive state and the second series-connected N-channel MOS transistor 23 is in a non-conductive state.

[0225] As a result, the voltage of the first node 91, that is, the gate voltage of the first pull-down N-channel MOS transistor 21, becomes VDD-Vtn.

[0226] On the other hand, when a first control signal with a logical value of 0 is input from the first control signal input terminal CNT0, that is, when the voltage of the terminal sel0 is VSS, the first series-connected N-channel MOS transistor 22B is in a non-conductive state.

[0227] Therefore, in the assist circuit 10J, once a logical value of 1 is input to the terminal c0, that is, once the voltage of the terminal c0 becomes VDD, the second series-connected N-channel MOS transistor 23 becomes conductive and the voltage of the first node 91 is reset (becomes VSS), and thereafter the voltage of the first node 91 will never become higher than VSS, that is, the first pull-down N-channel MOS transistor 21, the second pull-down N-channel MOS transistor 21J1, the third pull-down N-channel MOS transistor 21J2, and the fourth pull-down N-channel MOS transistor 21J3 will never pull down and reduce the voltages of the active word lines 20WL0, 20WL1, 20WL2, and 20WL3, respectively.

[0228] In this way, according to the semiconductor memory device 1J having the above configuration, it is possible to control whether or not the assist function of the active word line 20 is enabled by controlling the first control signal.

[0229] In the assist circuit 10J having the above configuration, the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the first pull-down N-channel MOS transistor 21, the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the second pull-down N-channel MOS transistor 21J1, the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the third pull-down N-channel MOS transistor 21J2, and the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the fourth pull-down N-channel MOS transistor 21J3 can be made into a single common first series-connected N-channel MOS transistor 22B. Furthermore, the N-channel MOS transistor located in the current path from the gate of the first pull-down N-channel MOS transistor 21 to the ground wiring, the N-channel MOS transistor located in the current path from the gate of the second pull-down N-channel MOS transistor 21J1 to the ground wiring, the N-channel MOS transistor located in the current path from the gate of the third pull-down N-channel MOS transistor 21J2 to the ground wiring, and the N-channel MOS transistor located in the current path from the gate of the fourth pull-down N-channel MOS transistor 21J3 to the ground wiring can be formed as a single common second series-connected N-channel MOS transistor 23.

[0230] Therefore, the size of the first series-connected N-channel MOS transistor 22B can be increased compared to when the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the first pull-down N-channel MOS transistor 21, the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the second pull-down N-channel MOS transistor 21J1, the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the third pull-down N-channel MOS transistor 21J2, and the N-channel MOS transistor located in the current path from the power supply wiring to the gate of the fourth pull-down N-channel MOS transistor 21J3 are formed separately.

[0231] This makes it possible to suppress variations in Vtn of the first series-connected N-channel MOS transistor 22B.

[0232] In the tenth embodiment, the assist circuit 10J has been described assuming that the number M of pull-down N-channel MOS transistors having gates connected to the first node 91 is four.

[0233] Alternatively, M may be an integer other than 4 that is equal to or greater than 2.

[0234] In this case, the semiconductor memory device 1E includes assist circuits 10E in a number 1 / M of the number of word lines 20.

[0235] Eleventh Embodiment A semiconductor memory device according to an eleventh embodiment, which is configured by partially modifying the configuration of the semiconductor memory device 1B according to the third embodiment, will be described below.

[0236] Here, for the semiconductor memory device of embodiment 11, components that are similar to those of semiconductor memory device 1B have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from semiconductor memory device 1B.

[0237] <Configuration> FIG. 24 is a block diagram showing the configuration of a semiconductor memory device 1K according to the eleventh embodiment.

[0238] As shown in FIG. 24, the semiconductor memory device 1K is configured by changing the assist circuit 10B of the semiconductor memory device 1B according to the third embodiment to an assist circuit 10K.

[0239] Here, the first control signal input terminal CNT0 is connected to all of the gates of first series-connected N-channel MOS transistors 22B (see FIG. 25 described later) included in each of the plurality of assist circuits 10K.

[0240] FIG. 25 is a circuit diagram showing the configuration of the assist circuit 10K.

[0241] As shown in FIG. 25, the assist circuit 10K is configured by adding a second pull-down N-channel MOS transistor 21K to the assist circuit 10B according to the third embodiment, the drain of which is connected to the word line 20, the source of which is connected to the ground line, and the gate of which is connected to the power supply line.

[0242] <Considerations> In the assist circuit 10K configured as described above, the voltage of the word line 20 is pulled down by the first pull-down N-channel MOS transistor 21, whose gate voltage is VDD-Vtn, and the second pull-down N-channel MOS transistor 21K, whose gate voltage is VDD.

[0243] FIG. 26 is a schematic diagram showing the relationship between the process variation conditions of the N-channel MOS transistor and the amount of voltage drop on the word line 20 in the following cases: (1) when the voltage on the word line 20 is pulled down by two transistors, a second pull-down N-channel MOS transistor 21K having a gate voltage of VDD and a first pull-down N-channel MOS transistor 21 having a gate voltage of VDD-Vtn; (2) when the voltage on the word line 20 is pulled down only by the second pull-down N-channel MOS transistor 21K having a gate voltage of VDD; and (3) when the voltage on the word line 20 is pulled down only by the first pull-down N-channel MOS transistor 21 having a gate voltage of VDD-Vtn.

[0244] In FIG. 26, the horizontal axis indicates the degree of fluctuation in the process variation conditions of the N-channel MOS transistor, and the vertical axis indicates the amount of voltage drop in the word line 20.

[0245] As shown in FIG. 26, (1) when the voltage of the word line 20 is pulled down by two transistors, the second pull-down N-channel MOS transistor 21K having a gate voltage of VDD and the first pull-down N-channel MOS transistor 21 having a gate voltage of VDD-Vtn, the amount of voltage drop on the word line 20 can be controlled more sensitively than (2) when the voltage of the word line 20 is pulled down only by the second pull-down N-channel MOS transistor 21K having a gate voltage of VDD, and (3) when the voltage of the word line 20 is pulled down only by the first pull-down N-channel MOS transistor 21 having a gate voltage of VDD-Vtn.

[0246] In this way, according to the semiconductor memory device 1K having the above configuration, the amount of voltage drop in the word line 20 can be controlled more sensitively.

[0247] Twelfth Embodiment Hereinafter, a semiconductor memory device according to a twelfth embodiment will be described, which is configured by partially modifying the configuration of the semiconductor memory device 1B according to the third embodiment.

[0248] Here, for the semiconductor memory device of embodiment 12, components that are similar to those of semiconductor memory device 1B have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from semiconductor memory device 1B.

[0249] <Configuration> FIG. 27 is a block diagram showing the configuration of a semiconductor memory device 1L according to the twelfth embodiment.

[0250] As shown in FIG. 27, a semiconductor memory device 1L is configured by replacing the assist circuit 10B of the semiconductor memory device 1B according to the third embodiment with an assist circuit 10L.

[0251] Here, the first control signal input terminal CNT0 is connected to all of the gates of first series-connected N-channel MOS transistors 22L (see FIG. 28 described later) included in each of the plurality of assist circuits 10L.

[0252] FIG. 28 is a circuit diagram showing the configuration of the assist circuit 10L.

[0253] As shown in FIG. 28, the assist circuit 10L is configured by changing the first series-connected N-channel MOS transistor 22B of the assist circuit 10L according to the third embodiment to a first series-connected N-channel MOS transistor 22L.

[0254] Here, the threshold voltage of the first series-connected N-channel MOS transistor 22L is lower than that of the first pull-down N-channel MOS transistor 21 and the second series-connected N-channel MOS transistor 23.

[0255] <Considerations> In the semiconductor memory device 1L having the above configuration, when the power supply voltage is lowered, the gate voltage of the first pull-down N-channel MOS transistor 21 becomes lower than the threshold voltage of the first pull-down N-channel MOS transistor 21, and as a result, the occurrence of the inconvenience that the first pull-down N-channel MOS transistor 21 cannot pull down the word line 20 is suppressed.

[0256] As a result, the semiconductor memory device 1L having the above configuration can expand the low voltage operating range of the pull-down operation of the word line 20.

[0257] Thirteenth Embodiment A semiconductor memory device according to a thirteenth embodiment, which is configured by partially modifying the configuration of the semiconductor memory device 1B according to the third embodiment, will be described below.

[0258] Here, for the semiconductor memory device of embodiment 13, components that are similar to those of semiconductor memory device 1B have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from semiconductor memory device 1B.

[0259] <Configuration> FIG. 29 is a block diagram showing the configuration of a semiconductor memory device 1M according to the thirteenth embodiment.

[0260] As shown in FIG. 29, the semiconductor memory device 1M is configured by adding a second control signal input terminal CNT1 to the semiconductor memory device 1B according to the third embodiment and changing the assist circuit 10B to an assist circuit 10M.

[0261] Here, the first control signal input terminal CNT0 is connected to all of the gates of the first series-connected N-channel MOS transistors 22B (see Figure 30 described below) that are provided in each of the multiple assist circuits 10M, and the second control signal input terminal CNT1 is connected to all of the gates of the third series-connected N-channel MOS transistors 22M (see Figure 30 described below) that are provided in each of the multiple assist circuits 10M.

[0262] FIG. 30 is a circuit diagram showing the configuration of the assist circuit 10M.

[0263] 30, the assist circuit 10M is configured by adding to the assist circuit 10B according to the third embodiment a second pull-down N-channel MOS transistor 21M having a drain connected to the word line 20, a source connected to a ground line, and a gate connected to a third node 91M, a second P-channel MOS transistor 25M having a source connected to a power supply line and a drain connected to a fourth node 92M, a third series-connected N-channel MOS transistor 22M having a drain connected to the fourth node 92M and a source connected to the third node 91M, and a fourth series-connected N-channel MOS transistor 23M having a drain connected to the third node 91M and a source connected to the ground line, and further by inputting a signal having the same logic as the signal input to the gate of the second series-connected N-channel MOS transistor 23 to the gate of the second P-channel MOS transistor 25M and the gate of the fourth series-connected N-channel MOS transistor 23M.

[0264] The gate of the third series-connected N-channel MOS transistor 22M is connected to the second control signal input terminal CNT1 via the terminal sel1.

[0265] <Considerations> According to the semiconductor memory device 1M having the above configuration, it is possible to control whether or not to enable the assist function using the first pull-down N-channel MOS transistor 21 by controlling the first control signal, and it is possible to control whether or not to enable the assist function using the second pull-down N-channel MOS transistor 21M by controlling the second control signal.

[0266] As a result, in the semiconductor memory device 1M having the above configuration, it is possible to select whether to pull down the word line 20 using the first pull-down N-channel MOS transistor 21, to pull down the word line 20 using the second pull-down N-channel MOS transistor 21M, to pull down the word line 20 using the first pull-down N-channel MOS transistor 21 and the second pull-down N-channel MOS transistor 21M, or not to pull down the word line 20.

[0267] (Supplementary Note) As described above, the first to thirteenth embodiments have been described as examples of the technology disclosed in this application. However, the present disclosure is not limited to these embodiments. As long as they do not deviate from the spirit of the present disclosure, various modifications that would occur to a person skilled in the art to the present embodiments, or forms constructed by combining components of different embodiments or modifications, may also be included within the scope of one or more aspects of the present disclosure.

[0268] The present disclosure is widely applicable to semiconductor memory devices.

[0269] 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1J, 1K, 1L, 1M Semiconductor memory device 10, 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, 10J, 10K, 10L, 10M Assist circuit 20, 20WL0, 20WL1, 20WL2, 20WL3, 20WL4, 20WL5, 20WL6, 20WL7 Word line 21 First pull-down N-channel MOS transistor 21C, 21D1, 21E1, 21F, 21H, 21J1, 21K, 21M Second pull-down N-channel MOS transistor 21D2, 21E2, 21J2 Third pull-down N-channel MOS transistor 21D3, 21E3, 21J3 21D4 4th pull-down N-channel MOS transistor 21D4 5th pull-down N-channel MOS transistor 21D5 6th pull-down N-channel MOS transistor 21D6 7th pull-down N-channel MOS transistor 21D7 8th pull-down N-channel MOS transistor 22, 22B, 22G, 22L 1st series-connected N-channel MOS transistors 22C, 22D, 22H, 22M 3rd series-connected N-channel MOS transistor 23 2nd series-connected N-channel MOS transistors 23C, 23D, 23H, 23M 4th series-connected N-channel MOS transistors 24, 24C, 24H Inverter 25, 25B 1st P-channel MOS transistor 25H, 25M 2nd P-channel MOS transistor 26, 26D NAND circuit 28 Bit line 29 Inverting bit line 30 Word line driver 40 Memory cell 41, 42 Access transistor 43, 44 Load transistor 45, 46 Drive transistor 50 Memory cell array 60 Row decoder 70 I / O circuit 80 Control unit 91 First node 91C, 91D, 91H, 92B Second node 92H Third node 92M Fourth node

Claims

1. A semiconductor memory device comprising: a first pull-down N-channel MOS (Metal Oxide Semiconductor) transistor having a drain connected to a first word line connected to one or more first memory cells, a source connected to a ground line supplying a ground voltage, and a gate connected to a first node; a first series-connected N-channel MOS transistor having a drain connected to a power supply line supplying a power supply voltage and a source connected to the first node; and a second series-connected N-channel MOS transistor having a drain connected to the first node and a source connected to the ground line, wherein a signal having the inverted logic of a signal input to the gate of the second series-connected N-channel MOS transistor is input to the gate of the first series-connected N-channel MOS transistor.

2. The semiconductor memory device according to claim 1, further comprising a first P-channel MOS transistor having a drain connected to the drain of said first series-connected N-channel MOS transistor, a source connected to said power supply line, and a gate connected to a first control signal input terminal to which a first control signal is input, wherein the drain of said first series-connected N-channel MOS transistor is connected to said power supply line via said first P-channel MOS transistor.

3. The semiconductor memory device according to claim 2, further comprising: a second pull-down N-channel MOS transistor having a drain connected to a second word line connected to one or more second memory cells, a source connected to the ground line, and a gate connected to a second node; a third series-connected N-channel MOS transistor having a drain connected to the drain of the first P-channel MOS transistor and a source connected to the second node; and a fourth series-connected N-channel MOS transistor having a drain connected to the second node and a source connected to the ground line, wherein a signal having an inverted logic of a signal input to the gate of the fourth series-connected N-channel MOS transistor is input to the gate of the third series-connected N-channel MOS transistor.

4. The memory cell further comprises: a second pull-down N-channel MOS transistor having a drain connected to a second word line connected to one or more second memory cells, a source connected to the ground line, and a gate connected to the first node; a third pull-down N-channel MOS transistor having a drain connected to a third word line connected to one or more third memory cells, a source connected to the ground line, and a gate connected to the second node; a fourth pull-down N-channel MOS transistor having a drain connected to a fourth word line connected to one or more fourth memory cells, a source connected to the ground line, and a gate connected to the second node; a third series-connected N-channel MOS transistor having a drain connected to the drain of the first P-channel MOS transistor and a source connected to the second node; and a fourth series-connected N-channel MOS transistor having a drain connected to the second node and a source connected to the ground line, 3. The semiconductor memory device according to claim 2, wherein a signal having an inverted logic of a signal input to the gate of the second series-connected N-channel MOS transistor is input to the gate of the first series-connected N-channel MOS transistor when the first word line and / or the second word line is active, and a signal having an inverted logic of a signal input to the gate of the fourth series-connected N-channel MOS transistor is input to the gate of the third series-connected N-channel MOS transistor when the third word line and / or the fourth word line is active.

5. The semiconductor memory device according to claim 2, further comprising: a second pull-down N-channel MOS transistor having a drain connected to the first word line, a source connected to the ground line, and a gate connected to a second node; a second P-channel MOS transistor having a drain connected to a third node, a source connected to the power supply line, and a gate connected to a second control signal input terminal to which a second control signal is input; a third series-connected N-channel MOS transistor having a drain connected to the third node and a source connected to the second node; and a fourth series-connected N-channel MOS transistor having a drain connected to the second node and a source connected to the ground line, wherein a signal having the same logic as a signal input to the gate of the third series-connected N-channel MOS transistor is input to the gate of the first series-connected N-channel MOS transistor, and a signal having the same logic as a signal input to the gate of the fourth series-connected N-channel MOS transistor is input to the gate of the second series-connected N-channel MOS transistor.

6. A semiconductor memory device comprising: a first pull-down N-channel MOS transistor having a drain connected to a first word line connected to one or more first memory cells, a source connected to a ground line supplying a ground voltage, and a gate connected to a first node; a first P-channel MOS transistor having a source connected to a power supply line supplying a power supply voltage and a drain connected to a second node; a first series-connected N-channel MOS transistor having a drain connected to the second node, a source connected to the first node, and a gate connected to a first control signal input terminal to which a first control signal is input; and a second series-connected N-channel MOS transistor having a drain connected to the first node and a source connected to the ground line, wherein a signal having the same logic as a signal input to the gate of the second series-connected N-channel MOS transistor is input to the gate of the first P-channel MOS transistor.

7. The semiconductor memory device according to claim 2 or claim 6, further comprising a second pull-down N-channel MOS transistor having a drain connected to a second word line connected to one or more second memory cells, a source connected to said ground line, and a gate connected to said first node.

8. The semiconductor memory device according to claim 2 or claim 6, further comprising a second pull-down N-channel MOS transistor having a drain connected to said first word line, a source connected to said ground line, and a gate connected to said power supply line.

9. The semiconductor memory device according to claim 2 or 6, wherein the first series-connected N-channel MOS transistor has a lower threshold voltage than the first pull-down N-channel MOS transistor and the second series-connected N-channel MOS transistor.

10. The semiconductor memory device according to claim 6, further comprising: a second pull-down N-channel MOS transistor having a drain connected to the first word line, a source connected to the ground line, and a gate connected to a third node; a second P-channel MOS transistor having a source connected to the power supply line and a drain connected to a fourth node; a third series-connected N-channel MOS transistor having a drain connected to the fourth node, a source connected to the third node, and a gate connected to a second control signal input terminal that receives a second control signal; and a fourth series-connected N-channel MOS transistor having a drain connected to the third node and a source connected to the ground line, wherein a signal having the same logic as a signal input to the gate of the second series-connected N-channel MOS transistor is input to the gate of the second P-channel MOS transistor and the gate of the fourth series-connected N-channel MOS transistor.

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