Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor that can suppress a decrease in strength against external stress even when the thickness is reduced. A multilayer ceramic capacitor 1 comprises: a multilayer body 10 in which a plurality of dielectric layers 20 formed from a ceramic material and a plurality of internal electrode layers 30 are layered; a plurality of external electrodes 40 disposed on at least a second main surface TS2 of the multilayer body 10; and a stress suppression film 50 that suppresses stress applied to the multilayer body 10 and the plurality of external electrodes 40. The stress suppression film 50 is formed from an insulating material and extends along a first main surface TS1 and two end surfaces LS1, LS2 or along the first main surface TS1 and two side surfaces to cover the multilayer body 10 and the plurality of external electrodes 40. The ends of the stress suppression film 50 protrude with respect to the outermost surfaces of the plurality of external electrodes 40 on the second main surface TS2 side.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors are known that include a laminate formed by stacking a plurality of dielectric layers and a plurality of internal electrode layers made of ceramic material, and external electrodes disposed on end faces or side faces of the laminate. There is a demand for further miniaturization and thinning of such multilayer ceramic capacitors (see, for example, Patent Document 1).

[0003] JP 2013-42110 A

[0004] When multilayer ceramic capacitors are made thinner, the strength of the laminate, especially the ceramic layers, decreases, and stress from the mounter during mounting can damage the multilayer ceramic capacitor. For example, cracks can occur in the ceramic layers of the laminate. If cracks in the ceramic layers propagate to the internal electrode layers, moisture can penetrate the cracks, reducing the insulation of the multilayer ceramic capacitor.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor that can suppress a decrease in strength against external stress even when the capacitor is made thinner.

[0006] The multilayer ceramic capacitor according to the present invention comprises a laminate including a plurality of dielectric layers and a plurality of internal electrode layers, the laminate having first and second main surfaces facing each other in the stacking direction, two side surfaces facing each other in a width direction intersecting the stacking direction, and two end surfaces facing each other in a length direction intersecting the stacking direction and the width direction, a plurality of external electrodes disposed on at least the second main surface of the laminate, and a stress suppression film for suppressing stress acting on the laminate and the plurality of external electrodes. The stress suppression film is made of an insulating material and extends along the first main surface and the two end surfaces or along the first main surface and the two side surfaces so as to cover the laminate and the plurality of external electrodes. Ends of the stress suppression film protrude from the second main surface beyond the outermost surfaces of the plurality of external electrodes.

[0007] According to the present invention, even when a multilayer ceramic capacitor is made thinner, it is possible to suppress a decrease in strength against external stress.

[0008] 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 2 is a cross-sectional view (LT cross-section) taken along line II-II of the multilayer ceramic capacitor shown in FIG. 1; FIG. 3 is a cross-sectional view (WT cross-section) taken along line III-III of the multilayer ceramic capacitor shown in FIG. 1; FIG. 4 is a cross-sectional view (LT cross-section) taken along line VV of the multilayer ceramic capacitor shown in FIG. 4; FIG. 5 is a cross-sectional view (WT cross-section) taken along line VI-VI of the multilayer ceramic capacitor shown in FIG. 4; FIG. 6 is a cross-sectional view (LT cross-section) taken along line VIII-VIII of the multilayer ceramic capacitor shown in FIG. 7; FIG. 7 is a cross-sectional view (WT cross-section) taken along line IX-IX of the multilayer ceramic capacitor shown in FIG. 7; FIG. 8 is a cross-sectional view (WT cross-section) taken along line IX-IX of the multilayer ceramic capacitor shown in FIG. 8; FIG. 9 is a perspective view showing a multilayer ceramic capacitor according to a modification of the present embodiment; FIG. 10 is a cross-sectional view (LT cross-section) taken along line VIII of the multilayer ceramic capacitor shown in FIG. 1;

[0009] An example of an embodiment of the present invention will be described below with reference to the accompanying drawings, in which the same or equivalent parts are designated by the same reference numerals.

[0010] <Multilayer Ceramic Capacitor> Fig. 1 is a perspective view showing a multilayer ceramic capacitor according to this embodiment, Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line II-II, and Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line III-III. The multilayer ceramic capacitor 1 shown in Figs. 1 to 3 includes a laminate 10, external electrodes 40, and a stress suppression film 50. The external electrodes 40 include a first external electrode 41 and a second external electrode 42.

[0011] 1 to 3 and the drawings described below show an XYZ Cartesian coordinate system. The X direction is the length direction L of the multilayer ceramic capacitor 1 and the laminate 10, the Y direction is the width direction W of the multilayer ceramic capacitor 1 and the laminate 10, and the Z direction is the lamination direction T of the multilayer ceramic capacitor 1 and the laminate 10. Therefore, the cross section shown in FIG. 2 is also referred to as an LT cross section, and the cross section shown in FIG. 3 is also referred to as a WT cross section.

[0012] The length direction L, width direction W, and stacking direction T do not necessarily have to be perpendicular to each other, and may intersect each other.

[0013] The laminate 10 has an approximately rectangular parallelepiped shape and has a first main surface TS1 and a second main surface TS2 facing in the stacking direction T, a first side surface WS1 and a second side surface WS2 facing in the width direction W, and a first end surface LS1 and a second end surface LS2 facing in the length direction L.

[0014] It is preferable that the corners and ridges of the laminate 10 are rounded. A corner is a portion where three surfaces of the laminate 10 intersect, and a ridge is a portion where two surfaces of the laminate 10 intersect.

[0015] 2 and 3 , the laminate 10 has a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 stacked in a stacking direction T. The laminate 10 also has, in the stacking direction T, an inner layer portion 100, and a first outer layer portion 101 and a second outer layer portion 102 arranged to sandwich the inner layer portion 100.

[0016] The internal layer portion 100 includes some of the dielectric layers 20 and a plurality of internal electrode layers 30. In the internal layer portion 100, the plurality of internal electrode layers 30 are arranged opposite each other with the dielectric layers 20 interposed therebetween. The internal layer portion 100 is a portion that generates capacitance and essentially functions as a capacitor.

[0017] The first outer layer portion 101 is disposed on the first main surface TS1 side of the laminate 10, and the second outer layer portion 102 is disposed on the second main surface TS2 side of the laminate 10. More specifically, the first outer layer portion 101 is disposed between the first main surface TS1 and an internal electrode layer 30 of the plurality of internal electrode layers 30 that is closest to the first main surface TS1, and the second outer layer portion 102 is disposed between the second main surface TS2 and an internal electrode layer 30 of the plurality of internal electrode layers 30 that is closest to the second main surface TS2. The first outer layer portion 101 and the second outer layer portion 102 do not include the internal electrode layer 30, but each include a portion of the plurality of dielectric layers 20 other than the portion for the internal layer portion 100. The first outer layer portion 101 and the second outer layer portion 102 function as protective layers for the internal layer portion 100.

[0018] The material of the dielectric layer 20 is, for example, BaTiO ３ , CaTiO ３ , SrTiO ３ , or CaZrO ３ A dielectric ceramic containing, as a main component, a material such as a manganese compound, an iron compound, a chromium compound, a cobalt compound, or a nickel compound may be used. The material of the dielectric layer 20 may also contain, as a secondary component, a manganese compound, an iron compound, a chromium compound, a cobalt compound, or a nickel compound. More specifically, the dielectric layer 20 includes a plurality of dielectric grains. The dielectric grains are barium titanate-based ceramics such as perovskite-type compounds containing barium and titanium. The dielectric grains may also include, as a secondary component, at least one of La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and Y.

[0019] The thickness of the dielectric layers 20 is not particularly limited, but may be, for example, 0.30 μm or more and 5.0 μm or less. The number of dielectric layers 20 is not particularly limited, but may be, for example, 5 to 2000. Note that the number of dielectric layers 20 is the total number of the dielectric layers in the inner layer portion and the dielectric layers in the outer layer portion.

[0020] 2 and 3 , the multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are alternately arranged in the stacking direction T of the laminate 10.

[0021] The first internal electrode layer 31 includes a counter electrode portion 311 and a lead electrode portion 312 , and the second internal electrode layer 32 includes a counter electrode portion 321 and a lead electrode portion 322 .

[0022] The opposing electrode portions 311 and 321 face each other via the dielectric layer 20 in the stacking direction T of the laminate 10. The shapes of the opposing electrode portions 311 and 321 are not particularly limited and may be, for example, approximately rectangular. The opposing electrode portions 311 and 321 are portions (effective regions) that generate electrostatic capacitance and essentially function as capacitors.

[0023] The extraction electrode portion 312 extends from the counter electrode portion 311 toward the first end surface LS1 of the laminate 10 and is exposed at the first end surface LS1. The extraction electrode portion 322 extends from the counter electrode portion 321 toward the second end surface LS2 of the laminate 10 and is exposed at the second end surface LS2. The shapes of the extraction electrode portion 312 and the extraction electrode portion 322 are not particularly limited and may be, for example, approximately rectangular.

[0024] As a result, the first internal electrode layer 31 is connected to the first external electrode 41, and a gap exists between the first internal electrode layer 31 and the second end surface LS2 of the laminate 10, i.e., the second external electrode 42. In addition, the second internal electrode layer 32 is connected to the second external electrode 42, and a gap exists between the second internal electrode layer 32 and the first end surface LS1 of the laminate 10, i.e., the first external electrode 41.

[0025] The first internal electrode layer 31 and the second internal electrode layer 32 contain metal Ni as a main component. The first internal electrode layer 31 and the second internal electrode layer 32 may contain, as a main component, or as a component other than the main component, at least one selected from metals such as Cu, Ag, Pd, or Au, or alloys containing at least one of these metals, such as an Ag-Pd alloy. Furthermore, the first internal electrode layer 31 and the second internal electrode layer 32 may contain, as a component other than the main component, particles of a dielectric material having the same composition as the ceramic contained in the dielectric layer 20. In this specification, the metal of the main component is defined as the metal component with the highest weight percentage.

[0026] The thicknesses of the first internal electrode layers 31 and the second internal electrode layers 32 are not particularly limited, but may be, for example, 0.30 μm or more and 1.0 μm or less. The number of the first internal electrode layers 31 and the second internal electrode layers 32 is not particularly limited, but may be, for example, 5 to 2000.

[0027] As shown in Fig. 3, the laminate 10 has, in the width direction W, an electrode facing portion W30 where the internal electrode layers 30 face each other, and a first side gap WG1 and a second side gap WG2 arranged to sandwich the electrode facing portion W30. The first side gap WG1 is located between the electrode facing portion W30 and the first side surface WS1, and the second side gap WG2 is located between the electrode facing portion W30 and the second side surface WS2. More specifically, the first side gap WG1 is located between the end of the internal electrode layer 30 on the first side surface WS1 side and the first side surface WS1, and the second side gap WG2 is located between the end of the internal electrode layer 30 on the second side surface WS2 side and the second side surface WS2. The first side gap WG1 and the second side gap WG2 do not include the internal electrode layer 30, but only include the dielectric layer 20. The first side gap WG1 and the second side gap WG2 are portions that function as protective layers for the internal electrode layers 30. The first side gap WG1 and the second side gap WG2 are also called W gaps.

[0028] 2 , the laminate 10 has, in the longitudinal direction L, an electrode facing portion L30 where the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layer 30 face each other, a first end gap LG1, and a second end gap LG2. The first end gap LG1 is located between the electrode facing portion L30 and the first end face LS1, and the second end gap LG2 is located between the electrode facing portion L30 and the second end face LS2. More specifically, the first end gap LG1 is located between the end of the second internal electrode layer 32 on the first end face LS1 side and the first end face LS1, and the second end gap LG2 is located between the end of the first internal electrode layer 31 on the second end face LS2 side and the second end face LS2. The first end gap LG1 does not include the second internal electrode layer 32 but includes the first internal electrode layer 31 and the dielectric layer 20, and the second end gap LG2 does not include the first internal electrode layer 31 but includes the second internal electrode layer 32 and the dielectric layer 20. The first end gap LG1 is a portion that functions as a lead electrode portion to the first end surface LS1 of the first internal electrode layer 31, and the second end gap LG2 is a portion that functions as a lead electrode portion to the second end surface LS2 of the second internal electrode layer 32. The first end gap LG1 and the second end gap LG2 are also referred to as L gaps.

[0029] The electrode opposing portion L30 is located with the opposing electrode portion 311 of the first internal electrode layer 31 and the opposing electrode portion 321 of the second internal electrode layer 32. The first end gap portion LG1 is located with the lead-out electrode portion 312 of the first internal electrode layer 31, and the second end gap portion LG2 is located with the lead-out electrode portion 322 of the second internal electrode layer 32.

[0030] The dimensions of the laminate 10 described above are not particularly limited, but may be, for example, a length in the length direction L of 0.05 mm to 1.00 mm, a width in the width direction W of 0.10 mm to 0.50 mm, and a thickness in the stacking direction T of 0.10 mm to 0.50 mm. The dimensions of the multilayer ceramic capacitor 1 including external electrodes 40 described later are not particularly limited, but may be, for example, a length in the length direction L of 0.05 mm to 1.00 mm, a width in the width direction W of 0.10 mm to 0.50 mm, and a thickness in the stacking direction T of 0.10 mm to 0.50 mm.

[0031] The thicknesses of the dielectric layers 20 and the internal electrode layers 30 may be measured by, for example, observing the LT cross section of the laminate exposed by polishing near the center in the width direction with a scanning electron microscope. Each value may be an average value of measurements taken at multiple locations in the length direction, or may be an average value of measurements taken at multiple locations in the stacking direction.

[0032] Similarly, the thickness of the laminate 10 or the thickness of the multilayer ceramic capacitor 1 can be measured, for example, by observing an LT cross section near the center in the width direction of the laminate exposed by polishing, or a WT cross section near the center in the length direction of the laminate or multilayer ceramic capacitor exposed by polishing, using a scanning electron microscope. Each value may also be an average of measurements taken at multiple locations in the length or width direction. Similarly, the length of the laminate 10 or the length of the multilayer ceramic capacitor 1 can be measured, for example, by observing an LT cross section near the center in the width direction of the laminate or multilayer ceramic capacitor exposed by polishing, using a scanning electron microscope. Each value may also be an average of measurements taken at multiple locations in the stacking direction. Similarly, the width of the laminate 10 or the width of the multilayer ceramic capacitor 1 can be measured, for example, by observing a WT cross section near the center in the length direction of the laminate or multilayer ceramic capacitor exposed by polishing, using a scanning electron microscope. Each value may also be an average of measurements taken at multiple locations in the stacking direction.

[0033] The external electrodes 40 include a first external electrode 41 and a second external electrode 42 .

[0034] The first external electrode 41 is disposed on at least the second main surface TS2 of the laminate 10, specifically, a portion of the second main surface TS2 on the first end face LS1 side. In the example of FIGS. 1 to 3, the first external electrode 41 is also disposed on the first end face LS1 of the laminate 10, and is connected to the first internal electrode layer 31. That is, the first external electrode 41 is L-shaped in the LT cross section, and is disposed along a portion of the second main surface TS2 of the laminate 10 on the first end face LS1 side and the first end face LS1. Note that in the example of FIGS. 1 to 3, the first external electrode 41 is not disposed on the first main surface TS1 or the two side faces WS1, WS2.

[0035] The second external electrode 42 is disposed on at least the second main surface TS2 of the laminate 10, specifically, a portion of the second main surface TS2 on the second end face LS2 side. In the example of FIGS. 1 to 3, the second external electrode 42 is also disposed on the second end face LS2 of the laminate 10, and is connected to the second internal electrode layer 32. That is, the second external electrode 42 is L-shaped, and is disposed along a portion of the second main surface TS2 of the laminate 10 on the second end face LS2 side and the second end face LS2. Note that in the example of FIGS. 1 to 3, the second external electrode 42 is not disposed on the first main surface TS1 or the two side faces WS1, WS2.

[0036] The first external electrode 41 has a first base electrode layer 415 and a first plating layer 416, and the second external electrode 42 has a second base electrode layer 425 and a second plating layer 426. The first external electrode 41 may be composed of only the first plating layer 416, and the second external electrode 42 may be composed of only the second plating layer 426.

[0037] The first base electrode layer 415 and the second base electrode layer 425 may be fired layers containing a metal and glass. The glass may be a glass component containing at least one selected from B, Si, Ba, Mg, Al, Li, etc. A specific example is borosilicate glass. The metal may contain Cu as a main component. The metal may contain at least one selected from metals such as Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys, as a main component or as a component other than the main component.

[0038] The fired layer is a layer formed by applying a conductive paste containing metal and glass to the laminate by a dipping method and firing the layer. The fired layer may be fired after firing the internal electrode layer or simultaneously with firing the internal electrode layer. The fired layer may also be a multi-layer structure.

[0039] Alternatively, the first base electrode layer 415 and the second base electrode layer 425 may be resin layers containing conductive particles and a thermosetting resin. The resin layers may be formed on the fired layer described above, or may be formed directly on the laminate without forming a fired layer.

[0040] The resin layer is a layer formed by applying a conductive paste containing conductive particles and a thermosetting resin to the laminate by a coating method and then firing the layer. The resin layer may be fired after firing the internal electrode layer or simultaneously with firing the internal electrode layer. The resin layer may also be a multi-layered layer.

[0041] The thickness of each of the first base electrode layer 415 and the second base electrode layer 425 as a fired layer or a resin layer is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0042] Alternatively, the first base electrode layer 415 and the second base electrode layer 425 may be thin film layers of 1 μm or less formed by a thin film forming method such as sputtering or vapor deposition, on which metal particles are deposited.

[0043] First plating layer 416 covers at least a portion of first base electrode layer 415, and second plating layer 426 covers at least a portion of second base electrode layer 425. First plating layer 416 and second plating layer 426 include, for example, at least one selected from metals such as Cu, Ni, Ag, Pd, and Au, and alloys such as Ag—Pd alloys.

[0044] Each of the first plating layer 416 and the second plating layer 426 may be formed of multiple layers. Preferably, they have a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the base electrode layer from being eroded by solder when mounting the ceramic electronic component, and the Sn plating layer improves the wettability of the solder when mounting the ceramic electronic component, facilitating mounting.

[0045] The thickness of each of first plating layer 416 and second plating layer 426 is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0046] <<Stress suppression film>> The stress suppression film 50 suppresses stress acting on the laminate 10 and the external electrodes 40. The stress suppression film 50 extends along the first main surface (top surface) TS1 and the two end surfaces LS1, LS2 so as to cover the laminate 10 and the external electrodes 40, and also extends along the first main surface TS1 and the two side surfaces WS1, WS2.

[0047] The end of the stress suppression film 50 protrudes by a distance D1 from the outermost surface (the surface located closest to the bottom) of the external electrode 40 on the second main surface (bottom surface, mounting surface) TS2 side. The protrusion dimension D1 of the end of the stress suppression film 50 may be 5 μm or more and 10 μm or less. When D1 is 5 μm or more, a stress suppression effect is obtained, and when D1 is 10 μm or less, connectivity between the external electrode 40 and the paste solder is obtained.

[0048] In the stress suppression film 50, the film thickness Da of the main surface portion (first portion) along the first main surface TS1 and the film thickness Db of the side surface portion (second portion) along the two end faces LS1, LS2 and the two side faces WS1, WS2 satisfy the following relational expression: 0.8Da≧Db The film thickness Da of the main surface portion (first portion) may be 4.5 μm or more and 5.5 μm or less.

[0049] If the film thickness Da of the main surface portion (first portion) is relatively thick, the main surface portion of the stress suppression film 50 that is along the first main surface TS1 can withstand the suction force applied to the first main surface TS1, which is the upper surface, during suction by a mounter, thereby suppressing the suction force applied to the laminate 10. On the other hand, if the film thickness Db of the side surface portion (second portion) is relatively thin, the solder pads on the mounting board can be made smaller, enabling high-density mounting.

[0050] The stress suppression film 50 is made of an insulating material, which can prevent short circuits of the external electrodes 40 .

[0051] The strength of the stress suppression film 50 is preferably higher than the strength of the plurality of dielectric layers 20 of the laminate 10. Specifically, in terms of strength against stress during mounting using a mounter, the strength of the stress suppression film 50 is preferably higher than the strength of the plurality of dielectric layers 20 of the laminate 10. For example, the Young's modulus of the stress suppression film 50 is preferably 400 GPa or more and 1500 GPa or less.

[0052] From the viewpoint of insulation and strength, diamond-like carbon, glass, etc., can be used as the material for the stress suppression film 50. Among these, diamond-like carbon is preferable as the material for the stress suppression film 50.

[0053] <Manufacturing Method> Next, a method for manufacturing the above-mentioned multilayer ceramic capacitor 1 will be described. First, a dielectric sheet for the dielectric layers 20 and a conductive paste for the internal electrode layers 30 are prepared. The dielectric sheet and the conductive paste contain a binder and a solvent. Known materials can be used as the binder and the solvent.

[0054] Next, a conductive paste is printed on the dielectric sheet in a predetermined pattern, for example, to form an internal electrode pattern on the dielectric sheet. The internal electrode pattern can be formed by screen printing, gravure printing, or the like.

[0055] Next, a predetermined number of dielectric sheets for the second outer layer portion 102, on which no internal electrode pattern is printed, are stacked. On top of these, dielectric sheets for the inner layer portion 100, on which internal electrode patterns are printed, are stacked in sequence. On top of these, a predetermined number of dielectric sheets for the first outer layer portion 101, on which no internal electrode pattern is printed, are stacked. In this way, a laminated sheet is produced.

[0056] Next, the laminated sheet is pressed in the lamination direction using a means such as a hydrostatic press to produce a laminated block. Next, the laminated block is cut to a predetermined size to cut out laminated chips. At this time, dielectric sheets for the first side margin portion W11 and the second side margin portion W12 may be attached to the side surfaces of the laminated chip. Also, at this time, the corners and ridges of the laminated chip are rounded by barrel polishing or the like. Next, the laminated chip is fired to produce the laminate 10. The firing temperature depends on the materials of the dielectric and internal electrodes, but is preferably 900°C or higher and 1400°C or lower.

[0057] Next, a conductive paste, which is an electrode material for the base electrode layer (for the first base electrode layer 415), is applied to the second main surface TS2 and the first end surface LS1 of the laminate 10 using a coating method. Similarly, a conductive paste, which is an electrode material for the base electrode layer (for the second base electrode layer 425), is applied to the second main surface TS2 and the second end surface LS2 of the laminate 10 using a coating method. Thereafter, these conductive pastes are fired to form the first base electrode layer 415 and the second base electrode layer 425, which are fired layers. The firing temperature is preferably 600°C or higher and 900°C or lower.

[0058] The first base electrode layer 415 and the second base electrode layer 425, which are thin films, may be formed by a thin film formation method such as sputtering or vapor deposition.

[0059] In the above description, the base electrode layer is formed and fired after firing the laminated chip, i.e., the laminate and the external electrodes are fired separately. However, the base electrode layer may be formed and fired before firing the laminated chip, i.e., the laminate and the external electrodes may be fired simultaneously.

[0060] Then, a first plating layer 416 is formed on the surface of the first base electrode layer 415 to form the first external electrode 41, and a second plating layer 426 is formed on the surface of the second base electrode layer 425 to form the second external electrode 42.

[0061] Next, the stress suppression film 50 is formed to cover the laminate 10 and the external electrodes 40. Examples of methods for forming the stress suppression film 50 include a PVD (Physical Vapor Deposition) method such as sputtering, and a vapor deposition method. The protrusion dimension D1 of the stress suppression film 50 can be adjusted by adjusting the height of the mounting jig. The shapes of the protrusions in FIG. 1 and in FIGS. 4, 7, and 10 to 12, which will be described later, may be modified by the mounting jig. The above-described multilayer ceramic capacitor 1 is obtained through the above steps.

[0062] In a conventional multilayer ceramic capacitor that does not include a stress suppression film 50, when the multilayer ceramic capacitor is thinned, the strength of the laminate 10, particularly the ceramic layers (dielectric layers 20), decreases, and stress from a mounter during mounting can damage the multilayer ceramic capacitor. For example, during mounting using a mounter, stress is applied to the first main surface TS1, which is the top surface of the multilayer ceramic capacitor, which in turn applies stress to the external electrodes 40 on the second main surface TS2, which is the bottom surface (mounting surface) of the multilayer ceramic capacitor, potentially damaging the multilayer ceramic capacitor. For example, cracks can occur in the ceramic layers (dielectric layers 20) of the laminate 10. If a crack in the ceramic layer (dielectric layer 20) progresses to the internal electrode layer 30, moisture can penetrate the crack, reducing the insulation of the multilayer ceramic capacitor.

[0063] In this regard, in the multilayer ceramic capacitor 1 of this embodiment, the stress suppression film 50 extends along the first main surface (top surface) TS1 and the two end surfaces LS1, LS2 so as to cover the laminate 10 and the external electrodes 40, and also extends along the first main surface (top surface) TS1 and the two side surfaces WS1, WS2, and the ends of the stress suppression film 50 protrude by a distance D1 from the outermost surfaces (the surfaces located closest to the bottom) of the external electrodes 40 on the second main surface (bottom surface, mounting surface) TS2 side. This allows stress acting on the first main surface TS1, which is the top surface, during mounting using a mounter to be dispersed from the main surface portion of the stress suppression film 50 along the first main surface TS1 to the end surface portions along the two end surfaces LS1, LS2 and the side surface portions along the two side surfaces WS1, WS2, and to be released to the protruding ends. This makes it possible to suppress stress acting on the external electrodes 40 on the second main surface TS2, which is the bottom surface (mounting surface), and on the laminate 10, thereby suppressing the occurrence of cracks in the ceramic layers (dielectric layers 20) of the laminate 10. In this way, according to the multilayer ceramic capacitor 1 of this embodiment, even when a thinner capacitor is employed, it is possible to suppress a decrease in strength against external stress.

[0064] Furthermore, with the multilayer ceramic capacitor 1 of this embodiment, when the mounter is used to attach the capacitor, the suction force applied to the first main surface TS1, which is the upper surface, can also be received by the main surface portion of the stress suppression film 50 that is aligned with the first main surface TS1. This makes it possible to suppress the suction force applied to the laminate 10.

[0065] Furthermore, in the multilayer ceramic capacitor 1 of this embodiment, the stress suppression film 50 covers the external electrodes 40 on the end faces LS1, LS2 or the side faces WS1, WS2, thereby preventing the solder paste from swelling up on the end faces LS1, LS2 or the side faces WS1, WS2. This allows the solder pads on the mounting board to be smaller, enabling higher-density mounting.

[0066] Furthermore, according to the multilayer ceramic capacitor 1 of this embodiment, since the external electrode 40 is not formed on the first main surface TS1 side, it is possible to increase the number of laminations in the laminate 10 and thereby increase the effective capacitor area. Furthermore, since the external electrode 40 is not formed on the two side surfaces WS1 and WS2 sides, it is possible to increase the area of ​​the laminate 10 and thereby increase the effective capacitor area.

[0067] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various modifications and variations are possible. For example, the above-described embodiments illustrate a configuration in which the stress suppression film 50 extends along five surfaces: the first main surface (top surface) TS1, the two end surfaces LS1 and LS2, and the two side surfaces WS1 and WS2. However, the present invention is not limited to this configuration, and the stress suppression film 50 may extend along only three surfaces: the first main surface (top surface) TS1 and the two end surfaces LS1 and LS2. Alternatively, the stress suppression film 50 may extend along only three surfaces: the first main surface (top surface) TS1 and the two side surfaces WS1 and WS2.

[0068] In the above-described embodiment, the two external electrodes 40 are arranged on a portion of the second main surface TS2 of the laminate 10 on the two end faces LS1, LS2 side and on the two end faces LS1, LS2. However, in the present invention, the shape, number, and arrangement position of the external electrodes 40 are not limited to this. For example, the present invention is also applicable to an embodiment in which a plurality of external electrodes 40 are arranged on at least a portion of the second main surface TS2 of the laminate 10. The present invention is also applicable to an embodiment in which a plurality of external electrodes 40 are arranged on at least a portion of the second main surface TS2 on the two side faces WS1, WS2 side. Below, several examples of the shape, number, and arrangement position of the external electrodes 40 are shown.

[0069] (Modification 1) Fig. 4 is a perspective view showing a multilayer ceramic capacitor according to a modification of the present embodiment, Fig. 5 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 4 taken along line VV, and Fig. 6 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 4 taken along line VI-VI. The multilayer ceramic capacitor 1 shown in Figs. 4 to 6 differs from the multilayer ceramic capacitor 1 shown in Figs. 1 to 3 in the shape of the external electrodes 40.

[0070] The first external electrode 41 is arranged only on the second main surface (bottom surface, mounting surface) TS2 of the laminate 10, specifically only on a portion of the second main surface TS2 on the first end face LS1 side. That is, the first external electrode 41 is not arranged on the first end face LS1, the first main surface (top surface) TS1, the first side face WS1, or the second side face WS2. In this case, for example, the first external electrode 41 and the first internal electrode layer 31 may be connected by one or more vias 35 extending in the stacking direction T on the first end face LS1 side of the laminate 10.

[0071] The second external electrode 42 is arranged only on the second main surface (bottom surface, mounting surface) TS2 of the laminate 10, specifically, only on a portion of the second main surface TS2 on the second end surface LS2 side. That is, the second external electrode 42 is not arranged on the second end surface LS2, the first main surface (top surface) TS1, the first side surface WS1, or the second side surface WS2. In this case, for example, the second external electrode 42 and the second internal electrode layer 32 may be connected by one or more vias 35 extending in the stacking direction T on the second end surface LS2 side of the laminate 10.

[0072] The method for forming the vias 35 is not limited, but for example, after producing the above-mentioned stacked block and before cutting out the stacked chips, multiple holes lined up in the width direction near the ends of the stacked chips can be formed, and the formed holes can be filled with conductive paste.

[0073] (Modification 2) Fig. 7 is a perspective view showing a multilayer ceramic capacitor according to a modification of the present embodiment, Fig. 8 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 7 taken along line VIII-VIII, and Fig. 9 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 7 taken along line IX-IX. The multilayer ceramic capacitor 1 shown in Figs. 7 to 9 differs from the multilayer ceramic capacitor 1 shown in Figs. 1 to 3 in the shape of the external electrodes 40.

[0074] The first external electrode 41 is arranged on a portion of the second main surface (bottom surface, mounting surface) TS2 of the laminate 10 on the first end face LS1 side and on the first end face LS1, and is connected to the first internal electrode layer 31. In the examples of FIGS. 7 to 9 , the first external electrode 41 is also arranged on a portion of the first main surface (top surface) TS1 of the laminate 10 on the first end face LS1 side, on a portion of the first side surface WS1 of the laminate 10 on the first end face LS1 side, and on a portion of the second side surface WS2 of the laminate 10 on the first end face LS1 side. That is, the first external electrode 41 has an angular U-shape in the LT cross section, and is arranged along a portion of the second main surface TS2 of the laminate 10 on the first end face LS1 side, the first end face LS1, and a portion of the first main surface TS1 on the first end face LS1 side. In addition, the first external electrode 41 has a U-shape (Angular U-shape) in the LW cross section, and is arranged along a portion of the first side surface WS1 of the laminate 10 on the first end face LS1 side, the first end face LS1, and a portion of the second side surface WS2 on the first end face LS1 side.

[0075] The second external electrode 42 is arranged on a portion of the second end face LS2 side of the second main surface (bottom surface, mounting surface) TS2 of the laminate 10 and on the second end face LS2, and is connected to the second internal electrode layer 32. In the examples of FIGS. 7 to 9 , the second external electrode 42 is also arranged on a portion of the first main surface (top surface) TS1 of the laminate 10 on the second end face LS2 side, on a portion of the first side surface WS1 of the laminate 10 on the second end face LS2 side, and on a portion of the second side surface WS2 of the laminate 10 on the second end face LS2 side. That is, the second external electrode 42 has an angular U-shape in the LT cross section, and is arranged along a portion of the second end face LS2 side of the second main surface TS2 of the laminate 10, the second end face LS2, and a portion of the first main surface TS1 on the second end face LS2 side. In addition, the second external electrode 42 has a U-shape (Angular U-shape) in the LW cross section, and is arranged along a portion of the first side surface WS1 of the laminate 10 on the second end face LS2 side, the second end face LS2, and a portion of the second side surface WS2 on the second end face LS2 side.

[0076] In this case, flat spacer members 55 may be disposed on each of the first main surface TS1 and the second main surface TS2 in portions where the plurality of external electrodes 40 are not disposed. In this case, the stress suppression film 50 may extend on the first main surface TS1 so as to further cover the spacer members 55. This reduces the step between the portions where the external electrodes 40 are disposed and the portions where the external electrodes 40 are not disposed on the first main surface TS1, which serves as the upper surface, and improves the suction performance of the mounter. Note that, because there is no distinction between the upper and lower surfaces before the stress suppression film 50 is formed, it is preferable that the spacer members 55 be disposed on both the first main surface TS1 and the second main surface TS2.

[0077] 10 is a perspective view showing a multilayer ceramic capacitor according to a modification of the present embodiment. The multilayer ceramic capacitor 1 shown in Fig. 10 has a different number of external electrodes 40 from the multilayer ceramic capacitor 1 shown in Figs. 7 to 9.

[0078] 7 to 9, the external electrodes 40 include a third external electrode 43 and a fourth external electrode 44 in addition to a first external electrode 41 and a second external electrode 42. In this way, the multilayer ceramic capacitor 1 includes the third external electrode 43 and the fourth external electrode 44, which are third electrodes, in addition to the first external electrode 41 and the second external electrode 42, and is therefore called a three-terminal multilayer ceramic capacitor. The features of the present invention can also be applied to such a three-terminal multilayer ceramic capacitor.

[0079] The third external electrode 43 is disposed between the first external electrode 41 and the second external electrode 42 on a portion of the second main surface (bottom surface, mounting surface) TS2 of the laminate 10 on the first side surface WS1 and on the first side surface WS1. In the example of Fig. 10, the third external electrode 43 is also disposed on a portion of the first main surface (top surface) TS1 of the laminate 10 on the first side surface WS1 side. That is, the third external electrode 43 has an angular U-shape in the WT cross section, and is disposed along a portion of the second main surface TS2 of the laminate 10 on the first side surface WS1 side, the first side surface WS1, and a portion of the first main surface TS1 on the first side surface WS1 side.

[0080] The fourth external electrode 44 is disposed between the first external electrode 41 and the second external electrode 42 on a portion of the second side surface WS2 of the second main surface (bottom surface, mounting surface) TS2 of the laminate 10 and on the second side surface WS2. In the example of Fig. 10, the fourth external electrode 44 is also disposed on a portion of the second side surface WS2 of the first main surface (top surface) TS1 of the laminate 10. That is, the fourth external electrode 44 has an angular U-shape in the WT cross section, and is disposed along a portion of the second main surface TS2 of the laminate 10 on the second side surface WS2 side, the second side surface WS2, and a portion of the first main surface TS1 on the second side surface WS2 side.

[0081] 7 to 9, the multilayer ceramic capacitor 1 shown in Fig. 10 may also have flat spacer members 55 arranged on each of the first main surface TS1 and the second main surface TS2 in areas where the plurality of external electrodes 40 are not arranged. In this case, the stress suppression film 50 may extend on the first main surface TS1 so as to further cover the spacer members 55.

[0082] 10 illustrates an example of an external electrode 40 having a U-shaped cross section (Angular U-shape). However, the features of the present invention are not limited to this. The multilayer ceramic capacitor 1 illustrated in FIG. 10 can also be applied to a multilayer ceramic capacitor 1 having an external electrode 40 having an L-shaped cross section, similar to the multilayer ceramic capacitors 1 illustrated in FIGS. 1 to 3. In this case, the third external electrode 43 is L-shaped in the WT cross section and is arranged along a portion of the second main surface TS2 of the multilayer body 10 on the side of the first side surface WS1 and the first side surface WS1. The fourth external electrode 44 is L-shaped in the WT cross section and is arranged along a portion of the second main surface TS2 of the multilayer body 10 on the side of the second side surface WS2 and the second side surface WS2.

[0083] Furthermore, the features of the present invention can also be applied to the multilayer ceramic capacitor 1 shown in FIG. 10 in a form in which the external electrodes 40 are provided only on the second main surface TS2, similar to the multilayer ceramic capacitor 1 shown in FIGS. 4 to 6 .

[0084] 11 is a perspective view showing a multilayer ceramic capacitor according to a modification of the present embodiment. The multilayer ceramic capacitor 1 shown in Fig. 11 differs from the multilayer ceramic capacitor 1 shown in Figs. 7 to 9 in the number and arrangement positions of the external electrodes 40.

[0085] For example, the external electrodes 40 include a first external electrode 41, a second external electrode 42, a third external electrode 43, and a fourth external electrode 44 at four corners of the laminate 10 when viewed from the second main surface TS2 side. Such a multilayer ceramic capacitor 1 may include, for example, two multilayer ceramic capacitor elements between the first external electrode 41 and the second external electrode 42, and between the third external electrode 43 and the fourth external electrode 44. The features of the present invention are also applicable to such a multi-terminal multilayer ceramic capacitor.

[0086] The first external electrodes 41 are arranged on corners of the second main surface (bottom surface, mounting surface) TS2 of the laminate 10 on the first end face LS1 side and the first side face WS1 side, and on parts of the first end face LS1 and the first side face WS1. In the example of Fig. 11, the first external electrodes 41 are also arranged on corners of the first main surface (top surface) TS1 of the laminate 10 on the first end face LS1 side and the first side face WS1 side. That is, the first external electrodes 41 have an angular U-shape in the LT cross section, and are arranged along parts of the second main surface TS2 of the laminate 10 on the first end face LS1 side, the first end face LS1, and parts of the first main surface TS1 on the first end face LS1 side. In addition, the first external electrode 41 has a U-shape (Angular U-shape) in the WT cross section, and is arranged along a portion of the second main surface TS2 of the laminate 10 on the first side surface WS1 side, the first side surface WS1, and a portion of the first main surface TS1 on the first side surface WS1 side.

[0087] The second external electrodes 42 are arranged on corners of the second main surface (bottom surface, mounting surface) TS2 of the laminate 10 on the second end face LS2 side and the first side face WS1 side, and on parts of the second end face LS2 and the first side face WS1. In the example of Fig. 11, the second external electrodes 42 are also arranged on corners of the first main surface (top surface) TS1 of the laminate 10 on the second end face LS2 side and the first side face WS1 side. That is, the second external electrodes 42 have an angular U-shape in the LT cross section, and are arranged along parts of the second main surface TS2 of the laminate 10 on the second end face LS2 side, the second end face LS2, and parts of the first main surface TS1 on the second end face LS2 side. In addition, the second external electrode 42 has a U-shape (Angular U-shape) in the WT cross section, and is arranged along a portion of the second main surface TS2 of the laminate 10 on the first side surface WS1 side, the first side surface WS1, and a portion of the first main surface TS1 on the first side surface WS1 side.

[0088] The third external electrode 43 is arranged on corners of the second main surface (bottom surface, mounting surface) TS2 of the laminate 10 on the first end face LS1 side and the second side face WS2 side, and on parts of the first end face LS1 and the second side face WS2. In the example of Fig. 11, the third external electrode 43 is also arranged on corners of the first main surface (top surface) TS1 of the laminate 10 on the first end face LS1 side and the second side face WS2 side. That is, the third external electrode 43 has an angular U-shape in the LT cross section, and is arranged along parts of the second main surface TS2 of the laminate 10 on the first end face LS1 side, the first end face LS1, and parts of the first main surface TS1 on the first end face LS1 side. In addition, the third external electrode 43 has a U-shape (Angular U-shape) in the WT cross section, and is arranged along a portion of the second side surface WS2 side of the second main surface TS2 of the laminate 10, the second side surface WS2, and a portion of the first main surface TS1 on the second side surface WS2 side.

[0089] The fourth external electrode 44 is arranged on corners of the second main surface (bottom surface, mounting surface) TS2 of the laminate 10 on the second end face LS2 side and the second side face WS2 side, and on parts of the second end face LS2 and the second side face WS2. In the example of Fig. 11 , the fourth external electrode 44 is also arranged on corners of the first main surface (top surface) TS1 of the laminate 10 on the second end face LS2 side and the second side face WS2 side. That is, the fourth external electrode 44 has an angular U-shape in the LT cross section, and is arranged along parts of the second main surface TS2 of the laminate 10 on the second end face LS2 side, the second end face LS2, and parts of the first main surface TS1 on the second end face LS2 side. In addition, the fourth external electrode 44 has a U-shape (Angular U-shape) in the WT cross section, and is arranged along a portion of the second side surface WS2 side of the second main surface TS2 of the laminate 10, the second side surface WS2, and a portion of the first main surface TS1 on the second side surface WS2 side.

[0090] 7 to 9, the multilayer ceramic capacitor 1 shown in Fig. 11 may also have flat spacer members 55 arranged on each of the first main surface TS1 and the second main surface TS2 in areas where the plurality of external electrodes 40 are not arranged. In this case, the stress suppression film 50 may extend on the first main surface TS1 so as to further cover the spacer members 55.

[0091] 11 illustrates an example of an external electrode 40 having a U-shaped cross section (Angular U-shape). However, the features of the present invention are not limited to this, and the multilayer ceramic capacitor 1 shown in FIG. 10 can also be applied to a multilayer ceramic capacitor 1 having an external electrode 40 having an L-shaped cross section, similar to the multilayer ceramic capacitors 1 shown in FIGS. 1 to 3. In this case, the first external electrode 41 is L-shaped in the LT cross section and is arranged along a part of the second main surface TS2 of the multilayer body 10 on the first end face LS1 side and the first end face LS1, and is L-shaped in the WT cross section and is arranged along a part of the second main surface TS2 of the multilayer body 10 on the first side face WS1 side and the first side face WS1. The second external electrode 42 is L-shaped in the LT cross section and is arranged along a portion of the second main surface TS2 of the laminate 10 on the second end face LS2 side and the second end face LS2, and is L-shaped in the WT cross section and is arranged along a portion of the second main surface TS2 of the laminate 10 on the first side face WS1 side and the first side face WS1. The third external electrode 43 is L-shaped in the LT cross section and is arranged along a portion of the second main surface TS2 of the laminate 10 on the first end face LS1 side and the first end face LS1, and is L-shaped in the WT cross section and is arranged along a portion of the second main surface TS2 of the laminate 10 on the second side face WS2 side and the second side face WS2. In addition, the fourth external electrode 44 is L-shaped in the LT cross section and is arranged along a portion of the second end face LS2 side of the second main surface TS2 of the laminate 10 and the second end face LS2, and is L-shaped in the WT cross section and is arranged along a portion of the second side face WS2 side of the second main surface TS2 of the laminate 10 and the second side face WS2.

[0092] Furthermore, the features of the present invention can also be applied to the multilayer ceramic capacitor 1 shown in FIG. 11 in a form in which the external electrodes 40 are provided only on the second main surface TS2, similar to the multilayer ceramic capacitor 1 shown in FIGS. 4 to 6 .

[0093] 12 is a perspective view showing a multilayer ceramic capacitor according to a modification of the present embodiment. The multilayer ceramic capacitor 1 shown in Fig. 12 differs from the multilayer ceramic capacitor 1 shown in Figs. 7 to 9 in the number and arrangement positions of the external electrodes 40.

[0094] For example, the external electrodes 40 include a first external electrode 41, a third external electrode 43, a fifth external electrode 45, and a seventh external electrode 47 on the first side surface WS1 side of the laminate 10, and a second external electrode 42, a fourth external electrode 44, a sixth external electrode 46, and an eighth external electrode 48 on the second side surface WS2 side of the laminate 10. In such a multilayer ceramic capacitor 1, for example, four multilayer ceramic capacitor elements can be arranged in an array between the first external electrode 41 and the second external electrode 42, between the third external electrode 43 and the fourth external electrode 44, between the fifth external electrode 45 and the sixth external electrode 46, and between the seventh external electrode 47 and the eighth external electrode 48. The features of the present invention can also be applied to such an array-type multilayer ceramic capacitor.

[0095] Each of the first external electrode 41, the third external electrode 43, the fifth external electrode 45, and the seventh external electrode 47 is arranged on the first side surface WS1 and on a portion of the second main surface (bottom surface, mounting surface) TS2 of the laminate 10. In the example of Fig. 12, each of the first external electrode 41, the third external electrode 43, the fifth external electrode 45, and the seventh external electrode 47 is also arranged on a portion of the first main surface (top surface) TS1 of the laminate 10 on the first side surface WS1. That is, each of the first external electrode 41, the third external electrode 43, the fifth external electrode 45 and the seventh external electrode 47 has a U-shape (Angular U-shape) in the WT cross section, and is arranged along a portion of the second main surface TS2 of the laminate 10 on the first side surface WS1 side, the first side surface WS1, and a portion of the first main surface TS1 on the first side surface WS1 side.

[0096] The second external electrode 42, the fourth external electrode 44, the sixth external electrode 46, and the eighth external electrode 48 are arranged on the second side surface WS2 and on a portion of the second main surface (bottom surface, mounting surface) TS2 of the laminate 10. In the example of Fig. 12, the second external electrode 42, the fourth external electrode 44, the sixth external electrode 46, and the eighth external electrode 48 are also arranged on a portion of the first main surface (top surface) TS1 of the laminate 10 on the second side surface WS2. That is, the second external electrode 42, the fourth external electrode 44, the sixth external electrode 46 and the eighth external electrode 48 are U-shaped (Angular U-shape) in the WT cross section, and are arranged along a portion of the second side surface WS2 side of the second main surface TS2 of the laminate 10, the second side surface WS2, and a portion of the first main surface TS1 on the second side surface WS2 side.

[0097] 7 to 9, the multilayer ceramic capacitor 1 shown in Fig. 12 may also have flat spacer members 55 arranged on each of the first main surface TS1 and the second main surface TS2 in areas where the plurality of external electrodes 40 are not arranged. In this case, the stress suppression film 50 may extend on the first main surface TS1 so as to further cover the spacer members 55.

[0098] 12 illustrates an example of an external electrode 40 having a U-shaped cross section (Angular U-shape). However, the features of the present invention are not limited to this. The multilayer ceramic capacitor 1 illustrated in FIG. 12 can also be applied to a multilayer ceramic capacitor 1 having external electrodes 40 having an L-shaped cross section, similar to the multilayer ceramic capacitors 1 illustrated in FIGS. 1 to 3. In this case, the first external electrode 41, the third external electrode 43, the fifth external electrode 45, and the seventh external electrode 47 are each L-shaped in the WT cross section and are arranged along a portion of the second main surface TS2 of the laminate 10 on the side of the first side face WS1 and along the first side face WS1. The second external electrode 42, the fourth external electrode 44, the sixth external electrode 46, and the eighth external electrode 48 are each L-shaped in the WT cross section and are arranged along a portion of the second main surface TS2 of the laminate 10 on the side of the second side face WS2 and along the second side face WS2.

[0099] Furthermore, the features of the present invention can also be applied to the multilayer ceramic capacitor 1 shown in FIG. 12 in a form in which the external electrodes 40 are provided only on the second main surface TS2, similar to the multilayer ceramic capacitor 1 shown in FIGS. 4 to 6 .

[0100] In the above-described first to fifth modifications, the stress suppression film 50 extends along five surfaces: the first main surface (top surface) TS1, the two end surfaces LS1 and TS2, and the two side surfaces WS1 and WS2. However, the present invention is not limited to this, and the stress suppression film 50 may extend along three surfaces: the first main surface (top surface) TS1 and the two end surfaces LS1 and LS2. Alternatively, the stress suppression film 50 may extend along three surfaces: the first main surface (top surface) TS1 and the two side surfaces WS1 and WS2.

[0101] The present invention may also be in the following forms: <1> A multilayer ceramic capacitor comprising: a laminate in which a plurality of dielectric layers and a plurality of internal electrode layers made of a ceramic material are stacked, the laminate having first and second main surfaces opposing each other in the stacking direction, two side surfaces opposing each other in a width direction intersecting the stacking direction, and two end surfaces opposing each other in a length direction intersecting the stacking direction and the width direction, a plurality of external electrodes arranged on at least the second main surface of the laminate, and a stress suppression film suppressing stress acting on the laminate and the plurality of external electrodes, the stress suppression film being made of an insulating material, and extending along the first main surface and the two end surfaces or along the first main surface and the two side surfaces so as to cover the laminate and the plurality of external electrodes, and an end of the stress suppression film protruding, on the second main surface side, beyond the outermost surfaces of the plurality of external electrodes.

[0102] <2> The multilayer ceramic capacitor according to <1>, wherein the stress suppression film extends along the first main surface and the two end faces, and also extends along the first main surface and the two side faces.

[0103] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the stress suppression film has a strength higher than that of the plurality of dielectric layers of the laminate.

[0104] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the stress suppression film has a Young's modulus of 400 GPa or more and 1500 GPa or less.

[0105] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the stress suppression film contains diamond-like carbon or glass as a material.

[0106] <6> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein in the stress suppression film, a thickness Da of a first portion along the first principal surface and a thickness Db of a second portion along the two end faces or the two side faces satisfy the following relational expression: 0.8Da≧Db

[0107] <7> The multilayer ceramic capacitor according to <6>, wherein the film thickness Da of the first portion is 4.5 μm or more and 5.5 μm or less.

[0108] <8> The multilayer ceramic capacitor according to any one of <1> to <7>, wherein each of the plurality of external electrodes is L-shaped in a cross section taken along the stacking direction and the length direction, and is arranged along the second main surface and one of the two end surfaces of the laminate, or is L-shaped in a cross section taken along the stacking direction and the width direction, and is arranged along the second main surface and one of the two side surfaces of the laminate.

[0109] <9> The multilayer ceramic capacitor according to any one of <1> to <7>, wherein each of the plurality of external electrodes is arranged only along the second main surface of the laminate, and the laminate has a plurality of vias extending in the stacking direction and connecting the plurality of external electrode layers to different parts of the plurality of internal electrode layers.

[0110] <10> The multilayer ceramic capacitor according to any one of <1> to <7>, wherein each of the plurality of external electrodes has a U-shape in cross section taken along the stacking direction and the length direction, and is arranged along the second main surface, one of the two end faces, and the first main surface of the laminate, or has a U-shape in cross section taken along the stacking direction and the width direction, and is arranged along the second main surface, one of the two side faces, and the first main surface of the laminate, and a flat spacer member is arranged on each of the first main surface and the second main surface in a portion where the plurality of external electrodes are not arranged, and the stress suppression film extends on the first main surface so as to further cover the spacer member.

[0111] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 10 Laminate 20 Dielectric layer 30 Internal electrode layer 31 First internal electrode layer 311 First opposing electrode portion 312 First lead electrode portion 32 Second internal electrode layer 321 Second opposing electrode portion 322 Second lead electrode portion 35 Via 40 External electrode 41 First external electrode 415 First base electrode layer 416 First plating layer 42 Second external electrode 425 Second base electrode layer 426 Second plating layer 50 Stress suppression film 55 Spacer member 100 Internal layer portion 101 First external layer portion 102 Second external layer portion L30 Electrode opposing portion LG1 First end gap portion LG2 Second end gap portion W30 Electrode opposing portion WG1 First side gap portion WG2 Second side gap portion L Length direction T Stacking direction W Width direction LS1 First end face LS2 Second end face TS1 First main surface TS2 Second main surface WS1 First side surface WS2 Second side surface

Claims

1. a laminate in which a plurality of dielectric layers and a plurality of internal electrode layers made of a ceramic material are laminated, the laminate having a first main surface and a second main surface opposed to each other in a lamination direction, two side surfaces opposed to each other in a width direction intersecting the lamination direction, and two end surfaces opposed to each other in a length direction intersecting the lamination direction and the width direction; A plurality of external electrodes disposed on at least the second main surface of the laminate; a stress suppression film that suppresses stress applied to the laminate and the plurality of external electrodes; Equipped with The stress suppression film is It is made of insulating material, the first main surface and the two end surfaces are extended along the first main surface and the two side surfaces so as to cover the laminate and the plurality of external electrodes, an end portion of the stress suppression film protrudes beyond an outermost surface of the plurality of external electrodes on the second principal surface side; Multilayer ceramic capacitor.

2. 2. The multilayer ceramic capacitor according to claim 1, wherein the stress suppression film extends along the first main surface and the two end faces, and also extends along the first main surface and the two side faces.

3. 3. The multilayer ceramic capacitor according to claim 1, wherein the stress suppression film has a strength higher than a strength of the plurality of dielectric layers of the laminate.

4. 3. The multilayer ceramic capacitor according to claim 1, wherein the stress suppression film has a Young's modulus of 400 GPa or more and 1500 GPa or less.

5. 3. The multilayer ceramic capacitor according to claim 1, wherein the stress suppression film contains diamond-like carbon or glass as a material.

6. 3. The multilayer ceramic capacitor according to claim 1, wherein in the stress suppression film, a thickness Da of a first portion along the first principal surface and a thickness Db of a second portion along the two end faces or the two side faces satisfy the following relational expression: 0.8 Da ≧ Db

7. 7. The multilayer ceramic capacitor according to claim 6, wherein the thickness Da of the first portion is not less than 4.5 μm and not more than 5.5 μm.

8. Each of the plurality of external electrodes is It is L-shaped in a cross section along the stacking direction and the length direction, and is arranged along the second main surface and one of the two end surfaces of the stack, or The laminate has an L-shape in a cross section along the stacking direction and the width direction, and is disposed along the second main surface and one of the two side surfaces of the laminate.

3. The multilayer ceramic capacitor according to claim 1.

9. each of the plurality of external electrodes is disposed only along the second main surface of the laminate; the laminate has a plurality of vias extending in the lamination direction and connecting the plurality of external electrode layers to different parts of the plurality of internal electrode layers, respectively; 3. The multilayer ceramic capacitor according to claim 1 or 2.

10. Each of the plurality of external electrodes is A cross section along the stacking direction and the length direction is U-shaped, and is disposed along the second main surface, one of the two end surfaces, and the first main surface of the laminate, or a U-shaped cross section along the stacking direction and the width direction, and disposed along the second main surface, one of the two side surfaces, and the first main surface of the laminate; a flat spacer member is disposed on each of the first main surface and the second main surface in a portion where the plurality of external electrodes are not disposed, the stress suppression film extends on the first main surface so as to further cover the spacer member; 3. The multilayer ceramic capacitor according to claim 1.