Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor that is capable of inhibiting the occurrence of cracks in the multilayer ceramic capacitor and has exceptional reliability.　This multilayer ceramic capacitor 1 comprises: a laminate 2 that includes a dielectric layer 14 and an internal electrode layer 15 that are alternately laminated, the laminate 2 having two main surfaces A that are on opposite sides from each other in a lamination direction T, two end surfaces C that are on opposite sides from each other in a length direction L orthogonal to the lamination direction T, and two side surfaces B that are on opposite sides from each other in a width direction W orthogonal to both the lamination direction T and the length direction L; and external electrodes 3 that are positioned at the two end surfaces C of the laminate 2. Each external electrode 3 has a base electrode layer 31, a first plating layer 32 that is positioned on the base electrode layer 31, a second plating layer 33 that is positioned on the first plating layer 32 and is in contact with the first plating layer, and an adhesion force relaxation layer 35 that is positioned between the first plating layer 32 and the second plating layer 33.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] When a bending stress such as bending is applied to a circuit board with a multilayer ceramic capacitor mounted thereon, the stress is transmitted to the capacitor body through the external electrodes, which may cause cracks in the capacitor body.

[0003] To prevent such cracks, for example, Patent Document 1 discloses an external electrode in which an adhesion-reducing film is disposed between the baked metal film and the plated metal film. The adhesion-reducing film reduces the adhesion of the plated metal film to the surface on which the plated metal film is formed. This allows the plated metal film to peel off from the baked metal when the circuit board is bent, thereby preventing stress from being transmitted to the capacitor body.

[0004] JP 2014-203910 A

[0005] However, if the plated metal film peels off from the baked metal film, the baked metal film is exposed to the outside air, which raises concerns about deterioration of the capacitor body and other components due to moisture and other factors that have penetrated the baked metal film.

[0006] An object of the present invention is to provide a multilayer ceramic capacitor that can suppress the occurrence of cracks and has excellent reliability.

[0007] In order to solve the above-mentioned problems, the present invention provides a multilayer ceramic capacitor comprising: a laminate including alternately stacked dielectric layers and internal electrode layers, the laminate having two main surfaces facing each other in a stacking direction, two end faces facing each other in a length direction perpendicular to the stacking direction, and two side surfaces facing each other in a width direction perpendicular to both the stacking direction and the length direction; and external electrodes respectively disposed on the two end faces of the laminate, wherein the external electrodes have a base electrode layer, a first plating layer disposed on the base electrode layer, a second plating layer disposed on the first plating layer and in contact with the first plating layer, and an adhesion relaxation layer disposed between the first plating layer and the second plating layer.

[0008] According to the present invention, it is possible to provide a multilayer ceramic capacitor that is capable of suppressing the occurrence of cracks in the multilayer ceramic capacitor and has excellent reliability.

[0009] 1A is a schematic perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention mounted on a circuit board. It is a partially enlarged cross-sectional view taken along line II-II in FIG. 1A showing a state in which the multilayer ceramic capacitor according to an embodiment of the present invention is mounted on a circuit board, in which (a) is a view showing the periphery of a first external electrode in a state in which the first plating layer and the second plating layer are bonded, and (b) is a view showing the periphery of a second external electrode in a state in which the first plating layer and the second plating layer are peeled off. It is a view corresponding to FIG. 2A showing the configuration of a multilayer ceramic capacitor according to a modified example of the present invention. It is a view corresponding to FIG. 2A showing the configuration of a multilayer ceramic capacitor according to a modified example of the present invention.

[0010] Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

[0011] 1 and 2 , the multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape and includes a laminate 2 and a pair of external electrodes 3 provided on both ends of the laminate 2. The multilayer ceramic capacitor 1 is mounted on a circuit board 50.

[0012] In the following description, the terms used to represent the orientation of the multilayer ceramic capacitor 1 are: a length direction L, which is the direction in which a pair of external electrodes 3 are provided in the multilayer ceramic capacitor 1; a stacking direction T, which is the direction in which the dielectric layers 14 and the internal electrode layers 15 are stacked; and a width direction W, which is the direction intersecting both the length direction L and the stacking direction T. In the embodiment, the width direction W is perpendicular to both the length direction L and the stacking direction T.

[0013] In the following description, of the six outer peripheral surfaces of the laminate 2 shown in FIG. 1 , a pair of outer surfaces facing each other in the stacking direction T will be referred to as two main surfaces A, a pair of outer surfaces facing each other in the width direction W will be referred to as two side surfaces B, and a pair of outer surfaces facing each other in the length direction L will be referred to as two end surfaces C. Of the two main surfaces A, one will be referred to as a first main surface AA, and the other will be referred to as a second main surface AB (see FIG. 2 ). Of the two end surfaces C, one will be referred to as a first end surface CA, and the other will be referred to as a second end surface CB. When it is not necessary to distinguish between the first main surface AA and the second main surface AB, they will be collectively referred to as the main surface A. When it is not necessary to distinguish between the first end surface CA and the second end surface CB, they will be collectively referred to as the end surface C. The circuit board 50 is disposed on the second main surface AB side of the multilayer ceramic capacitor 1.

[0014] (Laminate 2) The laminate 2 includes a laminate body portion 10 and a side margin portion 20.

[0015] (Laminate Body 10 ) The laminate body 10 includes an inner layer 11 and outer layer portions 12 disposed on both main surfaces A of the inner layer 11 .

[0016] (Inner Layer Portion 11) The inner layer portion 11 is configured by laminating a plurality of dielectric layers 14 and a plurality of internal electrode layers 15.

[0017] (Dielectric Layer 14) The dielectric layer 14 is made of a ceramic material, such as BaTiO ３ The dielectric ceramic may be a ceramic material containing the above-mentioned main component and at least one of a manganese compound, an iron compound, a chromium compound, a cobalt compound, a nickel compound, or the like.

[0018] (Internal electrode layer 15) The internal electrode layer 15 includes a plurality of first internal electrode layers 15A and a plurality of second internal electrode layers 15B. The first internal electrode layers 15A and the second internal electrode layers 15B are arranged alternately. Note that the first internal electrode layers 15A and the second internal electrode layers 15B will be collectively referred to as the internal electrode layers 15 unless there is a particular need to distinguish between them.

[0019] The internal electrode layers 15 are preferably made of a metal material such as Ni, Cu, Ag, Pd, an Ag—Pd alloy, or Au.

[0020] The first internal electrode layer 15A includes a first opposing portion 152a opposing the second internal electrode layer 15B, and a first lead portion 151a led from the first opposing portion 152a toward the first end face CA. An end of the first lead portion 151a is exposed at the first end face CA and is electrically connected to a first external electrode 3A described below.

[0021] The second internal electrode layer 15B includes a second opposing portion 152b opposing the first internal electrode layer 15A, and a second lead portion 151b extending from the second opposing portion 152b to the second end face CB. An end of the second lead portion 151b is electrically connected to a second external electrode 3B described below.

[0022] According to the above internal electrode layers 15, charges are accumulated in the first opposing portions 152a of the first internal electrode layers 15A and the second opposing portions 152b of the second internal electrode layers 15B, and the characteristics of a capacitor are exhibited.

[0023] (Outer Layer Portion 12) The outer layer portion 12 is made of the same dielectric ceramic material as the dielectric layer 14 of the inner layer portion 11.

[0024] (Side margin portions 20) The side margin portions 20 are provided on both side surfaces B of the portion where the inner layer portions 11 and the outer layer portions 12 are laminated. The side margin portions 20 cover the ends of the internal electrode layers 15 exposed on both side surfaces of the laminate body main body 10 in the width direction W along those ends. The side margin portions 20 are made of the same dielectric ceramic material as the dielectric layers 14.

[0025] (External electrode 3) The external electrode 3 includes a first external electrode 3A provided on a first end face CA of the laminate 2 and a second external electrode 3B provided on a second end face CB of the laminate 2. Note that, unless there is a particular need to distinguish between the first external electrode 3A and the second external electrode 3B, they will be collectively referred to as the external electrode 3. The external electrode 3 covers not only the end face C but also a portion of the main face A and the side face B on the end face C side.

[0026] The external electrode 3 comprises a base electrode layer 31, a first plating layer 32 arranged on the base electrode layer 31, a second plating layer 33 arranged on the first plating layer 32, and an adhesion relaxation layer 35 arranged between the first plating layer 32 and the second plating layer 33.

[0027] The base electrode layer 31 is formed by, for example, applying and baking a conductive paste containing a conductive metal and glass. The conductive metal of the base electrode layer 31 may be, for example, Cu, Ni, Ag, Pd, an Ag—Pd alloy, or Au.

[0028] The first plating layer 32 is a Cu plating layer, which can suitably prevent moisture from penetrating into the base electrode layer 31 .

[0029] The second plating layer 33 has an inner second plating layer 331 and an outer second plating layer 332 disposed on the inner second plating layer 331 and in contact with the inner second plating layer 331 .

[0030] The second inner plating layer 331 is a Ni plating layer, which can prevent the base electrode layer 31 and the adhesion relaxation layer 35 from being eroded by solder when the multilayer ceramic capacitor 1 is mounted on the circuit board 50.

[0031] The second outer plating layer 332 is a Sn plating layer, which improves the wettability of solder when mounting the multilayer ceramic capacitor 1 on the circuit board 50, making it easier to mount the multilayer ceramic capacitor 1.

[0032] The adhesion relaxation layer 35 is capable of relaxing the adhesion between the first plating layer 32 and the second plating layer 33 (more specifically, the inner second plating layer 331). This allows the first plating layer 32 to be easily peeled from the second plating layer 33 in the region where the adhesion relaxation layer 35 is disposed when the circuit board 50 is bent. The adhesion relaxation layer 35 contains an organosilicon compound. The organosilicon compound is preferably a polyfunctional alkoxysilane Si-(C ｎ H ２ｎ＋１ ) ３ This makes it possible to more reliably arrange the adhesion relaxation layer on the surface of the first plating layer 32, thereby suitably suppressing the occurrence of cracks in the laminate 2. Furthermore, plating defects and detachment of the multilayer ceramic capacitor 1 can be suppressed.

[0033] More specifically, the adhesion relaxation layer 35 is disposed in a region between the first plating layer 32 and the second plating layer 33 where the first plating layer 32 and the second plating layer 33 cover the main surface A. Although not shown, the adhesion relaxation layer 35 is annular and is also disposed in a region between the first plating layer 32 and the second plating layer 33 where the first plating layer 32 and the second plating layer 33 cover the side surface B. Note that the adhesion relaxation layer 35 only needs to be disposed in at least the region where the first plating layer 32 and the second plating layer 33 cover the second main surface AB, and does not necessarily have to be disposed in the region where the first plating layer 32 and the second plating layer 33 cover the first main surface AA or the region where the first plating layer 32 and the second plating layer 33 cover the side surface B.

[0034] The adhesion relaxation layer 35 has a plurality of voids penetrating the layer in the thickness direction. The adhesion relaxation layer 35 can also be said to have a porous structure. The first plating layer 32 and the second plating layer 33 are in contact with each other at the voids. Therefore, the first plating layer 32 and the second plating layer 33 can be electrically connected through the contact portions.

[0035] Furthermore, it is preferable that the surface roughness of at least the surface of the first plating layer 32 facing the adhesion relaxation layer 35 is in the range of 0.10 μm to 0.27 μm. This allows the ease of peeling when the first plating layer 32 and the second plating layer 33 are peeled off to fall within an appropriate range.

[0036] 2(b), when the circuit board 50 is bent, the first plating layer 32 and the second plating layer 33 may be separated from each other (hereinafter, simply referred to as a "separated state") in the region where the adhesion relaxation layer 35 is disposed. Even in the separated state, the base electrode layer 31 is covered with the first plating layer 32. This prevents moisture from penetrating the base electrode layer 31, etc., and thus prevents deterioration of the multilayer ceramic capacitor 1.

[0037] In the peeled state, it is assumed that, for example, the adhesion relaxation layer 35 is torn off, and each fragment of the adhesion relaxation layer 35 is attached to the first plating layer 32 and the second plating layer 33. However, the state of the adhesion relaxation layer 35 in the peeled state is not particularly limited, and it is also assumed that the entire adhesion relaxation layer 35 is attached to either the first plating layer 32 or the second plating layer 33.

[0038] (Method for Manufacturing Multilayer Ceramic Capacitor) Next, a description will be given of a method for manufacturing the multilayer ceramic capacitor 1. The manufacturing process for the multilayer ceramic capacitor 1 includes a laminate manufacturing step and an external electrode forming step.

[0039] (Laminate Manufacturing Process) First, a ceramic green sheet for lamination is prepared by forming a ceramic slurry into a sheet shape. A conductive paste is placed on the ceramic green sheet for lamination, and the pattern of each internal electrode layer 15 is printed on the conductive paste. In this way, a material sheet can be obtained.

[0040] Next, multiple material sheets are stacked so that the internal electrode patterns of adjacent material sheets are shifted by half a pitch in the longitudinal direction. Furthermore, ceramic green sheets for outer layers are stacked so as to sandwich the multiple stacked material sheets, and are thermocompression-bonded. This produces a mother block member.

[0041] The mother block member is then divided along cutting lines corresponding to the dimensions of the laminate, thereby obtaining a plurality of laminated chips, which may then have their corners and ridges rounded by barrel polishing or the like.

[0042] Next, the plurality of laminated chips are fired, thereby obtaining a laminate 2 having a laminate body 10 and side margins 20. The firing temperature at this time depends on the materials of the dielectric layers 14 and the internal electrode layers 15, but is preferably 900°C or higher and 1400°C or lower.

[0043] (External electrode forming process) First, a base electrode layer 31 is formed on the end surface C of the laminate 2. The end surface C of the laminate 2 is sequentially immersed in a conductive paste, which is an electrode material for the base electrode. In this way, the conductive paste is applied to each end surface C of the laminate 2. Then, this conductive paste is fired together with the laminate 2. In this way, the base electrode layer 31 is formed on each end surface C of the laminate 2. The firing temperature is preferably 600°C or higher and 900°C or lower. Note that the firing of the laminate 2 and the firing of the external electrode 3 may be performed simultaneously.

[0044] Next, a first plating layer 32 is formed on the base electrode layer 31. The first plating layer 32 is formed so that the ends of the first plating layer 32 on the main surface A and side surface B side cover the ends of the first plating layer 32 on the main surface A and side surface B side of the base electrode layer 31. The first plating layer 32 can be formed by, for example, electrolytic plating or electroless plating.

[0045] Next, an adhesion relaxation layer 35 is disposed on the first plating layer 32. A first organic treatment liquid and a second organic treatment liquid are used to form the adhesion relaxation layer 35. First, the first organic treatment liquid is applied to the first plating layer 32. The first organic treatment liquid contains an organosilicon compound. The organosilicon compound is a silane coupling agent. Examples of organosilicon compounds (silane coupling agents) include decyltrimethoxysilane, n-propyltrimethoxysilane, and octyltriethoxysilane. The first organic treatment liquid can be applied by, for example, a screen printing method. Thereafter, the first organic treatment liquid is dried at a temperature of 100°C to 200°C.

[0046] After the first organic treatment liquid has dried, a second organic treatment liquid is applied. The second organic treatment liquid contains an organosilicon compound, and preferably contains polyfunctional alkoxysilane Si-(C ｎ H ２ｎ＋１ ) ３ The second organic treatment liquid can be applied by, for example, screen printing. The second organic treatment liquid is then dried at a temperature of 100°C to 200°C. The dried first and second organic treatment liquids are disposed on the first plating layer 32 as the adhesion relaxation layer 35. The method for applying the first and second organic treatment liquids is not limited to screen printing; for example, a dipping method in which the target is immersed in the organic treatment liquid may also be used. Furthermore, the adhesion relaxation layer disposed in an area where the adhesion relaxation layer is not desired can be removed by polishing or the like. The number and size of the voids in the adhesion relaxation layer 35 can be adjusted by the application amounts of the first and second organic treatment liquids. When the application amounts of the first and second organic treatment liquids are large, the number of voids decreases and the size of the voids decreases. When the application amounts of the first and second organic treatment liquids are small, the number of voids increases and the size of the voids increases.

[0047] Next, the inner second plating layer 331 is formed on the first plating layer 32 and the adhesion relaxation layer 35. The inner second plating layer 331 is formed such that the ends of the inner second plating layer 331 on the main surface A and side surface B side cover the ends of the first plating layer 32 and the adhesion relaxation layer 35 on the main surface A and side surface B side. The inner second plating layer 331 can be formed by, for example, electrolytic plating.

[0048] Next, the outer second plating layer 332 is formed on the inner second plating layer 331. The outer second plating layer 332 is formed so that the ends of the outer second plating layer 332 on the main surface A and side surface B side cover the ends of the adhesion relaxation layer 35 on the main surface A and side surface B side. The outer second plating layer 332 can be formed by, for example, electrolytic plating. In this manner, the external electrode 3 is formed.

[0049] (Effects) According to the above embodiment, the following effects can be obtained.

[0050] According to the above embodiment, the external electrode 3 includes the base electrode layer 31, the first plating layer 32 disposed on the base electrode layer 31, the second plating layer 33 disposed on the first plating layer 32 and in contact with the first plating layer 32, and the adhesion relaxation layer 35 disposed between the first plating layer 32 and the second plating layer 33. The adhesion relaxation layer 35 is capable of relaxing the adhesion between the first plating layer 32 and the second plating layer 33. As a result, when the circuit board 50 is bent while the multilayer ceramic capacitor 1 is mounted on the circuit board 50, the resulting stress can cause the first plating layer 32 and the second plating layer 33 to peel off from each other. This can suppress the occurrence of cracks in the multilayer ceramic capacitor 1.

[0051] Furthermore, even if the first plating layer 32 and the second plating layer 33 are peeled off, the base electrode layer 31 remains covered with the first plating layer 32. This prevents moisture from penetrating the base electrode layer 31, etc., and thus prevents deterioration of the multilayer ceramic capacitor 1. This allows the multilayer ceramic capacitor 1 to have excellent reliability.

[0052] According to the above embodiment, the first plating layer 32 is a Cu plating layer, which can effectively prevent moisture from penetrating into the base electrode layer 31 .

[0053] Furthermore, according to the above embodiment, the second inner plating layer 331 is a Ni plating layer, which can prevent the base electrode layer 31 and the adhesion relaxation layer 35 from being eroded by solder when the multilayer ceramic capacitor 1 is mounted on the circuit board 50.

[0054] Furthermore, according to the above embodiment, the second outer plating layer 332 is a Sn plating layer, which improves the wettability of solder when mounting the multilayer ceramic capacitor 1 on the circuit board 50, making it easier to mount the multilayer ceramic capacitor 1.

[0055] According to the above embodiment, the adhesion relaxation layer 35 contains an organosilicon compound. This effectively prevents cracks from occurring in the laminate 2. Furthermore, plating defects and detachment of the multilayer ceramic capacitor 1 can be prevented.

[0056] According to the above embodiment, the organosilicon compound is a polyfunctional alkoxysilane, which more effectively suppresses the occurrence of cracks in the laminate 2, plating defects, and detachment of the multilayer ceramic capacitor 1.

[0057] According to the above embodiment, the surface roughness Sa of the first plating layer 32 is equal to or greater than 0.10 μm and equal to or less than 0.27 μm.

[0058] This allows the first plating layer 32 and the second plating layer 33 to be appropriately peeled off easily.

[0059] According to the above embodiment, the adhesion relaxation layer 35 is disposed in the region between the first plating layer 32 and the second plating layer 33, in the region located outside the main surface A and the region located outside the side surface B, but is not disposed in the region located outside the end surface C. This allows the adhesion between the first plating layer 32 and the second plating layer 33 to be of appropriate strength, thereby making it possible to suitably prevent the multilayer ceramic capacitor 1 from coming off.

[0060] (Modifications) Although the preferred embodiments and modifications of the present invention have been described above, the present invention is not limited to these, and includes the following scope.

[0061] In the above embodiment, the adhesion relaxation layer 35 is disposed in the region between the first plating layer 32 and the second plating layer 33, in the region located outside the main surface A and the region located outside the side surface B of the laminate 2, but not in the region located outside the end surface C. However, this is not limited to this. For example, as shown in FIG. 3 , the multilayer ceramic capacitor 100 includes an adhesion relaxation layer 135. The adhesion relaxation layer 135 is disposed so as to cover the entire region between the first plating layer 32 and the second plating layer 33. In this case, the adhesion relaxation layer can be easily disposed by, for example, using a dipping method. However, the configuration of the above embodiment is preferable in that it can suitably prevent the second plating layer from detaching from the multilayer ceramic capacitor.

[0062] The adhesion relaxation layer may also extend to the outside of the region between the first plating layer 32 and the second plating layer 33. For example, as shown in FIG. 4 , a multilayer ceramic capacitor 200 includes an adhesion relaxation layer 235. The adhesion relaxation layer 235 is disposed so as to cover the entire outer surface of the first plating layer 32 and the entire outer surfaces of the main surface A and side surface B of the laminate 2. In this case, the adhesion relaxation layer can be more easily disposed by using, for example, a dipping method. However, the configuration of the above embodiment is preferred in that it can suitably prevent the second plating layer from detaching from the multilayer ceramic capacitor.

[0063] In the above embodiment, the adhesion relaxation layer 35 contains an organosilicon compound, but this is not limited to this. The adhesion relaxation layer may be made of, for example, a metal. However, the configuration of the above embodiment is preferred in that it can more effectively suppress the occurrence of cracks in the multilayer ceramic capacitor.

[0064] In the above embodiment, the first plating layer 32 has a single layer structure, but may have multiple layers. When the first plating layer has multiple layers, the surface roughness Sa of the outer surface of the outermost layer of each layer is preferably 0.10 μm or more and 0.27 μm or less.

[0065] In the above embodiment, the second plating layer 33 has an inner second plating layer 331 and an outer second plating layer 332, but it may have a single layer structure or may have three or more layers.

[0066] Although the preferred embodiments and modifications of the present invention have been described above, the present invention is not limited to these, and includes the following scope.

[0067] <1> A multilayer ceramic capacitor comprising: a laminate including alternately stacked dielectric layers and internal electrode layers, the laminate having two main surfaces opposing each other in the stacking direction, two end faces opposing each other in a length direction perpendicular to the stacking direction, and two side surfaces opposing each other in a width direction perpendicular to both the stacking direction and the length direction; and external electrodes respectively disposed on the two end faces of the laminate, wherein the external electrodes have a base electrode layer, a first plating layer disposed on the base electrode layer, a second plating layer disposed on the first plating layer and in contact with the first plating layer, and an adhesion relaxation layer disposed between the first plating layer and the second plating layer.

[0068] <2> The multilayer ceramic capacitor according to <1>, wherein the second plating layer has an inner second plating layer and an outer second plating layer disposed on the inner second plating layer.

[0069] <3> The multilayer ceramic capacitor according to <2>, wherein the first plating layer is a Cu plating layer, the inner second plating layer is a Ni plating layer, and the outer second plating layer is a Sn plating layer.

[0070] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the adhesion relaxation layer contains an organosilicon compound.

[0071] <5> The multilayer ceramic capacitor according to <4>, wherein the organosilicon compound is a polyfunctional alkoxysilane.

[0072] <6> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein the surface roughness Sa of the first plating layer is 0.10 μm or more and 0.27 μm or less.

[0073] <7> The multilayer ceramic capacitor according to any one of <1> to <6>, wherein the adhesion relaxation layer is arranged in a region between the first plating layer and the second plating layer that is located outside the main surface and a region that is located outside the side surface, but is not arranged in a region that is located outside the end surface.

[0074] 1, 100, 200 Multilayer ceramic capacitor 2 Laminate 3 External electrode 3A First external electrode 3B Second external electrode 14 Dielectric layer 15 Internal electrode layer 31 Base electrode layer 32 First plating layer (Cu plating layer) 33 Second plating layer 35, 135, 235 Adhesion relaxation layer 331 Inner second plating layer (Ni plating layer) 332 Outer second plating layer (Sn plating layer) A Main surface AA First main surface AB Second main surface B Side surface C End surface CA First end surface CB Second end surface

Claims

1. A laminate including dielectric layers and internal electrode layers laminated alternately, having two main surfaces facing each other in the lamination direction, two end surfaces facing each other in the length direction orthogonal to the lamination direction, and two side surfaces facing each other in the width direction orthogonal to both the lamination direction and the length direction; External electrodes respectively disposed on the two end surfaces of the laminate; A multilayer ceramic capacitor comprising: The external electrode has an underlayer electrode layer, a first plating layer disposed on the underlayer electrode layer, a second plating layer disposed on the first plating layer and in contact with the first plating layer, and an adhesion relaxation layer disposed between the first plating layer and the second plating layer. Multilayer ceramic capacitor.

2. The multilayer ceramic capacitor according to claim 1, wherein the second plating layer has an inner second plating layer and an outer second plating layer disposed on the inner second plating layer.

3. The first plating layer is a Cu plating layer; The inner second plating layer is a Ni plating layer; The multilayer ceramic capacitor according to claim 2, wherein the outer second plating layer is a Sn plating layer.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the adhesion relaxation layer contains an organosilicon compound.

5. The multilayer ceramic capacitor according to claim 4, wherein the organosilicon compound is a polyfunctional alkoxysilane.

6. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the surface roughness Sa of the first plating layer is 0.10 μm or more and 0.27 μm or less.

7. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the adhesion relaxation layer is disposed in regions located outside the main surface and outside the side surface among the regions between the first plating layer and the second plating layer, and is not disposed in the region located outside the end surface.