Ceramic electronic component and manufacturing method therefor

Abstract

This ceramic electronic component is characterized by: comprising a laminated chip in which a plurality of dielectric layers and a plurality of internal electrode layers are layered in an alternating manner; and at least one layer of the plurality of dielectric layers comprising a first layer that is located toward the center in the lamination direction, and a second layer which is adjacent to the internal electrode layer, and the dielectric-particle average diameter of which is smaller than that of the first layer.　

Description

Ceramic electronic component and manufacturing method thereof

[0001] The present invention relates to a ceramic electronic component and a method for manufacturing the same.

[0002] 2. Description of the Related Art With the trend toward smaller size and larger capacitance, ceramic electronic components such as multilayer ceramic capacitors have been disclosed with thinner and more multi-layered dielectric layers and internal electrode layers (see, for example, Patent Documents 1 and 2).

[0003] JP 2008-305844 A JP 2009-319205 A

[0004] However, when the internal electrode layers are made thinner, discontinuities may occur in the internal electrode layers, resulting in a decrease in the continuity ratio.

[0005] The present invention has been made in view of the above-mentioned problems, and has as its object to provide a ceramic electronic component capable of improving the continuity ratio of internal electrode layers, and a method for manufacturing the same.

[0006] The ceramic electronic component according to the present invention comprises a laminated chip in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked, and at least one of the plurality of dielectric layers comprises a first layer located toward the center in the stacking direction, and a second layer adjacent to the internal electrode layer and having an average particle size of dielectric particles smaller than that of the first layer.

[0007] In the ceramic electronic component, the dielectric particles in the second layer may have an average particle size of 0.02 μm or less.

[0008] In the ceramic electronic component, the dielectric particles in the second layer may have a particle size of 0.025 μm or less.

[0009] In the ceramic electronic component, the dielectric particles in the first layer may have an average particle size of 0.035 μm or more.

[0010] In the ceramic electronic component, the particle diameter of the dielectric particles in the first layer may be 0.03 μm or more.

[0011] In the ceramic electronic component, the dielectric particles in the first layer may have an average particle size of 0.08 μm or less.

[0012] In the ceramic electronic component, the particle diameter of the dielectric particles in the first layer may be 0.085 μm or less.

[0013] In the ceramic electronic component, the first layer may include flat particles whose maximum length is three times or more its minimum length in a cross section including the stacking direction.

[0014] In the ceramic electronic component, 60% or more of the dielectric particles contained in the first layer may be the flat particles.

[0015] In a cross section of the ceramic electronic component including the lamination direction, the angle formed between the average direction of the major axes of the flat particles and the direction in which the dielectric layers extend may be ±20° or less.

[0016] In the ceramic electronic component, the plurality of dielectric layers may be mainly composed of a ferroelectric material.

[0017] In the ceramic electronic component, 80% or more of the plurality of dielectric layers may include the first layer and the second layer.

[0018] The method for manufacturing a ceramic electronic component according to the present invention is characterized by comprising the steps of: forming a laminate by alternately laminating dielectric green sheets, each of which has a first green sheet containing a ceramic material and a second green sheet laminated on the upper and lower surfaces thereof, the second green sheet containing a ceramic material having an average grain size smaller than the average grain size of the ceramic material of the first green sheet, and internal electrode patterns for internal electrode layers; and firing the laminate.

[0019] According to the present invention, it is possible to provide a ceramic electronic component capable of improving the continuity rate of internal electrode layers, and a method for manufacturing the same.

[0020] 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor; FIG. 2 is a cross-sectional view taken along line AA in FIG. 1; FIG. 3 is a cross-sectional view taken along line BB in FIG. 1; FIG. 4 is a diagram showing a continuity ratio; FIG. 5 is a diagram illustrating an XZ cross section; FIG. 6 is a diagram illustrating an XZ cross section; and FIG. 7 is a diagram illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. (a) to (c) are diagrams illustrating the lamination process.

[0021] Hereinafter, embodiments will be described with reference to the drawings.

[0022] (Embodiment) FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along line A-A in FIG. 1. FIG. 3 is a cross-sectional view taken along line B-B in FIG. 1. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a laminated chip 10 having a substantially rectangular parallelepiped shape and external electrodes 20a, 20b provided on two opposing end faces of the laminated chip 10. Of the four faces of the laminated chip 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces. The external electrodes 20a, 20b extend on the top, bottom, and two side faces of the laminated chip 10 in the stacking direction. However, the external electrodes 20a and 20b are spaced apart from each other.

[0023] 1 to 3, the Z-axis direction is the direction in which the multiple internal electrode layers 12 face each other, the stacking direction of the dielectric layers 11, and the direction in which the top and bottom surfaces of the laminated chip 10 face each other. The X-axis direction is the length direction of the laminated chip 10, the direction in which the two end faces of the element body 10 face each other, the direction in which the external electrodes 20a and 20b face each other, and the longitudinal direction in which the dielectric layers 11 extend. The Y-axis direction is the width direction of the internal electrode layers 12, and the direction in which the two side faces other than the two end faces of the four side faces of the laminated chip 10 face each other.

[0024] The laminated chip 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 primarily composed of metal are alternately stacked. In other words, the laminated chip 10 includes a plurality of mutually opposing internal electrode layers 12 and a dielectric layer 11 sandwiched between each of the plurality of internal electrode layers 12. The edges of the internal electrode layers 12 in the extending direction are alternately exposed to the first end face of the laminated chip 10 on which the external electrode 20a is provided and the second end face on which the external electrode 20b is provided. The internal electrode layer 12 connected to the external electrode 20a is not connected to the external electrode 20b. The internal electrode layer 12 connected to the external electrode 20b is not connected to the external electrode 20a. Therefore, each internal electrode layer 12 is alternately electrically connected to the external electrode 20a and the external electrode 20b. In addition, in a laminate of the dielectric layers 11 and the internal electrode layers 12, the internal electrode layer 12 is disposed on the uppermost layer in the lamination direction, and the internal electrode layer 12 is also disposed on the lowermost layer in the lamination direction, and the upper and lower surfaces of the laminate are covered with a cover layer 13. The cover layer 13 contains a ceramic material as a main component. For example, the cover layer 13 may have the same composition as or a different composition from the dielectric layers 11.

[0025] The main component of the dielectric layer 11 is a compound represented by the general formula ABO ３ The perovskite structure can be a ceramic material having a perovskite structure represented by the formula: ABO ３－α For example, the ceramic material may include BaTiO ３ (barium titanate), CaZrO ３ (Calcium zirconate), CaTiO ３ (Calcium titanate), SrTiO ３ (strontium titanate), MgTiO ３ (magnesium titanate), Ba that forms a perovskite structure １-ｘ－ｙ Ca ｘ Sr ｙ Ti １－ｚ Zr ｚ O ３ (0≦x≦1, 0≦y≦1, 0≦z≦1) and the like. １-ｘ－ｙ Caｘ Sr ｙ Ti １－ｚ Zr ｚ O ３ Examples include barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate, and barium calcium titanate zirconate.

[0026] Of these ceramic materials, it is preferable to use a ferroelectric material with a relative dielectric constant of 1000 or more.

[0027] An additive may be added to the dielectric layer 11. Examples of additives to the dielectric layer 11 include oxides of magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glasses containing Co, Ni, Li, B, Na, K, or Si.

[0028] The internal electrode layers 12 are mainly composed of base metals such as Ni, copper (Cu), tin (Sn), or alloys containing these metals. The internal electrode layers 12 may also be mainly composed of precious metals such as platinum (Pt), palladium (Pd), silver (Ag), or gold (Au), or alloys containing these metals.

[0029] The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.110 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.1 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but is not limited to these sizes. For example, the length and width may be interchanged. The multilayer ceramic capacitor 100 may also be a three-terminal multilayer ceramic capacitor having three external electrodes.

[0030] The thickness of each dielectric layer 11 is, for example, 0.3 μm to 20 μm, or 0.3 μm to 10 μm, or 0.4 μm to 8 μm, or 0.5 μm to 5 μm. The thickness of each dielectric layer 11 can be measured by exposing the cross section of the multilayer ceramic capacitor 100, for example, as shown in FIG. 2, by mechanical polishing, and then obtaining the average value of thicknesses at 10 locations from an image taken with a microscope such as a scanning transmission electron microscope.

[0031] The thickness of each internal electrode layer 12 is, for example, 0.1 μm to 2 μm, or 0.2 μm to 1 μm, or 0.3 μm to 0.8 μm. The thickness of each internal electrode layer 12 can be measured by exposing the cross section of the multilayer ceramic capacitor 100, for example, as shown in FIG. 2, by mechanical polishing, and then obtaining the average value of thicknesses at 10 locations from an image taken with a microscope such as a scanning transmission electron microscope.

[0032] In the multilayer ceramic capacitor 100, the number of stacked internal electrode layers 12 is, for example, about 50 to 500. In addition, in the multilayer ceramic capacitor 100, the stacking density of the internal electrode layers 12 is about 20 layers / mm to 1500 layers / mm.

[0033] 2, the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region where capacitance is generated in the multilayer ceramic capacitor 100. Therefore, this region where capacitance is generated is referred to as a capacitance portion 14. In other words, the capacitance portion 14 is a region where adjacent internal electrode layers connected to different external electrodes face each other.

[0034] The region where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b interposed therebetween is called the end margin 15. The region where the internal electrode layers 12 connected to the external electrode 20b face each other without an internal electrode layer 12 connected to the external electrode 20a interposed therebetween is also the end margin 15. In other words, the end margin is the region where internal electrode layers connected to the same external electrode face each other without an internal electrode layer connected to a different external electrode interposed therebetween. The end margin 15 is a region where no capacitance is generated. The end margin 15 may have the same composition as the dielectric layer 11 of the capacitive section 14, or a different composition.

[0035] 3, in the laminated chip 10, the regions extending from the two side surfaces of the laminated chip 10 to the internal electrode layers 12 are referred to as side margins 16. That is, the side margins 16 are regions provided so as to cover the ends of the multiple internal electrode layers 12 stacked in the above-mentioned laminated structure that extend toward the two side surfaces. The side margins 16 are also regions that do not generate capacitance. The side margins 16 may have the same composition as the dielectric layer 11 of the capacitive section 14, or may have a different composition.

[0036] In such a structure, increasing the number of laminations to achieve a smaller size and larger capacity requires reducing the thickness of the internal electrode layers 12. However, reducing the thickness of the internal electrode layers 12 reduces the continuity of the internal electrode layers 12. Here, the continuity ratio, which is an index representing the continuity of the internal electrode layers 12, will be described.

[0037] 4 is a diagram showing the continuity ratio. As shown in FIG. 4, in an observation area of ​​length L0 in a certain internal electrode layer 12, the lengths L1, L2, ..., Ln of the metal portions are measured and summed, and the ratio of the metal portions, ΣLn / L0, can be defined as the continuity ratio of that layer. The closer this continuity ratio is to 100%, the better the continuity of the internal electrode layer 12.

[0038] The multilayer ceramic capacitor 100 according to this embodiment has a configuration that can improve the continuity of the internal electrode layers 12 .

[0039] FIG. 5 is an enlarged view of the XZ cross section. FIG. 5 illustrates an enlarged view of the XZ cross section of the capacitance section 14 as an example. As illustrated in FIG. 5, the dielectric layer 11 has a structure in which a plurality of dielectric particles 30 are sintered. In this embodiment, the dielectric layer 11 includes a first layer 111 in the center in the Z-axis direction and second layers 112 at both ends in the Z-axis direction. That is, the dielectric layer 11 has a configuration in which one first layer 111 is sandwiched between two second layers 112. The second layers 112 are adjacent to the internal electrode layers 12. The average particle size of the dielectric particles 30 contained in the dielectric layer 11 is larger in the first layer 111 than in the second layer 112.

[0040] According to this configuration, the region of the dielectric layer 11 that contacts the adjacent internal electrode layer 12 becomes the second layer 112. Since the average particle size of the dielectric particles 30 in the second layer 112 is small, the surface roughness of the second layer 112 is reduced, and as a result, the internal electrode layer 12 that contacts the second layer 112 also becomes flat, and the continuity rate of the internal electrode layer 12 increases.

[0041] If the average particle size of the dielectric particles 30 is small throughout the dielectric layer 11, the dielectric constant of the dielectric layer 11 will be low. However, in this embodiment, the first layer 111 is provided in the center of the dielectric layer 11. This allows the dielectric constant of the dielectric layer 11 to be maintained high.

[0042] If the average particle size of the dielectric particles 30 in the second layer 112 is not sufficiently small, the surface roughness of the second layer 112 may not be sufficiently small. Therefore, it is preferable to set an upper limit to the average particle size in the second layer 112. In this embodiment, the average particle size in the second layer 112 is preferably 0.02 μm or less, more preferably 0.018 μm or less, and even more preferably 0.016 μm or less.

[0043] The upper limit of the particle size of each dielectric particle 30 contained in the second layer 112 is preferably 0.025 μm or less, more preferably 0.023 μm or less, and even more preferably 0.021 μm or less.

[0044] On the other hand, if the average particle size of the dielectric particles 30 in the second layer 112 is too small, there is a risk of aggregation during dispersion. Therefore, it is preferable to set a lower limit for the average particle size in the second layer 112. In this embodiment, the average particle size in the second layer 112 is preferably 0.010 μm or more, more preferably 0.012 μm or more, and even more preferably 0.014 μm or more.

[0045] The lower limit of the particle size of each dielectric particle 30 contained in the second layer 112 is preferably 0.005 μm or more, more preferably 0.007 μm or more, and even more preferably 0.009 μm or more.

[0046] If the average particle size of the dielectric particles 30 in the first layer 111 is not sufficiently large, a sufficient relative dielectric constant may not be obtained in the dielectric layer 11. Therefore, it is preferable to set a lower limit for the average particle size in the first layer 111. In this embodiment, the average particle size in the first layer 111 is preferably 0.035 μm or more, more preferably 0.037 μm or more, and even more preferably 0.039 μm or more.

[0047] The lower limit of the particle size of each dielectric particle 30 contained in the first layer 111 is preferably 0.03 μm or more, more preferably 0.032 μm or more, and even more preferably 0.034 μm or more.

[0048] On the other hand, if the average particle size of the dielectric particles 30 in the first layer 111 is too large, defects may easily occur when forming a thin sheet. Therefore, it is preferable to set an upper limit to the average particle size in the first layer 111. In this embodiment, the average particle size in the first layer 111 is preferably 0.08 μm or less, more preferably 0.078 μm or less, and even more preferably 0.076 μm or less.

[0049] The upper limit of the particle size of the dielectric particles 30 contained in the first layer 111 is preferably 0.085 μm or less, more preferably 0.083 μm or less, and even more preferably 0.081 μm or less.

[0050] In the dielectric layer 11, the thickness of the first layer 111 is 1 / 30 to 1 / 4 of the thickness of the dielectric layer 11, and the thickness of each second layer 112 is 1 / 20 to 1 / 50 of the thickness of the dielectric layer 11.

[0051] The particle size of the dielectric particles 30 can be measured by measuring the maximum diameter of the dielectric particles observed in an SEM photograph or a TEM photograph of the XZ cross section. The average particle size of the dielectric particles 30 can be measured by measuring the average value of the maximum diameters of the dielectric particles observed in an SEM photograph or a TEM photograph of the XZ cross section.

[0052] In order to increase the relative dielectric constant of the dielectric layer 11 without increasing the thickness of the dielectric layer 11, it is preferable that the dielectric particles 30 of the first layer 111 have a flat shape in the XZ cross section, as exemplified in Fig. 6. In this embodiment, among the dielectric particles 30 observed in the XZ cross section, particles whose maximum length is three times or more their minimum length are defined as flat particles.

[0053] For example, in the XZ cross section, it is preferable that 60% or more of all the dielectric particles 30 contained in the first layer 111 have a flat shape, it is more preferable that 55% or more have a flat shape, and it is even more preferable that 50% or more have a flat shape.

[0054] In the first layer 111, the flat-shaped dielectric particles 30 are preferably oriented. Specifically, the angle between the X-axis direction (the direction in which the dielectric layer 11 extends) and the average direction of the major axis of each dielectric particle 30 is preferably ±20° or less. This configuration can increase the relative dielectric constant of the dielectric layer 11 without increasing the thickness of the dielectric layer 11. The average direction of each dielectric particle 30 can be measured by measuring the average value of the major axis direction of the dielectric particles observed in an SEM or TEM photograph of the XZ cross section.

[0055] In the multilayer ceramic capacitor 100 according to this embodiment, it is sufficient that at least one dielectric layer 11 includes a first layer 111 and a second layer 112. The higher the ratio of the dielectric layers 11 that include the first layer 111 and the second layer 112 among all the dielectric layers 11, the better. In this embodiment, it is preferable that 80% or more of all the dielectric layers 11 include the first layer 111 and the second layer 112, more preferably 85% or more of the dielectric layers 11 include the first layer 111 and the second layer 112, and even more preferably 90% or more of the dielectric layers 11 include the first layer 111 and the second layer 112.

[0056] Next, a description will be given of a method for manufacturing the multilayer ceramic capacitor 100. FIG.

[0057] (Step of Preparing Raw Material Powder) First, a dielectric material is prepared for forming the dielectric layer 11. The A-site elements and B-site elements contained in the dielectric layer 11 are usually ABO ３ The dielectric layer 11 contains a sintered body of BaTiO particles. ３ is a tetragonal compound with a perovskite structure and exhibits a high dielectric constant. ３Generally, it can be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been known for synthesizing the ceramic that is the main component of the dielectric layer 11, such as a solid-phase method, a sol-gel method, and a hydrothermal method. Any of these methods can be used in this embodiment.

[0058] A predetermined additive compound is added to the obtained ceramic powder depending on the purpose. Examples of the additive compound include oxides of magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glasses containing Co, Ni, Li, B, Na, K, or Si. Among these, SiO is mainly used. ２ functions as a sintering aid.

[0059] For example, a ceramic material is prepared by wet-mixing a ceramic raw material powder with a compound containing an additive compound, followed by drying and pulverization. For example, the ceramic material obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size. A dielectric material is obtained by the above process.

[0060] The particle size of the dielectric material for forming the first layer 111 is made large, and the particle size of the dielectric material for forming the second layer 112 is made small.

[0061] (Lamination Process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained raw material powder and wet mixed. Using the obtained slurry, a dielectric green sheet 52 is coated on a substrate 51 by, for example, a die coater method, a doctor blade method, or spin coating, and then dried, as illustrated in Fig. 8(a). The substrate 51 is, for example, a polyethylene terephthalate (PET) film.

[0062] 8(b) is a diagram illustrating the details of the dielectric green sheet 52. As illustrated in FIG. 8(b), a dielectric material for forming the second layer 112 is applied to form a small particle size green sheet 522, a dielectric material for forming the first layer 111 is applied thereon to form a large particle size green sheet 521, and a dielectric material for forming the second layer 112 is applied thereon to form a small particle size green sheet 522. Note that when the first layer 111 is applied by spin coating, the major axis direction of the flat-shaped ceramic powder tends to be oriented close to the in-plane direction.

[0063] Alternatively, a small particle size green sheet 522 may be formed by depositing a dielectric material for forming the second layer 112 using a vacuum deposition method such as sputtering, a large particle size green sheet 521 may be formed on top of the small particle size green sheet 522 by depositing a dielectric material for forming the first layer 111 using a vacuum deposition method, and a small particle size green sheet 522 may be formed on top of the large particle size green sheet 521 by depositing a dielectric material for forming the second layer 112 using a vacuum deposition method.

[0064] Next, internal electrode patterns 53 are formed on the dielectric green sheets 52. In Fig. 8(a) , as an example, four layers of internal electrode patterns 53 are formed at predetermined intervals on the dielectric green sheets 52. The dielectric green sheets 52 on which the internal electrode patterns 53 are formed are used as lamination units.

[0065] The internal electrode patterns 53 are made of a metal paste containing the main component metal of the internal electrode layers 12. The film formation method may be printing, sputtering, vapor deposition, etc. The shape of each internal electrode pattern 53 corresponds to the shape of the internal electrode layer 12.

[0066] Next, while peeling off the dielectric green sheet 52 from the substrate 51, the lamination units are laminated as shown in FIG. 8(c).

[0067] Next, a predetermined number of cover sheets 54 (e.g., 2 to 10 layers) are laminated on top and bottom of the laminate obtained by laminating the lamination units, and are thermocompression bonded, and then cut to predetermined chip dimensions (e.g., 1.0 mm x 0.5 mm). In the example of Figure 8(c), cutting is performed along the dotted lines. The cover sheet 54 may have the same components as the dielectric green sheet 52, or may contain different additives.

[0068] (Coating step) The ceramic laminate thus obtained is coated with N ２ After the binder is removed in a deaerated atmosphere, a metal paste that will become the base layer of the external electrodes 20 a, 20 b is applied by a dipping method or the like. The metal paste contains a co-material. For example, the metal paste is applied to the two end faces of the laminate where the internal electrode pattern 53 is exposed.

[0069] (Firing step) After that, the oxygen partial pressure is 10 －５ ~10 －８ The mixture is fired in a reducing atmosphere at 1100 to 1300° C. for 10 minutes to 2 hours.

[0070] (Reoxidation treatment step) Then, N ２ A reoxidation treatment may be carried out in a gas atmosphere at 600° C. to 1000° C.

[0071] (Plating Process) Thereafter, a plating layer may be formed on the underlayer by plating, thereby completing the multilayer ceramic capacitor 100.

[0072] According to this embodiment, the dielectric green sheet 52 is formed by forming the small particle size green sheet 522, forming the large particle size green sheet 521 thereon, and forming the small particle size green sheet 522 thereon, so that the first layer 111 and the second layer 112 can be formed on the fired dielectric layer 11. This makes it possible to improve the continuity rate of the internal electrode layer 12 while maintaining a high relative dielectric constant of the dielectric layer 11.

[0073] Although the above embodiments have been described with reference to a multilayer ceramic capacitor as an example of a ceramic electronic component, the present invention is not limited thereto. For example, the configurations of the above embodiments can be applied to other multilayer ceramic electronic components such as varistors and thermistors.

[0074] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention as described in the claims.

[0075] REFERENCE SIGNS LIST 10 laminated chip 11 dielectric layer 12 internal electrode layer 13 cover layer 14 capacitance portion 15 end margin 16 side margin 20a, 20b external electrode 30 dielectric particle 40 metal particle 51 substrate 52 dielectric green sheet 53 internal electrode pattern 54 cover sheet 100 laminated ceramic capacitor 111 large grain size layer 112 small grain size layer 521 large grain size green sheet 522 small grain size green sheet

Claims

1. A ceramic electronic component comprising a laminated chip in which multiple dielectric layers and multiple internal electrode layers are alternately stacked, wherein at least one of the multiple dielectric layers comprises a first layer located toward the center in the stacking direction, and a second layer adjacent to the internal electrode layer, the average particle size of the dielectric particles being smaller than that of the first layer.

2. A ceramic electronic component according to claim 1, wherein the average particle size of the dielectric particles in the second layer is 0.02 μm or less.

3. A ceramic electronic component according to claim 1, wherein the particle size of the dielectric particles in the second layer is 0.025 μm or less.

4. The ceramic electronic component according to claim 1, wherein the average grain size of the first layer is 0.035 μm or more.

5. A ceramic electronic component according to claim 1, wherein the particle size of the dielectric particles in the first layer is 0.03 μm or more.

6. A ceramic electronic component according to claim 1, wherein the average particle size of the dielectric particles in the first layer is 0.08 μm or less.

7. A ceramic electronic component according to claim 1, wherein the particle size of the dielectric particles in the first layer is 0.085 μm or less.

8. The ceramic electronic component according to claim 1, wherein the first layer contains flat grains whose maximum length is at least three times the minimum length in a cross section including the stacking direction.

9. The ceramic electronic component according to claim 8, wherein 60% or more of the dielectric particles contained in said first layer are said flat particles.

10. A ceramic electronic component as described in claim 9, characterized in that in a cross section including the stacking direction, the angle between the average direction of the long diameters of the flat particles and the direction in which the dielectric layers extend is ±20° or less.

11. The ceramic electronic component according to claim 1, wherein the main component of the plurality of dielectric layers is a ferroelectric material.

12. A ceramic electronic component according to any one of claims 1 to 10, wherein 80% or more of the plurality of dielectric layers include the first layer and the second layer.

13. A method for manufacturing a ceramic electronic component, comprising: a step of alternately laminating dielectric green sheets, each of which has a first green sheet containing a ceramic material and a second green sheet containing a ceramic material having an average grain size smaller than that of the ceramic material of the first green sheet, on the upper and lower surfaces thereof, and internal electrode patterns for internal electrode layers to form a laminate; and a step of firing the laminate.