Power conversion device

Abstract

A power conversion device (1) comprises: a power converter (10) configured to have a plurality of leg circuits (100u, 100v, 100w) which are connected in parallel and in which positive-side arms and negative-side arms (110) are connected in series; and a control device (20) for controlling the power converter (10). The control device (20): generates an arm output voltage command value (Varm) that is a command value for a voltage to be outputted by the plurality of arms (100); controls the circulating current for each of the leg circuits (100u, 100v, 100w); makes a correction, with a voltage command correction value (ΔVarm), when a voltage total value (Vcu, Vcv, Vcw) of a direct current capacitor (111C) included in at least one leg circuit (100u, 100v, 100w) is at or above a first threshold value (δ1), so that in said leg circuit (100u, 100v, 100w), the arm output voltage command value (Varm) of one of the arms will come to an upper threshold value (Vcp, Vcn) or below if exceeding the upper threshold value, and will come to a lower threshold value (0 V) or above if being under the lower threshold value; and also corrects the arm output voltage command value (Varm) of the other of the arms on the basis of the correction voltage (ΔVarm).

Description

Power Conversion Device

[0001] The present application relates to a power conversion device.

[0002] In recent years, multilevel converters, which are configured by serially connecting multiple converter cells each equipped with an energy storage element, have been put to practical use in power conversion devices used in high-voltage applications such as power systems. These converters are called modular multilevel converters (MMCs) or cascaded multilevel converters (CMCs), and are used to convert three-phase AC to DC or vice versa.

[0003] A power converter equipped with a capacitor as an energy storage element can suppress voltage fluctuations. However, if the capacitor's capacity is small, the voltage applied to the switching elements that make up the converter cells may exceed the withstand voltage of the switching elements. Therefore, increasing the capacitor's capacity or the withstand voltage of the switching elements increases the cost or size of the power converter.

[0004] To address this issue, Patent Document 1 discloses a method for adjusting the circulating current flowing through the arm units that make up a power conversion device, thereby keeping the average value of the capacitor voltage in each arm unit constant and suppressing the range of fluctuation.

[0005] The applicant also discloses in Patent Document 2 that the arm voltage command value is corrected using the zero-phase sequence voltage command value so that the arm output voltage range is not exceeded.

[0006] JP 2018-196237 A International Publication No. 2021 / 199150

[0007] On the other hand, if the overmodulation is large during a fault or immediately after recovery from the fault, fluctuations in the system voltage to which the power conversion device is connected or imbalances in the capacitor voltages may prevent each arm from outputting the voltage it should be outputting, causing an unexpected current to flow. In this case, the imbalance in the capacitor voltages cannot be resolved, and the power conversion device may not be able to continue operating.

[0008] The present application discloses a technique for solving the above-mentioned problems, and has an object to provide a power conversion device that can quickly balance the imbalance in the arm capacitor voltages.

[0009] The power conversion device disclosed in the present application is a power conversion device including a power converter in which a plurality of leg circuits, each having a positive side arm and a negative side arm connected in series, are connected in parallel, and a connection point between the positive side arm and the negative side arm of the plurality of leg circuits is connected to an AC line of each phase, to perform power conversion between AC and DC of the plurality of phases, and a control device for controlling the power converter, wherein each of the positive side arm and the negative side arm has one or more converter cells connected in series, each of the converter cells having a series body in which a plurality of semiconductor switching elements are connected in series and a DC capacitor connected in parallel to the series body, and the control device has a valve branch output voltage command value generation unit that generates valve branch output voltage command values ​​that are command values ​​for voltages output by the plurality of valve branches, and performs circulating current control for each of the leg circuits, When the total value of the voltages of all the DC capacitors included in at least one of the leg circuits is equal to or greater than a predetermined first threshold, a voltage command correction value is generated to correct the arm output voltage command value of one of the positive side arm and the negative side arm in the leg circuit so that the arm output voltage command value of the one of the positive side arm and the negative side arm in the leg circuit becomes equal to or less than a predetermined upper threshold if the arm output voltage command value exceeds a predetermined upper threshold, or so that the arm output voltage command value of the one of the positive side arm and the negative side arm in the leg circuit becomes equal to or greater than the predetermined lower threshold if the arm output voltage command value is below a predetermined lower threshold, and the arm output voltage command value of the other arm of the leg circuit in which circulating current control is being performed is corrected based on the voltage command correction value.

[0010] According to the power conversion device of the present disclosure, it is possible to quickly balance the imbalance in the arm capacitor voltages.

[0011] 8A is a schematic diagram showing the configuration of a power conversion apparatus according to embodiment 1. FIG. 8B is a configuration diagram showing an example of a converter cell that constitutes the power conversion apparatus according to embodiment 1. FIG. 8C is a configuration diagram showing another example of a converter cell that constitutes the power conversion apparatus according to embodiment 1. FIG. 8D is a functional block diagram showing the configuration of a control apparatus according to embodiment 1. FIG. 8E is a diagram showing a state in which a generated modulation signal is input to a gate signal generation unit. FIG. 8F is a functional block diagram showing the configuration of a command generation unit of the control apparatus according to embodiment 1. FIG. 8G is a diagram showing the configuration of a voltage command value correction unit according to embodiment 1. FIG. 8H is a diagram showing the configuration of a correction voltage calculation unit according to embodiment 1. FIG. 8I is a diagram for explaining the effect of the power conversion apparatus according to embodiment 1. FIG. 8I is an enlarged view of areas A and B in dashed lines A and B in FIG. 8A. FIG. 8I is a functional block diagram showing the configuration of a command generation unit of a control apparatus according to embodiment 2. FIG. 8H is a diagram showing the configuration of a voltage command value correction unit according to embodiment 2. FIG. 8I is a diagram showing the configuration of a correction voltage calculation unit according to embodiment 2. FIG. 8I is a diagram for explaining the correction margin of a correctable voltage calculated by the correction voltage calculation unit. FIG. 8I is a diagram showing the configuration of a correction zero-phase sequence voltage calculation unit according to embodiment 2. FIG. 8I is a hardware configuration diagram that is an example of the control apparatus according to embodiments 1 and 2.

[0012] The present embodiment will be described below with reference to the drawings, in which the same reference numerals indicate the same or corresponding parts.

[0013] Embodiment 1. A power conversion device according to embodiment 1 will be described below with reference to the drawings. <Configuration of Power Conversion Device> FIG. 1 is a diagram showing a schematic configuration of an example of a power system to which a power conversion device 1 according to embodiment 1 is applied. As shown in FIG. 1, the power conversion device 1 includes a power converter 10, which is a main circuit, and a control device 20, which serves as a control unit for controlling the power converter 10. The power converter 10 converts power between AC and DC. Its AC side is connected to an AC power source 2, which is a three-phase AC system with multiple phases of AC, via a transformer 3, and its DC side is connected to a DC system (not shown) via a positive DC terminal 6P and a negative DC terminal 6N. The DC system may be, for example, a DC power source such as a large-scale solar power generation system or an industrial UPS (Uninterruptible Power Supply), or another power converter.

[0014] The power converter 10 includes three leg circuits 100u, 100v, and 100w, each corresponding to a U-phase, V-phase, and W-phase of a three-phase AC current, connected in parallel between a positive-side DC terminal 6P and a negative-side DC terminal 6N. The leg circuit 100u includes a pair of arms, a positive-side arm 100uP and a negative-side arm 100uN, which are connected in series with each other. One end of the positive-side arm 100uP is connected to the positive-side DC terminal 6P, and one end of the negative-side arm 100uN is connected to the negative-side DC terminal 6N. A connection point 4u between the positive-side arm 100uP and the negative-side arm 100uN is connected to the U-phase terminal of the transformer 3.

[0015] The leg circuit 100v has a pair of arms, a positive arm 100vP and a negative arm 100vN, which are connected in series with each other. One end of the positive arm 100vP is connected to the positive DC terminal 6P, and one end of the negative arm 100vN is connected to the negative DC terminal 6N. A connection point 4v between the positive arm 100vP and the negative arm 100vN is connected to the V-phase terminal of the transformer 3.

[0016] The leg circuit 100w has a pair of arms, a positive arm 100wP and a negative arm 100wN, which are connected in series with each other. One end of the positive arm 100wP is connected to the positive DC terminal 6P, and one end of the negative arm 100wN is connected to the negative DC terminal 6N. A connection point 4w between the positive arm 100wP and the negative arm 100wN is connected to the W-phase terminal of the transformer 3.

[0017] The configuration of each leg circuit 100u, 100v, 100w will be described below. Because the V-phase and W-phase leg circuits 100v, 100w have the same configuration as the U-phase leg circuit 100u, the U-phase leg circuit 100u will be used as a representative example for the description. The positive arm 100uP of the leg circuit 100u includes a plurality of converter cells 111 and a reactor 112uP connected in series, and these converter cells 111 and the reactor 112uP are connected in series with each other. Similarly, the negative arm 100uN of the leg circuit 100u includes a plurality of converter cells 111 and a reactor 112uN connected in series, and these converter cells 111 and the reactor 112uN are connected in series with each other. Note that each arm may include only one converter cell 111.

[0018] The reactor 112uP may be located anywhere within the positive arm 100uP, and similarly, the reactor 112uN may be located anywhere within the negative arm 100uN. The inductance values ​​of the reactors 112uP and 112uN may be different from each other, or they may be coupled to reactors of other phases. Furthermore, the reactor 112uP may be provided only within the positive arm 100uP, or the reactor 112uN may be provided only within the negative arm 100uN. In the following description, when it is not necessary to distinguish between the positive arms 100uP, 100vP, and 100wP and the negative arms 100uN, 100vN, and 100wN, they will be referred to as the arm 100, the positive arm 100P, and the negative arm 100N.

[0019] The configuration of the converter cell 111 that constitutes each of the leg circuits 100u, 100v, and 100w will be described below. FIG. 2A is a circuit diagram showing an example of the configuration of the converter cell 111 according to the first embodiment. FIG. 2B is a circuit diagram showing a configuration example of the converter cell 111 according to the first embodiment that is different from that shown in FIG. 2A. FIG. 2C is a circuit diagram showing a configuration example of the converter cell 111 according to the first embodiment that is different from that shown in FIGS. 2A and 2B. The converter cell 111 may use any of the circuit configurations shown in FIGS. 2A to 2C, and each circuit configuration may be combined within the positive arm 100uP and the negative arm 100uN.

[0020] 2A includes a series body of semiconductor switching elements 111U and 111L connected in series with each other, a DC capacitor 111C connected in parallel to the series body as an energy storage element, and a voltage sensor 111S that detects a voltage Vcap of the DC capacitor 111C. The connection point between the semiconductor switching elements 111U and 111L is connected to a positive input / output terminal 111a, and the connection point between the semiconductor switching element 111L and the DC capacitor 111C is connected to a negative input / output terminal 111b.

[0021] In the converter cell 111 having the configuration shown in Figure 2A, the semiconductor switching elements 111U and 111L are controlled by gate signals GU and GL so that one is turned on and the other is turned off. When the semiconductor switching element 111U is turned on and the semiconductor switching element 111L is turned off, the voltage across the DC capacitor 111C is applied between the input / output terminals 111a and 111b. A positive voltage is applied to the input / output terminal 111a, and a negative voltage is applied to the input / output terminal 111b.

[0022] 2B includes a series body of semiconductor switching elements 111U and 111L connected in series to each other, a DC capacitor 111C as an energy storage element connected in parallel to the series body, and a voltage sensor 111S that detects a voltage value Vcap of the DC capacitor 111C. The connection point between the semiconductor switching elements 111U and 111L is connected to a negative input / output terminal 111b, and the connection point between the semiconductor switching element 111U and the DC capacitor 111C is connected to a positive input / output terminal 111a.

[0023] In the converter cell 111 having the configuration shown in Figure 2B, the semiconductor switching elements 111U and 111L are controlled by gate signals GU and GL so that one is turned on and the other is turned off. When the semiconductor switching element 111U is in the off state and the semiconductor switching element 111L is in the on state, the voltage across the DC capacitor 111C is applied between the input / output terminals 111a and 111b. A positive voltage is applied to the input / output terminal 111a, and a negative voltage is applied to the input / output terminal 111b.

[0024] 2C includes a series body of semiconductor switching elements 111U1 and 111L1 connected in series to each other, a series body of semiconductor switching elements 111U2 and 111L2 connected in series to each other, a DC capacitor 111C as an energy storage element, and a voltage sensor 111S that detects a voltage Vcap of the DC capacitor 111C. The series body of semiconductor switching elements 111U1 and 111L1, the series body of semiconductor switching elements 111U2 and 111L2, and the DC capacitor 111C are connected in parallel.

[0025] In the converter cell 111 configured as shown in FIG. 2C , semiconductor switching elements 111U1 and 111L1 are controlled by gate signals GU1 and GL1 so that one is turned on and the other is turned off. Similarly, semiconductor switching elements 111U2 and 111L2 are controlled by gate signals GU2 and GL2 so that one is turned on and the other is turned off. When semiconductor switching element 111U1 is on and semiconductor switching element 111L1 is off, and when semiconductor switching element 111U2 is off and semiconductor switching element 111L2 is on, the voltage across DC capacitor 111C is applied between input / output terminals 111a and 111b. Note that a positive voltage is applied to input / output terminal 111a, and a negative voltage is applied to input / output terminal 111b.

[0026] Furthermore, the power conversion device 1 includes, in addition to the voltage sensor 111S that detects the DC capacitor voltage Vcap, a plurality of detectors that detect the voltage and current of the power converter 10. As shown in Fig. 1 , values ​​detected by these detectors are input to the control device 20. That is, the following are input to the control device 20: phase voltages Vacu, Vacv, and Vacw at the AC ends of the power converter 10; currents Iacu, Iacv, and Iacw at the AC ends; a DC voltage Vdc between the positive side DC terminal 6P and the negative side DC terminal 6N; a DC current Idc flowing through the positive side DC terminal 6P or the negative side DC terminal 6N; currents IuP, IvP, and IwP flowing through the positive side arms 100uP, 100vP, and 100wP; currents IuN, IvN, and IwN flowing through the negative side arms 100uN, 100vN, and 100wN; and a voltage Vcap of the DC capacitor 111C.

[0027] Next, a description will be given of the configuration of the control device 20. The control device 20 generates gate signals GU and GL that drive the semiconductor switching elements 111U and 111L in the converter cells 111 of the power converter 10, based on the detection values ​​detected by the detectors.

[0028] 3 is a functional block diagram showing the configuration of the main parts of the control device 20 according to embodiment 1. As shown in FIG. 3, the control device 20 includes a DC control unit 21, an AC current control unit 22, a circulating current control unit 23, a command value generation unit 24, and an arm capacitor voltage average value calculation unit 25.

[0029] The DC control unit 21 receives as input the DC voltage Vdc between the positive side DC terminal 6P and the negative side DC terminal 6N of the power converter 10, and the DC current Idc flowing through the positive side DC terminal 6P or the negative side DC terminal 6N. The DC control unit 21 also receives as input a DC voltage command value Vdcref and a DC current command value Idcref. The DC control unit 21 outputs an arm DC component voltage command value VarmDC such that the DC voltage Vdc follows the DC voltage command value Vdcref or the DC current Idc follows the DC current command value Idcref.

[0030] The AC current control unit 22 receives as input the AC current Iac at the AC end of the power converter 10 (when the AC end currents Iacu, Iacv, and Iacw are collectively referred to, the AC current Iac) and an AC voltage command value Iacref that controls the AC voltage of each phase (the AC voltage command value Iacref is used as a collective term for the AC voltage command values ​​of the U phase, V phase, and W phase). The AC current control unit 22 outputs an arm AC component voltage command value VarmAC that causes the AC current Iac to follow the AC current command value Iacref.

[0031] The circulating current control unit 23 outputs an arm circulating voltage command value Varmcc for controlling the circulating current Icc to follow the circulating current command value Iccref for balancing the voltage of the DC capacitor 111C included in each arm 100 between the arms 100. Here, the circulating current Icc indicates a current that does not flow through the AC end or the DC end in the power converter 10, but flows between the phase leg circuits 100u, 100v, and 100w.

[0032] The arm capacitor voltage average value calculation unit 25 calculates the average value of the voltage of the DC capacitor in each arm. Each arm capacitor total value Vcpu, Vcnu, Vcpv, Vcnv, Vcpw, Vcnw, which is the sum of the voltages Vcap of the DC capacitors 111C in the converter cells 111 provided in each arm, is input to the arm capacitor voltage average value calculation unit 25, and average values ​​Vcarmpu, Vcarmnu, Vcarmpv, Vcarmnv, Vcarmpw, Vcarmnw of each arm capacitor voltage, which are values ​​divided by the number N (N is an integer of 1 or more) of converter cells provided in each arm, are output. Note that when the arm capacitor total value is referred to collectively, the arm capacitor voltage total value Vc is used, and when the arm capacitor voltage average value is referred to collectively, the arm capacitor voltage average value Vcarm is used.

[0033] The command value generating unit 24 receives as input an arm DC component voltage command value VarmDC from the DC control unit 21, an arm AC component voltage command value VarmAC from the AC current control unit 22, an arm circulating voltage command value Varmcc from the circulating current control unit 23, and an average value Vcarm of the capacitor voltages of each arm from an arm capacitor voltage average value calculating unit 25. Details of the command value generating unit 24 will be described later, but the command value generating unit 24 outputs a modulation command kref for each arm (the modulation command kref for the arm is used as a general term for the modulation commands krefpu, krenu, krefpv, krefnv, krefpw, and krenw for the arms).

[0034] 4 is a diagram showing a state in which the modulation command kref for each arm generated and output by the command value generation unit 24 is input to the gate signal generation unit 26. The modulation command kref for each arm is input to the gate signal generation unit 26, and the gate signal generation unit 26 generates gate signals G (G1U, G1L, G2U, G2L, G3U, G3L, ...) that drive the semiconductor switching elements 111U, 111L included in all the converter cells 111 of the corresponding arm 100. The gate signal generation unit 26 obtains the gate signals G, for example, by a pulse width modulation (PWM) method that compares the magnitude of the input modulation command kref for the arm with a carrier wave.

[0035] The multiple gate signal generating units 26 may be provided in the control device 20 as a subsequent stage of the command value generating unit 24, but each gate signal generating unit 26 may also be configured to be included in each converter cell 111.

[0036] Next, a description will be given of the configuration of the command value generating unit 24. Fig. 5 is a functional block diagram showing the configuration of the command generating unit 24. As shown in Fig. 5, the command value generating unit 24 includes an arm output voltage command value generating unit 244, a voltage command value correcting unit 240, and a normalizing unit 246.

[0037] The arm DC component voltage command value VarmDC, the arm AC component voltage command value VarmAC, and the arm circulating voltage command value Varmcc are input to the arm output voltage command value generation unit 244, which calculates the voltages to be output by each arm and outputs them as arm output voltage command values ​​Varmpu, Varmnu, Varmpv, Varmnv, Varmpw, and Varmnw.

[0038] The voltage command value corrector 240 includes voltage command value correctors 240U, 240V, and 240W corresponding to the respective phases, and corrects the voltage output from the arm by referring to the average voltage Vcarm of the capacitor voltages in each arm (when the total voltage Vc of the capacitors in the arm is used, it is calculated by Vc = Vcarm × N), thereby correcting the arm output voltage command value. FIG. 6 is a diagram showing the configuration of the voltage command value corrector 240 included in the command generator 24. As shown in FIG. 6, the voltage command value corrector 240 includes a correction voltage calculator 241. FIG. 7 is a diagram showing the configuration of the correction voltage calculator 241. FIGS. 6 and 7 will be described using the U-phase voltage command value corrector 240U as an example of the voltage command value corrector.

[0039] A correction voltage calculation unit 241U of the U-phase voltage command value correction unit 240U receives as input a positive arm output voltage command value Varmpu, a negative arm output voltage command value Varmnu, a positive arm capacitor voltage sum Vcpu, a negative arm capacitor voltage sum Vcnu, and a determination signal CCprModeU indicating whether the power converter 10 is in the circulating current priority mode. In the correction voltage calculation unit 241, adders 2411p, 2413p, 2415p, 2416p, 2417, 2411n, 2413n, 2415n, and 2416n add and output the input signals, and filters 2412p, 2414p, 2412n, and 2414n output 0 when the input signals are 0 or less, and output the corresponding values ​​when the input signals are greater than 0. Multiplier 2418 receives a CCprModeU of 1 when power converter 10 is in the circulating current priority mode, and a CCprModeU of 0 when power converter 10 is not in the circulating current priority mode.

[0040] The circulating current priority mode is a mode in which, when the sum of all capacitor voltages included in one leg circuit exceeds a predetermined threshold (δ1) and the arm included in that leg circuit is overmodulated, the output voltage of the arm is corrected to prioritize the output of circulating current control. As shown in FIG. 6 , each arm capacitor voltage average value Vcarmpu, Vcarmnu is input to the U-phase voltage command value corrector 240U. That is, the positive arm capacitor voltage sum Vcpu and the negative arm capacitor voltage sum Vcnu are input. Therefore, the U-phase capacitor voltage sum Vcu (= Vcpu + Vcnu), obtained by adding both, is compared with the threshold (δ1) in the filter 242U. If the sum is equal to or greater than the threshold (δ1), the output of the circulating current priority mode determination signal CCprModeU is set to 1. When the U-phase capacitor voltage sum Vcu is below the threshold value (δ1) in the filter 242U, the output of the circulating current priority mode determination signal CCprModeU is set to 0. In this way, it is determined whether the circulating current priority mode is active, and the circulating current priority mode determination signal CCprModeU is output.

[0041] When the circulating current priority mode determination signal CCprModeU is 0, in FIG. 5, the valve branch output voltage command value generation unit 244 generates the valve branch output voltage command value Varm without considering the valve branch circulating voltage command value Varmcc.

[0042] The threshold value (δ1) is preferably set to a value equal to or greater than half of the DC voltage Vdc between the positive-side DC terminal 6P and the negative-side DC terminal 6N of the power converter 10. When the total value of all capacitor voltages included in one leg circuit is smaller than half of the DC inter-terminal voltage Vdc, it is necessary to charge the entire capacitor voltage, but performing a correction that prioritizes circulating current output affects the grid side (AC side), which may prevent sufficient charging.

[0043] The operation of the correction voltage calculation unit 241U will be described for the following five cases: (1) In the positive arm, when the positive arm capacitor voltage sum Vcpu is greater than the positive arm output voltage command value Varmpu (Vcpu>Varmpu) and the negative arm capacitor voltage sum Vcnu is greater than the negative arm output voltage command value Varmnu (Vcnu>Varmnu), that is, when overmodulation is not occurring, the positive arm output voltage command correction value ΔVarmpu output from the adder 2416p and the negative arm output voltage command correction value ΔVarmnu output from the adder 2416n are both 0, and a voltage command correction value ΔVarmu=0 is output from the correction voltage calculation unit 241.

[0044] (2) In the positive arm, in the case of overmodulation in which the positive arm output voltage command value Varmpu is larger than the total capacitor voltage value Vcpu in the positive arm (Vcpu<Varmpu), the adder 2416p outputs a positive arm output voltage command correction value ΔVarmpu (≠0). At this time, if the total capacitor voltage value (Vcpu+Vcnu) in the U-phase leg circuit 100u is larger than a preset threshold value δ1, 1 is input to the multiplier 2418 as a CCprModeU signal, and the multiplier 2418 outputs a voltage command correction value ΔVarmu. On the other hand, if the total capacitor voltage value (Vcpu+Vcnu) in the U-phase leg circuit 100u is equal to or less than the preset threshold value δ1, it is determined that there is a margin for the capacitor voltage, 0 is input to the multiplier 2418 as the CCprModeU signal, and the correction voltage calculation unit 241 outputs the voltage command correction value ΔVarmu=0.

[0045] (3) Similarly, in the negative arm, in the case of overmodulation in which the negative arm output voltage command value Varmnu is larger than the negative arm capacitor voltage sum value Vcnu (Vcnu<Varmnu), the adder 2416n outputs a negative arm output voltage command correction value ΔVarmnu (≠0). At this time, if the capacitor voltage sum value (Vcpu+Vcnu) in the U-phase leg circuit 100u is larger than a preset threshold value δ1, a signal CCprModeU of 1 is input to the multiplier 2418, and the multiplier 2418 outputs a voltage command correction value ΔVarmu. On the other hand, if the total capacitor voltage value (Vcpu+Vcnu) in the U-phase leg circuit 100u is equal to or less than the preset threshold value δ1, it is determined that there is a margin for the capacitor voltage, 0 is input to the multiplier 2418 as the CCprModeU signal, and the correction voltage calculation unit 241 outputs the voltage command correction value ΔVarmu=0.

[0046] (4) In the positive arm, when the positive arm output voltage command value Varmpu is less than 0 (Varmpu<0), the adder 2416p outputs a positive arm output voltage command correction value ΔVarmpu (≠0). At this time, when the total capacitor voltage value (Vcpu+Vcnu) in the U-phase leg circuit 100u is greater than a preset threshold δ1, a signal CCprModeU of 1 is input to the multiplier 2418, and a voltage command correction value ΔVarmu is output. On the other hand, when the total capacitor voltage value (Vcpu+Vcnu) in the U-phase leg circuit 100u is equal to or less than the preset threshold δ1, it is determined that there is a margin in the capacitor voltage, a CCprModeU signal of 0 is input to the multiplier 2418, and a voltage command correction value ΔVarmu=0 is output from the correction voltage calculation unit 241.

[0047] (5) In the negative arm, when the negative arm output voltage command value Varmnu is less than 0 (Varmnu<0), the adder 2416n outputs a negative arm output voltage command correction value ΔVarmnu (≠0). At this time, when the total capacitor voltage value (Vcpu+Vcnu) in the U-phase leg circuit 100u is greater than a preset threshold δ1, 1 is input as a CCprModeU signal to the multiplier 2418, and the voltage command correction value ΔVarmu is output. On the other hand, when the total capacitor voltage value (Vcpu+Vcnu) in the U-phase leg circuit 100u is equal to or less than the preset threshold δ1, it is determined that there is a margin in the capacitor voltage, 0 is input as a CCprModeU signal to the multiplier 2418, and the correction voltage calculation unit 241 outputs a voltage command correction value ΔVarmu=0.

[0048] That is, in the correction voltage calculation unit 241, if the arm output voltage command value on one side of the corresponding phase exceeds the arm capacitor voltage total value on that side, and if the arm output voltage command value is less than 0 V, the correction voltage calculation unit 241 outputs a correction voltage if the circulating current priority mode is in effect.

[0049] 6 , the voltage command correction value ΔVarmpu output from the correction voltage calculation unit 241 is subtracted from the positive arm output voltage command value Varmpu to output a corrected positive arm output voltage command value Varmpu*. Also, the voltage command correction value ΔVarmpu is added to the negative arm output voltage command value Varmnu to output a corrected negative arm output voltage command value Varmnu*.

[0050] The corrected valve branch output voltage command values ​​Varmpu*, Varmnu*, Varmpv*, Varmnv*, Varmpw*, and Varmnw* (when collectively referred to, the valve branch output voltage command value Varm*) for each phase output from the voltage command value correction unit 240 are input to a normalization unit 246.

[0051] In FIG. 5, a normalization unit 246 normalizes the corrected output voltage command value of each arm output from the voltage command value correction unit 240 based on the total capacitor voltage value of each arm, and outputs a modulation command kref for each arm.

[0052] 6 and 7 , it has been shown that the arm output voltage command value is corrected using the voltage command correction value ΔVarmu calculated by the correction voltage calculation unit 241. Specific details and effects of the correction will now be described using Fig. 8A and Fig. 8B. Fig. 8A is a diagram for explaining the effects of the power conversion device according to the first embodiment, and Fig. 8B is an enlarged view of the areas surrounded by dotted lines A and B in Fig. 8A.

[0053] FIG. 8A shows the behavior of the positive arm capacitor voltage sum Vcpu, positive arm output voltage command Varmpu, negative arm capacitor voltage sum Vcnu, and negative arm output voltage command Varmnu in the U-phase leg circuit 100u. An accident occurs at time t0, and an overmodulation state occurs immediately thereafter. At this time, in the negative arm, the negative arm output voltage command Varmnu increases and exceeds the negative arm capacitor voltage sum Vcnu. This period is indicated by the dotted line A in the figure. Meanwhile, in the positive arm, even if the positive arm output voltage command Varmpu oscillates, it never exceeds the positive arm capacitor voltage sum Vcpu. The dotted line B indicates the positive arm region at the same time corresponding to the dotted line A region of the negative arm. Note that the U-phase leg circuit 100u is in circulating current priority mode. 7, in the positive arm, the upper threshold of the positive arm output voltage command value Varmpu is the sum of the capacitor voltages in the positive arm Vcpu, and in the negative arm, the upper threshold of the negative arm output voltage command value Varmnu is the sum of the capacitor voltages in the negative arm Vcnu.

[0054] 8B, the negative arm output voltage command value Varmnu exceeds the sum of the capacitor voltages in the negative arm Vcnu in the region indicated by dotted line A. The negative arm output voltage command value Varmnu that exceeds this sum of the capacitor voltages in the negative arm Vcnu is indicated by a broken line. Here, the negative arm output voltage command value Varmnu is corrected by the voltage command correction value ΔVarmu so that it falls within a range that does not exceed the sum of the capacitor voltages in the negative arm Vcnu. The corrected negative arm output voltage command value Varmnu* is equal to the sum of the capacitor voltages in the negative arm Vcnu.

[0055] On the other hand, because the circulating current priority mode is in effect, the corresponding positive arm is corrected by the voltage command correction value ΔVarmu so that the total output voltage value in leg circuit 100u becomes equal before and after the correction so that the positive and negative capacitor voltages are balanced. Therefore, within the region of dotted line B, the positive arm output voltage command value Varmpu shown by the dashed line becomes the corrected positive arm output voltage command value Varmpu* shown by the solid line.

[0056] In this way, in circulating current priority mode, the correction voltage is used to make the output voltage of the arm that is overmodulated equal to the output range, which is the sum of the capacitor voltages, and the output voltage of the other arm is also corrected, so that the total output voltage of the two arms in one leg circuit does not change before and after correction. This makes it possible to control the desired circulating current even during overmodulation.

[0057] As described above, according to the first embodiment, a power conversion device is provided which includes a power converter in which a plurality of leg circuits, each having a positive side arm and a negative side arm connected in series, are connected in parallel, and connection points between the positive side arms and the negative side arms of the plurality of leg circuits are connected to AC lines of each phase, thereby converting power between AC and DC of multiple phases, and a control device which controls the power converter, and in which each arm is configured by series-connected converter cells, each having a series body in which a plurality of semiconductor switching elements are connected in series, and a DC capacitor connected in parallel to the series body. The control device includes a valve branch output voltage command value generator that generates valve branch output voltage command values, which are command values ​​for voltages output from multiple valve branches. The control device performs circulating current control for each of the leg circuits. When the sum of the voltages of all DC capacitors included in at least one leg circuit is equal to or greater than a predetermined first threshold (δ1), the control device generates a correction voltage to correct the valve branch output voltage command value of one of the legs in the leg circuit. If the valve branch output voltage command value of one of the legs exceeds a predetermined upper threshold, the correction voltage is set to be equal to or less than the upper threshold. If the valve branch output voltage command value of one of the legs is below a predetermined lower threshold, the correction voltage is set to be equal to or greater than the lower threshold. The control device also corrects the valve branch output voltage command value of the other arm based on the correction voltage. This configuration corrects the output voltage command values ​​of both arms with the correction voltage, thereby making the total output voltages equal and facilitating circulating current control. This allows for quick balancing of capacitor voltages between the arms during a fault or immediately after recovery from the fault.

[0058] Furthermore, when the voltage is equal to or greater than the first threshold, the circulating current priority mode is set, and the output voltage of the arm that is overmodulated is corrected so as to prioritize the circulating current control output, so that by functioning only when the capacitor voltage is equal to or greater than a certain level, it is possible to exert an effect only on the capacitor voltage imbalance between the arms. If the first threshold is set to be equal to or greater than half the DC voltage of the power converter, the output voltage of the arm can be corrected so as to prioritize the circulating current control output only when necessary in response to the capacitor voltage imbalance between the arms.

[0059] Since the possible output range of the arm output voltage is from 0 V to the total value of the capacitor voltages of the arm, the range of the arm output voltage can be maximized by setting the upper threshold for overmodulation to the total value of the capacitor voltages of the arm and setting the upper threshold to 0 V.

[0060] Second Embodiment A power conversion device according to a second embodiment will be described below with reference to the drawings. The power conversion device according to the second embodiment includes a control device 20 similar to that shown in FIG. 3, but the configuration of the command generation unit 24 differs from that of the first embodiment. The following description will focus on the differences from the first embodiment, and a description of the corresponding parts will be omitted.

[0061] Fig. 9 is a functional block diagram showing the configuration of the command generating unit 24 included in the control device 20 according to embodiment 2. As shown in Fig. 9, the command generating unit 24 includes a valve branch output voltage command value generating unit 244, a voltage command value correcting unit 1240, and a normalizing unit 246. The valve branch output voltage command value generating unit 244 and the normalizing unit 246 are the same as those shown in Fig. 5 of embodiment 1.

[0062] Fig. 10 is a diagram showing the configuration of the voltage command value corrector 1240. As shown in Fig. 10, the voltage command value corrector 1240 includes correction voltage calculators 1241 for each phase, namely, a U-phase correction voltage calculator 1241U, a V-phase correction voltage calculator 1241V, and a W-phase correction voltage calculator 1241W, as well as a correction zero-phase voltage calculator 1242 and various computing units. Fig. 11 is a diagram showing the configuration of the correction voltage calculators 1241 for each phase, and Fig. 13 is a diagram showing the configuration of the correction zero-phase voltage calculator 1242. Note that the correction voltage calculator 1241 is used as a general term for the U-phase correction voltage calculator 1241U, the V-phase correction voltage calculator 1241V, and the W-phase correction voltage calculator 1241W.

[0063] First, the configuration of the correction voltage calculation unit 1241 for each phase will be described, but the correction voltage calculation unit 1241 in Fig. 11 is assumed to be a U-phase correction voltage calculation unit 1241U, and the description will be given using a U-phase signal. Note that the correction voltage calculation unit 1241 in Fig. 11 has a similar configuration to the correction voltage calculation unit 241 for each phase shown in Fig. 7 of the first embodiment, and the input signals are the same but the output signals are partially different.

[0064] 11 , a U-phase correction voltage calculation unit 241U receives as input a positive arm output voltage command value Varmpu, a negative arm output voltage command value Varmnu, a positive arm capacitor voltage sum Vcpu, a negative arm capacitor voltage sum Vcnu, and a determination signal CCprModeU indicating whether the power converter 10 is in the circulating current priority mode. Although FIGS. 10 and 11 show that the determination signal CCprModeU is input, as described in FIG. 6 of the first embodiment, the determination signal CCprModeU is generated by comparing the sum Vcu of the positive arm capacitor voltage sum Vcpu and the negative arm capacitor voltage sum Vcnu with a threshold value (δ1). The generation of the determination signal CCprModeU is omitted in FIGS. 10 and 11 .

[0065] In the U-phase correction voltage calculation unit 1241U, adders 2411p, 2413p, 2416p, 2417, 2411n, 2413n, 2415n, and 2416n output the differences between the input signals, and filters 2412p, 2414p, 2412n, and 2414n output 0 when the input signal is equal to or less than 0, and output the corresponding value when the input signal is greater than 0. A multiplier 2418 receives an input of 1 when the power converter 10 is in the circulating current priority mode, and receives an input of 0 when the power converter 10 is not in the circulating current priority mode. Here, the circulating current priority mode is a mode in which the circulating current is controlled to follow a circulating current command value when the total value of all capacitor voltages included in one leg circuit becomes equal to or greater than a predetermined threshold, thereby balancing the output voltages of the positive and negative arms in the leg circuit.

[0066] The following cases (1) to (5) are similar to those in Fig. 7 of the first embodiment, and therefore their explanation will be simplified. (1) In the positive arm, when the positive arm capacitor voltage sum value Vcpu is greater than the positive arm output voltage command value Varmpu (Vcpu>Varmpu) and the negative arm capacitor voltage sum value Vcnu is greater than the negative arm output voltage command value Varmnu (Vcnu>Varmnu), that is, when overmodulation is not occurring, a voltage command correction value ΔVarmu=0 is output.

[0067] (2) In the positive arm, in the case of overmodulation in which the positive arm output voltage command value Varmpu is greater than the positive arm capacitor voltage sum Vcpu (Vcpu<Varmpu), when the CCprModeU signal is 1, a voltage command correction value ΔVarmu (≠0) is output. On the other hand, when the CCprModeU signal is 0, a voltage command correction value ΔVarmu=0 is output.

[0068] (3) Similarly, in the negative arm, in the case of overmodulation in which the negative arm output voltage command value Varmnu is greater than the negative arm capacitor voltage sum value Vcnu (Vcnu<Varmnu), a voltage command correction value ΔVarmu (≠0) is output when the CCprModeU signal is 1. On the other hand, when the CCprModeU signal is 0, a voltage command correction value ΔVarmu=0 is output.

[0069] (4) In the positive arm, when the positive arm output voltage command value Varmpu is less than 0 (Varmpu<0), a voltage command correction value ΔVarmu (≠0) is output when CCprModeU is 1. On the other hand, when the CCprModeU signal is 0, a voltage command correction value ΔVarmu=0 is output.

[0070] (5) In the negative arm, when the negative arm output voltage command value Varmnu is less than 0 (Varmnu<0), a voltage command correction value ΔVarmu (≠0) is output when the CCprModeU signal is 1. On the other hand, when the CCprModeU signal is 0, a voltage command correction value ΔVarmu=0 is output.

[0071] That is, in the correction voltage calculation unit 1241, if the arm output voltage command value on one side of the corresponding phase exceeds the arm capacitor voltage total value on that side or if the arm output voltage command value is less than 0 V, then in the circulating current priority mode, the correction voltage calculation unit 1241 outputs a voltage command correction value ΔVarm.

[0072] Furthermore, correction voltage calculation unit 1241 of the second embodiment calculates the voltage range in which correction can be performed for each arm as a correction margin. FIG. 12 is a diagram for explaining the voltage correction margin, showing the behavior of the U-phase positive arm output voltage command value Varmpu. In FIG. 12, σUpu is the U-phase positive arm upper-side correction margin, which is the value obtained by dividing the positive arm capacitor voltage sum Vcpu by the positive arm output voltage command value Varmpu. Furthermore, σLpu is the U-phase positive arm lower-side correction margin, which is the value of the positive arm output voltage command value Varmpu. However, since these are the outputs of filters 2412p and 2414p in FIG. 11, σUpu and σLpu are 0 when they are less than 0. That is, in the case of overmodulation in the above case (2) where the positive arm output voltage command value Varmpu is larger than the positive arm capacitor voltage sum Vcpu, the U-phase positive arm upper-side correction tolerance σUpu is 0. In the above case (4) where the positive arm output voltage command value Varmpu is <0, the U-phase positive arm lower-side correction tolerance σLpu is 0.

[0073] 11, a U-phase negative arm upper-side correction margin σUnu and a U-phase negative arm lower-side correction margin σLnu are also calculated. Similarly, a V-phase correction voltage calculation unit 1241V and a W-phase correction voltage calculation unit 1241W output a voltage command correction value ΔVarmv and correction margins σUpv, σLpv, σUnv, and σLnv, and a voltage command correction value ΔVarmw and correction margins σUpw, σLpw, σUnw, and σLnw, respectively.

[0074] Next, the correction zero-sequence voltage calculation unit 1242 will be described with reference to FIG. 13 . As shown in FIG. 13 , the correction voltage and correction margin for each phase, which are the outputs of the correction voltage calculation unit 1241 for each phase, are input to the correction zero-sequence voltage calculation unit 1242, and a correction zero-sequence voltage ΔVz is output. When the output voltage command value of any arm needs to be corrected, the correction is performed using the correction zero-sequence voltage ΔVz. As a result, if the AC system voltage is insulated by a transformer or the like, no change occurs in the phase-to-phase voltage, and overmodulation can be prevented without affecting the system side. However, because the zero-sequence voltage is a common component of the AC voltage output by each phase, the correction zero-sequence voltage ΔVz is used for correction in all arms. If the correction zero-sequence voltage ΔVz is large, there is a possibility that overmodulation will occur in other arms that are not experiencing overmodulation. To prevent this, the correction zero-sequence voltage calculation unit 1242 of the second embodiment sets a limit value for the correction zero-sequence voltage ΔVz based on the correction margin of the correction voltage of each arm, and calculates the correction zero-sequence voltage ΔVz.

[0075] A filter 2421 detects the maximum value from the voltage command correction values ​​ΔVarmu, ΔVarmv, and ΔVarmw of each phase input to the corrected zero-phase sequence voltage calculation unit 1242, and a filter 2422 detects the minimum value. The detected maximum and minimum values ​​are added together and input to a limiter 2423. The limiter 2423 limits the input value to a maximum value ΔVzLIMH and a minimum value ΔVzLIML. The maximum value ΔVzLIMH and minimum value ΔVzLIML of the limiter 2423 are calculated as follows.

[0076] When the correction zero-phase voltage ΔVz is positive, the negative arm upper correction margins σUnu, σUnv, and σUnw of each phase and the positive arm lower correction margins σLpu, σLpv, and σLpw of each phase decrease. That is, as a result of correction using the correction zero-phase voltage ΔVz, any of σUnu, σUnv, σUnw, σLpu, σLpv, and σLpw may become equal to or less than 0, which may cause overmodulation in an arm other than the correction arm. Therefore, it is necessary to limit the positive side value of the correction zero-phase voltage ΔVz to the minimum value of σUnu, σUnv, σUnw, σLpu, σLpv, and σLpw.

[0077] Therefore, the filter 2424 detects the minimum value from the negative arm upper correction margins σUnu, σUnv, σUnw of each phase and the positive arm lower correction margins σLpu, σLpv, σLpw of each phase among the correction margins of the correction voltages of each arm input to the corrected zero-phase sequence voltage calculation unit 1242, and sets the detected value as the maximum value ΔVzLIMH of the limiter 2423.

[0078] When the correction zero-sequence voltage ΔVz is negative, the positive-side arm upper-side correction margins σUpu, σUpv, and σUpw of each phase and the negative-side arm lower-side correction margins σLnu, σLnv, and σLnw of each phase decrease. That is, as a result of correction using the correction zero-sequence voltage ΔVz, any of σUpu, σUpv, σUpw, σLnu, σLnv, and σLnw may become equal to or less than 0, which may result in overmodulation in an arm other than the correction arm. Therefore, it is necessary to limit the negative value of the correction zero-sequence voltage ΔVz to a value obtained by multiplying the minimum value of σUpu, σUpv, σUpw, σLnu, σLnv, and σLnw by −1.

[0079] Therefore, a filter 2425 detects the minimum value from the positive arm upper correction margins σUpu, σUpv, σUpw of each phase and the negative arm lower correction margins σLnu, σLnv, σLnw of each phase among the correction margins of the correction voltages of each arm input to the corrected zero-phase sequence voltage calculation unit 1242, and an inversion circuit 2426 inverts the sign of the detected value to obtain the minimum value ΔVzLIML of the limiter 2423.

[0080] 10 , a method for calculating the corrected positive arm output voltage command value Varmpu* and the corrected negative arm output voltage command value Varmnu* will be described using the U phase as an example. Note that the U phase is a phase that includes an arm that is subject to overmodulation correction.

[0081] First, the U phase is a phase that includes an arm that is subject to overmodulation correction, and the other phases are phases that do not include an arm that is subject to overmodulation correction. The corrected zero-sequence voltage ΔVz output from the corrected zero-sequence voltage calculation unit 1242 is input to an adder 1243u and subtracted from the positive arm output voltage command value Varmpu. In addition, the corrected zero-sequence voltage ΔVz is added to the negative arm output voltage command value Varmnu by an adder 1244u.

[0082] The U-phase voltage command correction value ΔVarmu calculated by the U-phase correction voltage calculation unit 1241U is input to a filter 1246u. The filter 1246u outputs 0 to a multiplier 1247u when the input value (input) is 0, and outputs 1 when the input value (input) is other than 0. The adder 1245u subtracts the corrected zero-phase voltage ΔVz from the U-phase voltage command correction value ΔVarmu, and the result is input to the multiplier 1247u. Here, since the U-phase is a phase that includes an arm that is subject to overmodulation correction, the U-phase voltage command correction value ΔVarmu is not 0, and the output of the multiplier 1247u is 1. Therefore, the input from 1247u to adders 1248u and 1249u is ΔVarmu−ΔVz. Therefore, the voltage command value corrector 1240 outputs Varmpu-ΔVarmu as the corrected positive arm output voltage command value Varmpu*, and Varmnu+ΔVarmu as the corrected negative arm output voltage command value Varmnu*.

[0083] Since the other phases do not include arms to be corrected, the outputs of 1246v and 1246w are 0. Therefore, the corrected positive arm output voltage command value Varmpv* for the V phase is Varmpv-ΔVz, and the corrected negative arm output voltage command value Varmnv* for the V phase is Varmnv+ΔVz. Similarly, the corrected positive arm output voltage command value Varmpw* for the W phase is Varmpw-ΔVz, and the corrected negative arm output voltage command value Varmnw* for the W phase is Varmpw+ΔVz.

[0084] By doing this, if the U-phase voltage command correction value ΔVarmu is within the range between the maximum value ΔVzLIMH and the minimum value ΔVzLIML of the corrected zero-phase voltage calculation unit 1242, ΔVz = ΔVarmu, and correction is performed using only the zero-phase voltage component, so no change occurs in the phase-to-phase voltage and no influence is exerted on the grid side. If the U-phase voltage command correction value ΔVarmu exceeds the maximum value ΔVzLIMH (ΔVarmu > ΔVzLIMH), ΔVz = ΔVzLIMH, and correction is not possible using only the zero-phase voltage component. However, since the maximum value ΔVzLIMH of the U-phase voltage command correction value ΔVarmu is corrected using the zero-phase voltage component, changes in the phase-to-phase voltage can be minimized compared to when the zero-phase voltage is not used (when the V-phase and W-phase are not corrected). Furthermore, by correcting only the U-phase with the voltage command correction value ΔVarmu, the voltage for the U-phase circulating current control becomes equal before and after the correction, so the effect on the circulating current control is reduced, contributing to capacitor voltage balance. The same effect is achieved when the voltage command correction value ΔVarmu for the U-phase is below the minimum value ΔVzLIML (ΔVarmu<ΔVzLIML) or when another phase includes an arm to be corrected.

[0085] Although the voltage command value corrector 1240 has been described using the U phase as an example, it can also output corrected positive arm output voltage command values ​​and corrected negative arm output voltage command values ​​for other phases in the same manner.

[0086] 9 , the arm output voltage command values ​​Varmpu*, Varmnu*, Varmpv*, Varmnv*, Varmpw*, and Varmnw* of each phase after correction output from the voltage command value corrector 1240 are input to the normalizer 246. As described in the first embodiment, the normalizer 246 normalizes the output voltage command value of each arm after correction output from the voltage command value corrector 1240 based on the total value of the capacitor voltages of the arms, and outputs a modulation command kref for each arm.

[0087] As described above, according to the second embodiment, the same effects as those of the first embodiment can be achieved. Furthermore, when the circulating current control is performed in all of the plurality of leg circuits, the voltage command correction value ΔVarm corresponding to overmodulation is corrected by the zero-phase-sequence voltage, i.e., the correction zero-phase-sequence voltage that corrects the zero-phase-sequence voltage, so that the influence on the AC side can be suppressed.

[0088] Furthermore, the correction zero-phase sequence voltage used for correction is limited by the tolerances of all arm output voltage command values ​​and the upper and lower thresholds, so that the influence on arms in which overmodulation does not occur can also be suppressed.

[0089] An example of the hardware configuration of the control device 20 in the first and second embodiments is shown in Fig. 14. As shown in Fig. 14, the control device 20 includes, for example, a processor 1000 and a storage device 1100 as processing circuits. The processor 1000 may include a central processing unit (CPU), an application specific integrated circuit (ASIC), an integrated circuit (IC), a field programmable gate array (FPGA), various logic circuits, various signal processing circuits, etc. Furthermore, a plurality of processors 1000 of the same type or different types may be provided, and each process may be shared and executed. The storage device 1100 includes a RAM (Random Access Memory) configured to be able to read and write data from the processor 1000, and a ROM (Read Only Memory) configured to be able to read data from the processor 1000. The processor 1000 executes a program input from the storage device 1100 such as a ROM.

[0090] 4 is not provided in the control device 20 but is included in the converter cell 111, the hardware configuration may be as shown in FIG.

[0091] <Other Embodiments> (1) In Figures 2A to 2C, the semiconductor switching elements 111U and 111L that constitute the converter cell 111 are described as IGBTs (Insulated Gate Bipolar Transistors) with diodes connected in antiparallel, but MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) may also be used.

[0092] (2) The semiconductor switching element is not limited to one made of a silicon (Si) semiconductor, but may be made of a wide bandgap semiconductor such as silicon carbide (SiC) or gallium nitride (GaN). Wide bandgap semiconductors are suitable for application to MMCs due to their characteristics such as faster switching speeds, high temperature operation, and high dielectric breakdown field strength.

[0093] Although various exemplary embodiments and examples are described in this disclosure, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless variations not illustrated are anticipated within the scope of the technology disclosed in this specification. For example, this includes cases where at least one component is modified, added, or omitted, or where at least one component is extracted and combined with components of another embodiment.

[0094] 1: power conversion device, 2: AC power source, 3: transformer, 4u, 4v, 4w: connection points, 6P: positive DC terminal, 6N: negative DC terminal, 10: power converter, 100u, 100v, 100w: leg circuit, 100, 100P, 100N, 100uP, 100uN, 100vP, 100vN, 100wP, 100wN: arm, 111: converter cell, 111U, 111L, 111U1, 111L1, 111U2, 111L2: semiconductor switching element, 111C: DC capacitor, 111S: voltage sensor, 111a, 111b: input / output terminals, 112uP, 112uN, 112vP, 112vN, 112wP, 112wN: reactors, 20: control device, 21: DC control unit, 22: AC current control unit, 23: circulating current control unit, 24: command generation unit, 25: valve branch capacitor voltage average value calculation unit, 26: gate signal generation unit, 240, 240U, 240V, 240W, 1240: voltage command value correction unit, 241, 241U, 1241, 1241U, 1241V, 1241W: correction voltage calculation unit, 242, 242U: filter, 1243u, 1244u, 1245u, 1248u, 1249u: adder, 1246u: filter, 1247u: multiplier, 244: valve branch output voltage command value generation unit, 246: Normalization unit, 1242: Corrected zero-phase sequence voltage calculation unit, 2411p, 2413p, 2415p, 2416p, 2417, 2411n, 2413n, 2415n, 2416n: Adders, 2412p, 2414p, 2412n, 2414n: Filters, 2418: Multipliers, 2421, 2422, 2424, 2425: Filters, 2423: Limiter, 2426: Inverting circuit, 1000: Processor, 1100: Storage device, Idc: DC current, Vdc: DC voltage, Iac: AC current, Icc: circulating current, Vcap: Capacitor voltage, Vc: Total value of capacitor voltage in arm, Vcarm: Average value of capacitor voltage in arm Varm: Arm output voltage command value, kref: Arm modulation command, G: Gate signal

Claims

1. A power conversion device including a power converter in which a plurality of leg circuits, each having a positive-side arm and a negative-side arm connected in series, are connected in parallel, and connection points between the positive-side arms and the negative-side arms of the plurality of leg circuits are connected to AC lines of respective phases to perform power conversion between a plurality of phases of AC and DC, and a control device for controlling the power converter, wherein each of the positive-side arm and the negative-side arm includes one or more converter cells connected in series, each converter cell having a series body in which a plurality of semiconductor switching elements are connected in series and a DC capacitor connected in parallel to the series body, the control device includes an arm output voltage command value generation unit that generates an arm output voltage command value which is a command value of a voltage output from a plurality of the arms, performs circulating current control for each of the leg circuits, when a total value of voltages of all the DC capacitors included in at least one of the leg circuits is equal to or greater than a preset first threshold value, in the leg circuit, when an arm output voltage command value of one of the positive-side arm and the negative-side arm exceeds a preset upper threshold value, the arm output voltage command value is corrected to be equal to or less than the upper threshold value, and when the arm output voltage command value is less than a preset lower threshold value, the arm output voltage command value is corrected to be equal to or greater than the lower threshold value, and a voltage command correction value for correcting the arm output voltage command value is generated and corrected, and corrects an arm output voltage command value of the other arm of the leg circuit in which the circulating current control is being performed based on the voltage command correction value.

2. The power conversion device according to claim 1, wherein the first threshold value is equal to or greater than 1 / 2 of a voltage between DC terminals of the power converter.

3. The power conversion device according to claim 1 or 2, wherein in each of the plurality of arms, the upper threshold value is a total value of voltages of the DC capacitors in the arm, and the lower threshold value is 0V.

4. The control device controls such that in the leg circuit in which the total value of voltages of all the DC capacitors is equal to or greater than a preset first threshold value, a sum of total values of capacitor voltages of the positive-side arm and the negative-side arm is equal before and after being corrected based on the voltage command correction value.

5. in all of the plurality of leg circuits, when a total value of voltages of all the DC capacitors included in each of the leg circuits is equal to or greater than a preset first threshold value, The power conversion device according to claim 1 or 2, which corrects the voltage command correction value by using a corrected zero-phase voltage for correcting a zero-phase voltage.

6. The power conversion device according to claim 5, wherein the corrected zero-phase voltage is limited by a margin between all of the arm output voltage command values and the upper threshold value and the lower threshold value.

Images