Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor which is capable of suppressing or preventing the occurrence of a tombstone phenomenon and has high mounting reliability.　A multilayer ceramic capacitor 1 is provided with: a multilayer body 2 that comprises an inner layer part 11 in which a plurality of dielectric layers 14 and a plurality of internal electrode layers 15 are alternately stacked, the multilayer body 2 having a first main surface and a second main surface that are opposite to each other in the stacking direction; and a plurality of external electrodes that are arranged on two end faces C or two lateral surfaces B of the multilayer body 2, while being connected to the internal electrode layers 15. In a cross-section obtained by cutting the multilayer body 2 at a plane that is perpendicular to the length direction L at a position where the external electrodes are not arranged, the distance T1 between the first lateral surface Ba-side end of an internal electrode layer 15 which is closest to the first main surface and the first lateral surface Ba-side end of an internal electrode layer 15 which is closest to the second main surface is longer than the distance T2 between the second lateral surface Bb-side end of the internal electrode layer 15 which is closest to the first main surface and the second lateral surface Bb-side end of the internal electrode layer 15 which is closest to the second main surface.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] In recent years, multilayer ceramic capacitors have been widely used in electronic devices such as mobile phones, and development is underway to make them even smaller and lighter as electronic devices become more compact.

[0003] On the other hand, when mounting a multilayer ceramic capacitor, external electrodes are attached to solder paste applied to the lands of a substrate, and the entire substrate to which an electronic component such as a multilayer ceramic capacitor is attached is heated to melt the solder paste, which is then hardened, thereby mounting the electronic component on the substrate. If the balance of solder melting on the lands is disrupted and the solder flows under one of the external electrodes of the multilayer ceramic capacitor, forming a fillet, the surface tension of the melted solder can cause the chip of the multilayer ceramic capacitor to stand up, a phenomenon known as tombstoning. In particular, as multilayer ceramic capacitors become smaller in size and their weight decreases, the tombstoning phenomenon tends to occur more easily.

[0004] For this reason, there is a demand for multilayer ceramic capacitors with a structure that is less susceptible to tombstoning, with the aim of ensuring reliable mounting of miniaturized multilayer ceramic capacitors.

[0005] Japanese Patent Application Publication No. 8-306580

[0006] An object of the present invention is to provide a multilayer ceramic capacitor that can more reliably suppress and prevent the occurrence of tombstone phenomenon than conventional multilayer ceramic capacitors and has high mounting reliability.

[0007] The inventor discovered that in an inner layer portion in which dielectric layers and internal electrode layers are alternately stacked, by making the distance T1 between the end on the first side surface side of the internal electrode layer located closest to the first main surface and the end on the first side surface side of the internal electrode layer located closest to the second main surface longer than the distance T2 between the end on the second side surface side of the internal electrode layer located closest to the first main surface and the end on the second side surface side of the internal electrode layer located closest to the second main surface, the center of gravity of the multilayer ceramic capacitor can be shifted to the first side surface side, and by mounting the first side surface facing the substrate, the occurrence of the tombstone phenomenon can be suppressed and prevented, leading to the completion of the present invention.

[0008] That is, the present invention is a multilayer ceramic capacitor comprising: a laminate including an inner layer portion in which a plurality of dielectric layers and internal electrode layers are alternately laminated, the laminate forming first and second main faces opposing each other in a lamination direction, first end faces and second end faces opposing each other in a length direction intersecting the lamination direction, and first side faces and second side faces opposing each other in a width direction intersecting the lamination direction and the width direction; and a plurality of external electrodes arranged on either of the two end faces and the two side faces of the laminate and connected to the internal electrode layers, wherein, when viewing a cross section of the laminate cut along a plane perpendicular to the length direction at a position where the external electrodes are not arranged, a distance T1 between an end on the first side face side of an internal electrode layer located closest to the first main face and an end on the first side face side of an internal electrode layer located closest to the second main face is longer than a distance T2 between an end on the second side face side of an internal electrode layer located closest to the first main face and an end on the second side face side of an internal electrode layer located closest to the second main face.

[0009] According to the present invention, it is possible to suppress or prevent the occurrence of the tombstone phenomenon during mounting, and to provide a multilayer ceramic capacitor with high mounting reliability.

[0010] 7 is a schematic perspective view of a multilayer ceramic capacitor 1 (first embodiment); FIG. 8 is a cross-sectional view of the multilayer ceramic capacitor 1 (first embodiment) taken along line II-II shown in FIG. 1; FIG. 9 is a cross-sectional view of the multilayer ceramic capacitor 1 (first embodiment) taken along line III-III shown in FIG. 1; FIG. 10 is an exploded perspective view illustrating the lamination state of an internal layer portion 11 of the multilayer ceramic capacitor 1 (first embodiment); FIG. 11 is a flowchart illustrating a manufacturing method of the multilayer ceramic capacitor 1 (first embodiment); FIG. 12 is a perspective view of a material sheet 203 on the surface of which an internal electrode layer pattern 103 that will become the internal electrode layer 15 of the multilayer ceramic capacitor 1 (first embodiment) is printed; FIG. 13 is a perspective view illustrating a state in which a ceramic paste 102 is disposed on the material sheet 203; FIG. 14 is a partial cross-sectional view of FIG. 15; FIG. 16 is a diagram illustrating the lamination state of the material sheet 203; FIG. 17 is a diagram illustrating the mounted state of the multilayer ceramic capacitor 1 (first embodiment); FIG. 18 is a schematic perspective view of a multilayer ceramic capacitor 300 (second embodiment); FIG. 19 is an exploded perspective view illustrating the state of the internal electrode layer 15 in the internal layer portion 11 of the multilayer ceramic capacitor 300 (second embodiment). FIG. 10 is an exploded perspective view illustrating the arrangement of ceramic pastes 102A and 102B in an inner layer portion 11 of a multilayer ceramic capacitor 300 (second embodiment).

[0011] Hereinafter, the multilayer ceramic capacitor of the present invention will be described with a two-terminal ceramic capacitor as a first embodiment and a three-terminal multilayer ceramic capacitor as a second embodiment. Fig. 1 is a schematic perspective view of the multilayer ceramic capacitor 1 of the first embodiment. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 of the first embodiment taken along line II-II shown in Fig. 1. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 of the first embodiment taken along line III-III shown in Fig. 1.

[0012] The embodiments are illustrative of embodiments of the present invention, and the present invention is not limited to the contents of the embodiments. Furthermore, it is possible to combine the contents described in different embodiments, and such combined contents are also included in the present invention. Furthermore, the drawings are intended to facilitate understanding of the specification and may be drawn schematically, and the dimensional ratios of the depicted components or between the components may not match the dimensional ratios of those components described in the specification. Furthermore, components described in the specification may be omitted in the drawings, or the number of components may be omitted.

[0013] (Multilayer Ceramic Capacitor 1) The multilayer ceramic capacitor 1 is a two-terminal multilayer ceramic capacitor (first embodiment). The multilayer ceramic capacitor 1 includes a laminate 2 and a pair of end surface external electrodes 3 provided on both ends of the laminate 2. The laminate 2 includes an inner layer portion 11 including a plurality of pairs of dielectric layers 14 and internal electrode layers 15, and an outer layer portion 12. The dimensions of the multilayer ceramic capacitor 1 are not particularly limited, but it is preferable that the length direction L dimension is 0.6 mm to 3.2 mm, the width direction W dimension is 0.3 mm to 2.5 mm, and the stacking direction T dimension is 0.3 mm to 2.5 mm.

[0014] In the following description, the direction in which the dielectric layers 14 and the internal electrode layers 15 are stacked in the multilayer ceramic capacitor 1 will be referred to as the stacking direction T, which is a term used to indicate the orientation of the multilayer ceramic capacitor 1. In the multilayer ceramic capacitor 1, the direction in which a pair of end surface external electrodes 3 is provided and which intersects with the stacking direction T will be referred to as the length direction L. The direction intersecting both the length direction L and the stacking direction T will be referred to as the width direction W. In the embodiment, the stacking direction T, the length direction L, and the width direction W are mutually orthogonal. FIG. 2 is an LT cross section of the multilayer ceramic capacitor 1 cut along a plane perpendicular to the width direction W, which passes through the length direction L and the stacking direction T, and FIG. 3 is a WT cross section of the multilayer ceramic capacitor 1 cut along a plane perpendicular to the length direction L, which passes through the width direction W and the stacking direction T.

[0015] Furthermore, in the following description, of the six outer surfaces of the laminate 2, a pair of outer surfaces facing each other in the stacking direction T will be referred to as a first main surface Aa and a second main surface Ab, a pair of outer surfaces facing each other in the width direction W will be referred to as a first side surface Ba and a second side surface Bb, and a pair of outer surfaces facing each other in the length direction L will be referred to as a first end surface Ca and a second end surface Cb. Note that when there is no need to particularly distinguish between the first main surface Aa and the second main surface Ab, they will be collectively referred to as a main surface A; when there is no need to particularly distinguish between the first side surface Ba and the second side surface Bb, they will be collectively referred to as a side surface B; and when there is no need to particularly distinguish between the first end surface Ca and the second end surface Cb, they will be collectively referred to as an end surface C.

[0016] (Laminate 2) The laminate 2 includes an inner layer portion 11 and outer layer portions 12 disposed on both sides of the inner layer portion 11 in the stacking direction T. The dimensions of the laminate 2 are not particularly limited, but it is preferable that the length direction L dimension is 0.6 mm or more and 3.2 mm or less, the width direction W dimension is 0.3 mm or more and 2.5 mm or less, and the stacking direction T dimension is 0.3 mm or more and 2.5 mm or less.

[0017] (Inner Layer Portion 11) The inner layer portion 11 includes a plurality of pairs of dielectric layers 14 and internal electrode layers 15 alternately stacked along the stacking direction T.

[0018] (Internal electrode layer 15) The internal electrode layer 15 includes a plurality of first internal electrode layers 15A and a plurality of second internal electrode layers 15B. The first internal electrode layers 15A and the second internal electrode layers 15B are arranged alternately. Note that, when there is no need to particularly distinguish between the first internal electrode layers 15A and the second internal electrode layers 15B, they will be collectively referred to as the internal electrode layers 15.

[0019] The internal electrode layers 15 are preferably formed of a metal material such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au. The thickness of the internal electrode layers 15 in the stacking direction T is preferably 0.25 μm or more and 0.60 μm or less, and more preferably 0.3 μm or more and 0.5 μm or less. The number of internal electrode layers 15 is preferably 14 or more and 1000 or less.

[0020] The internal electrode layer 15 has a facing portion 15 a and an extension portion 15 b that extends from the facing portion 15 a to the end face C and is connected to the end face external electrode 3 .

[0021] (Dielectric Layer 14) The dielectric layer 14 is made of a ceramic material, such as BaTiO ３ A dielectric ceramic having these as its main component is used. Alternatively, the ceramic material may be one to which at least one of a manganese compound, an iron compound, a chromium compound, a cobalt compound, a nickel compound, or the like is added to the main component. The thickness of the dielectric layer 14 in the stacking direction T is preferably 0.3 μm or more and 1.5 μm or less, and more preferably 0.5 μm or more and 1.0 μm or less. The number of dielectric layers 14, including the upper outer layer portion 12 a and the lower outer layer portion 12 b, is preferably 14 or more and 1,000 or less.

[0022] 4 is an exploded perspective view illustrating the lamination state of the internal layer portion 11. As will be described in detail later, during the manufacture of the multilayer ceramic capacitor 1, a ceramic paste 102 is printed in an area where the internal electrode layer pattern 103 is not arranged on a material sheet 203 on which an internal electrode layer pattern 103 that becomes the internal electrode layer 15 is printed on a ceramic green sheet 101 that becomes the dielectric layer 14. The ceramic paste 102 also overlaps one side of the internal electrode layer 15 on the first side face Ba side by a certain width. The material sheet 203 on which the internal electrode layer pattern 103 and the ceramic paste 102 are printed and laminated on such a ceramic green sheet 101 forms the internal layer portion 11.

[0023] Since the ceramic paste 102 overlaps one side of the internal electrode layer 15 on the first side face Ba side by a certain width, the ends of the internal electrode layers 15 on the first side face Ba side are spaced apart from one another in the stacking direction T, as shown in Fig. 3. In a laminate 2 in which a plurality of such internal electrode layers 15 are stacked, a distance T1 between an end on the first side face Ba side of the uppermost internal electrode layer 15 as the internal electrode layer 15 located closest to the first main face Aa and an end on the first side face Ba of the lowermost internal electrode layer 15 as the internal electrode layer 15 located closest to the second main face Ab is longer than a distance T2 between an end on the second side face Bb of the uppermost internal electrode layer 15 as the internal electrode layer 15 located closest to the first main face Aa and an end on the second side face Bb of the lowermost internal electrode layer 15 as the internal electrode layer 15 located closest to the second main face Ab. Here, the distance T1 between the end of the first side face Ba of the uppermost internal electrode layer 15 as the internal electrode layer 15 located closest to the first main surface Aa and the end of the first side face Ba of the lowermost internal electrode layer 15 as the internal electrode layer 15 located closest to the second main surface Ab, and the distance T2 between the end of the second side face Bb of the uppermost internal electrode layer 15 as the internal electrode layer 15 located closest to the first main surface Aa and the end of the second side face Bb of the lowermost internal electrode layer 15 as the internal electrode layer 15 located closest to the second main surface Ab, can be measured using a scanning electron microscope (SEM) or a metallurgical microscope on a cross section of the multilayer ceramic capacitor 1 polished perpendicular to the longitudinal direction to a position that is ½ of the longitudinal dimension of the multilayer ceramic capacitor 1.

[0024] The difference in length between distance T1 and distance T2 corresponds to the difference in thickness in the stacking direction T between the first side face Ba side and the second side face Bb side of the laminate 2, and as shown in FIG. 1, a raised portion M is formed along the length direction L on the surface of the first side face Ba side of the first main face Aa and the second main face Ab of the multilayer ceramic capacitor 1.

[0025] Furthermore, when the internal electrode layers 15 are divided into a central region including a central portion, a first side surface region located closer to the first side surface Ba than the central region, and a second side surface region located closer to the second side surface Bb than the central region, it is preferable that the distance t1 in the stacking direction at any position in the first side surface region between two adjacent internal electrode layers 15 is longer than the distance t2 in the stacking direction at any position in the second side surface region. Here, the distance t1 in the stacking direction at any position in the first side surface region and the distance t2 in the stacking direction at any position in the second side surface region can be measured using a scanning electron microscope (SEM) or a metallurgical microscope on a cross section of the multilayer ceramic capacitor 1 polished perpendicular to the longitudinal length to a position that is half the longitudinal dimension of the laminate.

[0026] The volume of the laminate 2 constituting the multilayer ceramic capacitor 1 is larger on the first side face Ba side than on the second side face Bb side, and therefore the weight is greater, so the center of gravity of the laminate 2 is closer to the first side face Ba than to the center of the laminate 2. Therefore, by mounting the multilayer ceramic capacitor 1 with the first side face Ba facing the substrate as shown in Figure 10, the weight increase is minimized and the center of gravity of the multilayer ceramic capacitor 1 can be brought closer to the substrate, making it possible to effectively suppress and prevent the occurrence of tombstoning during mounting.

[0027] In order to reliably position the first side face Ba facing the substrate during mounting, it is preferable to provide an identification means for identifying the orientation on the first side face Ba and / or the second side face Bb of the laminate 2. The identification means is not particularly limited, but examples include printing, engraving, or coloring the second side face Bb.

[0028] Furthermore, since the first side face Ba is disposed facing the substrate, it is preferable to provide an identification means for identifying the direction in which the end face external electrode 3 is disposed. The identification means is not particularly limited, but examples include means for making the shape or length of the surface on the second side face Bb side of the end face external electrode 3 different from the shape of the first side face Ba.

[0029] (Outer layer portion 12) The outer layer portion 12 includes an upper outer layer portion 12a disposed on one side of the inner layer portion 11, and a lower outer layer portion 12b disposed on the other side of the inner layer portion 11 in the stacking direction T. When there is no need to particularly distinguish between the upper outer layer portion 12a and the lower outer layer portion 12b, they will be collectively referred to as the outer layer portion 12.

[0030] The outer layer portion 12 is made of the same material as the dielectric layer 14 of the inner layer portion 11. The thickness of the outer layer portion 12 is, for example, 20 μm or less, and preferably 10 μm or less. The upper outer layer portion 12 a and the lower outer layer portion 12 b are disposed on both sides of the inner layer portion in the stacking direction, each with a predetermined thickness. In the embodiment, the thicknesses are the same, but this is not limiting and the thicknesses may be different.

[0031] (End Face External Electrode 3) The end of the lead portion 15b of the first internal electrode layer 15A is exposed at the first end face Ca and is electrically connected to the first end face external electrode 3A. The end of the lead portion 15b of the second internal electrode layer 15B is exposed at the second end face Cb and is electrically connected to the second end face external electrode 3B. This results in a structure in which multiple capacitor elements are electrically connected in parallel between the first end face external electrode 3A and the second end face external electrode 3B. Furthermore, the end face external electrode 3 covers not only the end face C but also parts of the main face A and side face B on the end face C side, and also covers the raised portion M of the laminate 2.

[0032] The end surface external electrode 3 and the side surface external electrode 4 provided in the second embodiment described below can both have a structure including an underlying electrode layer and a plating layer disposed on the underlying electrode layer.

[0033] The base electrode layer includes at least one layer selected from a baked layer, a conductive resin layer, a direct plating layer, and the like, as described below.

[0034] (Baked Layer) The baked layer is formed by applying a conductive paste containing glass and metal to the laminate and baking it. The baked layer may be baked simultaneously with the internal electrodes or may be baked after the internal electrodes are baked. The baking temperature is preferably 700 to 900°C.

[0035] The glass component includes at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal includes at least one selected from Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, etc.

[0036] The thickness of the baked layer is preferably, for example, 3 μm or more and 70 μm or less. The baked layer may be a multi-layered layer.

[0037] (Conductive Resin Layer) The conductive resin layer is formed on the surface of the baked layer or directly on the surface of the laminate. The conductive resin layer may be a multi-layered layer.

[0038] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto the baked layer or the laminate, and then performing a heat treatment at a temperature of 250 to 550°C or higher to thermally cure the resin and form a conductive resin layer. The atmosphere during this heat treatment is N ２ In order to prevent the resin from scattering and the various metal components from being oxidized, it is preferable to keep the oxygen concentration at 100 ppm or less.

[0039] The thickness of the conductive resin layer at the center of the end face C is preferably, for example, not less than 10 μm and not more than 150 μm.

[0040] The resin for the conductive resin layer can be any of various known thermosetting resins, such as epoxy resin, phenol resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin is one of the most suitable resins, as it has excellent heat resistance, moisture resistance, and adhesion. The resin contained in the conductive resin layer is preferably contained in an amount of 25 vol% to 65 vol% of the total volume of the conductive resin.

[0041] The conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, and imidazole-based compounds can be used as the curing agent for the epoxy resin.

[0042] Because the conductive resin layer contains a thermosetting resin, it is more flexible than a conductive layer made of, for example, a plating film or a fired conductive paste. Therefore, even if the ceramic electronic component is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer functions as a buffer layer and can prevent cracks in the ceramic electronic component.

[0043] The metal contained in the conductive resin layer can be Ag, Cu, or an alloy thereof. Alternatively, a metal powder whose surface is coated with Ag can be used. When a metal powder whose surface is coated with Ag is used, it is preferable to use Cu or Ni as the metal powder. Alternatively, Cu that has been subjected to an anti-oxidation treatment can be used.

[0044] The reason for using Ag conductive metal powder as the conductive metal is that Ag has a relatively low resistivity among metals, making it suitable as an electrode material, and Ag is a noble metal, so it does not oxidize and is highly stable.The reason for using Ag-coated metal is that it makes it possible to use a cheaper base metal while maintaining the above-mentioned properties of Ag.

[0045] The metal contained in the conductive resin layer is preferably contained in an amount of 35 vol % or more and 75 vol % or less with respect to the volume of the entire conductive resin.

[0046] The shape of the metal contained in the conductive resin layer is not particularly limited. The conductive filler may be spherical, flat, or the like. The average particle size of the metal contained in the conductive resin layer is not particularly limited, but can be, for example, about 0.3 μm or more and 10 μm or less.

[0047] The metal contained in the conductive resin layer is mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, when the conductive fillers come into contact with each other, a current path is formed inside the conductive resin layer.

[0048] (Plating Layer) A plating layer may be provided directly on the end surfaces of the laminate where the internal electrodes are exposed. That is, the multilayer ceramic capacitor may have a structure including plating layers that are electrically connected directly to the internal electrode layers and the surface electrode layers. In such a case, a catalyst may be applied to the surface of the laminate as a pretreatment, and then the plating layer may be formed directly.

[0049] The plating layer preferably contains at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, Zn, etc., or an alloy containing the metal. For example, when the first internal electrode layer and the second internal electrode layer are formed using Ni, the direct plating layer is preferably formed using Cu, which has good bonding properties with Ni.

[0050] The thickness of each plating layer is preferably 2 μm or more and 15 μm or less. The plating layer preferably does not contain glass. The metal content per unit volume of the plating layer is preferably 99 volume % or more.

[0051] When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which makes the process more complicated. Therefore, electrolytic plating is usually preferred. As a plating method, barrel plating is preferably used. If necessary, an upper layer plating electrode may be formed on the surface of the lower layer plating electrode in the same manner.

[0052] When the base electrode layer is a thin film layer, the thin film layer is formed by a thin film forming method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0053] The plating layer disposed on the base electrode layer contains, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0054] The plating layer may be formed of multiple layers. Preferably, it has a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the base electrode layer from being eroded by solder when mounting the ceramic electronic component, and the Sn plating layer improves the wettability of the solder when mounting the ceramic electronic component, allowing for easier mounting. The thickness of each plating layer is preferably 2 μm or more and 15 μm or less.

[0055] (Method for Manufacturing the Multilayer Ceramic Capacitor 1) Next, an example of a method for manufacturing the multilayer ceramic capacitor 1 according to the embodiment will be described. FIG.

[0056] (Internal electrode layer pattern forming step S1) First, an internal electrode layer pattern 103 that will become the internal electrode layer 15 is formed on a ceramic green sheet 101 that will become the dielectric layer 14 using a conductive paste. Fig. 6 is a perspective view of a material sheet 203 in which the internal electrode layer pattern 103 that will become the internal electrode layer 15 is printed on the surface of the ceramic green sheet 101.

[0057] (Ceramic Green Sheet 101) The ceramic green sheet 101 is a strip-shaped sheet formed by forming a ceramic slurry containing ceramic powder, a binder, and a solvent onto a carrier film using a die coater, gravure coater, microgravure coater, or the like.

[0058] (Internal Electrode Layer Pattern 103) The internal electrode layer pattern 103 is formed by printing such as screen printing, gravure printing, or relief printing.

[0059] Here, the internal electrode layer pattern 103 forms a step 104 due to its thickness on the ceramic green sheet 101. In this embodiment, the step 104 is an inclined surface.

[0060] (Overlapping dielectric arrangement step S2) Next, the ceramic paste 102 forming the dielectric layer is arranged on the material sheet 203 so as to fill the step 104 due to the thickness of the internal electrode layer pattern 103 and overlap one side of the first side face Ba of the internal electrode layer pattern 103 by a certain width. Alternatively, the ceramic paste 102 forming the dielectric layer on the outer periphery of the area where the internal electrode layer pattern 103 is to be formed may be arranged on the material sheet 203 first, and then the internal electrode may be arranged so as to overlap one side of the first side face Ba of the internal electrode layer pattern 103 by a certain width. FIG. 7 is a perspective view showing a state in which the ceramic paste 102 is arranged on the material sheet 203. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7. The ceramic paste 102 is applied by printing, such as screen printing, gravure printing, or letterpress printing. The ceramic paste 102 may have a different component ratio from the dielectric as the material of the ceramic green sheet 101, or may have the same component ratio, or may contain different components.

[0061] The ceramic paste 102 is applied so as to overlap one side of the internal electrode layer 15 on the first side face Ba side by a certain width. The overlap width is preferably less than 33% of the width dimension of the internal electrode layer 15, and is preferably 2% to 25%. Also, as shown in FIG. 8, since the step 104 of the internal electrode layer pattern 103 is an inclined surface, the ceramic paste 102 gradually climbs onto the internal electrode layer pattern 103. Therefore, the upper surface of the ceramic paste 102 becomes smooth. The thickness of the ceramic paste 102 is preferably 0.4 to 0.8 times the thickness of the ceramic green sheet 101.

[0062] (Laminating step S3) Fig. 9 is a diagram illustrating the lamination state of the material sheets 203. As shown in Fig. 9, the material sheets 203 are arranged such that the internal electrode layer patterns 103 adjacent to each other in the lamination direction T are alternately shifted in position in the length direction L.

[0063] Furthermore, a ceramic green sheet 212 for the upper outer layer portion, which will become the upper outer layer portion 12a, is stacked on one side of the multiple laminated material sheets 203, and a ceramic green sheet 213 for the lower outer layer portion, which will become the lower outer layer portion 12b, is stacked on the other side.

[0064] (Mother Block Forming Step S4) Subsequently, the upper outer layer ceramic green sheet 212, the stacked material sheets 203, and the lower outer layer ceramic green sheet 213 are thermocompression bonded to form a mother block.

[0065] (Mother block dividing step S5) Next, the mother block is cut at positions Z shown in Fig. 9. Although only the cutting positions Z in the length direction L are shown, the laminate 2 is also cut at predetermined cutting positions in the width direction W that extend in a direction perpendicular to the position Z extending in the width direction, thereby producing a plurality of rectangular laminates 2.

[0066] (Firing step S6) In the firing step, the laminated chip is subjected to a binder removal process and a firing process to form an element part. The firing process causes the conductive paste layer and the green sheet for the dielectric layer to be co-sintered to form the internal electrode layer 15 and the dielectric layer 14, respectively. The conditions for the binder removal process can be determined depending on the type of organic binder contained in the green sheet and the conductive paste layer. The firing process can also be carried out at a temperature at which the laminated chip is sufficiently densified. The firing temperature depends on the materials of the dielectric and the internal electrode layer, but is preferably 900°C to 1400°C.

[0067] (External Electrode Forming Step S7) In the external electrode forming step, end surface external electrodes 3 are formed on the laminate 2 to form the multilayer ceramic capacitor 1. The end surface external electrodes 3 may be formed by a known method. The side surface external electrodes 4 provided in the second embodiment described below can also be formed in the same manner as the end surface external electrodes 3. For example, a base electrode layer, a conductive resin layer, or a direct plating layer is formed on the end surface C where the internal electrode layer 15 of the laminate 2 is drawn out and exposed, and further plating layers are provided as necessary. In this embodiment, a Ni plating layer and a Sn plating layer are formed on the baked layer. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating. In this manner, a multilayer ceramic capacitor can be obtained.

[0068] (Multilayer ceramic capacitor 300) The multilayer ceramic capacitor 300 is a three-terminal multilayer ceramic capacitor (second embodiment). Since the dielectric layers, internal electrode layers, external electrodes, etc. that constitute a three-terminal multilayer ceramic capacitor are often common to those of a two-terminal multilayer ceramic capacitor, the following description will mainly focus on the configuration that differs from the two-terminal multilayer ceramic capacitor.

[0069] 11 to 13 show the shape and structure of the multilayer ceramic capacitor 300. FIG. 11 is an external view of the three-terminal multilayer ceramic capacitor 300. FIG. 12 is an exploded perspective view illustrating the state of the internal electrode layers 15 in the internal layer portion 11 of the multilayer ceramic capacitor 300. FIG. 13 is an exploded perspective view illustrating the arrangement of ceramic pastes 102A and 102B in the internal layer portion 11 of the multilayer ceramic capacitor 300. The structure of the multilayer ceramic capacitor 300 will be described using the direction in which the dielectric layers and internal electrode layers are stacked as the stacking direction T, a length direction L perpendicular to the stacking direction T, and a width direction W perpendicular to the stacking direction T and the length direction L. In the embodiment, the width direction W, the length direction L, and the stacking direction T are perpendicular to one another, but they do not necessarily have to be perpendicular to one another and may intersect one another.

[0070] On the surface of the laminate 2, a first end surface external electrode 3A, a second end surface external electrode 3B, and a side surface external electrode 4 are formed.

[0071] The first end surface external electrode 3A is formed on the first end surface Ca of the laminate 2. The first end surface external electrode 3A is formed in a cap shape, and its edge portion extends from the first end surface Ca of the laminate 2 to the first main surface Aa, the second main surface Ab, the first side surface Ba, and the second side surface Bb.

[0072] The second end surface external electrode 3B is formed on the second end surface Cb of the laminate 2. The second end surface external electrode 3B is formed in a cap shape, and its edge portion extends from the second end surface Cb of the laminate 2 to the first main surface Aa, the second main surface Ab, the first side surface Ba, and the second side surface Bb.

[0073] The side surface external electrode 4 can be formed on either the left or right side surface of the laminate 2, but Fig. 11 shows a configuration in which a first side surface external electrode 4A and a second side surface external electrode 4B are formed on the first side surface Ba and the second side surface Bb, respectively, of the laminate 2. The side surface external electrode 4 is also formed to extend onto the first main surface Aa and the second main surface Ab.

[0074] FIG. 11 is a schematic diagram showing the internal electrode layers 15 and the dielectric layers 14 of the multilayer ceramic capacitor 300 .

[0075] The internal electrode layer 15 is composed of a first internal electrode layer 15 A and a second internal electrode layer 15 B. The first internal electrode layer 15 A and the second internal electrode layer 15 B are disposed on the dielectric layer 14 .

[0076] The first internal electrode layer 15A penetrates the inside of the laminate 2 in the width direction W, connects to the side surface external electrode 4, and forms electrostatic capacitance with the second internal electrode layer 15B. In the embodiment, both ends of the first internal electrode layer 15A are drawn out to the side surface B of the laminate 2 and connected to the side surface external electrode 4, but are not drawn out to the end surface C of the laminate 2 and are not connected to the end surface external electrode 3. The first internal electrode layer 15A can be formed in a substantially cross shape as shown in Fig. 12, but is not limited to this and any shape can be adopted as long as it is connected to the side surface external electrode 4 and not connected to the end surface external electrode 3.

[0077] In the embodiment shown in Figure 12, the first internal electrode layer 15A has a first opposing portion 15Aa that faces the second internal electrode layer 15B via the dielectric layer 14, a first side surface side lead portion 15Ab1 that extends from the first opposing portion 15Aa and is led out to the first side surface Ba of the laminate 2, and a second side surface side lead portion 15Ab2 that extends from the first opposing portion 15Aa and is led out to the second side surface Bb of the laminate 2, but if only one of the lead portions, for example the first side surface side lead portion 15Ab1, is provided, the capacitor will function as a three-terminal multilayer ceramic capacitor.

[0078] The second internal electrode layer 15B penetrates the inside of the laminate 2 in the length direction L and connects to the end surface external electrodes 3. The second internal electrode layer 15B has a shape in which both ends thereof are drawn out to the end surfaces C of the laminate and connected to the end surface external electrodes 3, but are not drawn out to the side surfaces B of the laminate and are not connected to the side surface external electrodes 4.

[0079] 12 , the second internal electrode layer 15B has a rectangular shape, but is not limited thereto, and may have a second opposing portion 15Ba opposing the first internal electrode layer 15A across the dielectric layer 14, a first leading portion 15Bb1 extending from the second opposing portion 15Ba and drawn to one of two side surfaces B or two end surfaces C of the laminate 2, at a position different from the first side surface leading portion 15Ab1 when the laminate 2 is viewed in plan from the stacking direction T, and a second leading portion 15Bb2 extending from the second opposing portion 15Ba and drawn to one of two side surfaces B or two end surfaces C of the laminate 2, at a position different from the first side surface leading portion 15Ab1, the second side surface leading portion 15Ab2, and the first leading portion 15Bb1 when the laminate 2 is viewed in plan from the stacking direction T. The external electrodes can be arranged according to the positions of the first leading portion 15Bb1 and the second leading portion 15Bb2.

[0080] The multilayer ceramic capacitor 300, in which the first internal electrode layer 15A is connected to the side surface external electrode 4 and the second internal electrode layer 15B is connected to the first end surface external electrode 3A and the second end surface external electrode 3B, can be used as a three-terminal capacitor. That is, the multilayer ceramic capacitor 300 can be used as a three-terminal capacitor by interrupting the power supply line or signal line in the circuit, connecting the first end surface external electrode 3A to one end of the interrupted line and the second end surface external electrode 3B to the other end of the interrupted line, and connecting the side surface external electrode 4 to ground. In this case, the second internal electrode layer 15B serves as a through electrode, and the first internal electrode layer 15A serves as a ground electrode.

[0081] 13 is a schematic diagram showing the ranges of the ceramic pastes 102A and 102B applied to the inner layer portion 11 of the multilayer ceramic capacitor 300 during manufacturing. During manufacturing of the multilayer ceramic capacitor 300, the ceramic paste 102A is printed in an area of ​​a material sheet 203A on which an internal electrode layer pattern 103A to be the first internal electrode layer 15A is printed on a ceramic green sheet 101A to be the dielectric layer 14, where the internal electrode layer pattern 103A is not arranged. The ceramic paste 102A also covers the first side surface side drawn portion 15Ab1 extending from the first opposing portion 15Aa of the first internal electrode layer 15A to the first side surface external electrode 4A on the first side surface Ba side. The ceramic paste 102A also covers, by a certain width, the internal electrode layer pattern 103A at a position corresponding to one side of the first opposing portion 15Aa of the first internal electrode layer 15A on the first side surface Ba side. Similarly, ceramic paste 102B is printed in an area where the internal electrode layer pattern 103B to be the second internal electrode layer 15B is not arranged on a material sheet 203B on which the internal electrode layer pattern 103B to be the second internal electrode layer 15B is printed on a ceramic green sheet 101B to be the dielectric layer 14. In addition, the ceramic paste 102B covers, by a certain width, the internal electrode layer pattern 103B at a position corresponding to one side of the second internal electrode layer 15B on the first side face Ba side.

[0082] Since the ceramic pastes 102A and 102B overlap one side of the internal electrode layer 15 on the first side face Ba side by a certain width, the ends of the internal electrode layers 15 on the first side face Ba side are spaced apart from each other in the stacking direction T. In a laminate 2 in which a plurality of such internal electrode layers 15 are stacked, when a cross section of the laminate 2 cut along a plane perpendicular to the longitudinal direction L at a position where no side face external electrode 4 is disposed is viewed, as shown in the cross section of FIG. 3 , a distance T1 between an end of the first side face Ba side of the internal electrode layer 15 of the uppermost layer and an end of the first side face Ba side of the internal electrode layer 15 of the lowermost layer is longer than a distance T2 between an end of the second side face Bb side of the internal electrode layer 15 of the uppermost layer and an end of the second side face Bb side of the internal electrode layer 15 of the lowermost layer.

[0083] The volume of the laminate 2 constituting the multilayer ceramic capacitor 300 is larger on the first side surface side than on the second side surface side, and the weight is therefore greater, so the center of gravity of the laminate 2 is closer to the first side surface Ba than to the center of the laminate 2. Therefore, by mounting the multilayer ceramic capacitor 300 with the first side surface Ba facing the substrate, the weight increase is minimized and the center of gravity of the multilayer ceramic capacitor 1 can be brought closer to the substrate, making it possible to effectively suppress and prevent the occurrence of tombstoning during mounting.

[0084] Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments and can be embodied in various forms without departing from the spirit of the present invention. The present invention includes the following combinations.

[0085] <1> A multilayer ceramic capacitor comprising: a laminate including an inner layer portion in which a plurality of dielectric layers and internal electrode layers are alternately stacked, the laminate forming first and second main faces opposing each other in a stacking direction, first end faces and second end faces opposing each other in a length direction intersecting the stacking direction, and first and second side faces opposing each other in a width direction intersecting the stacking direction and the length direction; and a plurality of external electrodes arranged on either of the two end faces and two side faces of the laminate and connected to the internal electrode layers, wherein, when viewing a cross section of the laminate cut along a plane perpendicular to the length direction at a position where the external electrodes are not arranged, a distance T1 between an end on the first side face side of an internal electrode layer located closest to the first main face and an end on the first side face side of an internal electrode layer located closest to the second main face is longer than a distance T2 between an end on the second side face side of an internal electrode layer located closest to the first main face and an end on the second side face side of an internal electrode layer located closest to the second main face.

[0086] <2> A multilayer ceramic capacitor according to <1>, wherein when the internal electrode layers are divided into a central region including a central portion, a first side surface region located on the first side surface side of the central region, and a second side surface region located on the second side surface side of the central region, the distance between two adjacent internal electrode layers is such that a distance t1 in the stacking direction of the first side surface side region has a portion longer than a distance t2 in the stacking direction of the second side surface side region.

[0087] <3> The multilayer ceramic capacitor according to <1> or <2>, further comprising an identification means for identifying the direction in which the laminate is disposed on the first side surface and / or the second side surface.

[0088] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, further comprising an identification means for identifying the orientation of the external electrodes.

[0089] <5> A multilayer ceramic capacitor according to any one of <1> to <4>, wherein the plurality of internal electrode layers include a plurality of first internal electrode layers drawn to the first end surface and a plurality of second internal electrode layers drawn to the second end surface, and external electrodes are provided on the first end surface and the second end surface.

[0090] <6> The plurality of internal electrode layers include first internal electrode layers and second internal electrode layers, the first internal electrode layer having a first opposing portion opposing the second internal electrode layer via the dielectric layer, and a first side surface side drawn portion extending from the first opposing portion and drawn to a first side surface of the laminate, the second internal electrode layer having a second opposing portion opposing the first internal electrode layer via the dielectric layer, a first drawn portion extending from the second opposing portion and drawn to a position different from the first side surface side drawn portion on either of the two side surfaces or the two end surfaces of the laminate when the laminate is viewed in plan from the stacking direction, and a second drawn portion extending from the second opposing portion and drawn to a position different from the first side surface side drawn portion and the first drawn portion on either of the two side surfaces or the two end surfaces of the laminate when the laminate is viewed in plan from the stacking direction, <4> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the plurality of external electrodes include a first side surface side external electrode connected to the first side surface side extended portion, a first external electrode connected to the first extended portion, and a second external electrode connected to the second extended portion.

[0091] A Principal surface Aa First principal surface Ab Second principal surface B Side surface Ba First side surface Bb Second side surface C End surface Ca First end surface Cb Second end surface M Protruding portion T Stacking direction W Width direction L Length direction 1 Multilayer ceramic capacitor 2 Laminate 3 End surface external electrode 4 Side surface external electrode 11 Inner layer portion 12 Outer layer portion 14 Dielectric layer 15 Internal electrode layer 15a Opposing portion 15b Lead-out portion 101 Ceramic green sheet 102 Ceramic paste 103 Internal electrode layer pattern 104 Step 203 Material sheet 300 Multilayer ceramic capacitor

Claims

1. a laminate including an inner layer portion in which a plurality of dielectric layers and internal electrode layers are alternately stacked, and forming a first main surface and a second main surface opposite to each other in a stacking direction, a first end surface and a second end surface opposite to each other in a length direction intersecting with the stacking direction, and a first side surface and a second side surface opposite to each other in a width direction intersecting with the stacking direction and the length direction; a plurality of external electrodes arranged on either one of the two end faces or two side faces of the laminate and connected to the internal electrode layers; A multilayer ceramic capacitor comprising: When the cross section of the laminate is cut along a plane perpendicular to the longitudinal direction at a position where the external electrodes are not arranged, a distance T1 between an end portion of the internal electrode layer closest to the first main surface on the first side surface side and an end portion of the internal electrode layer closest to the second main surface side on the first side surface side is longer than a distance T2 between an end portion of the internal electrode layer closest to the first main surface on the second side surface side and an end portion of the internal electrode layer closest to the second main surface side on the second side surface side.

2. When the internal electrode layer is divided into a central region including a central portion, a first side surface region located on the first side surface side of the central region, and a second side surface region located on the second side surface side of the central region, The distance between two adjacent internal electrode layers is 2. The multilayer ceramic capacitor according to claim 1, wherein the first side surface region has a portion where a distance t1 in the stacking direction is longer than a distance t2 in the stacking direction in the second side surface region.

3. 3. The multilayer ceramic capacitor according to claim 1, further comprising an identification means for identifying the direction in which the laminate is disposed on the first side surface and / or the second side surface of the laminate.

4. 3. The multilayer ceramic capacitor according to claim 1, further comprising an identification means for identifying the orientation of said external electrodes.

5. 3. The multilayer ceramic capacitor according to claim 1, wherein the plurality of internal electrode layers include a plurality of first internal electrode layers extended to the first end surface and a plurality of second internal electrode layers extended to the second end surface, and the external electrodes are provided on the first end surface and the second end surface.

6. the plurality of internal electrode layers include a first internal electrode layer and a second internal electrode layer; the first internal electrode layer has a first opposing portion opposing the second internal electrode layer via the dielectric layer, and a first side surface side drawn portion extending from the first opposing portion and drawn to a first side surface of the laminate, the second internal electrode layer has: a second opposing portion opposing the first internal electrode layer via the dielectric layer; a first lead portion extending from the second opposing portion and drawn to one of the two side surfaces or the two end surfaces of the laminate, at a position different from the first side surface lead portion when the laminate is viewed in a plane in the stacking direction; and a second lead portion extending from the second opposing portion and drawn to one of the two side surfaces or the two end surfaces of the laminate, at a position different from the first side surface lead portion and the first lead portion when the laminate is viewed in a plane in the stacking direction, 3. The multilayer ceramic capacitor according to claim 1, wherein the plurality of external electrodes include a first side surface external electrode connected to the first side surface extended portion, a first external electrode connected to the first extended portion, and a second external electrode connected to the second extended portion.

7. A laminate including an inner layer portion in which a plurality of dielectric layers and internal electrode layers are stacked, forming a first main surface and a second main surface opposite to each other in the stacking direction, a first end face and a second end face opposite to each other in a length direction intersecting with the stacking direction, and a first side face and a second side face opposite to each other in a width direction intersecting with the stacking direction and the length direction; a plurality of external electrodes arranged on either one of the two end faces or two side faces of the laminate and connected to the internal electrode layers; A multilayer ceramic capacitor comprising: When the cross section of the laminate is cut along a plane perpendicular to the longitudinal direction at a position where the external electrodes are not arranged, The internal electrode layer is a central region including a central portion; a first side region located closer to the first side than the central region; a second side region located closer to the second side than the central region; Equipped with The distance between two adjacent internal electrode layers is a distance t1 in the stacking direction in the first side surface region is longer than a distance t2 in the stacking direction in the second side surface region.