Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor which is capable of ensuring reliability, while achieving a good balance among the initial capacity, the effective capacity and the dielectric breakdown voltage under dimensional constraints. The present invention specifically provides a multilayer ceramic capacitor 1 which comprises a dielectric layer 14 containing Ba and Ti, wherein: an internal electrode layer 15 contains Ni; if L0 is the size in the longitudinal direction, T0 is the size in the stacking direction and W0 is the size in the width direction, 1.7 ≤ L0 / T0 ≤ 2.3 and 1.0 ≤ W0 / T0 ≤ 1.4 are satisfied; if d is the amount of positional deviation in the width direction between ends in the width direction of internal electrode layers 15 that are adjacent to each other in the stacking direction, d ≤ 5 µm is satisfied; 2 at% or more of Sn in terms of the atomic composition percentage is segregated at the interface between the internal electrode layer 15 and the dielectric layer 14; if WS is the size of a side gap part 20 in the width direction and TG is the size of an outer layer part 12 in the stacking direction, 0.3 ≤ WS / TG ≤ 0.6 is satisfied; and if WI is the size of the internal electrode layer 15 in the width direction, T0 < WI is satisfied.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] A technology is known for reducing voltage failures and enabling increased capacitance in multilayer ceramic capacitors (see Patent Document 1). This technology achieves both suppression of voltage failures and increased capacitance by adjusting the curvature radius of the corners of the internal electrode layers and the curvature radius of the ridges of the laminate.

[0003] Japanese Patent Application Laid-Open No. 2005-259772

[0004] However, in the multilayer ceramic capacitor of the above-mentioned prior art, it is necessary to adjust the shape of the internal electrode layers and the shape of the ridges of the laminate, which makes the manufacturing process complicated.

[0005] In recent years, with the trend toward even higher performance and smaller size of portable devices, there has been a growing need for smaller, larger capacity multilayer ceramic capacitors. An object of the present invention is to provide a multilayer ceramic capacitor that can ensure sufficient reliability while achieving a balance between capacitance and breakdown voltage in devices with dimensional constraints in the height and width directions.

[0006] In order to solve the above-mentioned problems, the present invention provides a multilayer ceramic capacitor comprising: a laminate including an inner layer portion in which dielectric layers and internal electrode layers are alternately stacked; a laminate chip having outer layer portions respectively disposed on both sides of the inner layer portion in a stacking direction; and side gap portions respectively disposed on both sides of the laminate chip in a width direction perpendicular to the stacking direction; and external electrodes respectively disposed on both sides of the laminate in a length direction intersecting the stacking direction and the width direction, wherein the dielectric layers contain Ba and Ti, and the internal electrode layers contain Ni, and the multilayer ceramic capacitor has a dimension L0 in the length direction, a dimension T0 in the stacking direction, and a dimension W0 in the width direction. and wherein, in a cross section at the center in the longitudinal direction, passing through the stacking direction and the width direction, when a positional deviation in the width direction of ends in the width direction of the internal electrode layers adjacent to each other in the stacking direction is d, d≦5 μm; Sn having an atomic composition percentage of 2 at % or more is segregated at interfaces between the internal electrode layers and the dielectric layers; when a dimension in the width direction of the side gap portion is WS and a dimension in the stacking direction of the outer layer portion is TG, 0.3≦WS / TG≦0.6; and when a dimension in the width direction of the internal electrode layer is T0<WI.

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can ensure sufficient reliability while balancing capacitance / dielectric breakdown voltage within dimensional constraints.

[0008] Fig. 3 is a schematic perspective view of a multilayer ceramic capacitor 1 according to an embodiment. Fig. 4 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor 1 of Fig. 1. Fig. 5 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor 1 of Fig. 1. Fig. 6 is an enlarged view of a portion S of Fig. 3. Fig. 7 is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 1.

[0009] A multilayer ceramic capacitor 1 according to an embodiment of the present invention will now be described. Fig. 1 is a schematic perspective view of the multilayer ceramic capacitor 1 according to the embodiment. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II in Fig. 1. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III in Fig. 1.

[0010] (Multilayer ceramic capacitor 1) The multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape and includes a laminate 2 and a pair of external electrodes 3 provided on both ends of the laminate 2. The laminate 2 includes an inner layer portion 11 in which a plurality of dielectric layers 14 and a plurality of internal electrode layers 15 are stacked.

[0011] In the following description, the terms used to represent the orientation of the multilayer ceramic capacitor 1 are: a length direction L, which is the direction in which a pair of external electrodes 3 are provided in the multilayer ceramic capacitor 1; a stacking direction T, which is the direction in which the dielectric layers 14 and the internal electrode layers 15 are stacked; and a width direction W, which is the direction intersecting both the length direction L and the stacking direction T. In the embodiment, the width direction W is perpendicular to both the length direction L and the stacking direction T.

[0012] 2 , a pair of outer peripheral surfaces facing each other in the stacking direction T will be referred to as main surfaces A, a pair of outer peripheral surfaces facing each other in the width direction W will be referred to as side surfaces B, and a pair of outer peripheral surfaces facing each other in the length direction L will be referred to as first end surfaces C1 and second end surfaces C2. Note that, unless it is necessary to particularly distinguish between the first end surfaces C1 and the second end surfaces C2, they will be collectively referred to as end surfaces C.

[0013] When the dimension of the multilayer ceramic capacitor 1 in the length direction L is L0, the dimension in the stacking direction T is T0, and the dimension in the width direction W is W0, the dimensions of the multilayer ceramic capacitor 1 are preferably 1.15≦L0≦1.25 μm, more preferably about 1.220 μm, preferably 0.65≦W0≦0.75 μm, more preferably about 0.725 μm, preferably 0.55≦T0≦0.65 μm, and more preferably about 0.620 μm. This makes it possible to ensure mountable height and width dimensions and capacitance in devices with dimensional constraints in the height and width directions.

[0014] Furthermore, it is preferable that 1.7≦L0 / T0≦2.3 and 1.0≦W0 / T0≦1.4 are satisfied, which makes it possible to ensure mountable dimensions in the height and width directions and capacity in a device that has dimensional restrictions in the height and width directions.

[0015] Furthermore, it is preferable that the ratio of L0, T0, and W0 is approximately L0:T0:W0=2:1:1.2, which makes it possible to ensure mountable height and width dimensions and capacity in devices with height and width dimensional constraints.

[0016] (Laminate 2 ) The laminate 2 includes a laminate chip 10 and a side gap portion 20 .

[0017] (Laminated Chip 10 ) The laminated chip 10 includes an inner layer portion 11 and outer layer portions 12 disposed on both main surfaces A of the inner layer portion 11 .

[0018] (Inner Layer Portion 11) The inner layer portion 11 is formed by laminating a plurality of dielectric layers 14 and internal electrode layers 15. The dielectric layers 14 and the internal electrode layers 15 will be described in detail later.

[0019] (Outer layer portion 12) The outer layer portion 12 is made of the same dielectric ceramic material as the dielectric layer 14 of the inner layer portion 11. The dimension TG of the outer layer portion 12 in the stacking direction T is preferably 36 μm≦TG≦43 μm, and more preferably about 40 μm. By setting the above dimensions, it is possible to ensure the necessary capacity while maintaining dimensions that can be installed in devices with dimensional constraints.

[0020] (Side gap portion 20) The side gap portion 20 is provided on both side surfaces B of the laminate chip 10. The side gap portion 20 covers the ends of the internal electrode layers 15 exposed on both side surfaces of the laminate chip 10 in the width direction W along those ends. The side gap portion 20 is made of the same dielectric ceramic material as the dielectric layer 14.

[0021] (Dimensions of Side Gap 20) The dimension WS of the side gap 20 in the width direction W is preferably 15 μm≦WS≦20 μm, and more preferably about 17 μm. The ratio of the dimension WS of the side gap 20 in the width direction W to the dimension TG of the outer layer 12 in the stacking direction T is preferably 0.3≦WS / TG≦0.6, and more preferably 0.4≦WS / TG≦0.5. By setting the above dimension ratio, it is possible to ensure the necessary capacity while maintaining dimensions that can be implemented in devices with dimensional constraints.

[0022] (External electrode 3) The external electrode 3 includes a first external electrode 3A provided on the first end face C1 of the laminate 2 and a second external electrode 3B provided on the second end face C2 of the laminate 2. When there is no need to particularly distinguish between the first external electrode 3A and the second external electrode 3B, they will be collectively described as the external electrode 3. The external electrode 3 covers not only the end face C but also a portion of the main face A and the side face B on the end face C side.

[0023] (Dielectric layer 14) Fig. 4 is an enlarged view of the S portion in Fig. 3. The dielectric layer 14 is made of BaTiO ３ as a base material. ３ In this case, the first element M1 is a rare earth element such as Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, or Yb, and the second element M2 is Ni diffused from the internal electrode layer 15 and other optional additive elements. ３ The base material is a ferroelectric material and has a very large dielectric constant, which allows the multilayer ceramic capacitor 1 to have a large capacitance.

[0024] M1 is BaTiO ３ Ba in the crystal lattice of perovskite compounds of the system ２＋ Part of M1 ３＋ Ni is substituted with BaTiO ３ Ti in the crystal lattice of perovskite compounds of the system ４＋ A part of the Ni is replaced by Ni 2+ and is dissolved in the grain 140 .

[0025] The dielectric layer 14 includes a plurality of grains 140. Each grain 140 has a core-shell structure including a core portion 141 located in the center and a shell portion 142 surrounding the core portion 141. The core portion 141 has a smaller amount of the above-mentioned elements dissolved therein than the shell portion 142, and is composed of pure BaTiO ３ The molar ratio of Ba to Ti contained in the grains 140 of the core portion 141 is higher than the molar ratio of Ba to Ti contained in the grains 140 of the shell portion 142. The molar ratio of Ba to Ti contained in the grains 140 of the core portion 141 is higher than the molar ratio of Ba to Ti contained in the grains 140 of the shell portion 142, thereby improving the insulation resistance.

[0026] The shell portion 142 contains a larger amount of the first element M1 than the core portion 141. Therefore, in the vicinity of the grain boundary, ３＋ and Ba ２＋ As a result, oxygen vacancies are anchored to the Ba vacancies in the dielectric layer 14, which suppresses the movement of oxygen vacancies in the dielectric layer 14 when a DC voltage is applied. This results in BaTiO ３ The reliability of the multilayer ceramic capacitor 1 having the dielectric layer 14 containing the above-mentioned material is improved.

[0027] However, the grain 140 is not limited to a core-shell structure, and the first element and the second element may be uniformly distributed throughout the grain 140 .

[0028] (Number of Grains in Dielectric Layer 14) The multilayer ceramic capacitor 1 according to the embodiment has, for example, the following characteristics: Rated voltage: 6.3 V Initial capacitance: 15 μF Effective capacitance: 5 μF at DC 3 V Breakdown voltage: 60 V In this case, the thickness (dimension in the stacking direction T) TD of the dielectric layer 14 is preferably 0.67 μm≦TD≦0.73 μm, and more preferably approximately 0.70 μm. The number of dielectric layers 14 is preferably 405 to 430. The particle size of the grains 140 is preferably 150 nm to 200 nm, and the average number GN of the grains 140 in the thickness direction (stacking direction T) of the dielectric layer 14 is preferably 3≦GN≦4. By setting the thickness (dimension in the stacking direction T) TD of the dielectric layer 14 to 0.67 μm≦TD≦0.73 μm or less, it becomes possible to make the size of the multilayer ceramic capacitor 1 mountable in devices with restrictions on the overall height dimension of the multilayer ceramic capacitor 1, and by setting the average value GN of the number of grains 140 in the thickness direction (stacking direction T) of the dielectric layer 14 to 3≦GN≦4, it becomes possible to suppress a decrease in the insulation resistance of the dielectric layer 14 while maintaining a mountable dimension in devices with dimensional restrictions.

[0029] Further, another example of the multilayer ceramic capacitor 1 of the embodiment is as follows: Required characteristics: 10 V Initial capacitance: 10 μF Effective capacitance: 4 μF at DC 3 V Breakdown voltage: 80 V In this case, the thickness TD of the dielectric layer 14 (dimension in the stacking direction T) is preferably 0.85 μm≦TD≦0.91 μm or less, and more preferably about 0.88 μm. The number of dielectric layers 14 is preferably 350 to 375. The grain size of the grains 140 is preferably 150 to 200 nm, and the average number GN of the grains 140 in the thickness direction (stacking direction T) of the dielectric layer 14 is preferably 4≦GN≦5. By setting the thickness (dimension in the stacking direction T) TD of the dielectric layer 14 to 0.85 μm≦TD≦0.91 μm or less, it becomes possible to make the size of the multilayer ceramic capacitor 1 mountable in devices where the overall height dimension of the multilayer ceramic capacitor 1 is restricted, and by setting the average value GN of the number of grains 140 in the thickness direction (stacking direction T) of the dielectric layer 14 to 4≦GN≦5, it becomes possible to suppress a decrease in the insulation resistance of the dielectric layer 14 while observing the dimensional restriction in the height direction.

[0030] As will be described later, the opposing portions 152 where the adjacent internal electrode layers 15 face each other are effective portions that function as capacitors. The grain diameter of the dielectric layer 14 present between these effective portions is preferably larger than the grain diameter of the dielectric in the side gap portion 20.

[0031] The larger the grain diameter of a dielectric, the higher the dielectric constant, and the smaller the grain diameter, the higher the moisture resistance and durability. Since the grain diameter of the dielectric layer 14 between the effective portions is larger than the grain diameter of the dielectric in the side gap portion 20, the dielectric constant between the effective portions can be kept high, ensuring sufficient capacitance. Furthermore, high moisture resistance is achieved in the side gap portion 20, resulting in high overall moisture resistance and durability.

[0032] (Internal electrode layer 15) When the dimension of the internal electrode layer 15 in the width direction W is WI, T0<WI. Furthermore, when the dimension (thickness) of the internal electrode layer 15 in the stacking direction T is T1, TI is preferably 0.49 μm≦TI≦0.55 μm, and more preferably about 0.53 μm. When the dimension of the internal electrode layer 15 in the width direction W is WI, since T0<WI, a large internal electrode area can be secured while securing the height of the multilayer ceramic capacitor 1 that can be mounted in devices with dimensional constraints, it is possible to secure a large capacitance of the multilayer ceramic capacitor 1.

[0033] Although the internal electrode layers 15 are made of a metal material, they are not completely filled with the metal material. The internal electrode layers 15 include hollow portions where no metal material is present. When the ratio of the metal material in the internal electrode layers 15 is defined as the coverage, this coverage is preferably 85% or more.

[0034] The internal electrode layer 15 includes a plurality of first internal electrode layers 15A and a plurality of second internal electrode layers 15B. The first internal electrode layers 15A and the second internal electrode layers 15B are arranged alternately. Note that, when there is no need to particularly distinguish between the first internal electrode layers 15A and the second internal electrode layers 15B, they will be collectively referred to as the internal electrode layers 15.

[0035] The first internal electrode layer 15A includes a first opposing portion 152a opposing the second internal electrode layer 15B, and a first lead portion 151a led from the first opposing portion 152a toward the first end face C1. An end of the first lead portion 151a is exposed at the first end face C1 and is electrically connected to a first external electrode 3A described below.

[0036] The second internal electrode layer 15B includes a second opposing portion 152b opposing the first internal electrode layer 15A, and a second lead portion 151b extending from the second opposing portion 152b to the second end face C2. An end of the second lead portion 151b is electrically connected to a second external electrode 3B described below.

[0037] According to the above-described internal electrode layers 15, electric charges are accumulated in the first opposing portion 152 a of the first internal electrode layer 15 A and the second opposing portion 152 b of the second internal electrode layer 15 B, and they function as a capacitor. The opposing portion 152 where the adjacent internal electrode layers 15 face each other is an effective portion that functions as a capacitor.

[0038] (Shift amount d) As will be described later, the laminate chip 10 is formed by cutting a mother block, so that the side surfaces are formed flat by cutting, and the ends of the internal electrode layers 15 are exposed. The side gaps 20 are formed on both side surfaces of the laminate chip 10 and are manufactured by a so-called side gap 20 post-installation method.

[0039] 3 , in a WT cross section, which is a cross section in the width direction W and stacking direction T passing through the center of the laminate 2, the positional deviation d in the stacking direction T of the ends in the width direction W of two first internal electrode layers 15A and second internal electrode layers 15B adjacent to each other vertically in the stacking direction T is small, d≦5 μm. That is, the ends in the width direction W of the first internal electrode layers 15A and second internal electrode layers 15B adjacent to each other vertically in the stacking direction T are at approximately the same position in the width direction W, and the positions of the ends are aligned in the stacking direction T. By satisfying d≦5 μm, the area of ​​the internal electrode layers 15 can be secured as large as possible within dimensional constraints, and this makes it possible to secure a large capacitance of the multilayer ceramic capacitor 1.

[0040] The internal electrode layer 15 is mainly composed of Ni and contains Sn. Sn having an atomic composition percentage of 2 at % (atomic %) or more is segregated in an interface vicinity region 153, for example, about 20 nm from the surface of the internal electrode layer 15 facing the dielectric layer 14. That is, the interface vicinity region 153 shown in FIG. 4 has a larger amount of Sn than other parts of the internal electrode layer 15.

[0041] The internal electrode layer 15 is formed by firing a conductive paste for forming an internal electrode, which contains Ni powder, Ni-Sn alloy powder, and a Sn-component compounded co-material. During the firing process, the Sn-component compounded co-material, which has a high affinity, is attracted to the dielectric layer 14, and the Sn component compounded in the co-material is also attracted to the dielectric layer 14.

[0042] As a result, Sn is more likely to be present in the interface vicinity region 153 with the dielectric layer 14 than inside the internal electrode layer 15. As a result, the internal electrode layer 15 is Ni-Sn alloyed, changing the state of the interface vicinity region 153. That is, the formation of an alloy between Ni and Sn (Ni-Sn alloying) changes the state of the interface (electrical barrier height) between the ceramic dielectric layer 14 and the internal electrode layer 15, which is thought to contribute to improving the high-temperature accelerated life. In particular, the presence of a large amount of Ni-Sn alloy in the interface vicinity region 153 is presumed to play an important role in improving the high-temperature accelerated life. Therefore, it is possible to obtain a multilayer ceramic capacitor 1 with excellent high-temperature accelerated life and high reliability.

[0043] 5 is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 1. The method for manufacturing the multilayer ceramic capacitor 1 includes a material sheet preparation step S1, a material sheet lamination step S2, a mother block cutting step S3, a side gap portion formation step S4, a first firing step S5, an external electrode formation step S6, and a second firing step S7.

[0044] (Material Sheet Preparation Step S1) A powder containing the first element M1 and other additive elements is added to a powder of a barium titanate-based perovskite compound containing Ti and Ba to obtain a raw material powder. A ceramic slurry containing the raw material powder, a binder, and a solvent is prepared.

[0045] This ceramic slurry is formed into sheets on a carrier film using a die coater, gravure coater, microgravure coater or the like, to prepare ceramic green sheets for the inner layer portion 11 and ceramic green sheets for the outer layer portion 12 .

[0046] A conductive paste for forming the internal electrodes, which contains Ni powder, Ni—Sn alloy powder, and a Sn component blend, is printed in a strip-like pattern on the ceramic green sheet for the internal layer portion 11 by screen printing, inkjet printing, gravure printing, or the like. This prepares a material sheet in which the conductive paste that will become the internal electrode layer 15 is printed on the surface of the ceramic green sheet for the internal layer portion 11 that will become the dielectric layer 14.

[0047] (Material Sheet Lamination Step S2) Next, a plurality of material sheets are laminated. Specifically, the plurality of material sheets are stacked so that the strip-shaped conductive paste faces the same direction and the strip-shaped conductive paste is shifted by half a pitch between adjacent material sheets in the width direction W. Furthermore, ceramic green sheets for the outer layer portion 12, which will become the outer layer portion 12, are stacked on both sides of the plurality of stacked material sheets. Then, the stacked plurality of material sheets and the ceramic green sheets for the outer layer portion 12 are thermocompression bonded together. This forms a mother block.

[0048] (Mother Block Cutting Step S3) Next, the mother block is cut into sizes corresponding to the dimensions of the laminated chip 10.

[0049] (Side gap portion forming step S4) Next, layers that become side gap portions 20 are formed by attaching ceramic green sheets for side gap portions to both side portions of the laminate chip 10. Here, since the laminate chip 10 is formed by cutting a mother block, the side surfaces are formed flat by cutting, and the ends of the internal electrode layers 15 are exposed. The side gap portions 20 are formed on both side surfaces of the laminate chip 10, and are manufactured by a so-called side gap portion post-attachment method.

[0050] (First firing step S5) The laminate chip 10 on which the layer that will become the side gap portion 20 is formed is degreased under specified conditions in a nitrogen atmosphere, and then fired and sintered at a specified temperature in a nitrogen-hydrogen-water vapor mixed atmosphere to become the laminate 2.

[0051] The internal electrode layer 15 is formed by firing a conductive paste for forming an internal electrode, which contains Ni powder, Ni-Sn alloy powder, and a Sn-component compounded co-material. During this firing process, the Sn-component compounded co-material, which has a high affinity, is attracted to the dielectric layer 14, and the Sn component compounded in the co-material is also attracted to the dielectric layer 14.

[0052] (External Electrode Forming Step S6) Subsequently, a conductive paste for forming the external electrodes 3 is applied to the end faces C of the laminate 2.

[0053] (Second firing step S7) Then, the laminate is heated in a nitrogen atmosphere at a set firing temperature for a predetermined time, thereby baking the external electrodes 3 onto the laminate 2 to produce the multilayer ceramic capacitor 1. Note that the first firing step may not be included, and the laminate 2 may also be fired together with the external electrodes 3 in the second firing step.

[0054] As described above, the multilayer ceramic capacitor 1 of the embodiment comprises: a laminate chip 10 having inner layer portions 11 in which dielectric layers 14 and internal electrode layers 15 are alternately stacked, and outer layer portions 12 arranged on both sides of the inner layer portions 11 in the stacking direction T; a laminate 2 including side gap portions 20 arranged on both sides of the laminate chip 10 in a width direction W perpendicular to the stacking direction T; and external electrodes 3 arranged on both sides of the laminate 2 in a length direction L intersecting the stacking direction T and the width direction W, wherein the dielectric layers 14 contain Ba and Ti, and the internal electrode layers 15 contain Ni, and wherein, when the dimension of the multilayer ceramic capacitor 1 in the length direction L is L0, the dimension in the stacking direction T is T0, and the dimension in the width direction W is W0, the following relationships hold: 1.7≦L0 / T0≦2.3, and 1.0≦W0 / T0≦1.4, In a cross section passing through the stacking direction T and the width direction W at the center of the length direction L, when the amount of positional deviation in the width direction W of ends in the width direction W of internal electrode layers 15 adjacent to each other in the stacking direction T is d, d≦5 μm; Sn having an atomic composition percentage of 2 at % or more is segregated at the interface between the internal electrode layer 15 and the dielectric layer 14; when the dimension WS in the width direction W of the side gap portion 20 is and the dimension TG in the stacking direction T of the outer layer portion 12 is, 0.3≦WS / TG≦0.6; and when the dimension WI of the internal electrode layer 15 in the width direction W is, T0<WI.

[0055] (Effect) In this way, Sn with an atomic composition percentage of 2 at % or more is segregated at the interface between the internal electrode layer 15 and the dielectric layer 14. As a result, the internal electrode layer 15 is alloyed with Ni—Sn, changing the state of the interface between the dielectric layer 14 and the internal electrode layer 15. In other words, by forming an alloy of Ni and Sn (Ni—Sn alloying), the state (electrical barrier height) of the interface between the ceramic dielectric layer 14 and the internal electrode layer 15 changes, so that a highly reliable multilayer ceramic capacitor 1 with an improved high-temperature loaded life can be obtained.

[0056] Furthermore, in a cross section at the center of the length direction L, passing through the stacking direction T and the width direction W, when the amount of positional deviation in the width direction W of the ends in the width direction W of the internal electrode layers 15 adjacent to each other in the stacking direction T is d, d≦5 μm. Therefore, when the dimension WS in the width direction W of the side gap portion 20 is defined as the dimension TG in the stacking direction T of the outer layer portion 12, the dimension WS / TG can be reduced to 0.3≦WS / TG≦0.6. As a result, when the dimension L0 in the length direction L, the dimension T0 in the stacking direction T, and the dimension W0 in the width direction W of the multilayer ceramic capacitor 1 are defined as 1.7≦L0 / T0≦2.3 and 1.0≦W0 / T0≦1.4, the dimension WI in the width direction W of the internal electrode layer 15 can be increased to T0<WI, thereby increasing the area of ​​the internal electrode layer 15.

[0057] Furthermore, when the dimension TD of the dielectric layer 14 in the stacking direction T is 0.67 μm≦TD≦0.73 μm, the average number of grains in the stacking direction T of the dielectric layer 14 is 3≦GN≦5. In other words, since the average number of grains GN is relatively large, there are more grain boundaries in the dielectric layer 14 than when the number of grains is 1, and therefore the insulation resistance value is higher and durability is improved.

[0058] Furthermore, when the dimension TD of the dielectric layer 14 in the stacking direction T is 0.85 μm≦TD≦0.91 μm, the average number of grains in the stacking direction T of the dielectric layer 14 is 4≦GN≦5. In other words, since the average number of grains GN is relatively large, there are more grain boundaries in the dielectric layer 14 than when the number of grains is 1, and therefore the insulation resistance value is higher and durability is improved.

[0059] The multilayer ceramic capacitor 1 has a length direction L dimension L0 of 1.15≦L0≦1.25 μm, a width direction W dimension W0 of 0.65≦W0≦0.75 μm, a stacking direction T dimension T0 of 0.55≦T0≦0.65 μm, a width direction W dimension WS of the side gap portion 20 of 15 μm≦WS≦20 μm, and a stacking direction T dimension TG of each outer layer portion 12 of 36 μm≦TG≦43 μm, so that the size is highly versatile and ensures a balance between capacitance and breakdown voltage even in devices with dimensional constraints.

[0060] The dielectric layer 14 includes a plurality of grains 140, and the grains 140 have a core-shell structure consisting of a core portion 141 and a shell portion 142 surrounding the core portion 141, and the molar ratio of Ba to Ti contained in the grains 140 of the core portion 141 is higher than the molar ratio of Ba to Ti contained in the grains 140 of the shell portion 142. Therefore, the temperature characteristic of the dielectric constant can be flattened, and reliability can be improved.

[0061] As described above, according to the multilayer ceramic capacitor 1 of the embodiment, it is possible to provide a multilayer ceramic capacitor 1 that can ensure sufficient reliability while balancing the initial capacitance, effective capacitance, and breakdown voltage within dimensional constraints.

[0062] Although the embodiments of the present invention have been described above, the present invention also includes the following combinations. <1> A multilayer ceramic capacitor comprising: a laminate including a laminate chip having inner layer portions in which conductor layers and internal electrode layers are alternately stacked, and outer layer portions respectively disposed on both sides of the inner layer portions in a stacking direction; and side gap portions respectively disposed on both sides of the laminate chip in a width direction perpendicular to the stacking direction; and external electrodes respectively disposed on both sides of the laminate in a length direction intersecting the stacking direction and the width direction, wherein the dielectric layers contain Ba and Ti, and the internal electrode layers contain Ni, and wherein, when the length direction dimension of the multilayer ceramic capacitor is L0, the length direction dimension is T0, and the width direction dimension is W0, 1.7≦L0 / T0≦2.3 and 1.0≦W0 / T0≦1.4 are satisfied, and when the amount of positional deviation in the width direction of ends of the width direction of the internal electrode layers adjacent to each other in the stacking direction is d in a cross section at the center of the length direction, passing through the stacking direction and the width direction, d≦5 μm, a multilayer ceramic capacitor in which Sn having an atomic composition percentage of 2 at % or more is segregated at interfaces between the internal electrode layers and the dielectric layers, and where WS is the dimension in the width direction of the side gap portion and TG is the dimension in the stacking direction of the outer layer portion, WS / TG satisfies 0.3≦WS / TG≦0.6, and T0<WI is the dimension in the width direction of the internal electrode layers.

[0063] <2> The multilayer ceramic capacitor according to <1>, wherein, when the dimension TD of the dielectric layer in the stacking direction is 0.67 μm≦TD≦0.73 μm, the dielectric layer includes a plurality of grains, and an average number of grains in the stacking direction in the dielectric layer is 3≦GN≦4.

[0064] <3> The multilayer ceramic capacitor according to <1>, wherein, when the dimension TD of the dielectric layer in the stacking direction is 0.85 μm≦TD≦0.91 μm, the dielectric layer includes a plurality of grains, and an average grain number in the stacking direction in the dielectric layer is 4≦GN≦5.

[0065] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the length direction dimension L0 is 1.15≦L0≦1.25 μm, the width direction dimension W0 is 0.65≦W0≦0.75 μm, the stacking direction dimension T0 is 0.55≦T0≦0.65 μm, the width direction dimension WS of the side gap portion is 15 μm≦WS≦20 μm, and the stacking direction dimension TG of each of the outer layer portions is 36 μm≦TG≦43 μm.

[0066] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the dielectric layer includes a plurality of grains, the grains have a core-shell structure including a core portion and a shell portion surrounding the core portion, and a molar ratio of Ba to Ti contained in the grains of the core portion is higher than a molar ratio of Ba to Ti contained in the grains of the shell portion.

[0067] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 3 External electrode 10 Laminate chip 11 Inner layer portion 12 Outer layer portion 14 Dielectric layer 15 Internal electrode layer 20 Side gap portion 140 Grain 141 Core portion 142 Shell portion 151a Protruding portion 151b Protruding portion 152 Opposing portion 152a First opposing portion 152b Second opposing portion 153 Interface vicinity region

Claims

1. A multilayer ceramic capacitor comprising: a laminate including an inner layer portion in which dielectric layers and internal electrode layers are alternately stacked, a laminate chip having outer layer portions respectively disposed on both sides of the inner layer portion in a stacking direction, and side gap portions respectively disposed on both sides of the laminate chip in a width direction perpendicular to the stacking direction; and external electrodes respectively disposed on both sides of the laminate in a length direction intersecting the stacking direction and the width direction, the dielectric layers contain Ba and Ti, and the internal electrode layers contain Ni; where L0 is the length direction dimension of the multilayer ceramic capacitor, T0 is the lamination direction dimension, and W0 is the width direction dimension, and 1.7≦L0 / T0≦2.3 and 1.0≦W0 / T0≦1.4 are satisfied; In a cross section at the center in the length direction, which crosses the stacking direction and the width direction, when a positional deviation amount in the width direction of ends of the internal electrode layers adjacent to each other in the stacking direction is d, d≦5 μm; Sn having an atomic composition percentage of 2 at % or more is segregated at the interface between the internal electrode layer and the dielectric layer, where WS is the dimension in the width direction of the side gap portion and TG is the dimension in the stacking direction of the outer layer portion, and 0.3≦WS / TG≦0.6; The dimension WI of the internal electrode layer in the width direction is T0<WI. Multilayer ceramic capacitor.

2. When the dimension TD of the dielectric layer in the stacking direction is 0.67 μm≦TD≦0.73 μm, the dielectric layer includes a plurality of grains, and an average value GN of the number of grains in the stacking direction of the dielectric layer satisfies 3≦GN≦4. The multilayer ceramic capacitor according to claim 1 .

3. When the dimension TD of the dielectric layer in the stacking direction is 0.85 μm≦TD≦0.91 μm, the dielectric layer includes a plurality of grains, and an average grain number GN in the stacking direction of the dielectric layer satisfies 4≦GN≦5. The multilayer ceramic capacitor according to claim 1 .

4. The length direction dimension L0 is 1.15 μm≦L0≦1.25 μm, The width direction dimension W0 is 0.65 μm≦W0≦0.75 μm, The dimension T0 in the stacking direction is 0.55 μm≦T0≦0.65 μm, The width direction dimension WS of the side gap portion is 15 μm≦WS≦20 μm, The dimension TG of each of the outer layer portions in the stacking direction is 36 μm≦TG≦43 μm. The multilayer ceramic capacitor according to claim 1 .

5. the dielectric layer includes a plurality of grains; The grain has a core-shell structure consisting of a core portion and a shell portion surrounding the core portion, a molar ratio of Ba to Ti contained in the grains of the core portion is higher than a molar ratio of Ba to Ti contained in the grains of the shell portion; The multilayer ceramic capacitor according to claim 1 .

6. The dielectric layer includes a plurality of grains, The grain has a core-shell structure consisting of a core portion and a shell portion surrounding the core portion, a molar ratio of Ba to Ti contained in the grains of the core portion is higher than a molar ratio of Ba to Ti contained in the grains of the shell portion; The multilayer ceramic capacitor according to claim 5 .