Semiconductor device

Abstract

This semiconductor device comprises: a semiconductor element; a lead; a bonding object; a conductive bonding material that forms an electrically conductive bond between the bonding object and the lead; and a sealing resin that covers the bonding object and the lead. The lead has a lead body that has a main surface facing the bonding object, and a metal layer disposed on the main surface. The wettability of the conductive bonding material in a molten state to the material of the metal layer is more excellent than that to the material of the lead body. The conductive bonding material is bonded to the metal layer. The main surface includes, in a plan view, a relief region away from the metal layer and a flat region positioned between the metal layer and the relief region.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Various configurations have been proposed for semiconductor devices including semiconductor elements. Patent Document 1 discloses an example of a conventional semiconductor device. The semiconductor device disclosed in this document includes multiple leads, a semiconductor element, and a sealing resin. The semiconductor element is supported by the multiple leads. This semiconductor device employs a flip-chip mounting method in which electrodes of the semiconductor element are joined to the leads by solder. Parts of the leads are covered with a sealing resin.

[0003] Japanese Patent Application Laid-Open No. 2020-77694

[0004] During the manufacturing process of a semiconductor device, if molten solder spreads to unintended areas, it becomes difficult to maintain a proper bond. Also, if the sealing resin peels off from the leads, it may cause problems in using the semiconductor device.

[0005] An object of the present disclosure is to provide an improved semiconductor device compared to conventional semiconductor devices. In particular, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device that can suppress peeling of the sealing resin while maintaining an appropriate bonding state.

[0006] A semiconductor device provided by a first aspect of the present disclosure includes a semiconductor element, a lead, a bonding object, a conductive bonding material that electrically connects the bonding object and the lead, and a sealing resin that covers the bonding object and at least a portion of the lead. The lead includes a lead body having a main surface facing the bonding object, and a metal layer disposed on the main surface. The material of the metal layer has better wettability with the conductive bonding material in a molten state than the material of the lead body. The conductive bonding material is bonded to the metal layer. The main surface includes an uneven region separated from the metal layer in a plan view, and a smooth region located between the metal layer and the uneven region.

[0007] According to the above configuration, in the semiconductor device, peeling of the sealing resin can be suppressed while maintaining an appropriate bonding state.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 3 is a bottom view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 4 is a front view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 5 is a right side view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 2. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 2. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 2. FIG. 9 is a partially enlarged plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 10 is a partially enlarged cross-sectional view taken along line X-X in FIG. 9. FIG. 11 is a partially enlarged plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 12 is a partially enlarged cross-sectional view taken along line XII-XII in FIG. 11. FIG. 13 is a partially enlarged plan view showing a first modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 14 is a partially enlarged plan view showing a second modified example of the semiconductor device according to the first embodiment of the present disclosure. Fig. 15 is a partially enlarged plan view showing a third modified example of the semiconductor device according to the first embodiment of the present disclosure. Fig. 16 is a partially enlarged cross-sectional view showing a fourth modified example of the semiconductor device according to the first embodiment of the present disclosure. Fig. 17 is a partially enlarged cross-sectional view showing a fifth modified example of the semiconductor device according to the first embodiment of the present disclosure. Fig. 18 is a partially enlarged cross-sectional view showing a semiconductor device according to a second embodiment of the present disclosure. Fig. 19 is a partially enlarged cross-sectional view showing a semiconductor device according to a third embodiment of the present disclosure.

[0010] Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0011] The terms "first," "second," "third," etc. in this disclosure are used for identification purposes only and are not intended to impose any ranking on their objects.

[0012] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." In the present disclosure, "a surface A faces in (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0013] 1 to 12 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A1 of this embodiment includes a semiconductor element 1, a sealing resin 2, and a plurality of leads 4, 8, and 9. The semiconductor device A1 is a QFN (Quad Flat No-lead package) type semiconductor device, but the basic configuration of the semiconductor device of the present disclosure is not limited in any way.

[0014] FIG. 1 is a perspective view showing the semiconductor device A1. FIG. 2 is a plan view showing the semiconductor device A1. FIG. 3 is a bottom view showing the semiconductor device A1. FIG. 4 is a front view showing the semiconductor device A1. FIG. 5 is a right side view showing the semiconductor device A1. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 2. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 2. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 2. FIG. 9 is a partially enlarged plan view showing the semiconductor device A1. FIG. 10 is a partially enlarged cross-sectional view taken along line X-X in FIG. 9. FIG. 11 is a partially enlarged plan view showing the semiconductor device A1. FIG. 12 is a partially enlarged cross-sectional view taken along line XII-XII in FIG. 11.

[0015] In these figures, the thickness direction of the semiconductor element 1 is referred to as the thickness direction z. In this disclosure, "plan view" is synonymous with "viewed in the thickness direction z." A direction perpendicular to the thickness direction z is referred to as the first direction x. A direction perpendicular to the thickness direction z and the first direction x is referred to as the second direction y.

[0016] Semiconductor element 1: When the semiconductor device A1 is mounted on a circuit board or the like to form part of an electric circuit, the semiconductor element 1 performs the main electrical function of the semiconductor device A1. The specific configuration of the semiconductor element 1 is not limited in any way, and examples include an LSI (Large Scale Integration), an IC (Integrated Circuit), etc. The semiconductor element 1 of this embodiment has a rectangular shape with two sides along the first direction x and two sides along the second direction y when viewed in the z direction.

[0017] 2, 3, 6 to 8, 10, and 12, the semiconductor element 1 has an element body 10 and a plurality of electrodes 15. The element body 10 is a main body portion including a semiconductor material such as Si (silicon), and has, for example, a functional circuit (not shown) built in.

[0018] The multiple electrodes 15 are for flip-chip mounting the semiconductor element 1 to the multiple leads 4, 9. The electrodes 15 are an example of a bonding object of the present disclosure. The multiple electrodes 15 protrude from the element body 10 toward the z2 side in the thickness direction z. The material of the electrodes 15 is not limited in any way and includes metals such as Cu (copper) and Cu (copper) alloys. A plating layer (not shown) containing, for example, Ni (nickel) may be appropriately provided on the tip of the electrode 15 on the z2 side in the thickness direction z.

[0019] In the illustrated example, the semiconductor device 1 has a wiring layer 11, a first protective layer 12, a second protective layer 13, and an underlayer 14. The wiring layer 11 is disposed on the z2 side of the device body 10 in the thickness direction z. The wiring layer 11 is electrically connected to a functional circuit (not shown) formed in the device body 10. The wiring layer 11 includes, for example, Al (aluminum). The first protective layer 12 covers the wiring layer 11 from the z2 side in the thickness direction z. The first protective layer 12 includes, for example, SiN (silicon nitride). The first protective layer 12 has an opening that exposes a portion of the wiring layer 11. The second protective layer 13 covers the first protective layer 12 from the z2 side in the thickness direction z. The second protective layer 13 includes, for example, polyimide. The second protective layer 13 has an opening that overlaps the opening in the first protective layer 12. The underlayer 14 is provided to cover the opening in the second protective layer 13. The second protective layer 13 includes, for example, Cu (copper), Ni (nickel), etc. The electrode 15 is formed by growing a metal on the second protective layer 13 by, for example, plating.

[0020] Sealing resin 2: The sealing resin 2 covers the semiconductor element 1 and portions of each of the leads 4, 8, and 9. The specific configuration of the sealing resin 2 is not limited, and the constituent materials include, for example, epoxy resin. As shown in FIGS. 1 to 8 , the sealing resin 2 of this embodiment has a resin main surface 21, a resin back surface 22, a first resin side surface 23, a second resin side surface 24, a third resin side surface 25, and a fourth resin side surface 26.

[0021] The resin main surface 21 is a surface facing the z1 side in the z direction, and in the illustrated example, is a flat rectangular surface. The resin back surface 22 is a surface facing the z2 side in the z direction, and in the illustrated example, is a flat rectangular surface. The first resin side surface 23 is a surface extending along the first direction x and z directions, and facing the y1 side in the second direction y. The second resin side surface 24 is a surface extending along the second direction y and z directions, and facing the x1 side in the first direction x. The third resin side surface 25 is a surface extending along the second direction y and z directions, and facing the x2 side in the first direction x. The fourth resin side surface 26 is a surface extending along the first direction x and z directions, and facing the y2 side in the second direction y.

[0022] In this embodiment, the length of the first resin side surface 23 and the fourth resin side surface 26 in the first direction x is longer than the length of the second resin side surface 24 and the third resin side surface 25 in the second direction y.

[0023] The multiple leads 4, 8, and 9 perform functions such as supporting the semiconductor element 1 and providing a conductive path to the semiconductor element 1. The specific configuration of the multiple leads 4, 8, and 9 is not limited in any way. The multiple leads 4, 8, and 9 may include, as constituent materials, for example, Cu (copper), Ni (nickel), Fe (iron), and alloys thereof. In the following description, the multiple leads 4, 8, and 9 will be distinguished and described as the multiple leads 4, the multiple corner leads 8, and the center lead 9.

[0024] Lead 4: As shown in FIGS. 1 to 12, the multiple leads 4 are arranged in a rectangular shape in the first direction x and the second direction y. The lead 4 has a lead body 40 and a metal layer 49. FIGS. 9 and 10 show the second lead 4, counting from the y2 side in the second direction y, of the multiple leads 4 arranged on the x2 side in the first direction x in FIG. 2. FIGS. 11 and 12 show the first lead 4, counting from the y2 side in the second direction y, of the multiple leads 4 arranged on the x2 side in the first direction x in FIG. 2. For ease of understanding, the semiconductor element 1 and the sealing resin 2 are omitted in FIGS. 9 and 11.

[0025] The lead body 40 is a main body portion that constitutes the majority of the lead 4, and contains the above-mentioned Cu (copper), Ni (nickel), Fe (iron), and alloys thereof, etc. The lead body 40 has a main surface 400, a thick portion 41, a thin portion 42, a mounting surface 43, end faces 44, side faces 45, and an intermediate surface 46.

[0026] The thick portion 41 is a portion of the lead 4 that is relatively thicker in the thickness direction z (compared to the thin portion 42). The thin portion 42 is a portion of the lead 4 that is relatively thinner in the thickness direction z (compared to the thick portion 41). The shapes of the thick portion 41 and the thin portion 42 as viewed in the thickness direction z are set appropriately depending on, for example, the position where the semiconductor element 1 is mounted, etc.

[0027] The main surface 400 faces the z1 side in the thickness direction z. The main surface 400 faces the electrodes 15 of the semiconductor element 1. The main surface 400 is formed across both the thick portion 41 and the thin portion 42. The main surface 400 is covered with the sealing resin 2.

[0028] The mounting surface 43 is a surface exposed from the resin rear surface 22 of the sealing resin 2, and is formed on the thick portion 41. In the illustrated example, the mounting surface 43 is flush with the resin rear surface 22.

[0029] The end surface 44 is a surface exposed from the first resin side surface 23, the second resin side surface 24, the third resin side surface 25, and the fourth resin side surface 26 of the sealing resin 2, and faces the first direction x or the second direction y. The end surface 44 is formed in the thick portion 41. In the illustrated example, the mounting surface 43 and the end surface 44 are connected. A concave surface or the like may be interposed between the mounting surface 43 and the end surface 44. A plating layer (not shown) containing, for example, Sn (tin) may be appropriately provided on the mounting surface 43 and the end surface 44. In the illustrated example, the end surface 44 is flush with any of the first resin side surface 23, the second resin side surface 24, the third resin side surface 25, and the fourth resin side surface 26.

[0030] The side surface 45 is a surface facing a direction intersecting the thickness direction z, and is located between the main surface 400 and the end surface 443 in the thickness direction z. The side surface 45 is covered with the sealing resin 2.

[0031] The intermediate surface 46 is formed in the thin-walled portion 42. The intermediate surface 46 is located between the main surface 400 and the mounting surface 43 in the thickness direction z, and faces the z2 side in the thickness direction z, similar to the mounting surface 43. The intermediate surface 46 is covered with the sealing resin 2. The intermediate surface 46 is spaced from the resin rear surface 22 on the z1 side in the thickness direction z.

[0032] The metal layer 49 is disposed on the main surface 400. The metal layer 49 is a member to which the conductive bonding material 19 is bonded. The material of the metal layer 49 has better wettability with the molten conductive bonding material 19 than the material of the lead body 40. The shape of the metal layer 49 is not limited in any way, and various shapes such as a circle, an ellipse, a polygon, etc. can be adopted. In the illustrated example, the metal layer 49 is circular.

[0033] The main surface 400 includes a smooth region 401 and a roughened region 402. The roughened region 402 has a surface roughness greater than that of the smooth region 401. The surface roughness of the roughened region 402 is not particularly limited. An example of the surface roughness of the roughened region 402 is an arithmetic mean roughness Ra of 1 μm or more and 10 μm or less. The method for forming the roughened region 402 is not particularly limited. Examples of methods for forming the roughened region 402 include roughening treatment by etching and roughening treatment in which CuO or CuO (copper oxide) grows in a needle-like shape. Both the smooth region 401 and the roughened region 402 are covered with a sealing resin 2, and the sealing resin 2 is in direct contact with them.

[0034] In the illustrated example, the side surface 45 and the intermediate surface 46 are made to have the same textured surfaces as the textured region 402. The method for making the end surface 445 and the intermediate surface 46 have the same textured surfaces as the method for forming the textured region 402.

[0035] 9 to 12, the uneven region 402 is spaced apart from the metal layer 49 in a plan view. The smooth region 401 is located between the metal layer 49 and the uneven region 402 in a plan view. In the illustrated example, the smooth region 401 surrounds the entire periphery of the metal layer 49, and the uneven region 402 surrounds the entire periphery of the smooth region 401 in a plan view.

[0036] The uneven region 402 reaches the edge of the main surface 400 in a plan view. In the example shown, the uneven region 402 reaches all edges of the main surface 400. The uneven region 402 may reach only a part of the edge of the main surface 400, or may not reach the edge of the main surface 400. The smooth region 401 is away from the edge of the main surface 400. The smooth region 401 may reach the edge of the main surface 400.

[0037] 9 and 11 , size D of metal layer 49 (diameter of metal layer 49 in the illustrated example) is, for example, 50 μm or more and 200 μm or less, e.g., about 100 μm. Size W1 is the distance between metal layer 49 and uneven region 402, and corresponds to the width of smooth region 401. Size W1 may be, for example, 5% or more and 50% or less of size D.

[0038] The size W2 is the distance between the smooth region 401 and the edge of the main surface 400. In the example shown, the size W2 is the distance between the smooth region 401 and the tip portion of the main surface 400 in the first direction x. The size W2 may be, for example, 5% to 50% of the size D.

[0039] In the lead 4 shown in FIGS. 9 and 10 , two metal layers 49 are disposed on a main surface 400. The two metal layers 49 are spaced apart from each other. The main surface 400 includes two smooth regions 401. The two smooth regions 401 individually surround the two metal layers 49. The uneven region 402 has a portion located between the two metal layers 49 (the two smooth regions 401). The size W3 is the distance between two adjacent smooth regions 401. The size W3 may be, for example, 5% to 90% of the size D. The size W4 is the distance between adjacent metal layers 49. In the illustrated example, the size W4 is smaller than the size D.

[0040] Corner leads 8: As shown in FIGS. 1 to 5, the corner leads 8 are arranged at the four corners of the sealing resin 2 when viewed in the thickness direction z.

[0041] The corner lead 8 has a corner mounting surface 83 , a first corner end face 841 and a second corner end face 842 .

[0042] The corner mounting surface 83 faces the z2 side in the thickness direction z, and is exposed from the resin rear surface 22 of the sealing resin 2.

[0043] The first corner end face 841 faces in the second direction y and is exposed from the first resin side face 23 or the fourth resin side face 26. In the example shown, the first corner end face 841 is flush with the first resin side face 23 or the fourth resin side face 26. The second corner end face 842 faces in the first direction x and is exposed from the second resin side face 24 or the third resin side face 25. In the example shown, the second corner end face 842 is flush with the second resin side face 24 or the third resin side face 25. In the example shown, the first corner end face 841 and the second corner end face 842 are connected to each other.

[0044] Center lead 9: As shown in FIGS. 1 to 3, 5, and 7, the center lead 9 is arranged between the multiple leads 4 in the second direction y. In the illustrated example, the center lead 9 overlaps the center of the semiconductor device A1 (sealing resin 2) in the second direction y. In the illustrated example, the center lead 9 has a center thick portion 911, a center thick portion 912, a center thick portion 913, a center thin portion 921, a center thin portion 922, a center mounting surface 931, a center mounting surface 932, a center mounting surface 933, a center end surface 941, and a center end surface 942.

[0045] The center mounting surface 931, the center mounting surface 932, and the center mounting surface 933 are portions of the center lead 9 that are relatively thick in the thickness direction z (compared to the center thin portion 921 and the center thin portion 922). The center thick portion 911 has a center mounting surface 931 and a center end face 941, the center thick portion 912 has a center mounting surface 932 and a center end face 942, and the center thick portion 913 has a center mounting surface 933. The center thick portion 911 is disposed on the x1 side in the first direction x, the center thick portion 912 is disposed on the x2 side in the first direction x, and the center thick portion 913 is disposed in the center in the first direction x.

[0046] The center thin portion 921 and the center thin portion 922 are portions of the center lead 9 that are relatively thin in the thickness direction z (compared to the center thick portion 911, the center thick portion 912, and the center thick portion 913), and are spaced apart on the z1 side in the thickness direction z from the resin back surface 22. In this embodiment, the semiconductor element 1 is mounted on the center thin portion 921 and the center thin portion 922.

[0047] 2 and 3 , in this embodiment, some of the multiple electrodes 15 of the semiconductor element 1 are conductively joined to the center lead 9. The conductive joint between the electrode 15 and the center lead 9 may have the same configuration as the conductive joint between the electrode 15 and the lead 4, for example. Like the lead 4, the center lead 9 may have a configuration including a lead body 40 and members corresponding to the metal layer 49. Like the lead 4, the center lead 9 may have a surface having the same configuration as the main surface 400 including a smooth region 401 and an uneven region 402.

[0048] Next, the operation of the semiconductor device A1 will be described.

[0049] As shown in FIGS. 9 to 12 , the main surface 400 includes a smooth region 401 and an uneven region 402. The smooth region 401 surrounds the metal layer 49. The material of the metal layer 49 has better wettability with the molten conductive bonding material 19 than the material of the lead body 40. The smooth region 401 is smoother than the uneven region 402 and has worse wettability with the molten conductive bonding material 19 than the uneven region 402. Therefore, when manufacturing the semiconductor device A1, the molten conductive bonding material 19 quickly spreads along the metal layer 49 but is less likely to spread across the smooth region 401. Therefore, the molten conductive bonding material 19 tends to remain on the metal layer 49, preventing it from spreading across the smooth region 401. The uneven shape of the uneven region 402 provides a stronger adhesive strength with the sealing resin 2 than the smooth region 401. This increases the adhesive strength between the lead 4 and the sealing resin 2. This prevents the sealing resin 2 from peeling off while maintaining an appropriate bond.

[0050] If the size W1 is 5% or more and 50% or less of the size D, it helps to prevent the conductive bonding material 19 in a molten state from spreading unintentionally and the sealing resin 2 from peeling off.

[0051] The uneven region 402 reaches the edge of the main surface 400. This makes it possible to prevent the sealing resin 2 from peeling off from the main surface 400 at the edge of the main surface 400. In particular, in this example, the uneven region 402 reaches all of the edge of the main surface 400. This contributes to preventing the sealing resin 2 from peeling off.

[0052] 10 and 12 , the side surface 45 is an uneven surface. As a result, an uneven surface exists across the uneven region 402 and the side surface 45. Therefore, peeling of the sealing resin 2 at the edge of the main surface 400 can be more effectively suppressed. Since the intermediate surface 46 is an uneven surface, peeling of the sealing resin 2 can be more reliably suppressed.

[0053] 9 and 10, a part of the uneven region 402 exists between two adjacent metal layers 49. This makes it possible to suppress peeling of the sealing resin 2.

[0054] 13 to 19 show modified examples and other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above-described embodiment are given the same reference numerals. The configurations of the various parts in each modified example and each embodiment can be combined with each other as appropriate within the scope of not causing technical contradictions.

[0055] 13 shows a first modification of the semiconductor device A1. The semiconductor device A11 of this modification differs from the above-described example in the shapes of the electrode 15, the metal layer 49, and the smooth region 401.

[0056] In this modification, the metal layer 49 has a rectangular shape in a plan view. The shape of the metal layer 49 corresponds to the shape of the electrode 15, which is rectangular, for example. The smooth region 401 has a rectangular ring shape in a plan view. In this modification, the size D is, for example, the length of one side of the metal layer 49 or the size in the first direction x, which is the direction in which two metal layers 49 are adjacent to each other.

[0057] This modification also makes it possible to maintain an appropriate bonded state and suppress peeling of the sealing resin 2. As can be seen from this modification, the shapes of the electrode 15, the metal layer 49, and the smooth region 401 are not limited in any way.

[0058] 14 shows a second modification of the semiconductor device A1. The semiconductor device A12 of this modification has a different shape from the above-described example in terms of the smooth region 401 and the rough region 402.

[0059] In this modification, one smooth region 401 surrounds two metal layers 49. That is, the uneven region 402 does not exist between adjacent metal layers 49. In this modification, the size W4 may be smaller than the size W4 in the semiconductor device A1, and may be, for example, half or less of the size D.

[0060] This modification also makes it possible to maintain an appropriate bonding state and suppress peeling of the sealing resin 2. As can be seen from this modification, the shapes of the smooth region 401 and the uneven region 402 are not limited in any way.

[0061] 15 shows a third modification of the semiconductor device A1. The semiconductor device A13 of this modification has a different shape from the above-described examples in terms of the smooth region 401 and the concave-convex region 402.

[0062] In this modification, the smooth region 401 reaches the edge of the main surface 400 in a plan view. That is, a part of the edge of the main surface 400 is not in contact with the uneven region 402. The edge of the main surface 400 on the x1 side in the first direction x (the edge opposite to the end surface 44) is in contact with the uneven region 402.

[0063] This modification also makes it possible to suppress peeling of the sealing resin 2 while maintaining an appropriate bonding state. As can be understood from this modification, there are no limitations on the shapes of the smooth region 401 and the uneven region 402. The edge of the main surface 400 on the x1 side in the first direction x (the edge opposite the end surface 44) is in contact with the uneven region 402, thereby suppressing peeling between the end of the main surface 400 on the x1 side in the first direction x and the sealing resin 2.

[0064] 16 shows a fourth modification of the semiconductor device A14 of the first embodiment. The semiconductor device A14 of this modification has a different configuration of the leads 4 from the examples described above.

[0065] In this modification, the intermediate surface 46 is a smooth surface compared to the uneven region 402 and the side surface 45. This modification also makes it possible to maintain an appropriate bonding state while suppressing peeling of the sealing resin 2. As can be understood from this modification, the intermediate surface 46 may be a smooth surface.

[0066] 17 shows a fifth modification of the semiconductor device A1. The semiconductor device A15 of this modification has a different configuration of the leads 4 from the examples described above.

[0067] In this modification, the side surface 45 is a smooth surface compared to the uneven region 402. This modification also makes it possible to maintain an appropriate bonding state while suppressing peeling of the sealing resin 2. As can be understood from this modification, the side surface 45 may be a smooth surface.

[0068] 18 shows a semiconductor device according to a second embodiment of the present disclosure. A semiconductor device A2 of this embodiment includes a conductive member 5.

[0069] The conductive member 5 is electrically connected to, for example, the semiconductor element 1 (not shown). The conductive member 5 includes, for example, Cu (copper), Ni (nickel), Fe (iron), and alloys thereof. The conductive member 5 is electrically connected to the metal layer 49 of the lead 4 via a conductive bonding material 59. The conductive member 5 is an example of an object to be bonded in the present disclosure. The conductive bonding material 59 has a configuration similar to that of the conductive bonding material 19 described above.

[0070] This embodiment also makes it possible to maintain an appropriate bonding state while suppressing peeling of the sealing resin 2. As can be understood from this embodiment, the bonding object of the present disclosure is not limited in any way and may be a member containing a metal, such as the conductive member 5.

[0071] 19 shows a semiconductor device according to a third embodiment of the present disclosure. In the semiconductor device A3 of this embodiment, the semiconductor element 1 corresponds to the object to be bonded of the present disclosure.

[0072] The semiconductor element 1 of this embodiment has a metal layer 18. The metal layer 18 is disposed on the z2 side in the thickness direction z of the element body 10. The metal layer 18 includes, for example, Cu (copper), Al (aluminum), Ni (nickel), or the like.

[0073] The metal layer 18 and the metal layer 49 are bonded together by a conductive bonding material 19. The conductive bonding material 19 is not limited in any way and may be, for example, an Ag (silver) paste.

[0074] This embodiment also makes it possible to maintain an appropriate bonding state while suppressing peeling of the sealing resin 2. As can be understood from this embodiment, the object to be bonded in the present disclosure is not limited in any way and may be the semiconductor element 1 (metal layer 18). The conductive bonding material 19 may be made of various materials such as solder or Ag (silver) paste.

[0075] The semiconductor device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways. The present disclosure includes the embodiments described in the following appendices.

[0076] Supplementary Note 1. A semiconductor device comprising: a semiconductor element; a lead; an object to be bonded; a conductive bonding material that electrically connects the object to be bonded and the lead; and a sealing resin that covers the object to be bonded and at least a portion of the lead, wherein the lead has a lead body having a main surface facing the object to be bonded and a metal layer disposed on the main surface, wherein the material of the metal layer has better wettability with the conductive bonding material in a molten state than the material of the lead body, and the conductive bonding material is bonded to the metal layer, and the main surface includes an uneven region separated from the metal layer in a planar view and a smooth region located between the metal layer and the uneven region. Supplementary Note 2. The semiconductor device according to Supplementary Note 1, wherein the semiconductor element has an electrode as the object to be bonded. Supplementary Note 3. The semiconductor device according to Supplementary Note 1, wherein the minimum distance between the metal layer and the uneven region in a planar view is 5% to 50% of the size of the metal layer. Supplementary Note 4. The semiconductor device according to Supplementary Note 2 or 3, wherein the uneven region reaches an edge of the main surface in plan view.Supplementary Note 5. The semiconductor device according to Supplementary Note 4, wherein the lead body has a side surface facing a direction intersecting the main surface and covered with the sealing resin, the side surface being an uneven surface.Supplementary Note 6. The semiconductor device according to Supplementary Note 5, wherein the lead body has a mounting surface facing the opposite side to the main surface and exposed from the sealing resin, and an intermediate surface located between the main surface and the mounting surface and facing the same side as the mounting surface, the intermediate surface being an uneven surface.Supplementary Note 7. The semiconductor device according to any of Supplementary Notes 2 to 6, wherein the lead has two of the metal layers adjacent to each other.Supplementary Note 8. The semiconductor device according to Supplementary Note 7, wherein the uneven region includes a portion located between the two metal layers.Supplementary Note 9. The semiconductor device according to Supplementary Note 8, wherein the distance between the two metal layers in plan view is smaller than the size of the metal layer in plan view.Supplementary Note 10. The semiconductor device of claim 7, wherein the uneven region is not present between two of the metal layers. The semiconductor device of claim 2, wherein the uneven region surrounds the smooth region.Appendix 12. The semiconductor device according to any one of Appendixes 2 to 11, wherein the smooth region is spaced apart from the edge of the main surface in a planar view. Appendix 13. The semiconductor device according to any one of Appendixes 2 to 11, wherein the smooth region is in contact with the edge of the main surface in a planar view. Appendix 14. The semiconductor device according to any one of Appendixes 2 to 13, wherein the conductive bonding material is solder. Appendix 15. The semiconductor device according to Appendix 14, wherein the lead body contains Cu. Appendix 16. The semiconductor device according to Appendix 15, wherein the metal layer contains Ag. Appendix 17. The semiconductor device according to Appendix 15, wherein the metal layer contains Ni.

[0077] A1, A11 to A15, A2, A3: semiconductor device 1: semiconductor element 2: sealing resin 4: lead 5: conductive member (object to be bonded) 8: corner lead 9: center lead 10: element body 11: wiring layer 12: first protective layer 13: second protective layer 14: underlayer 15: electrode (object to be bonded) 18: metal layer (object to be bonded) 19: conductive bonding material 21: resin main surface 22: resin back surface 23: first resin side surface 24: second resin side surface 25: third resin side surface 26: fourth resin side surface 40: lead body 41: thick portion 42: thin portion 43: mounting surface 44: end surface 45: side surface 46: intermediate surface 49: metal layer 59: conductive bonding material 83: corner mounting surface 400: main surface 401: smooth area 402: Uneven region 443: End face 445: End face 841: First corner end face 842: Second corner end face 911 to 913: Central thick portion 921, 922: Central thin portion 931 to 933: Central mounting surface 941, 942: Central end face x: First direction y: Second direction z: Thickness direction

Claims

1. A semiconductor element; Lead and an object to be joined; a conductive bonding material that electrically bonds the object to be bonded and the lead; a sealing resin that covers the object to be joined and at least a part of the lead, the lead includes a lead body having a main surface facing the object to be bonded, and a metal layer disposed on the main surface; the material of the metal layer has better wettability with the conductive bonding material in a molten state than the material of the lead body; the conductive bonding material is bonded to the metal layer, The semiconductor device, wherein the main surface includes, in a plan view, a rough region spaced apart from the metal layer, and a smooth region located between the metal layer and the rough region.

2. The semiconductor device according to claim 1 , wherein the semiconductor element has an electrode as the object to be bonded.

3. 2. The semiconductor device according to claim 1, wherein a minimum distance between said metal layer and said concave-convex region in a plan view is 5% to 50% of a size of said metal layer.

4. The semiconductor device according to claim 2 , wherein the uneven region reaches an edge of the main surface in a plan view.

5. the lead body has a side surface facing in a direction intersecting the main surface and covered with the sealing resin, The semiconductor device according to claim 4 , wherein the side surface is an uneven surface.

6. the lead body has a mounting surface facing the opposite side to the main surface and exposed from the sealing resin, and an intermediate surface located between the main surface and the mounting surface and facing the same side as the mounting surface, 6. The semiconductor device according to claim 5, wherein said intermediate surface is an uneven surface.

7. 4. The semiconductor device according to claim 2, wherein the lead has two of the metal layers adjacent to each other.

8. The semiconductor device according to claim 7 , wherein said uneven region includes a portion located between two of said metal layers.

9. The semiconductor device according to claim 8 , wherein the distance between the two metal layers in a plan view is smaller than the size of the metal layers in a plan view.

10. The semiconductor device according to claim 7 , wherein the uneven region is not present between two of the metal layers.

11. The semiconductor device according to claim 2 , wherein the uneven region surrounds the smooth region.

12. The semiconductor device according to claim 2 , wherein the smooth region is spaced apart from an edge of the main surface in a plan view.

13. The semiconductor device according to claim 2 , wherein the smooth region is in contact with an edge of the main surface in a plan view.

14. 4. The semiconductor device according to claim 2, wherein the conductive bonding material is solder.

15. The semiconductor device according to claim 14 , wherein the lead body includes Cu.

16. The semiconductor device according to claim 15 , wherein the metal layer contains Ag.

17. The semiconductor device according to claim 15 , wherein the metal layer contains Ni.