Boost converter

Abstract

The present invention addresses the problem of achieving size reduction while suppressing a common mode noise. A boost converter (100) comprises: a positive input terminal (T1) and a negative input terminal (T2); a positive output terminal (T3) and a negative output terminal (T4); a first positive wiring portion (W11); a first negative wiring portion (W12); a second positive wiring portion (W21); a second negative wiring portion (W22); a first capacitor (1); a first switching element (Q1); a second switching element (Q2); a first inductor (11); a second inductor (12); a second capacitor (2); a third capacitor (3); a fourth capacitor (4); a third inductor (13); a fourth inductor (14); a ground conductor portion (9); a fifth capacitor (5); a sixth capacitor (6); and a seventh capacitor (7). The seventh capacitor (7) is connected between a third node (N3) and the fourth capacitor (4).

Description

Boost Converter

[0001] The present disclosure relates to a boost converter, and more particularly to a boost converter including a switching element.

[0002] In recent years, the switching frequencies of switching elements have been increasing in order to reduce the size of passive components included in switching power supply circuits. However, increasing the switching frequency can lead to increased electromagnetic noise. In particular, common-mode noise is dominant in the frequency band of 1 MHz to 300 MHz (hereinafter also referred to as the MHz band) in switching power supply circuits. Therefore, reducing common-mode noise is important in order to accommodate higher switching frequencies.

[0003] Japanese Patent Application Laid-Open No. 2003-144222 discloses a power supply circuit capable of reducing common-mode noise.

[0004] The power supply circuit disclosed in Patent Document 1 includes a DC-DC converter and a choke coil. The DC-DC converter has a switching element that switches a DC input voltage input from a DC power supply, and supplies a DC output voltage to a load according to the on / off duty ratio of the switching element. The DC-DC converter is configured, for example, by connecting the switching element in parallel with the DC power supply and using a boost chopper circuit that boosts the DC input voltage.

[0005] The choke coil has a pair of windings wound in opposite directions, and this pair of windings is connected between a DC power supply and a DC-DC converter. The power supply circuit disclosed in Patent Document 1 uses the choke coil to reduce noise generated between the DC power supply and the load.

[0006] In the power supply circuit disclosed in Patent Document 1, as the switching frequency becomes higher, the impedance of the choke coil that constitutes the noise filter needs to be increased, which may result in the choke coil becoming larger and hinder the miniaturization of the power supply circuit.

[0007] International Publication No. 2017 / 002550

[0008] An object of the present disclosure is to provide a boost converter that can be miniaturized while suppressing common-mode noise.

[0009] A boost converter according to one aspect of the present disclosure includes a positive input terminal and a negative input terminal, a positive output terminal and a negative output terminal, a first positive wiring section, a first negative wiring section, a second positive wiring section, a second negative wiring section, a first capacitor, a first switching element, a second switching element, a first inductor, a second inductor, a second capacitor, a third capacitor, a fourth capacitor, a ground conductor section, a fifth capacitor, a sixth capacitor, and a seventh capacitor. The first positive wiring section is connected to the positive input terminal. The first negative wiring section is connected to the negative input terminal. The second positive wiring section is connected to the positive output terminal. The second negative wiring section is connected to the negative output terminal. The first capacitor is connected between a first node of the first positive wiring section and a second node of the first negative wiring section. The first switching element is connected between the first positive side wiring portion and the second positive side wiring portion. The second switching element is connected between the first switching element and the first negative side wiring portion. The first inductor is provided between the first node and a third node between the first switching element and the second switching element. The second inductor is provided between a connection point of the second switching element in the first negative side wiring portion and the second node. The second capacitor is connected in parallel with the first inductor. The third capacitor is connected between a fourth node of the second positive side wiring portion and a fifth node of the second negative side wiring portion. The fourth capacitor is connected between a sixth node of the second positive side wiring portion and a seventh node of the second negative side wiring portion. The third inductor is provided between the fourth node and the sixth node. The fourth inductor is provided between the fifth node and the seventh node. The fifth capacitor is connected between an eighth node of the second positive side wiring portion and the ground conductor. The sixth capacitor is connected between a ninth node of the second negative wiring portion and the ground conductor portion, and the seventh capacitor is connected between the third node and the fourth capacitor.

[0010] FIG. 1 is a schematic circuit diagram of a boost converter according to a first embodiment. FIG. 2 is a circuit diagram of the boost converter according to the same. FIG. 3 is a circuit diagram showing an equivalent circuit in the MHz band of the boost converter according to the same. FIG. 4 is a circuit diagram used in simulating noise generated in the boost converter according to the same. FIG. 5 is a graph showing frequency characteristics of noise generated in the boost converter according to the same and a boost converter according to a comparative example. FIG. 6 is a circuit diagram of a boost converter according to a first modification of the first embodiment. FIG. 7 is a schematic circuit diagram of a boost converter according to a second modification of the first embodiment. FIG. 8 is a schematic circuit diagram of a boost converter according to a second embodiment. FIG. 9 is a circuit diagram showing an equivalent circuit in the MHz band of the boost converter according to the same. FIG. 10 is a circuit diagram of a boost converter circuit according to a third embodiment.

[0011] First Embodiment A boost converter 100 according to a first embodiment will be described below with reference to FIGS.

[0012] 1 and 2 , the boost converter 100 includes a positive input terminal T1, a negative input terminal T2, a positive output terminal T3, and a negative output terminal T4. The boost converter 100 converts a first voltage input between the positive input terminal T1 and the negative input terminal T2 into a second voltage greater than the first voltage and outputs the second voltage between the positive output terminal T3 and the negative output terminal T4. In the boost converter 100, for example, a DC power supply is connected between the positive input terminal T1 and the negative input terminal T2, and a load is connected between the positive output terminal T3 and the negative output terminal T4.

[0013] (2) Details As shown in Fig. 1 , the boost converter 100 includes a positive input terminal T1, a negative input terminal T2, a positive output terminal T3, a negative output terminal T4, a first positive wiring section W11, a first negative wiring section W12, a second positive wiring section W21, and a second negative wiring section W22. The boost converter 100 also includes a first capacitor 1, a first switching element Q1, a second switching element Q2, a first inductor 11, a second inductor 12, a second capacitor 2, a third capacitor 3, a fourth capacitor 4, a third inductor 13, and a fourth inductor 14. The boost converter 100 also includes a ground conductor 9, a fifth capacitor 5, a sixth capacitor 6, and a seventh capacitor 7. The boost converter 100 also includes a control device 10.

[0014] The positive input terminal T1 is connected to, for example, a high-potential output terminal (positive electrode) of a DC power supply E1 (see FIG. 4). The DC power supply E1 may include, for example, a battery, but is not limited to this, and may also include a DC-DC converter or an AC-DC converter.

[0015] The negative input terminal T2 is connected to, for example, the low-potential output terminal (negative electrode) of the DC power supply E1 (see FIG. 4).

[0016] A load R12 (see FIG. 4), for example, is connected between the positive output terminal T3 and the negative output terminal T4. Instead of the load R12 being connected between the positive output terminal T3 and the negative output terminal T4 of the boost converter 100, for example, a DC-AC converter may be connected.

[0017] The first positive side wiring section W11 is connected to the positive input terminal T1. That is, the first positive side wiring section W11 is a wiring section connected to the positive input terminal T1 in the boost converter 100. More specifically, the first positive side wiring section W11 is a wiring section between the positive input terminal T1 and the first switching element Q1. In other words, the first positive side wiring section W11 is an input positive bus.

[0018] The first negative side wiring section W12 is connected to the negative input terminal T2. That is, the first negative side wiring section W12 is a wiring section connected to the negative input terminal T2 in the boost converter 100. The first negative side wiring section W12 has a first end and a second end. The negative input terminal T2 is connected to the first end of the first negative side wiring section W12, and the second switching element Q2 is connected to the second end of the first negative side wiring section W12. Therefore, the second switching element Q2 is connected between the first positive side wiring section W11 and the first negative side wiring section W12. The first negative side wiring section W12 is an input negative bus.

[0019] The second positive side wiring section W21 is connected to the positive output terminal T3. That is, the second positive side wiring section W21 is a wiring section connected to the positive output terminal T3 in the boost converter 100. The second positive side wiring section W21 is a wiring section between the first switching element Q1 and the positive output terminal T3. The second positive side wiring section W21 is an output positive bus.

[0020] The second negative wiring section W22 is connected to the negative output terminal T4. That is, the second negative wiring section W22 is a wiring section connected to the negative output terminal T4 in the boost converter 100. The second negative wiring section W22 has a first end and a second end, and the first end of the second negative wiring section W22 is connected to the second switching element Q2 and the second end of the first negative wiring section W12, and the second end of the second negative wiring section W22 is connected to the negative output terminal T4. The second negative wiring section W22 is an output negative bus.

[0021] The first capacitor 1 is connected between a first node N1 of the first positive wiring portion W11 and a second node N2 of the first negative wiring portion W12. In other words, the first capacitor 1 is connected between the positive input terminal T1 and the negative input terminal T2. The first capacitor 1 has a first end and a second end. The first end of the first capacitor 1 is connected to the first node N1 of the first positive wiring portion W11, and the second end of the first capacitor 1 is connected to the second node N2 of the first negative wiring portion W12. The first capacitor 1 functions as a smoothing capacitor. The first capacitor 1 is, for example, an electrolytic capacitor. The capacitance of the first capacitor 1 is, for example, 200 nF or more and 500 μF or less.

[0022] The first switching element Q1 is connected to the first positive side wiring portion W11. The second switching element Q2 is connected between the first switching element Q1 and the first negative side wiring portion W12.

[0023] As shown in FIG. 2 , each of the first switching element Q1 and the second switching element Q2 is, for example, a normally-off n-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). In FIG. 2 , the first diode D1 connected in anti-parallel to the first switching element Q1 is a parasitic diode of the n-channel MOSFET constituting the first switching element Q1, but the present invention is not limited to this and may be an external diode. The second diode D2 connected in anti-parallel to the second switching element Q2 is a parasitic diode of the n-channel MOSFET constituting the second switching element Q2, but the present invention is not limited to this and may be an external diode. In the example shown in FIG. 2 , each of the first switching element Q1 and the second switching element Q2 has a first main terminal (drain terminal), a second main terminal (source terminal), and a control terminal (gate terminal). 2 , the first main terminal of the first switching element Q1 is connected to the second positive side wiring W21, the second main terminal of the first switching element Q1 is connected to the first main terminal of the second switching element Q2, and the second main terminal of the second switching element Q2 is connected to the first negative side wiring W12. Regarding the first diode D1, the anode of the first diode D1 is connected to the second main terminal (source terminal) of the first switching element Q1, and the cathode of the first diode D1 is connected to the first main terminal (drain terminal) of the first switching element Q1. Regarding the second diode D2, the anode of the second diode D2 is connected to the second main terminal (source terminal) of the second switching element Q2, and the cathode of the second diode D2 is connected to the first main terminal (drain terminal) of the second switching element Q2.

[0024] In the boost converter 100, the first switching element Q1 and the second switching element Q2 are controlled by the control device 10. In the boost converter 100, the first switching element Q1 and the second switching element Q2 are alternately turned on and off. The switching frequency of the first switching element Q1 and the second switching element Q2 is, for example, 1 kHz or more and 1 MHz or less.

[0025] The first inductor 11 is provided between the first node N1 and the third node N3. In terms of the circuit, the third node N3 is a connection point between the first switching element Q1 and the second switching element Q2. The first inductor 11 is, for example, a choke coil. The inductance of the first inductor 11 is, for example, not less than 200 nH and not more than 30 μH.

[0026] The second inductor 12 is provided between the second node N2 and the second negative side wiring portion W22. The inductance of the second inductor 12 is smaller than the inductance of the first inductor 11. The inductance of the second inductor 12 is, for example, 2 nH or more and 30 nH or less. The second inductor 12 is, for example, configured by a part of the first negative side wiring portion W12. In other words, the second inductor 12 is formed by, for example, a parasitic inductance component of a portion of the first negative side wiring portion W12 between the second node N2 and the second negative side wiring portion W22. In this case, the inductance of the second inductor 12 can be calculated by three-dimensional electromagnetic field analysis or impedance measurement as the parasitic inductance component of a portion of the first negative side wiring portion W12 formed on a circuit board between the second node N2 and the second negative side wiring portion W22.

[0027] The second capacitor 2 is connected in parallel to the first inductor 11. The capacitance of the second capacitor 2 is smaller than the capacitance of each of the first capacitor 1, the third capacitor 3, and the fourth capacitor 4. The second capacitor 2 is formed, for example, by the line capacitance of the first inductor 11. In this case, the capacitance of the second capacitor 2 can be calculated by three-dimensional electromagnetic field analysis or impedance measurement as the line capacitance of the first inductor 11, which is a choke coil. Therefore, the capacitance of the second capacitor 2 is uniquely determined by the winding structure of the first inductor 11, which is a choke coil.

[0028] The third capacitor 3 is connected between a fourth node N4 of the second positive side wiring portion W21 and a fifth node N5 of the second negative side wiring portion W22. In other words, the third capacitor 3 is connected in parallel to the series circuit of the first switching element Q1 and the second switching element Q2. The third capacitor 3 functions as a smoothing capacitor. The third capacitor 3 is, for example, an electrolytic capacitor. The capacitance of the third capacitor 3 is, for example, 200 nF or more and 500 μF or less.

[0029] The fourth capacitor 4 is connected between a sixth node N6 of the second positive side wiring portion W21 and a seventh node N7 of the second negative side wiring portion W22. In other words, the fourth capacitor 4 is connected between the positive output terminal T3 and the negative output terminal T4. The fourth capacitor 4 has a first end and a second end. The first end of the fourth capacitor 4 is connected to the sixth node N6 of the second positive side wiring portion W21, and the second end of the fourth capacitor 4 is connected to a seventh node N7 of the second negative side wiring portion W22. The fourth capacitor 4 functions as a smoothing capacitor. The fourth capacitor 4 is, for example, an electrolytic capacitor. The capacitance of the fourth capacitor 4 is, for example, 200 nF or more and 500 μF or less.

[0030] The third inductor 13 is connected between the fourth node N4 and the sixth node N6 of the second positive side wiring portion W21. The inductance of the third inductor 13 is smaller than the inductance of the first inductor 11. The inductance of the third inductor 13 is, for example, 2 nH or more and 30 nH or less. The third inductor 13 is, for example, configured by a part of the second positive side wiring portion W21. In other words, the third inductor 13 is formed, for example, by a parasitic inductance component of a portion of the second positive side wiring portion W21 between the fourth node N4 and the sixth node N6. In this case, the inductance of the third inductor 13 can be calculated, for example, by three-dimensional electromagnetic field analysis or impedance measurement, as the parasitic inductance component of a portion of the second positive side wiring portion W21 formed on a circuit board between the fourth node N4 and the sixth node N6.

[0031] The fourth inductor 14 is provided between the fifth node N5 and the seventh node N7 of the second negative side wiring portion W22. The inductance of the fourth inductor 14 is smaller than the inductance of the first inductor 11. The inductance of the fourth inductor 14 is, for example, 2 nH or more and 30 nH or less. The fourth inductor 14 is, for example, configured by a part of the second negative side wiring portion W22. In other words, the fourth inductor 14 is formed, for example, by a parasitic inductance component of a portion of the second negative side wiring portion W22 between the fifth node N5 and the seventh node N7. In this case, the inductance of the fourth inductor 14 can be calculated, for example, by three-dimensional electromagnetic field analysis or impedance measurement, as the parasitic inductance component of a portion of the second negative side wiring portion W22 formed on a circuit board between the fifth node N5 and the seventh node N7.

[0032] The ground conductor 9 is formed, for example, by a housing provided in the boost converter 100. The housing accommodates a circuit module of the boost converter 100. The circuit module has a circuit board (e.g., a printed wiring board) and a plurality of circuit elements arranged on the circuit board. The plurality of circuit elements include the first capacitor 1, the first switching element Q1, the second switching element Q2, the first inductor 11, the third capacitor 3, and the fourth capacitor 4 described above. The housing is conductive. The housing is made of, for example, a metal or an alloy. The housing has a function of shielding a leakage magnetic field generated in the boost converter 100. The ground conductor 9 may be a ground conductor provided on the circuit board.

[0033] The fifth capacitor 5 is connected between an eighth node N8 of the second positive wiring portion W21 and the ground conductor 9. The eighth node N8 is located in the second positive wiring portion W21 between the sixth node N6 and the positive output terminal T3. The capacitance of the fifth capacitor 5 is smaller than the capacitances of the first capacitor 1, the third capacitor 3, and the fourth capacitor 4. The fifth capacitor 5 may be formed, for example, by parasitic capacitance generated between the second positive wiring portion W21 and the ground conductor 9.

[0034] The sixth capacitor 6 is connected between a ninth node N9 of the second negative wiring portion W22 and the ground conductor 9. The ninth node N9 is located between the seventh node N7 and the negative output terminal T4 in the second negative wiring portion W22. The capacitance of the sixth capacitor 6 is smaller than the capacitances of the first capacitor 1, the third capacitor 3, and the fourth capacitor 4. The sixth capacitor 6 may be formed, for example, by parasitic capacitance generated between the second negative wiring portion W22 and the ground conductor 9.

[0035] The seventh capacitor 7 is connected between the third node N3 and the fourth capacitor 4 .

[0036] The control device 10 controls the first switching element Q1 and the second switching element Q2. The execution entity of the control device 10 includes a computer system. The computer system has one or more computers. The computer system is mainly composed of a processor and memory as hardware. The processor executes a program stored in the memory of the computer system, thereby realizing the function of the control device 10 as the execution entity in the present disclosure. The program may be pre-stored in the memory of the computer system, provided via a telecommunications line, or provided by being recorded on a non-transitory recording medium such as a memory card, optical disk, or hard disk drive (magnetic disk) readable by the computer system. The processor of the computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). The multiple electronic circuits may be integrated into a single chip or distributed across multiple chips. The multiple chips may be integrated into a single device or distributed across multiple devices.

[0037] The control device 10 outputs a first control signal that controls the on / off of the first switching element Q1 and a second control signal that controls the on / off of the second switching element Q2. Each of the first control signal and the second control signal is, for example, a PWM (Pulse Width Modulation) signal whose potential level changes between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) that is higher than the first potential level. The first switching element Q1 is turned on when the first control signal is at a high level and turned off when the first control signal is at a low level. The second switching element Q2 is turned on when the second control signal is at a high level and turned off when the second control signal is at a low level. The control device 10 sets a dead time period between the high-level period of the first control signal and the high-level period of the second control signal so that the on-period of the first switching element Q1 and the on-period of the second switching element Q2 do not overlap.

[0038] In this specification, the circuit constants of the components are defined as follows.

[0039] In this specification, the capacitance of the first capacitor 1 is C1, the capacitance of the second capacitor 2 is C2, the capacitance of the third capacitor 3 is C3, the capacitance of the fourth capacitor 4 is C4, the capacitance of the fifth capacitor 5 is C5, the capacitance of the sixth capacitor 6 is C6, and the capacitance of the seventh capacitor 7 is C7.

[0040] In this specification, the inductance of the first inductor 11 is L1, the inductance of the second inductor 12 is L2, the inductance of the third inductor 13 is L3, and the inductance of the fourth inductor 14 is L4.

[0041] Fig. 3 is a circuit diagram showing an equivalent circuit in the MHz band of the boost converter 100 of Fig. 1. In Fig. 3, the inductor 15 is an inductor having a parallel combined inductance of the third inductor 13 and the fourth inductor 14 = (L3 × L4) / (L3 + L4). Also in Fig. 3, the capacitor 56 is a capacitor having a parallel combined capacitance of the fifth capacitor 5 and the sixth capacitor 6 = C5 + C6.

[0042] Each of the first capacitor 1, the third capacitor 3, and the fourth capacitor 4 is a smoothing capacitor having a relatively large capacitance, for example, greater than or equal to 200 nF and less than or equal to 500 μF. In the boost converter 100, the impedance of each of the first capacitor 1, the third capacitor 3, and the fourth capacitor 4 in the MHz band is negligibly small compared to the impedance of each of the third inductor 13, the fourth inductor 14, and the second capacitor 2 in the MHz band. As a result, in an equivalent circuit of the boost converter 100 in the MHz band, the first node N1 and the second node N2 are considered to be short-circuited, and the first node N1 and the second node N2 can be considered to be the same node. Furthermore, in an equivalent circuit of the boost converter 100 in the MHz band, the fourth node N4 and the fifth node N5 are considered to be short-circuited, and the fourth node N4 and the fifth node N5 can be considered to be the same node. In addition, in the equivalent circuit of the boost converter 100 in the MHz band, the sixth node N6 and the seventh node N7 can be considered to be short-circuited, and the sixth node N6 and the seventh node N7 can be considered to be the same node.

[0043] The first inductor 11 is a choke coil and has an inductance of, for example, 200 nH or more and 30 μH or less. In the boost converter 100, the impedance of the first inductor 11 in the MHz band is much larger than the impedances of the third inductor 13 and the fourth inductor 14 in the MHz band. As a result, in the equivalent circuit of the boost converter 100 in the MHz band, the portion of the first inductor 11 can be considered to be in an open state.

[0044] In the equivalent circuit diagram of the boost converter 100 in the MHz band, the switching circuit unit including the first switching element Q1 and the second switching element Q2 is connected between the third node N3 and the fourth node N4 and between the third node N3 and the fourth node N4 and the fifth node N5 as a noise source that generates a voltage Vsw between the third node N3 and the fourth node N4 (or the fifth node N5) due to the operation of the first switching element Q1 and the second switching element Q2.

[0045] If we ignore mode conversion outside the circuit of the boost converter 100, the common mode noise of the boost converter 100 in the MHz band originates from the potential V1 (common mode voltage V1) of the first node N1 (or the second node N2) relative to the ground conductor 9, or the current I1 (hereinafter also referred to as the common mode current I1) flowing through the ground conductor 9.

[0046] 3 has a Wheatstone bridge circuit configuration. Therefore, when the ratio of the "impedance of the second capacitor 2" to the "second inductor 12" is equal to the ratio of the "impedance of the seventh capacitor 7" to the "parallel combined impedance of the third inductor 13 and the fourth inductor 14," the voltage transfer coefficient (= V1 / Vsw) from the switching circuit to the positive input terminal T1 and the negative input terminal T2 becomes zero. In other words, when the condition of the following equation (1) is satisfied, the voltage transfer coefficient is ideally zero.

[0047] where ω is the angular frequency.

[0048] In equation (1), the angular frequency ω can be canceled out on both sides, so equation (1) can be transformed into the following equation (2).

[0049]

[0050] In the boost converter 100, by designing each circuit constant (L2, L3, L4, C2, C7) so as to satisfy the condition of equation (2) (hereinafter also referred to as the impedance balance condition), it is possible to suppress the generation of common-mode noise due to the operation of the first switching element Q1 and the second switching element Q2, regardless of the frequency in the MHz band.

[0051] Here, equation (2) can be transformed into the following equation (3).

[0052]

[0053] Therefore, in the boost converter 100, by designing each circuit constant (L2, L3, L4, C2, C7) so as to satisfy the condition of equation (3), it is possible to suppress the generation of common-mode noise due to the operation of the first switching element Q1 and the second switching element Q2, regardless of the frequency in the MHz band.

[0054] From the viewpoint of suppressing the occurrence of common-mode noise compared to when the seventh capacitor 7 is not provided, the capacitance C7 of the seventh capacitor 7 is not limited to a value that satisfies the impedance balance condition, but may be, for example, a value that is 0.5 to 2 times the value that satisfies the impedance balance condition. In other words, the capacitance C7 of the seventh capacitor 7 may be a value that satisfies the following equation (4).

[0055]

[0056] In other words, even if the impedance balance condition is not satisfied, the boost converter 100 can reduce common-mode noise compared to a configuration that does not include the seventh capacitor 7, as long as the capacitance C7 of the seventh capacitor 7 is between 0.5 and 2 times the value that satisfies the impedance balance condition.

[0057] (3) Characteristics A1 in Fig. 5 indicates the frequency characteristics of the common mode current I1 (see Fig. 3 ) that is generated when Example 1 of the boost converter 100 according to Embodiment 1 is operated in a state in which the DC power supply E1 and the load R12 are connected as shown in Fig. 4. The common mode current I1 includes a current that flows from the third node N3 to the ground conductor 9 via the sixth node N6 and the fifth capacitor 5, and a current that flows from the third node N3 to the ground conductor 9 via the seventh node N7 and the sixth capacitor 6.

[0058] In the circuit shown in Fig. 4, a DC power supply E1 is connected between a positive input terminal T1 and a negative input terminal T2 of a boost converter 100 via a pseudo power supply network 17. In the example of Fig. 4, the pseudo power supply network 17 is a circuit network for stabilizing the power supply impedance when the DC power supply E1 is viewed from the boost converter 100. In the example of Fig. 4, the pseudo power supply network 17 includes two inductors 170 and 175, four capacitors 171, 172, 176, and 177, and four resistors 173, 174, 178, and 179. Also, in the example of Fig. 4, a load R12 is a load resistor.

[0059] The frequency characteristics of the common mode current I1 indicated by A1 in Fig. 5 are calculated by performing transient analysis using the simulation model of the circuit shown in Fig. 4 to calculate the common mode current I1 flowing through the ground conductor 9 and performing a fast Fourier transform to calculate the frequency characteristics of the common mode current I1. Also, B1 in Fig. 5 shows the frequency characteristics of the common mode current of the boost converter according to the comparative example. The boost converter according to the comparative example does not include the seventh capacitor 7 of the boost converter 100 according to the first embodiment.

[0060] In the above-described Example 1, the circuit constants of the components were set to the values ​​shown in Table 1 so as to satisfy the impedance balance conditions. Furthermore, the ESR (Equivalent Series Resistance) and ESL (Equivalent Series Inductance) were taken into consideration for each of the first capacitor 1, the third capacitor 3, the fourth capacitor 4, the fifth capacitor 5, and the sixth capacitor 6.

[0061]

[0062] 5A1 of the first embodiment shows the frequency characteristics of the common mode current I1 when the output voltage of the DC power supply E1 is 12 V, the switching frequencies of the first switching element Q1 and the second switching element Q2 are each 100 kHz, and the output power of the boost converter 100 is 144 W. The frequency characteristics of the common mode current of the comparative example shown in B1 of FIG. 5B show the characteristics under the same conditions as those of the first embodiment.

[0063] It can be seen from FIG. 5 that in Example 1, the common mode current can be reduced by several dBμA to several tens of dBμA in the frequency band of 20 MHz or more, compared to the comparative example.

[0064] In the above-described Example 1, the results of a simulation were performed using circuit constants designed to satisfy the impedance balance condition, but in reality, variations in the circuit constants occur for each component. Therefore, Table 2 shows the results of a simulation performed when the circuit constants other than the capacitance C7 of the seventh capacitor 7 were set to the same values ​​as in Table 1 and the capacitance C7 of the seventh capacitor 7 was variously changed. In Example 1, the impedance balance condition was satisfied only when the capacitance C7 of the seventh capacitor 7 was 4 nF. Note that the common mode current values ​​in Table 2 are common mode currents at 50 MHz.

[0065]

[0066] From Table 2, it can be seen that the common-mode current is minimized when the capacitance C7 of the seventh capacitor 7 satisfies the impedance balance condition (i.e., when C7 = 4 nF). Furthermore, even if the capacitance C7 of the seventh capacitor 7 does not satisfy the impedance balance condition, it can still be seen that the common-mode current can be reduced more than in the comparative example as long as the capacitance C7 of the seventh capacitor 7 is 0.5 to 2 times the value when the impedance balance condition is satisfied.

[0067] (4) Advantages The boost converter 100 according to the first embodiment includes the first capacitor 1, the second capacitor 2, the first inductor 11, the second inductor 12, the third capacitor 3, the fourth capacitor 4, the third inductor 13, the fourth inductor 14, the fifth capacitor 5, the sixth capacitor 6, and the seventh capacitor 7, with the seventh capacitor 7 connected between the third node N3 and the fourth capacitor 4. As a result, the boost converter 100 according to the first embodiment can be miniaturized while suppressing common-mode noise. More specifically, the boost converter 100 according to the first embodiment includes the second inductor 12, the second capacitor, the third inductor 13, the fourth inductor 14, and the seventh capacitor 7, and thus its equivalent circuit in the MHz band has a Wheatstone bridge circuit configuration. As a result, the boost converter 100 according to the first embodiment can suppress common-mode noise without using a common-mode choke coil, and therefore can be miniaturized while suppressing common-mode noise.

[0068] Furthermore, in the boost converter 100 according to the first embodiment, when the capacitance C7 of the seventh capacitor 7 is a value that satisfies the above-mentioned formula (3), it is possible to further reduce common-mode noise.

[0069] Furthermore, in the boost converter 100 according to the first embodiment, when the capacitance C7 of the seventh capacitor 7 satisfies the above-mentioned equation (4), a capacitor with a larger tolerance for capacitance C7 can be used as the seventh capacitor 7, and the cost of the boost converter 100 can be reduced by reducing the cost of the seventh capacitor 7.

[0070] (5) Modifications of Embodiment 1 (5.1) Modification 1 A boost converter 101 according to Modification 1 of Embodiment 1 will be described with reference to Fig. 6. Regarding the boost converter 101 according to Modification 1, components that are the same as those of the boost converter 100 according to Embodiment 1 (see Figs. 1 and 2) are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0071] The boost converter 101 according to the first modification differs from the boost converter 100 according to the first embodiment in that the first switching element Q1 is configured as a diode. The diode configuring the first switching element Q1 has an anode connected to the second switching element Q2 via the third node N3 and a cathode connected to the second positive side wiring portion W21. In the boost converter 101 according to the first modification, the control device 10 controls the on / off of the second switching element Q2.

[0072] The boost converter 101 according to the first modification includes the seventh capacitor 7, similar to the boost converter 100 according to the first embodiment, and therefore can be miniaturized while suppressing common-mode noise.

[0073] (5.2) Modification 2 A boost converter 102 according to Modification 2 of the first embodiment will be described with reference to Fig. 7. With regard to the boost converter 102 according to Modification 2, the same components as those of the boost converter 100 according to the first embodiment (see Figs. 1 and 2) are denoted by the same reference numerals, and description thereof will be omitted.

[0074] The boost converter 102 of the second modification example differs from the boost converter 100 of the first embodiment in that the seventh capacitor 7 is connected between the third node N3 and the sixth node N6, rather than between the third node N3 and the seventh node N7.

[0075] In the boost converter 102 according to Modification 2, the first node N1 and the second node N2 can be regarded as the same node in the MHz band, similar to the boost converter 100 according to Embodiment 1. Therefore, the equivalent circuit of the boost converter 102 according to Modification 2 in the MHz band is the same as that shown in Fig. 3. Therefore, similar to the boost converter 100 according to Embodiment 1, the boost converter 102 according to Modification 2 includes the seventh capacitor 7, and therefore, it is possible to achieve miniaturization while suppressing common-mode noise.

[0076] Furthermore, in the boost converter 100 according to the first embodiment, the wiring portion between the third-node N3 and the seventh capacitor 7 intersects with the second negative-side wiring portion W22 in a plan view from the thickness direction of the circuit board, and therefore, for example, a multilayer printed wiring board may be used as the circuit board, and part of the wiring portion between the third-node N3 and the seventh capacitor 7 may be routed via a via conductor or the like to a layer of the circuit board different from the layer on which the second negative-side wiring portion W22 is formed. In contrast, in the boost converter 102 according to the second modification, the wiring portion between the third-node N3 and the seventh capacitor 7 does not intersect with other wiring portions (including the second positive-side wiring portion W21 and the second negative-side wiring portion W22), and therefore it is possible to suppress the generation of unnecessary parasitic inductance components in the wiring portion between the third-node N3 and the seventh capacitor 7. Furthermore, in the boost converter 102 according to the second modification, the wiring section between the third node N3 and the seventh capacitor 7, the second positive side wiring section W21, and the second negative side wiring section W22 can be routed on the same layer, thereby improving the degree of freedom in the wiring design of the circuit board.

[0077] (5.3) Modification 3 The circuit configuration of the boost converter 100 according to Modification 3 of the first embodiment is the same as the circuit configuration of the boost converter 100 according to the first embodiment (see FIGS. 1 and 2), and therefore is not shown in the drawings.

[0078] The boost converter 100 according to Modification 3 differs from the boost converter 100 according to Embodiment 1 in that the second inductor 12, the third inductor 13, and the fourth inductor 14 are each formed of a chip inductor, and the second capacitor 2 and the seventh capacitor 7 are each formed of a chip capacitor. The inductance L2 of the second inductor 12, the inductance L3 of the third inductor 13, and the inductance L4 of the fourth inductor 14 are each, for example, 2 nH or more and 30 nH or less. Furthermore, the capacitance C2 of the second capacitor 2 and the capacitance C7 of the seventh capacitor 7 are each, for example, 2 nF or more and 30 nF or less.

[0079] In the boost converter 100 according to the third modification, it is easy to calculate the impedance between the first node N1 and the third node N3, the impedance between the second node N2 and the fifth node N5, the impedance between the fourth node N4 and the sixth node N6, and the impedance between the fifth node N5 and the seventh node N7, making it easy to design the boost converter 100 so as to satisfy the impedance balance conditions.

[0080] Second Embodiment A boost converter 103 according to a second embodiment will be described with reference to Fig. 8. With respect to the boost converter 103 according to the second embodiment, components that are the same as those of the boost converter 102 according to the second modification of the first embodiment (see Fig. 7) are denoted by the same reference numerals, and description thereof will be omitted.

[0081] (1) Configuration The boost converter 103 according to the second embodiment differs from the boost converter 102 according to the second modification of the first embodiment in that the boost converter 103 according to the second embodiment further includes an eighth capacitor 8 connected between the third node N3 and the seventh node N7. Therefore, the boost converter 103 according to the second embodiment includes a seventh capacitor 7 connected between the first end of the fourth capacitor 4 and the third node N3, and an eighth capacitor 8 connected between the second end of the fourth capacitor 4 and the third node N3.

[0082] Fig. 9 is a circuit diagram showing an equivalent circuit in the MHz band of the boost converter 103 of Fig. 8. In Fig. 9, the inductor 15 is an inductor having a parallel combined inductance of the third inductor 13 and the fourth inductor 14 = (L3 x L4) / (L3 + L4). Also in Fig. 9, the capacitor 56 is a capacitance having a parallel combined capacitance of the fifth capacitor 5 and the sixth capacitor 6 = C5 + C6.

[0083] The equivalent circuit in the MHz band of the boost converter 103 according to the second embodiment has a Wheatstone bridge circuit configuration, similar to that of the first embodiment. The impedance balance condition in the second embodiment is expressed by the following equation (5), where the capacitance of the eighth capacitor 8 is C8.

[0084]

[0085] In the boost converter 103, by designing each circuit constant (L2, L3, L4, C2, C7, C8) so as to satisfy the impedance balance condition of equation (5), it is possible to suppress the generation of common-mode noise due to the operation of the first switching element Q1 and the second switching element Q2, regardless of the frequency in the MHz band.

[0086] Here, equation (5) can be transformed into the following equation (6).

[0087]

[0088] Therefore, in the boost converter 103, by designing each circuit constant (L2, L3, L4, C2, C7, C8) so as to satisfy the condition of equation (6), it is possible to further suppress the generation of common-mode noise due to the operation of the first switching element Q1 and the second switching element Q2, regardless of the frequency in the MHz band.

[0089] Furthermore, from the viewpoint of suppressing the generation of common-mode noise compared to when the seventh capacitor 7 and the eighth capacitor 8 are not provided, the combined capacitance of the seventh capacitor 7 and the eighth capacitor 8 (=C7+C8) is not limited to a value that satisfies the impedance balance condition, but may be, for example, a value that is 0.5 to 2 times the value that satisfies the impedance balance condition. In other words, C7+C8 may be a value that satisfies the following equation (7).

[0090]

[0091] In other words, even if the impedance balance condition is not satisfied, the boost converter 103 can reduce common-mode noise compared to a configuration that does not include the seventh capacitor 7 and the eighth capacitor 8, as long as C7+C8 is a value that is 0.5 to 2 times the value that satisfies the impedance balance condition.

[0092] (2) Advantages The boost converter 103 according to the second embodiment includes a first capacitor 1, a second capacitor 2, a first inductor 11, a second inductor 12, a third capacitor 3, a fourth inductor 14, a fifth capacitor 5, a sixth capacitor 6, a seventh capacitor 7, and an eighth capacitor 8. The seventh capacitor 7 is connected between the third node N3 and the sixth node N6, and the eighth capacitor 8 is connected between the third node N3 and the seventh node N7. This enables the boost converter 103 according to the second embodiment to be miniaturized while suppressing common-mode noise. More specifically, the boost converter 103 according to the third embodiment includes the second capacitor 2, the second inductor 12, the third inductor 13, the fourth inductor 14, the seventh capacitor 7, and the eighth capacitor 8, and therefore its equivalent circuit in the MHz band has a Wheatstone bridge circuit configuration. As a result, the boost converter 103 according to the second embodiment can suppress common mode noise without using a common mode choke coil, and therefore can achieve miniaturization while suppressing common mode noise.

[0093] Furthermore, since the boost converter 103 according to the second embodiment includes the eighth capacitor 8, the capacitance of each of the seventh capacitor 7 and the eighth capacitor 8 can be made smaller than the capacitance of the seventh capacitor 7 in the boost converter 100 according to the first embodiment. As a result, the boost converter 103 according to the second embodiment can reduce the capacitance components in, for example, the first current loop when the first switching element Q1 is in the on state and the second current loop when the second switching element Q2 is in the on state, thereby suppressing ringing due to LC resonance. The first current loop is a current loop that includes the first switching element Q1, the seventh capacitor 7, and the third inductor 13. The second current loop is a current loop that includes the second switching element Q2, the eighth capacitor 8, and the fourth inductor 14.

[0094] Furthermore, in the boost converter 103 according to the second embodiment, when C7+C8 has a value that satisfies the above-mentioned formula (6), it is possible to further reduce common-mode noise.

[0095] Furthermore, in the boost converter 103 according to the second embodiment, when C7+C8 is a value that satisfies the above-mentioned equation (7), capacitors with larger capacitance tolerances can be used as the seventh capacitor 7 and the eighth capacitor 8, and the cost of the boost converter 103 can be reduced by reducing the cost of the seventh capacitor 7 and the eighth capacitor 8.

[0096] Third Embodiment A boost converter 104 according to a third embodiment will be described with reference to Fig. 10. With respect to the boost converter 104 according to the third embodiment, components that are the same as those of the boost converter 101 according to the first modification of the first embodiment (see Fig. 6) are denoted by the same reference numerals, and description thereof will be omitted.

[0097] (1) Configuration The boost converter 104 according to the third embodiment differs from the boost converter 101 according to the first modification of the first embodiment in that the boost converter 104 further includes a resistor 31 connected in series with the seventh capacitor 7 between the third node N3 and the seventh node N7. In the boost converter 104, the resistor 31 is connected between the seventh capacitor 7 and the third node N3.

[0098] In the boost converter 104, the impedance of the resistor 31 in the MHz band is sufficiently smaller than the impedance of the seventh capacitor 7 in the MHz band. "The impedance of the resistor 31 in the MHz band is sufficiently smaller than the impedance of the seventh capacitor 7 in the MHz band" means that the impedance of the resistor 31 in the MHz band is one-tenth or less, more preferably one-hundredth or less, of the impedance of the seventh capacitor 7 in the MHz band. In the boost converter 104, the circuit constant of the resistor 31 is set so that the impedance of the resistor 31 in the MHz band is sufficiently smaller than the impedance of the seventh capacitor 7 in the MHz band. The resistor 31 has a characteristic that its impedance is constant regardless of frequency. The seventh capacitor 7 has a characteristic that its impedance decreases as the frequency increases.

[0099] In the boost converter 104 according to the third embodiment, the impedance of the resistor 31 in the MHz band is sufficiently smaller than the impedance of the seventh capacitor 7 in the MHz band, so the resistor 31 can be ignored when considering the equivalent circuit of the boost converter 104 in the MHz band. Therefore, the equivalent circuit of the boost converter 104 in the MHz band is the same as the equivalent circuit of the boost converter 100 according to the first embodiment in the MHz band. Therefore, the impedance balance condition in the third embodiment is the same as the impedance balance condition in the first embodiment, and is the same as the above-mentioned equation (2). Note that in the boost converter 104, the first switching element Q1 is configured as a diode, but may be configured as an n-channel MOSFET, as in the boost converter 100 according to the first embodiment.

[0100] (2) Advantages The boost converter 104 according to the third embodiment includes the seventh capacitor 7, similar to the boost converter 100 according to the first embodiment, and therefore can be miniaturized while suppressing common-mode noise.

[0101] Furthermore, the boost converter 104 according to the third embodiment further includes a resistor 31 connected in series to the seventh capacitor 7 between the third node N3 and the seventh node N7, and therefore the resistor 31 is also included in the current loop including the second diode D2, the seventh capacitor 7, and the fourth inductor 14.

[0102] According to the above configuration, resonance in the current loop can be suppressed, and ringing when the second switching element Q2 changes from the off state to the on state can be suppressed, thereby making it possible to further suppress common-mode noise.

[0103] (Other Modifications) The above-described first to third embodiments are merely examples of various embodiments of the present disclosure. The above-described first to third embodiments can be modified in various ways depending on the design, etc., as long as the object of the present disclosure can be achieved.

[0104] Furthermore, each of the first switching element Q1 and the second switching element Q2 in the boost converter 100 according to the first embodiment is not limited to an n-channel MOSFET, but may be a p-channel MOSFET. Although each of the first switching element Q1 and the second switching element Q2 is a Si-based MOSFET, the present invention is not limited thereto and may be, for example, a SiC-based MOSFET. Each of the first switching element Q1 and the second switching element Q2 may be, for example, a bipolar transistor, an IGBT (Insulated Gate Bipolar Transistor), or a GaN-based GIT (Gate Injection Transistor).

[0105] Furthermore, the resistor 31 described in the third embodiment may be provided in each of the second modification of the first embodiment, the third modification of the first embodiment, and the second embodiment.

[0106] (Aspects) The following aspects are disclosed in this specification.

[0107] A boost converter (100; 101; 102; 103) according to a first aspect includes a positive input terminal (T1) and a negative input terminal (T2), a positive output terminal (T3) and a negative output terminal (T4), a first positive side wiring portion (W11), a first negative side wiring portion (W12), a second positive side wiring portion (W21), a second negative side wiring portion (W22), a first capacitor (1), a first switching element (Q1), a second switching element (Q2), a first inductor (11), a second inductor (12), a second capacitor (2), a third capacitor (3), a fourth capacitor (4), a third inductor (13), a fourth inductor (14), a ground conductor portion (9), a fifth capacitor (5), a sixth capacitor (6), and a seventh capacitor (7). The first positive wiring portion (W11) is connected to the positive input terminal (T1). The first negative wiring portion (W12) is connected to the negative input terminal (T2). The second positive wiring portion (W21) is connected to the positive output terminal (T3). The second negative wiring portion (W22) is connected to the negative output terminal (T4). The first capacitor (1) is connected between a first node (N1) of the first positive wiring portion (W11) and a second node (N2) of the first negative wiring portion (W12). The first switching element (Q1) is connected between the first positive wiring portion (W11) and the second positive wiring portion (W21). The second switching element (Q2) is connected between the first switching element (Q1) and the first negative wiring portion (W12). The first inductor (11) is provided between the first node (N1) and a third node (N3) between the first switching element (Q1) and the second switching element (Q2). The second inductor (12) is provided between the connection point of the second switching element (Q2) in the first negative side wiring portion (W12) and the second node (N2). The second capacitor (2) is connected in parallel with the first inductor (11). The third capacitor (3) is connected between the fourth node (N4) of the second positive side wiring portion (W21) and the fifth node (N5) of the second negative side wiring portion (W22). The fourth capacitor (4) is connected between the sixth node (N6) of the second positive side wiring portion (W21) and the seventh node (N7) of the second negative side wiring portion (W22). The third inductor (13) is provided between the fourth node (N4) and the sixth node (N6).The fourth inductor (14) is provided between the fifth node (N5) and the seventh node (N7). The fifth capacitor (5) is connected between the eighth node (N8) of the second positive side wiring portion (W21) and the ground conductor portion (9). The sixth capacitor (6) is connected between the ninth node (N9) of the second negative side wiring portion (W22) and the ground conductor portion (9). The seventh capacitor (7) is connected between the third node (N3) and the fourth capacitor (4).

[0108] According to this aspect, it is possible to achieve miniaturization while suppressing common mode noise.

[0109] In the boost converter (100; 101; 102; 103) according to the second aspect, in the first aspect, the seventh capacitor (7) is connected between the third node (N3) and the sixth node (N6).

[0110] According to this aspect, it is possible to prevent an unnecessary parasitic inductance component from occurring between the third node (N3) and the seventh capacitor (7).

[0111] A boost converter (100; 101; 102; 104) according to a third aspect is the boost converter (100; 101; 102; 104) according to the first or second aspect, wherein, when the capacitance of the second capacitor (2) is C2, the inductance of the second inductor (12) is L2, the inductance of the third inductor (13) is L3, the inductance of the fourth inductor (14) is L4, and the capacitance of the seventh capacitor (7) is C7,

[0112] Satisfy.

[0113] According to this aspect, it is possible to further reduce common mode noise.

[0114] A boost converter (100; 101; 102; 104) according to a fourth aspect is a boost converter (100; 101; 102; 104) according to the first or second aspect, in which, when the capacitance of the second capacitor (2) is C2, the inductance of the second inductor (12) is L2, the inductance of the third inductor (13) is L3, the inductance of the fourth inductor (14) is L4, and the capacitance of the seventh capacitor (7) is C7,

[0115] Satisfy.

[0116] According to this aspect, a capacitor with a larger capacitance tolerance can be used as the seventh capacitor (7), and the cost of the boost converter (100; 101; 102; 104) can be reduced by reducing the cost of the seventh capacitor (7).

[0117] The boost converter (103) according to the fifth aspect is the second aspect, further comprising an eighth capacitor (8) connected between the third node (N3) and the seventh node (N7).

[0118] According to this aspect, the capacitance components in the first current loop when the first switching element (Q1) is in the on state and the second current loop when the second switching element (Q2) is in the on state can be reduced, thereby suppressing the occurrence of ringing due to LC resonance.

[0119] A boost converter (103) according to a sixth aspect is the fifth aspect, in which, when the capacitance of the second capacitor (2) is C2, the inductance of the second inductor (12) is L2, the inductance of the third inductor (13) is L3, the inductance of the fourth inductor (14) is L4, the capacitance of the seventh capacitor (7) is C7, and the capacitance of the eighth capacitor (8) is C8,

[0120] Satisfy.

[0121] According to this aspect, it is possible to further reduce common mode noise.

[0122] A boost converter (103) according to a seventh aspect is the fifth aspect, in which, when the capacitance of the second capacitor (2) is C2, the inductance of the second inductor (12) is L2, the inductance of the third inductor (13) is L3, the inductance of the fourth inductor (14) is L4, the capacitance of the seventh capacitor (7) is C7, and the capacitance of the eighth capacitor (8) is C8,

[0123] Satisfy.

[0124] According to this aspect, it is possible to use capacitors with a larger capacitance tolerance as each of the seventh capacitor (7) and the eighth capacitor (8), and it is possible to reduce the cost of the boost converter (103) by reducing the cost of the seventh capacitor (7) and the eighth capacitor (8).

[0125] In a boost converter (100; 101; 102; 103; 104) according to an eighth aspect, in any one of the first to seventh aspects, the second inductor (12) is configured from a part of the first negative side wiring portion (W12), the third inductor (13) is configured from a part of the second positive side wiring portion (W21), and the fourth inductor (14) is configured from a part of the second negative side wiring portion (W22).

[0126] According to this aspect, the number of parts can be reduced, and it is possible to achieve miniaturization and cost reduction.

[0127] In a boost converter (100; 101; 102; 103; 104) according to a ninth aspect, in any one of the first to eighth aspects, the first inductor (11) is a choke coil, and the second capacitor (2) is a line capacitance of the choke coil.

[0128] According to this aspect, the number of parts can be reduced, and it is possible to achieve miniaturization and cost reduction.

[0129] The boost converter (100; 101; 102; 103; 104) according to a tenth aspect is any one of the first to ninth aspects, and further comprises a resistor (31) connected in series with the seventh capacitor (7) between the third node (N3) and the seventh node (N7).

[0130] According to this aspect, it is possible to further suppress common mode noise.

[0131] REFERENCE SIGNS LIST 1 First capacitor 2 Second capacitor 3 Third capacitor 4 Fourth capacitor 5 Fifth capacitor 6 Sixth capacitor 7 Seventh capacitor 8 Eighth capacitor 9 Ground conductor section 10 Control device 11 First inductor 12 Second inductor 13 Third inductor 14 Fourth inductor 31 Resistor 100, 101, 102, 103, 104 Boost converter Q1 First switching element Q2 Second switching element T1 Positive input terminal T2 Negative input terminal T3 Positive output terminal T4 Negative output terminal W11 First positive side wiring section W12 First negative side wiring section W21 Second positive side wiring section W22 Second negative side wiring section

Claims

1. a positive input terminal and a negative input terminal; a positive output terminal and a negative output terminal; a first positive wiring portion connected to the positive input terminal; a first negative wiring portion connected to the negative input terminal; a second positive wiring portion connected to the positive output terminal; a second negative wiring portion connected to the negative output terminal; a first capacitor connected between a first node of the first positive wiring portion and a second node of the first negative wiring portion; a first switching element connected between the first positive side wiring portion and the second positive side wiring portion; a second switching element connected between the first switching element and the first negative side wiring portion; a first inductor provided between the first node and a third node between the first switching element and the second switching element; a second inductor provided between a connection point of the second switching element in the first negative side wiring portion and the second node; a second capacitor connected in parallel to the first inductor; a third capacitor connected between a fourth node of the second positive wiring portion and a fifth node of the second negative wiring portion; a fourth capacitor connected between a sixth node of the second positive wiring portion and a seventh node of the second negative wiring portion; a third inductor provided between the fourth node and the sixth node; a fourth inductor provided between the fifth node and the seventh node; a ground conductor portion; a fifth capacitor connected between an eighth node of the second positive wiring portion and the ground conductor portion; a sixth capacitor connected between a ninth node of the second negative wiring portion and the ground conductor portion; a seventh capacitor connected between the third node and the fourth capacitor; Boost converter.

2. the seventh capacitor is connected between the third node and the sixth node; The boost converter of claim 1 .

3. When the capacitance of the second capacitor is C2, the inductance of the second inductor is L2, the inductance of the third inductor is L3, the inductance of the fourth inductor is L4, and the capacitance of the seventh capacitor is C7, [Equation 1] Satisfy the 3. The boost converter according to claim 1 or 2.

4. When the capacitance of the second capacitor is C2, the inductance of the second inductor is L2, the inductance of the third inductor is L3, the inductance of the fourth inductor is L4, and the capacitance of the seventh capacitor is C7, [Equation 2] Satisfy the 3. The boost converter according to claim 1 or 2.

5. further comprising an eighth capacitor connected between the third node and the seventh node; The boost converter of claim 2 .

6. When the capacitance of the second capacitor is C2, the inductance of the second inductor is L2, the inductance of the third inductor is L3, the inductance of the fourth inductor is L4, the capacitance of the seventh capacitor is C7, and the capacitance of the eighth capacitor is C8, [Equation 3] Satisfy the The boost converter of claim 5 .

7. When the capacitance of the second capacitor is C2, the inductance of the second inductor is L2, the inductance of the third inductor is L3, the inductance of the fourth inductor is L4, the capacitance of the seventh capacitor is C7, and the capacitance of the eighth capacitor is C8, [Equation 4] Satisfy the The boost converter of claim 5 .

8. the second inductor is configured by a part of the first negative side wiring portion, the third inductor is configured by a part of the second positive side wiring portion, the fourth inductor is configured by a part of the second negative side wiring portion; The boost converter according to any one of claims 1, 2, and 5 to 7.

9. the first inductor is a choke coil, the second capacitor is a line capacitance of the choke coil; The boost converter according to any one of claims 1, 2, and 5 to 7.

10. further comprising a resistor connected in series with the seventh capacitor between the third node and the seventh node; The boost converter according to any one of claims 1, 2, and 5 to 7.

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