Semiconductor substrate, and method and apparatus for producing semiconductor substrate

Abstract

This semiconductor substrate is provided with: a base substrate which comprises a main substrate that is mainly composed of a material that is not a nitride semiconductor, and a first modification layer that is positioned on the main substrate and comprises one or more modification spots; a mask pattern which is positioned on the base substrate, and has a first opening part, a mask part and a second opening part aligned in this order in a first direction; a first nitride semiconductor part which is positioned above the first opening part and the mask part; and a second nitride semiconductor part which is positioned above the second opening part and the mask part, while being at a distance from the first nitride semiconductor part in the first direction.

Description

Semiconductor substrate, semiconductor substrate manufacturing method and manufacturing apparatus

[0001] The present disclosure relates to semiconductor substrates and the like.

[0002] Patent Document 1 discloses a technique for forming a GaN-based semiconductor layer on a heterogeneous substrate (for example, a sapphire substrate) using an ELO (Epitaxial Lateral Overgrowth) method.

[0003] JP 2013-251304 A

[0004] The semiconductor substrate according to the present disclosure includes a main substrate mainly composed of a material that is not a nitride semiconductor, and is provided with a base substrate on which a first modified layer including one or more modified spots is located, a first nitride semiconductor portion located on the base substrate and having the second direction as its longitudinal direction, and a second nitride semiconductor portion located on the base substrate and having the second direction as its longitudinal direction, the first direction and the second direction intersecting each other.

[0005] 1 is a perspective view showing an example of the configuration of a semiconductor substrate according to the present embodiment; FIG. 2 is a perspective view showing an example of the configuration of a semiconductor substrate according to the present embodiment; FIG. 3 is a schematic view showing an example of the configuration of a modified spot; FIG. 4 is a schematic view showing the effect of reducing warpage of a semiconductor substrate according to the present embodiment; FIG. 5 is a schematic plan view showing an example of the configuration of a first modified layer; FIG. 6 is a perspective view showing an example of the configuration of a semiconductor substrate; FIG. 7 is a perspective view showing an example of the configuration of a semiconductor substrate; FIG. 8 is a perspective view showing an example of the configuration of a semiconductor substrate; FIG. 9 is a perspective view showing an example of the configuration of a semiconductor substrate; FIG. 10 is a schematic plan view showing an example of the configuration of a second modified layer; FIG. 11 is a perspective view showing an example of the configuration of a semiconductor substrate; FIG. 12 is a perspective view showing an example of the configuration of a semiconductor substrate; FIG. 13 is a flowchart showing a method for manufacturing a semiconductor substrate according to the present embodiment; FIG. 14 is a perspective view showing a method for manufacturing a semiconductor substrate according to the present embodiment; FIG. 15 is a perspective view showing a method for manufacturing a semiconductor substrate according to the present embodiment; FIG. 16 is a cross-sectional view showing a change in warpage when a first modified layer is formed in a layer below a main substrate; FIG. 17 is a schematic view showing an example of layer quality change of a modified layer. 27 is a cross-sectional view showing a change in warpage when a modified layer is formed in an intermediate layer of a main substrate. FIG. 27 is a cross-sectional view when a nitride semiconductor section is formed on the base substrate of FIG. 24. FIG. 27 is a perspective view when a nitride semiconductor section is formed on the base substrate of FIG. 24. FIG. 27 is a cross-sectional view showing a change in warpage when a plurality of modified layers are formed over the entire main substrate. FIG. 27 is a perspective view when a nitride semiconductor section is formed on the base substrate of FIG. 27. FIG. 27 is a cross-sectional view showing an example of the configuration of a semiconductor substrate. FIG. 27 is a cross-sectional view showing an example of the configuration of a semiconductor substrate. FIG. 27 is a flowchart showing a method for manufacturing a semiconductor substrate according to the present embodiment. FIG. 27 is a perspective view showing a method for manufacturing a semiconductor substrate according to the present embodiment. FIG. 27 is a perspective view showing an example of the configuration of a semiconductor substrate. FIG. 27 is a perspective view showing an example of the configuration of a semiconductor substrate. FIG. 27 is a perspective view showing an example of the configuration of a semiconductor substrate.10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor element according to a second embodiment.

[0006] 1 and 2 are perspective views showing an example of the configuration of a semiconductor substrate according to this embodiment. As shown in FIGS. 1 and 2, a semiconductor substrate 10 according to this embodiment includes a main substrate 1 mainly composed of a material other than a nitride semiconductor, and includes a base substrate BS on which a first modified layer F1 including one or more modified spots S is located; a mask pattern 6 located on the base substrate BS and including a first opening K1, a mask portion 5, and a second opening K2 arranged in this order in a first direction X1; a first nitride semiconductor portion 8F located on the first opening K1 and the mask portion 5 and having a longitudinal direction that is a second direction X2 intersecting the first direction X1; and a second nitride semiconductor portion 8S located on the second opening K2 and the mask portion 5 and having a longitudinal direction that is the second direction X2 and spaced apart from the first nitride semiconductor portion 8F in the first direction X1. The first direction X1 and the second direction X2 may be orthogonal, for example.

[0007] Hereinafter, the first nitride semiconductor portion 8F and the second nitride semiconductor portion 8S may be collectively referred to as the nitride semiconductor portion 8. The first opening K1 and the second opening K2 may be collectively referred to as the opening K. The direction from the base substrate BS to the nitride semiconductor portion 8 may be described as "upward." Viewing an object with a line of sight parallel to the normal direction of the semiconductor substrate 10 (including perspective views) may be referred to as "planar view."

[0008] FIG. 3 is a schematic diagram showing an example of the configuration of a modified spot. As shown in FIG. 3, the modified spot S of the first modified layer F1 may include at least one of a void portion 12 (void 12) and a crystalline modified portion 13 (crystalline modified substance 13). The crystalline modified portion 13 may be a polycrystalline portion contained in the single-crystal main substrate 1. The crystalline modified portion 13 may be an amorphous portion contained in the single-crystal main substrate 1. The void 12 of the modified spot S may have a downwardly or upwardly convex crescent shape. The diameter of the modified spot S may be a diameter, a major axis, or a minor axis. The void 12 and the crystalline modified substance 13 can be confirmed, for example, by SEM or TEM.

[0009] The nitride semiconductor portion 8 contains a nitride semiconductor as a main component. The nitride semiconductor can be expressed as AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), for example. Specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). A GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.

[0010] The nitride semiconductor portion 8 may be doped (e.g., n-type including donors) or non-doped. The semiconductor substrate means a substrate including a nitride semiconductor, and the base substrate BS may include a semiconductor that is not a nitride semiconductor (e.g., silicon, silicon carbide, etc.) or a non-semiconductor. The base substrate BS and the mask pattern 6 may be collectively referred to as the template substrate TS (growth substrate).

[0011] The first direction X1 may be the a-axis direction (<11-20> direction) of the nitride semiconductor portion 8. The second direction X2 may be the m-axis direction (<1-100> direction) of the nitride semiconductor portion 8. The third direction X3 may be the c-axis direction (<0001> direction) of the first nitride semiconductor portion 8F.

[0012] The first nitride semiconductor portion 8F can be formed by the epitaxial lateral overgrowth (ELO) method, starting from the seed portion 3 exposed below the first opening K1. The portion of the first nitride semiconductor portion 8F located above the first opening K1 becomes a dislocation inherited portion with many threading dislocations, while the portion located above the mask portion 5 (wing portion) becomes a low-defect portion with a lower threading dislocation density than the dislocation inherited portion. The second nitride semiconductor portion 8S grows laterally on the mask portion 5 starting from the seed portion 3 exposed below the second opening K2, and growth is stopped before joining the first nitride semiconductor portion 8F. The mask portion 5 is not limited to a member covered by the base substrate BS. The mask portion 5 may be any portion that suppresses semiconductor growth.

[0013] 4 is a schematic diagram showing the effect of reducing warpage of a semiconductor substrate according to this embodiment. In the semiconductor substrate 10, the main substrate 1 includes a first modified layer F1, and the first modified layer F1 can adjust the thermal expansion characteristics of the main substrate 1. As a result, as shown in FIG. 4 , warpage (e.g., downward convex warpage in the X2 direction) of the semiconductor substrate 10 including the striped nitride semiconductor portion 8 having the second direction X2 as its longitudinal direction can be reduced.

[0014] The nitride semiconductor portion 8 may be primarily composed of a GaN-based semiconductor, and the main substrate 1 may be primarily composed of silicon (Si), which has a thermal expansion coefficient at 1000°C that is smaller than that of a GaN-based semiconductor. For example, if the nitride semiconductor portion 8 (GaN) is epitaxially grown above the main substrate 1 (Si substrate) at approximately 1000°C and then returned to room temperature, the nitride semiconductor portion 8 may shrink more than the main substrate 1, resulting in downward convex warping. However, by providing a first modified layer F1 on the main substrate 1 before epitaxial growth of the nitride semiconductor portion 8, the shrinkage of the main substrate 1 and the nitride semiconductor portion 8 when returned to room temperature is reduced, thereby reducing downward convex warping. The main substrate 1 is not limited to a silicon substrate and may be, for example, a silicon carbide substrate or a sapphire substrate. In other words, the main substrate may have silicon, silicon carbide, or sapphire as its primary component. As another example, the main substrate and the nitride semiconductor portion may be made of a material having the same primary component. When the main substrate is primarily made of a nitride semiconductor, stress due to differences in the thermal expansion coefficients of the materials is nonexistent or extremely small compared to heterogeneous substrates. However, stress may occur due to other structural factors or the external environment, and the modified layer can alleviate this stress.

[0015] The base substrate BS may have a seed portion 3 located between the main substrate 1 and the mask pattern 6, and the seed portion 3 may be exposed in the first opening K1 and the second opening K2. Providing the seed portion 3 can improve the crystallinity of the nitride semiconductor portion 8. A buffer portion 2 may be provided between the main substrate 1 and the seed portion 3. For example, when a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is used for the seed portion 3, the buffer portion 2 may be made of AlN (aluminum nitride) or the like.

[0016] 1, the first modified layer F1 may be located above the midpoint MP between the upper and lower surfaces of the main substrate 1. By increasing the thermal expansion characteristics of the upper side of the main substrate, warpage of the semiconductor substrate 10 can be more effectively reduced.

[0017] 5 is a schematic plan view showing an example of the configuration of the first modified layer. As shown in FIG. 5, in the first modified layer F1, a plurality of modified spots S (modified spot group) arranged in a matrix may include a first spot row L1 consisting of a plurality of modified spots S arranged in the first direction X1 and a first spot column C1 consisting of a plurality of modified spots S arranged in the second direction X2. The first spot column C1 may have a larger number of modified spots per unit length than the first spot row L1. This can more effectively reduce downward convex warping in the X2 direction.

[0018] 6 is a perspective view showing an example of the configuration of a semiconductor substrate. As shown in FIG. 6, the first spot row L1 may have a larger number of modified spots per unit length than the first spot column C1.

[0019] FIG. 7 is a perspective view showing an example of the configuration of a semiconductor substrate. FIG. 8 is a schematic plan view showing an example of the configuration of a first modified layer. As shown in FIGS. 2 , 6 , 7 , and 8 , the first modified layer F1 may include a modified spot S located below the first opening K1. The first modified layer F1 may include a first spot row C1 consisting of a plurality of modified spots S aligned in the second direction X2, and the first spot row C1 may be located below the first opening K1. In other words, in a plan view, the first spot row C1 may overlap with the elongated first opening K1. Because the nitride semiconductor portion 8 is crystalline bonded to the seed portion 3 exposed in the first opening K1, arranging the first spot row C1 below the first opening K1, whose elongated direction is the second direction X2, can more effectively reduce warpage of the semiconductor substrate 10. As shown in Figures 2 and 6, a portion of the multiple first spot rows C1 arranged at equal pitch in the first direction X1 may be arranged under the openings of the mask pattern, or as shown in Figures 7 and 8, the first spot rows C1 may be arranged only under the openings of the mask pattern.

[0020] As shown in Figures 1 and 7, the first nitride semiconductor portion 8F includes a wing portion W1 located on the mask portion 5, and the value obtained by dividing the number of modified spots S located under the wing portion W1 (overlapping with the wing portion W1 in a planar view) by the area of ​​the wing portion W1 (e.g., the area of ​​the top surface) may be smaller than the value obtained by dividing the number of modified spots S located under the first opening K1 (overlapping with the first opening K1 in a planar view) by the area of ​​the first opening K1 (e.g., the area of ​​the opening surface).

[0021] 9 is a perspective view showing an example of the configuration of a semiconductor substrate. As shown in Fig. 9, the first nitride semiconductor portion 8F includes a wing portion W1 located on the mask portion 5, and the value obtained by dividing the number of modified spots located below the wing portion W1 by the area of ​​the wing portion W1 may be larger than the value obtained by dividing the number of modified spots located below a gap GP between the first nitride semiconductor portion 8F and the second nitride semiconductor portion 8S by the area of ​​the gap GP.

[0022] 10 is a perspective view showing an example of the configuration of a semiconductor substrate. As shown in Fig. 10, the first nitride semiconductor portion 8F includes a wing portion W1 located on the mask portion 5, and the average diameter of the multiple modified spots S located below the first opening K1 may be larger than the average diameter of the multiple modified spots S located below the wing portion W1.

[0023] 11 and 12 are perspective views showing exemplary configurations of a semiconductor substrate. As shown in FIGS. 11 and 12, the first modified layer F1 may be located below the midpoint MP between the top and bottom surfaces of the main substrate 1. In the first modified layer F1, a plurality of modified spots S (modified spot groups) arranged in a matrix may include a first spot row L1 consisting of a plurality of modified spots S arranged in a first direction X1 and a first spot column C1 consisting of a plurality of modified spots S arranged in a second direction X2. As shown in FIG. 11, the first spot column C1 may have a greater number of modified spots per unit length than the first spot row L1. As shown in FIG. 12, the first spot row L1 may have a greater number of modified spots per unit length than the first spot column C1.

[0024] Fig. 13 is a perspective view showing an example of the configuration of a semiconductor substrate. Fig. 14 is a plan view showing an example of the configuration of a second modified layer. As shown in Fig. 13, the main substrate 1 may have a first modified layer F1 located above the midpoint between the top and bottom surfaces of the main substrate 1, and a second modified layer F2 located below the midpoint between the top and bottom surfaces of the main substrate 1 and including one or more modified spots S.

[0025] In the first modified layer F1, the plurality of modified spots S (modified spot group) arranged in a matrix may include a first spot row L1 consisting of a plurality of modified spots S arranged in a first direction X1, and a first spot column C1 consisting of a plurality of modified spots S arranged in a second direction X2. In the second modified layer F2, the plurality of modified spots S (modified spot group) arranged in a matrix may include a second spot row L2 consisting of a plurality of modified spots S arranged in the first direction X1, and a second spot column C2 consisting of a plurality of modified spots S arranged in the second direction X2. The first spot column C1 may have a larger number of modified spots per unit length than the first spot row L1, and the second spot column C2 may have a larger number of modified spots per unit length than the second spot row L2.

[0026] 15 is a perspective view showing an example of the configuration of a semiconductor substrate, in which the first spot row L1 may have a larger number of modified spots per unit length than the first spot column C1, and the second spot row L2 may have a larger number of modified spots per unit length than the second spot column C2.

[0027] 16 is a perspective view showing an example of the configuration of a semiconductor substrate. As shown in Fig. 16, the first modified layer F1 has a first spot row C1 made up of a plurality of modified spots S aligned in the second direction X2, and the first spot row C1 may be located below the gap GP between the first nitride semiconductor portion 8F and the second nitride semiconductor portion 8S.

[0028] 17 is a perspective view showing an example of the configuration of a semiconductor substrate. As shown in FIG. 17 , the semiconductor substrate 10 may have a first modified layer F1 located above the main substrate 1, a second modified layer F2 located below the main substrate 1, and a third modified layer F3 located below the main substrate 1 and above the second modified layer F2. The first modified layer F1 may have a first spot row C1 consisting of a plurality of modified spots S aligned in the second direction X2, and the first spot row C1 may be located below the gap GP between the first nitride semiconductor portion 8F and the second nitride semiconductor portion 8S. In the second modified layer F2, the plurality of modified spots S (modified spot group) aligned in a matrix may include a second spot row L2 consisting of a plurality of modified spots S aligned in the first direction X1 and a second spot row C2 consisting of a plurality of modified spots S aligned in the second direction X2. In the third modified layer F3, the plurality of modified spots S (modified spot group) arranged in a matrix may include a third spot row L3 consisting of a plurality of modified spots S arranged in the first direction X1, and a third spot column C3 consisting of a plurality of modified spots S arranged in the second direction X2. The second spot row L2 may have a larger number of modified spots per unit length than the second spot column C2, and the third spot column C3 may have a larger number of modified spots per unit length than the third spot row L3.

[0029] 18 is a perspective view showing an example of the configuration of a semiconductor substrate. As shown in FIG. 18, the semiconductor substrate 10 may have a first modified layer F1 located above the main substrate 1, a second modified layer F2 located below the main substrate 1, a third modified layer F3 located below the main substrate 1 and above the second modified layer F2, and a fourth modified layer F4 located above the main substrate 1 and below the first modified layer F1. In the first modified layer F1, the plurality of modified spots S (modified spot group) arranged in a matrix may include a spot row L1 consisting of the plurality of modified spots S arranged in the first direction X1 and a first spot column C1 consisting of the plurality of modified spots S arranged in the second direction X2. In the second modified layer F2, the plurality of modified spots S (modified spot group) arranged in a matrix may include a second spot row L2 consisting of the plurality of modified spots S arranged in the first direction X1 and a second spot column C2 consisting of the plurality of modified spots S arranged in the second direction X2. In the third modified layer F3, the plurality of modified spots S (modified spot group) arranged in a matrix may include a third spot row L3 consisting of a plurality of modified spots S arranged in the first direction X1 and a third spot column C3 consisting of a plurality of modified spots S arranged in the second direction X2. In the fourth modified layer F4, the plurality of modified spots S (modified spot group) arranged in a matrix may include a fourth spot row L4 consisting of a plurality of modified spots S arranged in the first direction X1 and a fourth spot column C4 consisting of a plurality of modified spots S arranged in the second direction X2. The first spot column C1 may have a larger number of modified spots per unit length than the first spot row L1, the second spot row L2 may have a larger number of modified spots per unit length than the second spot column C2, the third spot column C3 may have a larger number of modified spots per unit length than the third spot row L3, and the fourth spot row L4 may have a larger number of modified spots per unit length than the fourth spot column C4.

[0030] FIG. 19 is a flowchart showing a method for manufacturing a semiconductor substrate according to this embodiment. FIGS. 20 and 21 are perspective views showing a method for manufacturing a semiconductor substrate according to this embodiment. As shown in FIGS. 19 to 21, the method for manufacturing a semiconductor substrate according to this embodiment includes the steps of: preparing a base substrate BS having a main substrate 1 mainly composed of a material that is not a nitride semiconductor (S10); forming a first modified layer F1 including one or more modified spots S on the main substrate 1 (S20); forming a mask pattern 6 located on the base substrate BS and including a first opening K1, a mask portion 5, and a second opening K2 aligned in this order in a first direction X1 (S30); and forming a first nitride semiconductor portion 8F located on the first opening K1 and the mask portion 5, the first nitride semiconductor portion 8F having a longitudinal direction in a second direction X2 intersecting the first direction X1, and a second nitride semiconductor portion 8S located on the second opening K2 and the mask portion 5, the second direction X2 being a longitudinal direction and spaced apart from the first nitride semiconductor portion 8F in the first direction X1 (S40).

[0031] For example, by focusing a pulsed laser within the main substrate 1, a modified spot S including at least one of a void portion 12 and a crystalline altered portion 13 can be formed at the focused location. The mask pattern 6 may be formed after the first modified layer F1 is formed on the base substrate BS, or the first modified layer F1 may be formed after the mask pattern 6 is formed on the base substrate BS.

[0032] Forming the first modified layer F1 on the main substrate 1 makes it possible to adjust the thermal expansion characteristics of the main substrate 1. This makes it possible to reduce warpage (e.g., downward convex warpage in the X2 direction) of the semiconductor substrate 10 including the striped nitride semiconductor portion 8 whose longitudinal direction is the second direction X2.

[0033] As shown in Figure 20, it was found that when the first modification layer F1 is formed above the midpoint between the top and bottom surfaces of the main substrate 1, this has the effect of reducing the warping (downward convex shape) of the base substrate BS before the nitride semiconductor portion 8 is epitaxially grown, and further reducing the warping (downward convex shape) of the semiconductor substrate 10 after the nitride semiconductor portion 8 has been epitaxially grown.

[0034] As shown in Figure 21, it was found that when the first modification layer F1 is formed below the midpoint between the top and bottom surfaces of the main substrate 1, this has the effect of accelerating the warping (downward convex shape) of the base substrate BS before epitaxially growing the nitride semiconductor portion 8, while mitigating the warping (downward convex shape) of the semiconductor substrate 10 after epitaxially growing the nitride semiconductor portion 8.

[0035] FIG. 22 is a cross-sectional view showing the change in warpage when a modified layer is formed in the lower layer of the main substrate. As shown in FIG. 22, the primary effect of the first modified layer F1 is the effect of local expansion of the main substrate 1 observed at room temperature after void formation. In the case of FIG. 22 (when the first modified layer F1 is formed in the lower layer of the silicon substrate 1), the base substrate BS has a downward convex shape. Therefore, for example, by forming the first modified layer F1 in the lower layer of the main substrate 1 for a base substrate BS having an upward convex shape, the upward convex shape can be alleviated. The secondary effect of the first modified layer F1 is the effect of a change in the layer quality of the first modified layer F1 observed when the base substrate BS having the first modified layer F1 is placed at a high temperature (e.g., 800°C to 1200°C) and then placed at room temperature. In the case of FIG. 22 (when the seed portion 3 is a nitride semiconductor and the first modified layer is formed in the lower layer of the silicon substrate 1), the base substrate BS has an upward convex shape. This is thought to be because, at high temperatures, the expansion rate of the seed portion 3 (nitride semiconductor) is higher than that of the silicon substrate 1, resulting in an upward convex shape, and the portion where recrystallization is occurring due to changes in the layer quality of the first modified layer F1 becomes more susceptible to plastic deformation, and the upward convex shape is partially maintained during the temperature reduction process.

[0036] It is known that when amorphous or polycrystalline silicon is melted and then recrystallized, the solubility of impurities drops significantly, increasing the purity of the silicon. Meanwhile, it is also known that high-purity silicon substrates are prone to plastic deformation when cooled from high temperatures. Experiments were conducted to confirm the difference in plastic deformation between silicon substrates of different purities, and it was found that even in substrates without voids, high-purity silicon substrates undergo plastic deformation and tend to partially maintain their shape at high temperatures.

[0037] The base substrate BS that assumes an upwardly convex shape at high temperatures has the advantage that a semiconductor substrate 10 with less warpage can be obtained when the nitride semiconductor portion 8, which has a larger thermal expansion coefficient than the main substrate 1, is formed on the base substrate BS at high temperature (for example, by ELO film formation). The main substrate 1 is preferably a substrate with a smaller thermal expansion coefficient than nitride semiconductor materials such as a silicon substrate.

[0038] 23 is a schematic diagram showing an example of layer quality change of the modified layer. As shown in FIG. 23, when the spot S is cooled to room temperature after being exposed to a high temperature, recrystallization, dislocation movement, impurity precipitation, etc. occur in the crystalline modified portion 13a located on the laser irradiation side and containing crystal defects, crystal misorientation, etc., causing the shape of the void 12 to change and shrink. The amorphous and polycrystalline portions around the void 12 crystallize, and the crystal defects, crystal misorientation, etc. are also alleviated in the crystalline modified portion 13b located on the opposite side of the laser irradiation side. It is known that the primary effect of the modified layer decreases as the void shrinks at high temperatures.

[0039] Figure 24 is a cross-sectional view showing the change in warpage when a modified layer is formed in the middle layer of the main substrate. In the case of Figure 24 (when a first modified layer F1 is formed in the middle layer of the silicon substrate 1), the warpage of the base substrate BS hardly changes. When a base substrate BS having a first modified layer F1 is placed at a high temperature (e.g., 800°C to 1200°C) and then placed at room temperature (when the seed portion 3 is a nitride semiconductor and the first modified layer is formed in the middle layer of the silicon substrate), the base substrate BS takes on an upward convex shape. This is thought to be because, at high temperatures, the seed portion 3 (nitride semiconductor) has a higher expansion coefficient than the main substrate 1 (silicon substrate), resulting in an upward convex shape. During the cooling process, the portion where recrystallization has occurred due to the change in layer quality of the first modified layer F1 becomes more susceptible to plastic deformation, and the upward convex shape is partially maintained during the cooling process. The reason why the upward convex shape of the base substrate BS is larger in the case of Figure 24 (when the first modified layer F1 is formed in the middle layer of the main substrate) than in the case of Figure 22 (when the first modified layer F1 is formed in the lower layer of the main substrate) is that when it is in the middle layer of the substrate, laser light is irradiated over a wide film thickness range on both the laser incident side, focus, and light exit side, making it possible to change the film quality, etc., but in the case of the lower or upper layer of the main substrate, there is a limit to the film thickness range on either the incident side or the light exit side, and therefore film quality does not change sufficiently due to laser irradiation.

[0040] 24, the first modified layer F1 is formed at a position that divides the main substrate 1 into two equal parts in the thickness direction, but this is not limiting. One or more modified layers F may be formed in the middle layer of the upper, middle, and lower layers obtained by virtually dividing the main substrate 1 into three equal parts in the thickness direction.

[0041] Fig. 25 is a cross-sectional view when a nitride semiconductor portion is formed on the base substrate of Fig. 24. Fig. 26 is a perspective view when a nitride semiconductor portion is formed on the base substrate of Fig. 24. As shown in Figs. 24 to 26, the base substrate BS that assumes an upwardly convex shape at high temperatures has the advantage that a semiconductor substrate 10 with little warping can be obtained when a nitride semiconductor portion 8 (8F / 8S) having a larger thermal expansion coefficient than the main substrate 1 (e.g., a silicon substrate) is formed on the base substrate BS at high temperature (e.g., ELO film formation).

[0042] FIG. 27 is a cross-sectional view showing the change in warpage when multiple modified layers are formed over the entire main substrate. FIG. 28 is a perspective view showing the case where a nitride semiconductor portion is formed on the base substrate of FIG. 27. When multiple modified layers F are formed over the entire main substrate 1, the warpage of the base substrate BS hardly changes. When a base substrate BS (seed portion 3 is a nitride semiconductor) having multiple modified layers F is exposed to a high temperature (e.g., 800°C to 1200°C) and then cooled to room temperature, the base substrate BS assumes a downwardly convex shape. When modified layers containing multiple voids are formed over the entire main substrate, the base substrate BS tends to change to a downwardly convex shape after cooling. This is thought to be due to the presence of numerous voids in the substrate, which softens the substrate. While crystallized portions tend to maintain their upwardly convex shape due to plastic change, the presence of numerous voids increases the impact of softening the substrate, leading to a tendency for the base substrate to change to a downwardly convex shape.

[0043] 29 and 30 are cross-sectional views showing examples of the configuration of a semiconductor substrate. In Fig. 29 and Fig. 30, when the main substrate 1 (silicon substrate) is virtually divided into thirds in the thickness direction, the first modified layer F1 is located in the middle layer ML of the lower, middle, and upper layers, and the second modified layer F2 is located in the upper layer UL. In Fig. 29, the spot rows of the first modified layer F1 and the second modified layer F2 (including multiple modified spots aligned in the first direction X1) may have a larger number of modified spots per unit length than the spot columns (including multiple modified spots aligned in the second direction X2). In Fig. 30, the spot columns of the first modified layer F1 may have a larger number of modified spots per unit length than the spot rows, and the spot rows of the second modified layer F2 may have a larger number of modified spots per unit length than the spot columns.

[0044] 29 and 30, the expansion coefficient of the seed portion 3 (nitride semiconductor) is higher than that of the main substrate 1 (silicon substrate) at high temperatures, resulting in an upwardly convex shape. Furthermore, the change in the layer quality of the first modified layer F1 makes the recrystallized portion more susceptible to plastic deformation, and it is thought that the upwardly convex shape is partially maintained during the cooling process. By providing the second modified layer F2 in the upper layer (forming voids on the surface side), the base substrate BS becomes more upwardly convex at room temperature, and this effect is carried over even when the temperature is raised to a high temperature, further increasing the impact of maintaining the upwardly convex shape. Therefore, even when the temperature is lowered to room temperature, the base substrate BS tends to become upwardly convex compared to when the second modified layer F2 in the upper layer is not provided. Therefore, this is very useful when forming a semiconductor substrate that tends to become downwardly convex when the temperature is lowered (for example, when forming the first and second nitride semiconductor portions 8F and 8S using a silicon substrate as the main substrate 1).

[0045] 31 is a flowchart showing a method for manufacturing a semiconductor substrate according to this embodiment. FIG. 30 is a perspective view showing a method for manufacturing a semiconductor substrate according to this embodiment. As shown in FIGS. 31 and 32 , the method for manufacturing a semiconductor substrate according to this embodiment includes the steps of: preparing a base substrate BS having a main substrate 1 mainly composed of a material that is not a nitride semiconductor; forming a mask pattern 6 located on the base substrate BS and including first openings K1, mask portions 5, and second openings K2 aligned in this order in a first direction X1; forming first nitride semiconductor portions 8F located on the first openings K1 and the mask portion 5 and having a longitudinal direction in a second direction X intersecting the first direction X1; and forming second nitride semiconductor portions 8S located on the second openings K2 and the mask portion 5 and having a longitudinal direction in the second direction X2 and spaced apart from the first nitride semiconductor portion 8F in the first direction X1; and forming one or more modified spots S located in the main substrate 1 below gaps GP between the first nitride semiconductor portions 8F and the second nitride semiconductor portions 8S.

[0046] As shown in Figure 32, a first modified layer F1 including one or more modified spots S may be located on a main substrate 1, and a first nitride semiconductor portion 8F and a second nitride semiconductor portion 8S may be epitaxially grown on the base substrate BS, and then a second modified layer F2 including one or more modified spots S may be formed below the gap GP between the first nitride semiconductor portion 8F and the second nitride semiconductor portion 8S.

[0047] FIG. 33 is a perspective view showing an example of the configuration of this semiconductor substrate. As shown in FIG. 33 , the base substrate BS may include a main substrate 1 and a seed portion 3 located above the main substrate 1 and having a thermal expansion coefficient greater than that of the main substrate 1. The main substrate 1 may be a silicon substrate, and the seed portion 3 may include a nitride semiconductor (e.g., AlN). The buffer portion 2 and the seed portion 3 may form an underlayer. The first modified layer F1 is located above the middle between the top and bottom surfaces of the main substrate 1. In the first modified layer F1, the matrix-shaped modified spot group SG includes a first spot row L1 consisting of a plurality of modified spots S aligned in the first direction X1 and a first spot column C1 consisting of a plurality of modified spots aligned in the second direction X1. The first spot row L1 may have a greater number of modified spots per unit length than the first spot column C1. The spot pitch of the first spot row L1 may be 1 / 5 or less, 1 / 10 or less, 1 / 20 or less, or 1 / 50 or less of the spot pitch of the first spot column C1. The spot pitch is the center distance between adjacent modified spots.

[0048] FIG. 34 is a perspective view showing an example of the configuration of the semiconductor substrate. As shown in FIG. 34 , the base substrate BS may include a main substrate 1 and a seed portion 3 located above the main substrate 1 and having a smaller thermal expansion coefficient than the main substrate 1. The main substrate 1 may be a sapphire substrate, and the seed portion 3 may include a nitride semiconductor (e.g., AlN). The buffer portion 2 and the seed 3 may form an underlayer. The first modified layer F1 is located below the middle between the top and bottom surfaces of the main substrate 1. In the first modified layer F1, the matrix-arranged modified spot group SG includes a first spot row L1 consisting of a plurality of modified spots S arranged in the first direction X1 and a first spot column C1 consisting of a plurality of modified spots arranged in the second direction, and the first spot row L1 may have a larger number of modified spots per unit length than the first spot column C1.

[0049] 35 is a perspective view showing an example of the configuration of the semiconductor substrate. As shown in FIG. 35, the base substrate BS may have a main substrate 1 and a seed portion 3 located above the main substrate 1 and having a thermal expansion coefficient greater than that of the main substrate 1. The main substrate 1 may be a silicon substrate, and the seed portion 3 may include a nitride semiconductor (e.g., AlN). The buffer portion 2 and the seed 3 may form an underlayer. The first modified layer F1 may be located above the midpoint between the top and bottom surfaces of the main substrate 1, and the second modified layer F2 may be located below the midpoint between the top and bottom surfaces of the main substrate. In the first modified layer F1, the modified spot group SG arranged in a matrix may include a first spot row L1 consisting of a plurality of modified spots S arranged in a first direction X1, and a first spot column C1 consisting of a plurality of modified spots S arranged in a second direction X2, and in the second modified layer F2, the modified spot group SG arranged in a matrix may include a second spot row L2 consisting of a plurality of modified spots S arranged in the first direction X1, and a second spot column C2 consisting of a plurality of modified spots S arranged in the second direction X2.

[0050] 35, the first spot row L1 may have a larger number of modified spots per unit length than the first spot column C1, and the second spot column C2 may have a larger number of modified spots per unit length than the second spot row L2. The second spot row L2 may have a smaller number of modified spots per unit length than the first spot column C1. The spot pitch of the first spot row L1 may be 1 / 5 or less, 1 / 10 or less, 1 / 20 or less, or 1 / 50 or less of the spot pitch of the first spot column C1. The spot pitch of the second spot column C2 may be 1 / 5 or less, 1 / 10 or less, 1 / 20 or less, or 1 / 50 or less of the spot pitch of the second spot row L2. When forming the modified spot group SG after forming the nitride semiconductor portion (8F / 8S), for example, the spot pitch of the first spot row L1 and the second spot column C2 may be 3.8 μm, the spot pitch of the first spot column C1 may be 200 μm, and the spot pitch of the second spot row L2 may be 800 μm.

[0051] When the modified spot group SG is formed before the formation of the nitride semiconductor portions (8F and 8S), the spot pitch of the first spot column C1 and the second spot row L2 can be made smaller (the modified spots can be formed more densely) than when the modified spot group SG is formed after the above-mentioned formation. The laser light for forming the modified spots may be incident on the front side (the side on which the nitride semiconductor portions are formed) of each of the first modified layer F1 (front side) and the second modified layer F2 (rear side).

[0052] 36 is a perspective view showing an example of the configuration of the semiconductor substrate. As shown in FIG. 36, the base substrate BS may have a main substrate 1 and a seed portion 3 located above the main substrate 1 and having a smaller thermal expansion coefficient than the main substrate 1. The main substrate 1 may be a sapphire substrate, and the seed portion 3 may include a nitride semiconductor (e.g., AlN). The buffer portion 2 and the seed 3 may form an underlayer. The first modified layer F1 may be located above the midpoint between the top and bottom surfaces of the main substrate 1, and the second modified layer F2 may be located below the midpoint between the top and bottom surfaces of the main substrate. In the first modified layer F1, the modified spot group SG arranged in a matrix may include a first spot row L1 consisting of a plurality of modified spots S arranged in the first direction X1 and a first spot column C1 consisting of a plurality of modified spots S arranged in the second direction X2, and in the second modified layer F2, the modified spot group SG arranged in a matrix may include a second spot row L2 consisting of a plurality of modified spots S arranged in the first direction X1 and a second spot column C2 consisting of a plurality of modified spots S arranged in the second direction X2. The first spot column C1 may have a larger number of modified spots per unit length than the first spot row L1, and the second spot row L2 may have a larger number of modified spots per unit length than the second spot column C2.

[0053] Fig. 37 is a schematic diagram showing the state of warpage of a semiconductor substrate. When a silicon substrate is used for the main substrate 1, the upper modified layer (F1) shown in Fig. 33 reduces downward convex warpage (warpage in the second direction) having an axis in the first direction X1, and the upper modified layer (F1) and the lower modified layer (F2) shown in Fig. 35 reduce upward convex warpage (warpage in the first direction) having an axis in the second direction X2.

[0054] Fig. 38 is a schematic diagram showing the state of warpage of a semiconductor substrate. When a sapphire substrate is used for the main substrate 1, it can be seen that the lower modified layer (F1) shown in Fig. 34 reduces the upward convex warpage (warpage in the second direction) whose axis is the first direction X1, and the lower modified layer (F2) and the upper modified layer (F1) shown in Fig. 36 reduce the downward convex warpage (warpage in the first direction) whose axis is the second direction X2.

[0055] 39 is a block diagram showing a semiconductor substrate manufacturing apparatus according to this embodiment. The semiconductor substrate manufacturing apparatus 50 includes an apparatus M10 that performs step S10 of FIG. 19, an apparatus M20 that performs step S20 of FIG. 19, an apparatus M30 that performs step S30 of FIG. 19, an apparatus M40 that performs step S40 of FIG. 19, and a control device MC that controls the apparatuses M10 to M40. The apparatus M40 may be an MOCVD apparatus. The apparatus M10 may perform step S60 of FIG. 31, the apparatus M20 may perform step S90 of FIG. 31, the apparatus M30 may perform step S70 of FIG. 31, and the apparatus M20 may perform step S90 of FIG. 31.

[0056] [Example 1] (Base Substrate) Fig. 40 is a cross-sectional view showing an example of the configuration of a base substrate. The base substrate BS may have a main substrate 1 which is a heterogeneous substrate having a lattice constant different from that of the nitride semiconductor portion 8. The nitride semiconductor portion 8 may include a GaN-based semiconductor, and the heterogeneous substrate, the main substrate 1, may be a silicon substrate. As the heterogeneous substrate, in addition to a silicon substrate, sapphire (Al ２ O ３ ) substrate, silicon carbide (SiC) substrate, etc. The surface orientation of the main substrate 1 is, for example, the (111) surface of a silicon substrate, the (0001) surface of a sapphire substrate, or the 6H—SiC (0001) surface of a SiC substrate. These are merely examples, and any substrate and surface orientation may be used as long as it allows the nitride semiconductor portion 8 to be grown by the ELO method.

[0057] The base substrate BS may include a main substrate 1, a buffer portion 2 on the main substrate 1, and a seed portion 3 on the buffer portion 2. The main substrate 1 may be, for example, a Si substrate, the buffer portion 2 may be, for example, AlN or SiC, and the seed portion 3 may be a GaN-based semiconductor. The buffer portion 2 and the seed portion 3 do not have to be formed over the entire surface of the main substrate 1, and may be provided locally so as to overlap with the opening K in plan view (so that the base portion 4 is exposed from the opening K).

[0058] The base substrate BS may include a main substrate 1 and a seed portion 3 on the main substrate 1. A Si substrate, for example, may be used for the main substrate 1, and AlN or SiC, for example, may be used for the seed portion 3. The seed portion 3 does not have to be formed over the entire surface of the main substrate 1, and may be provided locally so as to overlap with the opening K in plan view (so that the base portion 4 is exposed from the opening K).

[0059] (Mask Pattern) The mask pattern 6 includes a mask portion 5 and an opening K. The opening K functions as a growth initiation hole that exposes the seed portion 3 and initiates growth of the nitride semiconductor portion 8, and the mask portion 5 may function as a selective growth mask (deposition suppression mask) for lateral growth of the nitride semiconductor portion 8. The mask portion 5 may be, for example, a single-layer film including one of a silicon oxide film (SiOx), a titanium nitride film (TiN, etc.), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), and a metal film having a high melting point (e.g., 1000°C or higher), or a stacked film including at least two of these. A thermal oxide film obtained by subjecting a silicon substrate, a silicon nitride substrate, or the like to thermal oxidation treatment may also be used as the mask portion 5.

[0060] A laminated film in which a silicon oxide film and a silicon nitride film are formed in this order can be used as the mask portion 5. Depending on the film formation conditions, the nitride semiconductor portion 8 and the mask portion 5 may react and adhere to each other, so the upper film in contact with the nitride semiconductor portion 8 may be a silicon nitride film. Furthermore, in the process of locally forming the seed portion 3, a film (lower film) on the support substrate 1 may be removed, and using a silicon oxide film, which can easily be completely removed from the support substrate 1, as the lower film also has the effect of improving the process yield.

[0061] (Deposition of nitride semiconductor portion) Fig. 41 is a cross-sectional view showing a method for forming a nitride semiconductor portion according to Example 1. In Example 1, the nitride semiconductor portion 8 is a GaN layer, and ELO deposition is performed on the template substrate TS using the apparatus M40 (e.g., MOCVD apparatus) of Fig. 39. Examples of ELO deposition conditions include substrate temperature: 1120°C, growth pressure: 50 kPa, TMG (trimethylgallium): 22 sccm, NH ３ : 15 slm, V / III=6000 (ratio of the supply amount of group V source material to the supply amount of group III source material) can be adopted.

[0062] The initial growth portion 8p serves as the starting point for lateral growth of the nitride semiconductor portion 8. The initial growth layer 8p can be formed to a thickness of, for example, 30 nm to 1000 nm, 50 nm to 400 nm, or 70 nm to 350 nm. By causing the initial growth portion 8p to grow laterally from a state in which it slightly protrudes from the mask portion 5, growth of the nitride semiconductor portion 8 in the c-axis direction (thickness direction) is suppressed, allowing the nitride semiconductor portion 8 to grow laterally at high speed with high crystallinity, and reducing raw material consumption. This allows a thin, wide, and low-defect nitride semiconductor portion 8 (crystal of a nitride semiconductor such as GaN) to be formed at low cost.

[0063] The nitride semiconductor portions 8 that have grown laterally in opposite directions from two adjacent openings K do not come into contact (meet) with each other on the mask portion 5, and a gap (gap) GP is formed, thereby reducing the internal stress of the nitride semiconductor portion 8. This reduces cracks and defects (dislocations) that occur in the nitride semiconductor portion 8. This effect is particularly effective when the main substrate 1 is a heterogeneous substrate. The width of the gap GP can be, for example, 10 μm or less, 5 μm or less, 3 μm or less, 2 μm or less, or 0.5 μm or less.

[0064] Of the nitride semiconductor portion 8, the portion located above the initial growth portion 8p becomes a dislocation inheritance portion having many threading dislocations, and the portion above the mask portion 5 (wing portion W1) becomes a low defect portion YS having a threading dislocation density of 1 / 10 or less compared to the dislocation inheritance portion. Threading dislocations are dislocations (defects) that extend in the c-axis direction (<0001> direction) in the nitride semiconductor portion 8. The threading dislocation density of the low defect portion YS is, for example, 5×10 ６ [pcs / cm ２ As will be described later, when an active section (active layer) including a light emitting section is formed above the nitride semiconductor section 8, the light emitting section can be disposed above the low defect section YS (so as to overlap the low defect section YS in plan view).

[0065] For the low-defect portion YS, the ratio (WW / d1) of the size WW in the a-axis direction to the thickness d1 can be set to, for example, 2.0 or more. By using the technique of Example 1, WW / d1 can be set to 1.5 or more, 2.0 or more, 4.0 or more, 5.0 or more, 7.0 or more, or 10.0 or more. By setting WF / d1 to 1.5 or more, the internal stress of the nitride semiconductor portion 8 is reduced, and warpage of the semiconductor substrate 10 is reduced.

[0066] The aspect ratio of the nitride semiconductor portion 8 (ratio of size in the X direction to thickness = WL / d1) can be 3.5 or more, 5.0 or more, 6.0 or more, 8.0 or more, 10 or more, 15 or more, 20 or more, 30 or more, or 50 or more. Furthermore, by using the technique of Example 1, the ratio of the size WL of the nitride semiconductor portion 8 in the X direction to the width WK of the opening K (WL / WK) can be 3.5 or more, 5.0 or more, 6.0 or more, 8.0 or more, 10 or more, 15 or more, 20 or more, 30 or more, or 50 or more, thereby increasing the proportion of low-defect portions. The nitride semiconductor portion 8 (including the initial growth portion 8p) shown in FIG. 35 can be a nitride semiconductor crystal (e.g., a GaN crystal, an AlGaN crystal, an InGaN crystal, or an InAlGaN crystal).

[0067] Example 2 Figure 42 is a cross-sectional view showing a semiconductor device manufacturing method according to Example 2. In Figure 42, the process includes the steps of preparing a semiconductor substrate 10 including a template substrate TS, forming a compound semiconductor portion 9 and electrodes E1 and E2 on the semiconductor substrate 10, bonding a light emitter T1 including a nitride semiconductor portion 8, the compound semiconductor portion 9, and the electrodes E1 and E2 to a support substrate SK via bonding layers H1 and H2, peeling off the base substrate BS, and singulating the support substrate SK into multiple supports ST to form semiconductor devices SD on the supports ST, each with the light emitter T1 supported thereon. Before peeling off the base substrate BS, the mask portion 5 may be removed by wet etching or the like. The support substrate SK may be a submount substrate including a silicon substrate.

[0068] The nitride semiconductor portion 8 may be an n-type semiconductor crystal. The compound semiconductor portion 9 may include a GaN-based semiconductor. The compound semiconductor portion 9 may include an active portion (e.g., an active layer such as a quantum well structure) and a p-type semiconductor portion, or may include an n-type semiconductor portion (e.g., a regrowth layer, an n-type contact layer) below the active portion. When the active portion of the compound semiconductor portion 9 includes a light-emitting portion, the light-emitting portion can be disposed above the low-defect portion YS (wing portion W1) so as to overlap the low-defect portion YS in a planar view. This can improve the light-emitting efficiency.

[0069] The electrode E1 located above the low-defect portion YS may be an anode, and the electrode E2 may be a cathode. The support substrate SK may have a conductive pad in contact with the bonding layer H1 and a conductive pad in contact with the bonding layer H2. The bonding layers H1 and H2 may be formed of a solder material. The elongated light emitter T1 may be divided into multiple pieces (by cutting in the short direction) before, during, or after bonding to the support substrate SK. In this case, the dividing step may be performed by cleaving the nitride semiconductor portion 8 and the compound semiconductor portion 9 (for example, m-plane cleavage in which the cleavage plane is the m-plane). When forming a semiconductor laser element, the m-plane, which is the cleavage plane, may be facet-coated (with a reflector film formed).

[0070] The semiconductor element SD may function as an LED (light emitting diode) element or a semiconductor laser element. The support ST may be a submount substrate. Example 2 includes electronic devices (e.g., lighting devices, laser devices, display devices, measuring devices, information processing devices, etc.) that have the semiconductor element SD.

[0071] (Note) The above disclosure is intended to be illustrative and explanatory, and is not intended to be limiting. Based on these examples and explanations, many variations will be obvious to those skilled in the art, and it should be noted that these variations are also included in the embodiments.

[0072] REFERENCE SIGNS LIST 1 Main substrate 2 Base portion 3 Buffer portion 5 Mask portion 6 Mask pattern 10 Semiconductor substrate 50 Semiconductor substrate manufacturing apparatus S Modified spot GP Gap K1 First opening K2 Second opening F1 First modified layer F2 Second modified layer L1 First modified spot row L2 Second modified spot row C1 First modified spot row C2 Second modified spot row 8F First nitride semiconductor portion 8S Second nitride semiconductor portion BS Base substrate

Claims

1. a base substrate including a main substrate mainly composed of a material other than a nitride semiconductor, the main substrate having a first modified layer including one or more modified spots located thereon; a first nitride semiconductor portion located on the base substrate and having a longitudinal direction along the second direction, the first direction and the second direction intersecting each other; a second nitride semiconductor portion located on the base substrate, with the second direction as a longitudinal direction, and spaced apart from the first nitride semiconductor portion in the first direction;

2. a mask pattern located on the base substrate, the mask pattern including a first opening, a mask portion, and a second opening arranged in this order in the first direction; the first nitride semiconductor portion is located above the first opening and the mask portion, The semiconductor substrate according to claim 1 , wherein the second nitride semiconductor portion is located above the second opening and the mask portion.

3. The semiconductor substrate of claim 1 , wherein the one or more modified spots are at least one of voids and crystalline modifications.

4. the base substrate has a seed portion located between the main substrate and the mask pattern; The semiconductor substrate according to claim 2 , wherein the seed portion is exposed in the first opening and the second opening.

5. 5. The semiconductor substrate according to claim 1, wherein the first modified layer is located above the middle between the top and bottom surfaces of the main substrate.

6. The semiconductor substrate of claim 2 , wherein the first modified layer includes a modified spot located below the first opening.

7. The semiconductor substrate of claim 6 , wherein the first modified layer includes a first spot row consisting of a plurality of modified spots aligned in the second direction, and the first spot row is located below the first opening.

8. A semiconductor substrate as described in claim 5, wherein in the first modified layer, the group of modified spots arranged in a matrix includes a first spot row consisting of a plurality of modified spots arranged in the first direction, and a first spot column consisting of a plurality of modified spots arranged in the second direction.

9. The semiconductor substrate of claim 8 , wherein the first spot column has a greater number of modified spots per unit length than the first spot row.

10. The semiconductor substrate of claim 8 , wherein the first spot row has a greater number of modified spots per unit length than the first spot column.

11. the first nitride semiconductor portion includes a wing portion located on the mask portion, The semiconductor substrate of claim 2, wherein the value obtained by dividing the number of modified spots located under the wing portion by the area of ​​the wing portion is smaller than the value obtained by dividing the number of modified spots located under the first opening by the area of ​​the first opening.

12. the first nitride semiconductor portion includes a wing portion located on the mask portion, The semiconductor substrate of claim 2, wherein the value obtained by dividing the number of modified spots located under the wing portion by the area of ​​the wing portion is greater than the value obtained by dividing the number of modified spots located under the gap between the first nitride semiconductor portion and the second nitride semiconductor portion by the area of ​​the gap.

13. the first nitride semiconductor portion includes a wing portion located on the mask portion, The semiconductor substrate according to claim 2 , wherein an average diameter of the plurality of modified spots located under the wing portion is smaller than an average diameter of the plurality of modified spots located under the first opening.

14. The semiconductor substrate according to claim 3 , wherein the void has a crescent shape that is convex upward or convex downward.

15. 5. The semiconductor substrate according to claim 1, wherein the first modified layer is located below the midpoint between the top and bottom surfaces of the main substrate.

16. the main substrate is a silicon substrate or a silicon carbide substrate; 5. The semiconductor substrate according to claim 1, wherein the first nitride semiconductor portion and the second nitride semiconductor portion include a GaN-based semiconductor.

17. The semiconductor substrate of claim 5 , further comprising a second modified layer located below the middle of the upper and lower surfaces of the main substrate and including one or more modified spots.

18. In the first modified layer, the group of modified spots arranged in a matrix includes a first spot row consisting of a plurality of modified spots arranged in the first direction, and a first spot column consisting of a plurality of modified spots arranged in the second direction, A semiconductor substrate as described in claim 17, wherein in the second modified layer, the group of modified spots arranged in a matrix includes a second spot row consisting of a plurality of modified spots arranged in the first direction, and a second spot column consisting of a plurality of modified spots arranged in the second direction.

19. 19. The semiconductor substrate of claim 18, wherein the first spot column has a greater number of modified spots per unit length than the first spot row, and the second spot column has a greater number of modified spots per unit length than the second spot row.

20. 19. The semiconductor substrate of claim 18, wherein the first spot row has a greater number of modified spots per unit length than the first spot column, and the second spot row has a greater number of modified spots per unit length than the second spot column.

21. The semiconductor substrate of claim 17, wherein the second modified layer includes a second spot row consisting of a plurality of modified spots aligned in the second direction, and the second spot row is located below the gap between the first nitride semiconductor portion and the second nitride semiconductor portion.

22. a third modified layer located below the middle between the upper and lower surfaces of the main substrate; A semiconductor substrate as described in claim 18, wherein in the third modified layer, the group of modified spots arranged in a matrix includes a third spot row consisting of a plurality of modified spots arranged in the first direction, and a third spot column consisting of a plurality of modified spots arranged in the second direction.

23. 23. The semiconductor substrate of claim 22, wherein the first spot column has a greater number of modified spots per unit length than the first spot row, the second spot row has a greater number of modified spots per unit length than the second spot column, and the third spot column has a greater number of modified spots per unit length than the third spot row.

24. a third modified layer located below the midpoint between the upper and lower surfaces of the main substrate; and a fourth modified layer located above the midpoint between the upper and lower surfaces of the main substrate, In the third modified layer, the group of modified spots arranged in a matrix includes a third spot row consisting of a plurality of modified spots arranged in the first direction, and a third spot column consisting of a plurality of modified spots arranged in the second direction, A semiconductor substrate as described in claim 18, wherein in the fourth modified layer, the group of modified spots arranged in a matrix includes a fourth spot row consisting of a plurality of modified spots arranged in the first direction and a fourth spot column consisting of a plurality of modified spots arranged in the second direction.

25. 25. The semiconductor substrate of claim 24, wherein the first spot column has a greater number of modified spots per unit length than the first spot row, the second spot column has a greater number of modified spots per unit length than the second spot column, the third spot column has a greater number of modified spots per unit length than the third spot row, and the fourth spot row has a greater number of modified spots per unit length than the fourth spot column.

26. The semiconductor substrate according to any one of claims 1 to 4, wherein the first modified layer is located in the middle layer of the lower layer, middle layer, and upper layer when the main substrate is virtually divided into three equal parts in the thickness direction.

27. 27. The semiconductor substrate of claim 26, further comprising a second modified layer located within the upper layer and including a plurality of modified spots.

28. The semiconductor substrate according to claim 10 , wherein the base substrate comprises a main substrate and a seed portion located above the main substrate and having a thermal expansion coefficient greater than that of the main substrate.

29. In the first modified layer, the group of modified spots arranged in a matrix includes a first spot row consisting of a plurality of modified spots arranged in the first direction, and a first spot column consisting of a plurality of modified spots arranged in the second direction, The semiconductor substrate of claim 15 , wherein the first row of spots has a greater number of modified spots per unit length than the first column of spots.

30. 30. The semiconductor substrate of claim 29, wherein the base substrate comprises a main substrate and a seed portion located above the main substrate and having a thermal expansion coefficient smaller than that of the main substrate.

31. The semiconductor substrate according to claim 18 , wherein the base substrate comprises a main substrate and a seed portion located above the main substrate and having a thermal expansion coefficient greater than that of the main substrate.

32. the first spot row has a greater number of modified spots per unit length than the first spot column; 32. The semiconductor substrate of claim 31, wherein the second column of spots has a greater number of modified spots per unit length than the second row of spots.

33. 33. The semiconductor substrate of claim 32, wherein the second row of spots has fewer modified spots per unit length than the first column of spots.

34. 32. The semiconductor substrate of claim 31, wherein the primary substrate is a silicon substrate and the seed portion comprises a nitride semiconductor.

35. The semiconductor substrate according to claim 18 , wherein the base substrate comprises a main substrate and a seed portion located above the main substrate and having a thermal expansion coefficient smaller than that of the main substrate.

36. the first spot column has a greater number of modified spots per unit length than the first spot row; 36. The semiconductor substrate of claim 35, wherein the second row of spots has a greater number of modified spots per unit length than the second column of spots.

37. 37. The semiconductor substrate of claim 36, wherein the first row of spots has fewer modified spots per unit length than the second column of spots.

38. 36. The semiconductor substrate of claim 35, wherein the primary substrate is a sapphire substrate and the seed portion comprises a nitride semiconductor.

39. providing a base substrate having a main substrate primarily composed of a material that is not a nitride semiconductor; forming a first modified layer on the primary substrate, the first modified layer including one or more modified spots; forming a mask pattern located on the base substrate, the mask pattern including a first opening, a mask portion, and a second opening arranged in this order in a first direction; forming a first nitride semiconductor section located on the first opening and on the mask section, the first nitride semiconductor section having a longitudinal direction that is a second direction intersecting the first direction, and a second nitride semiconductor section located on the second opening and on the mask section, the second direction being a longitudinal direction and spaced apart from the first nitride semiconductor section in the first direction.

40. providing a base substrate having a main substrate primarily composed of a material that is not a nitride semiconductor; forming a mask pattern located on the base substrate, the mask pattern including a first opening, a mask portion, and a second opening arranged in this order in a first direction; forming a first nitride semiconductor section located on the first opening and on the mask portion, the first nitride semiconductor section having a longitudinal direction that is a second direction intersecting the first direction, and a second nitride semiconductor section located on the second opening and on the mask portion, the second direction being a longitudinal direction, and spaced apart from the first nitride semiconductor section in the first direction; forming one or more modified spots in the main substrate located below the gap between the first nitride semiconductor portion and the second nitride semiconductor portion.

41. 41. The method for manufacturing a semiconductor substrate of claim 40, further comprising providing a base substrate, the base substrate having a first modified layer including one or more modified spots located on the main substrate.

42. 41. The method for manufacturing a semiconductor substrate according to claim 39 or 40, wherein the one or more modified spots are formed by focusing a laser inside the main substrate.

43. A semiconductor substrate manufacturing apparatus that performs each step according to claim 39 or 40.