Interposer

Abstract

Provided is an interposer which can be made compact while comprising a plurality of capacitors having different capacitances. In this interposer (100), a first capacitor (1) and a second capacitor (2) are embedded in a dielectric substrate (4). The first capacitor (1) and the second capacitor (2) have mutually different capacitances. The first capacitor (1) has a first electrode (11), a second electrode (12), and a first dielectric part (13). The second capacitor (2) has a third electrode (21), a fourth electrode (22), and a second dielectric part (23). The thickness (T2) of the second dielectric part (23) of the second capacitor (2) is less than the thickness (T1) of the first dielectric part (13) of the first capacitor (1), and the capacitance of the second capacitor (2) is greater than the capacitance of the first capacitor (1).

Description

Interposer

[0001] The present disclosure relates to interposers, and more particularly to interposers incorporating capacitors.

[0002] A package substrate having an embedded thin-film capacitor has been known as an interposer (see Patent Document 1). Patent Document 1 illustrates a package assembly including a package substrate, a die bonded to the package substrate by flip-chip bonding or the like, and a printed circuit board bonded to the package substrate via solder balls.

[0003] In addition to being provided with a plurality of capacitors with different capacitances, an interposer may also be required to be miniaturized.

[0004] Japanese Patent Application Laid-Open No. 2017-130653

[0005] An object of the present disclosure is to provide an interposer that can be miniaturized while being provided with a plurality of capacitors with different capacitances.

[0006] An interposer according to one aspect of the present disclosure includes a dielectric substrate, a wiring portion, a first capacitor, and a second capacitor. The dielectric substrate has a first main surface and a second main surface opposite the first main surface. The wiring portion penetrates the dielectric substrate. The first capacitor and the second capacitor are embedded in the dielectric substrate. The first capacitor and the second capacitor have different capacitances. The first capacitor has a first electrode, a second electrode, and a first dielectric portion. The first electrode and the second electrode face each other in the thickness direction of the dielectric substrate. The first dielectric portion is interposed between the first electrode and the second electrode. The second capacitor has a third electrode, a fourth electrode, and a second dielectric portion. The third electrode and the fourth electrode face each other in the thickness direction of the dielectric substrate. The second dielectric portion is interposed between the third electrode and the fourth electrode. The second dielectric portion has a thickness smaller than that of the first dielectric portion, and the second capacitor has a capacitance larger than that of the first capacitor.

[0007] FIG. 1 is a cross-sectional view of an interposer according to a first embodiment. FIGS. 2A to 2D are cross-sectional views illustrating steps in a method for manufacturing the interposer according to the first embodiment. FIGS. 3A to 3C are cross-sectional views illustrating steps in a method for manufacturing the interposer according to the first embodiment. FIG. 4 is a cross-sectional view of an interposer according to a second embodiment. FIGS. 5A to 5D are cross-sectional views illustrating steps in a method for manufacturing the interposer according to the first embodiment. FIGS. 6A to 6C are cross-sectional views illustrating steps in a method for manufacturing the interposer according to the first embodiment. FIGS. 7A and 7B are cross-sectional views illustrating steps in a method for manufacturing the interposer according to the second embodiment. FIG. 8A is a plan view of a main part illustrating a method for manufacturing an interposer according to a modified example of the second embodiment. FIG. 8B is a cross-sectional view taken along line X1-X1 of FIG. 8A. FIG. 9 is a cross-sectional view of a main part illustrating a comparative example of the method for manufacturing the interposer according to the second embodiment.

[0008] The drawings described in the following embodiments are schematic diagrams, and the ratios of the sizes and thicknesses of the components in the drawings do not necessarily reflect the actual dimensional ratios.

[0009] First Embodiment An interposer 100 according to a first embodiment will be described below with reference to FIG.

[0010] (1) Overview The interposer 100 according to the first embodiment is disposed between, for example, multiple semiconductor chips and a package substrate of a SiP (System in Package). The multiple semiconductor chips include, for example, a processor, a logic IC (Integrated Circuit), a memory (for example, a High Bandwidth Memory (HBM)), etc.

[0011] The interposer 100 according to the first embodiment includes a dielectric substrate 4, a plurality of wiring portions 5, a first capacitor 1, a second capacitor 2, and a third capacitor 3. The plurality of wiring portions 5 penetrate the dielectric substrate 4. Note that two of the plurality of wiring portions 5 are visible in FIG.

[0012] The first capacitor 1, the second capacitor 2, and the third capacitor 3 are embedded in a dielectric substrate 4. The first capacitor 1, the second capacitor 2, and the third capacitor 3 have different capacitances.

[0013] (2) Details The dielectric substrate 4 has a first main surface 401 and a second main surface 402 opposite to the first main surface 401. When viewed in a plan view from the thickness direction D1 of the dielectric substrate 4, the outer edge shape of the dielectric substrate 4 is rectangular, but is not limited to this.

[0014] The dielectric substrate 4 has a first dielectric layer 41 and a second dielectric layer 42. The second dielectric layer 42 is laminated on the first dielectric layer 41. A first main surface 401 of the dielectric substrate 4 is formed by a main surface 411 of the first dielectric layer 41 opposite to the second dielectric layer 42 side. A second main surface 402 of the dielectric substrate 4 is formed by a main surface 421 of the second dielectric layer 42 opposite to the first dielectric layer 41 side.

[0015] The material of the first dielectric layer 41 includes an organic material (for example, a polyimide resin, a bismaleimide resin, or a fluorine-based resin).

[0016] The material of the second dielectric layer 42 includes an organic material (e.g., polyimide resin, bismaleimide resin, or fluorine-based resin). The material of the second dielectric layer 42 is the same as the material of the first dielectric layer 41, but may be different.

[0017] The first capacitor 1 has a first electrode 11, a second electrode 12, and a first dielectric portion 13. The first electrode 11 and the second electrode 12 face each other in the thickness direction D1 of the dielectric substrate 4. The first dielectric portion 13 is interposed between the first electrode 11 and the second electrode 12. When viewed from above in the thickness direction D1 of the dielectric substrate 4, the outer edge shape of each of the first electrode 11 and the second electrode 12 is rectangular, but is not limited to this.

[0018] In the first capacitor 1, the first electrode 11 is embedded in the first dielectric layer 41. The first electrode 11 is exposed from the first main surface 401 of the dielectric substrate 4. The first electrode 11 penetrates the first dielectric layer 41. In the interposer 100, the thickness of the first electrode 11 is approximately the same as the thickness of the first dielectric layer 41, and the lower surface of the first electrode 11 and the first main surface 401 of the dielectric substrate 4 are approximately flush with each other.

[0019] In the first capacitor 1, the second electrode 12 is embedded in the second dielectric layer 42. The second electrode 12 is exposed from the second main surface 402 of the dielectric substrate 4. The second electrode 12 does not penetrate the second dielectric layer 42. The second electrode 12 is exposed from the second main surface 402 of the dielectric substrate 4 to a thickness thinner than the thickness of the second dielectric layer 42. In the interposer 100, the thickness of the second electrode 12 is thinner than the thickness of the second dielectric layer 42, and the upper surface of the second electrode 12 and the second main surface 402 of the dielectric substrate 4 are approximately flush with each other.

[0020] The material of the first electrode 11 and the second electrode 12 includes, for example, copper. The material of the first electrode 11 and the second electrode 12 is not limited to copper, and may be, for example, a copper alloy, aluminum, or titanium. The material of the second electrode 12 is the same as the material of the first electrode 11, but may be different.

[0021] In the interposer 100, the material of the first dielectric portion 13 is the same as the material of the second dielectric layer 42, and includes an organic material. The thickness T1 of the first dielectric portion 13 is thinner than the thickness of the second dielectric layer 42. The first dielectric portion 13 overlaps the second dielectric layer 42 in a direction perpendicular to the thickness direction D1 of the dielectric substrate 4. The first dielectric portion 13 is formed integrally with the second dielectric layer 42.

[0022] The second capacitor 2 has a third electrode 21, a fourth electrode 22, and a second dielectric portion 23. The third electrode 21 and the fourth electrode 22 face each other in the thickness direction D1 of the dielectric substrate 4. The second dielectric portion 23 is interposed between the third electrode 21 and the fourth electrode 22. When viewed from above in the thickness direction D1 of the dielectric substrate 4, the outer edge shape of each of the third electrode 21 and the fourth electrode 22 is rectangular, but is not limited to this.

[0023] In the second capacitor 2, the third electrode 21 is embedded in the first dielectric layer 41. The third electrode 21 is exposed from the first main surface 401 of the dielectric substrate 4. The third electrode 21 penetrates the first dielectric layer 41. In the interposer 100, the thickness of the third electrode 21 is approximately the same as the thickness of the first dielectric layer 41, and the lower surface of the third electrode 21 and the first main surface 401 of the dielectric substrate 4 are approximately flush with each other.

[0024] In the second capacitor 2, the fourth electrode 22 is embedded in the second dielectric layer 42. The fourth electrode 22 is exposed from the second main surface 402 of the dielectric substrate 4. The fourth electrode 22 does not penetrate the second dielectric layer 42. The fourth electrode 22 is thinner than the thickness of the second dielectric layer 42 and is exposed from the second main surface 402 of the dielectric substrate 4. In the interposer 100, the thickness of the fourth electrode 22 is thinner than the thickness of the second dielectric layer 42, and the upper surface of the fourth electrode 22 and the second main surface 402 of the dielectric substrate 4 are approximately flush with each other.

[0025] The material of the third electrode 21 and the fourth electrode 22 includes, for example, copper. The material of the third electrode 21 and the fourth electrode 22 is not limited to copper, and may be, for example, a copper alloy, aluminum, or titanium. The material of the fourth electrode 22 is the same as the material of the third electrode 21, but may be different. However, the material of the third electrode 21 is the same as the material of the first electrode 11. Furthermore, the material of the fourth electrode 22 is the same as the material of the second electrode 12.

[0026] In the interposer 100, the material of the second dielectric portion 23 is the same as the material of the second dielectric layer 42, and includes an organic material. The thickness T2 of the second dielectric portion 23 is thinner than the thickness of the second dielectric layer 42. The second dielectric portion 23 overlaps the second dielectric layer 42 in a direction perpendicular to the thickness direction D1 of the dielectric substrate 4. The second dielectric portion 23 is formed integrally with the second dielectric layer 42.

[0027] The third capacitor 3 has a fifth electrode 31, a sixth electrode 32, and a third dielectric portion 33. The fifth electrode 31 and the sixth electrode 32 face each other in the thickness direction D1 of the dielectric substrate 4. The third dielectric portion 33 is interposed between the fifth electrode 31 and the sixth electrode 32. When viewed from above in the thickness direction D1 of the dielectric substrate 4, the outer edge shape of each of the fifth electrode 31 and the sixth electrode 32 is rectangular, but is not limited to this.

[0028] In the third capacitor 3, the fifth electrode 31 is embedded in the first dielectric layer 41. The fifth electrode 31 is exposed from the first main surface 401 of the dielectric substrate 4. The fifth electrode 31 penetrates the first dielectric layer 41. In the interposer 100, the thickness of the fifth electrode 31 is approximately the same as the thickness of the first dielectric layer 41, and the lower surface of the fifth electrode 31 and the first main surface 401 of the dielectric substrate 4 are approximately flush with each other.

[0029] In the third capacitor 3, the sixth electrode 32 is embedded in the second dielectric layer 42. The sixth electrode 32 is exposed from the second main surface 402 of the dielectric substrate 4. The sixth electrode 32 does not penetrate the second dielectric layer 42. The sixth electrode 32 is thinner than the thickness of the second dielectric layer 42 and is exposed from the second main surface 402 of the dielectric substrate 4. In the interposer 100, the thickness of the sixth electrode 32 is thinner than the thickness of the second dielectric layer 42, and the upper surface of the sixth electrode 32 and the second main surface 402 of the dielectric substrate 4 are approximately flush with each other.

[0030] The material of the fifth electrode 31 and the sixth electrode 32 includes, for example, copper. The material of the fifth electrode 31 and the sixth electrode 32 is not limited to copper, and may be, for example, a copper alloy, aluminum, or titanium. The material of the sixth electrode 32 is the same as the material of the fifth electrode 31, but may be different. However, the material of the fifth electrode 31 is the same as the material of the first electrode 11. Furthermore, the material of the sixth electrode 32 is the same as the material of the second electrode 12.

[0031] In the interposer 100, the material of the third dielectric portion 33 is the same as the material of the second dielectric layer 42, and includes an organic material. The thickness T3 of the third dielectric portion 33 is thinner than the thickness of the second dielectric layer 42. The third dielectric portion 33 overlaps the second dielectric layer 42 in a direction perpendicular to the thickness direction D1 of the dielectric substrate 4. The third dielectric portion 33 is formed integrally with the second dielectric layer 42.

[0032] Each of the multiple wiring sections 5 includes a first conductor section 51, a second conductor section 52, and a via conductor section 53. Each first conductor section 51 is embedded in the first dielectric layer 41. Each first conductor section 51 penetrates the first dielectric layer 41. In the interposer 100, the thickness of each first conductor section 51 is approximately the same as the thickness of the first dielectric layer 41, and the lower surface of each first conductor section 51 is approximately flush with the first main surface 401 of the dielectric substrate 4. The second conductor section 52 is embedded in the second dielectric layer 42. The second conductor section 52 is thinner than the thickness of the second dielectric layer 42 and is exposed from the second main surface 402 of the dielectric substrate 4. In the interposer 100, the thickness of each second conductor section 52 is thinner than the thickness of the second dielectric layer 42, and the upper surface of each second conductor section 52 is approximately flush with the second main surface 402 of the dielectric substrate 4. The via conductor portion 53 is embedded in the second dielectric layer 42 and connects the first conductor portion 51 and the second conductor portion 52. In a plan view from the thickness direction D1 of the dielectric substrate 4, the via conductor portion 53 is smaller than the first conductor portion 51 and smaller than the second conductor portion 52. In a plan view from the thickness direction D1 of the dielectric substrate 4, the outer edge shape of the via conductor portion 53 is circular, but is not limited to this. In each of the multiple wiring portions 5, the via conductor portion 53 is formed integrally with the second conductor portion 52. That is, in each of the multiple wiring portions 5, the via conductor portion 53 is seamlessly connected to the second conductor portion 52.

[0033] 1 , the first conductor portion 51 of one of the two wiring portions 5 is connected to the fifth electrode 31 of the third capacitor 3. The interposer 100 may further include a wiring portion connected to the first capacitor 1. The interposer 100 may further include a wiring portion connected to the second capacitor 2.

[0034] In the interposer 100, the thickness T2 of the second dielectric portion 23 is thinner than the thickness T1 of the first dielectric portion 13, and the capacitance of the second capacitor 2 is greater than the capacitance of the first capacitor 1. Furthermore, in the interposer 100, the thickness T3 of the third dielectric portion 33 is thinner than the thickness T2 of the second dielectric portion 23, and the capacitance of the third capacitor 3 is greater than the capacitance of the second capacitor 2. If the capacitance of the first capacitor 1 is C1, the dielectric constant of the first dielectric portion 13 is ε1, and the opposing area between the first electrode 11 and the second electrode 12 is S1, then the capacitance of the first capacitor 1 is C1 = ε1·S1 / T1. Furthermore, if the capacitance of the second capacitor 2 is C2, the dielectric constant of the second dielectric portion 23 is ε2, and the opposing area between the third electrode 21 and the fourth electrode 22 is S2, then the capacitance of the second capacitor 2 is C2 = ε2·S2 / T2. Furthermore, if the capacitance of the third capacitor 3 is C3, the dielectric constant of the third dielectric portion 33 is ε3, and the opposing area between the fifth electrode 31 and the sixth electrode 32 is S3, then the capacitance of the third capacitor 3 is C3 = ε3 S3 / T3. Here, in the interposer 100, ε1 = ε2 = ε3, and T1 > T2 > T3, so [capacitance density of the first capacitor 1] < [capacitance density of the second capacitor 2] < [capacitance density of the third capacitor 3], and for example, if S1 = S2 = S3, then C1 < C2 < C3.

[0035] In the interposer 100, the areas of the first capacitor 1 (same value as the facing area S1 described above), the second capacitor 2 (same value as the facing area S2 described above), and the third capacitor 3 (same value as the facing area S3 described above) are the same as one another in a plan view from the thickness direction D1 of the dielectric substrate 4, but may be different. The area of ​​the first capacitor 1 in a plan view from the thickness direction D1 of the dielectric substrate 4 is determined by the area of ​​a portion of the second electrode 12 that overlaps with the first electrode 11 in a plan view from the thickness direction D1 of the dielectric substrate 4. The area of ​​the second capacitor 2 in a plan view from the thickness direction D1 of the dielectric substrate 4 is determined by the area of ​​a portion of the fourth electrode 22 that overlaps with the third electrode 21 in a plan view from the thickness direction D1 of the dielectric substrate 4. The area of ​​the third capacitor 3 in a plan view from the thickness direction D1 of the dielectric substrate 4 is determined by the area of ​​a portion of the sixth electrode 32 that overlaps with the fifth electrode 31 in a plan view from the thickness direction D1 of the dielectric substrate 4.

[0036] (3) Method for Manufacturing Interposer A method for manufacturing the interposer 100 according to the first embodiment will be described with reference to FIGS. 2A to 3C.

[0037] In the manufacturing method of the interposer 100, after preparing a support substrate 9 (see FIG. 2A), steps 1 to 7 are performed in sequence. The support substrate 9 is, for example, an organic film, a silicon substrate, a glass substrate, or a metal substrate. Examples of organic films that can be used include an LCP (Liquid Crystal Polymer) film, a PET (Polyethylene terephthalate) film, and a PTFE (Polytetrafluoroethylene) film.

[0038] In the first step, as shown in FIG. 2A , a first resin layer 44, which will become the first dielectric layer 41, is formed on a support substrate 9. The material of the first resin layer 44 contains the organic material (resin material) of the first dielectric layer 41. The thickness of the first resin layer 44 is greater than the thickness of the first dielectric layer 41. In the first step, a solution containing the organic material of the first resin layer 44 is applied to the support substrate 9 using a coater (e.g., a spin coater) or a dispenser, and pre-baked to form the first resin layer 44. Note that in the first step, the first resin layer 44 may also be formed on the support substrate 9 by laminating a resin film that will become the first resin layer 44 on the support substrate 9.

[0039] 2B , in the second step, a first recess 441, a second recess 442, a third recess 443, and a plurality of fourth recesses 444 are formed in the first resin layer 44, defining regions where the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51 are to be formed, respectively. Here, in the second step, the first recess 441, the second recess 442, the third recess 443, and the plurality of fourth recesses 444 are formed in the first resin layer 44 by an imprinting method (e.g., thermal imprinting). More specifically, in the second step, a first mold (first metal mold) is prepared, on which a first concavo-convex pattern is formed, the first concavo-convex pattern being designed according to the shapes of the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51. The first mold is then pressed against the first resin layer 44 to deform and harden (e.g., thermally harden) the first resin layer 44, thereby forming a first recess 441, a second recess 442, a third recess 443, and a plurality of fourth recesses 444 in the regions where the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51 are to be formed, respectively, and the first mold is then separated from the first resin layer 44. The opening shape of the first recess 441 corresponds to the outer edge shape of the first electrode 11 in a planar view, and the depth of the first recess 441 corresponds to the thickness of the first electrode 11. The opening shape of the second recess 442 corresponds to the outer edge shape of the third electrode 21 in a planar view, and the depth of the second recess 442 corresponds to the thickness of the third electrode 21. The opening shape of the third recess 443 corresponds to the outer edge shape of the fifth electrode 31 in a planar view, and the depth of the third recess 443 corresponds to the thickness of the fifth electrode 31. The opening shape of each of the plurality of fourth recesses 444 corresponds to the outer edge shape of the first conductor 51 in a plan view, and the depth of the fourth recess 444 corresponds to the thickness of the first conductor 51. The first recess 441, the second recess 442, the third recess 443, and the plurality of fourth recesses 444 have the same depth. Note that the imprinting method is not limited to thermal imprinting, and may be, for example, optical imprinting.

[0040] In the third step, as shown in FIG. 2C , the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51 are formed. More specifically, the third step includes, for example, a first step, a second step, and a third step. In the first step, a seed layer covering the surface of the first resin layer 44 is formed by, for example, sputtering. The material of the seed layer is the same as the material of the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51, such as copper, but is not limited thereto and may be, for example, a copper alloy, aluminum, or titanium. In the second step, a first metal portion that will become the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51 is formed by, for example, electrolytic plating. The material of the first metal portion is, for example, copper, but is not limited thereto and may be, for example, a copper alloy, aluminum, or titanium. In the third step, the first metal portion is subjected to chemical mechanical polishing (CMP) until it has a thickness equal to that of the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51, thereby forming the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51. Note that in the first step, the seed layer is formed by sputtering, but this is not limiting and the seed layer may be formed by, for example, electroless plating or chemical vapor deposition (CVD). In the third step, the first resin layer 44 is also subjected to CMP so that the upper surfaces of the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51 are exposed and the main surface 440 of the first resin layer 44 is approximately flush with the upper surfaces of the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51.

[0041] 2D , a second resin layer 45, which will be the basis of the second dielectric layer 42, is formed so as to cover the upper surfaces of the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51, as well as the main surface 440 of the first resin layer 44. The material of the second resin layer 45 contains the organic material (resin material) of the second dielectric layer 42. In the fourth step, a solution containing the organic material of the second resin layer 45 is applied by a coater (e.g., a spin coater) or a dispenser so as to cover the upper surfaces of the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51, as well as the main surface 440 of the first resin layer 44, and the second resin layer 45 is formed by pre-baking.

[0042] 3A , in the fifth step, a first recess 451, a second recess 452, a third recess 453, and a plurality of fourth recesses 454 are formed in the second resin layer 45. The first recess 451, the second recess 452, the third recess 453, and a plurality of fourth recesses 454 define regions where the second electrode 12, the fourth electrode 22, the sixth electrode 32, and a plurality of conductors (including the second conductor 52 and the via conductor 53) are to be formed, respectively. Here, in the fifth step, the first recess 451, the second recess 452, the third recess 453, and the plurality of fourth recesses 454 are formed in the second resin layer 45 by an imprinting method (e.g., thermal imprinting). More specifically, in the fifth step, a second mold (second metal mold) is prepared, on which a second concavo-convex pattern is formed, the second concavo-convex pattern being designed according to the shapes of the second electrode 12, the fourth electrode 22, the sixth electrode 32, and the plurality of second conductors 52. The second mold is then pressed against the second resin layer 45 to deform and harden (e.g., thermally harden) the second resin layer 45, thereby forming a first recess 451, a second recess 452, a third recess 453, and a plurality of fourth recesses 454 in regions where the second electrode 12, the fourth electrode 22, the sixth electrode 32, and the plurality of conductors are to be formed, respectively, and the second mold is then separated from the second resin layer 45. The opening shape of the first recess 451 corresponds to the outer edge shape of the second electrode 12 in a planar view, and the depth of the first recess 451 corresponds to the thickness of the second electrode 12. The opening shape of the second recess 452 corresponds to the outer edge shape of the fourth electrode 22 in a planar view, and the depth of the second recess 452 corresponds to the thickness of the fourth electrode 22. The opening shape of the third recess 453 corresponds to the outer edge shape of the sixth electrode 32 in a planar view, and the depth of the third recess 453 corresponds to the thickness of the sixth electrode 32. The depth of the second recess 452 is deeper than the depth of the first recess 451. The depth of the third recess 453 is deeper than the depth of the second recess 452. Note that the imprinting method is not limited to thermal imprinting, and may be, for example, optical imprinting.

[0043] In the sixth step, as shown in FIG. 3B , the second electrode 12, the fourth electrode 22, the sixth electrode 32, the plurality of via conductors 53, and the plurality of second conductors 52 are formed. More specifically, the sixth step includes, for example, a first step, a second step, and a third step. In the first step, a seed layer covering the surface of the second resin layer 45 is formed by, for example, sputtering. The material of the seed layer is the same as the material of the second electrode 12, the fourth electrode 22, the sixth electrode 32, the plurality of via conductors 53, and the plurality of second conductors 52, such as copper, but is not limited thereto and may be, for example, a copper alloy, aluminum, or titanium. In the second step, a second metal portion that will become the second electrode 12, the fourth electrode 22, the sixth electrode 32, the plurality of via conductors 53, and the plurality of second conductors 52 is formed by, for example, electrolytic plating. The material of the second metal portion is, for example, copper, but is not limited thereto and may be, for example, a copper alloy, aluminum, or titanium. In the third step, the second metal portion is subjected to CMP until it reaches the thickness of the second electrode 12, the fourth electrode 22, the sixth electrode 32, and the plurality of second conductors 52, thereby forming the second electrode 12, the fourth electrode 22, the sixth electrode 32, the plurality of via conductors 53, and the plurality of second conductors 52. Note that in the first step, the seed layer is formed by sputtering, but this is not limiting and the seed layer may be formed by, for example, electroless plating or CVD. In the third step, the second resin layer 45 is also subjected to CMP so that the upper surfaces of the second electrode 12, the fourth electrode 22, the sixth electrode 32, and the plurality of second conductors 52 are exposed and the main surface 450 of the second resin layer 45 is substantially flush with the upper surfaces of the second electrode 12, the fourth electrode 22, the sixth electrode 32, and the plurality of second conductors 52. As a result, the second resin layer 45 after CMP constitutes the second dielectric layer 42.

[0044] In the seventh step, the support substrate 9 and a portion of the first resin layer 44 are subjected to CMP from the main surface 92 of the support substrate 9 opposite the first resin layer 44 side, thereby forming a first dielectric layer 41 consisting of the remaining portion of the first resin layer 44 (see FIG. 3C ). In the seventh step, the lower surfaces of the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51 are exposed, and the first resin layer 44 is also subjected to CMP so that the lower surface of the first resin layer 44 is approximately flush with the lower surfaces of the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51. In the seventh step, it is essential that the lower surfaces of the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51 are exposed, but it is not essential that the lower surface of the first resin layer 44 be approximately flush with the lower surfaces of the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51. In the seventh step, the support substrate 9 may be peeled off, and then a part of the first resin layer 44 may be subjected to CMP. For example, in the first step, an adhesive layer made of a pressure-sensitive adhesive or adhesive agent such as acrylic or silicone may be formed on the support substrate 9, and then the first resin layer 44 may be formed. In the seventh step, the adhesive strength or bond strength of the adhesive layer may be reduced by heating, ultraviolet irradiation, laser light irradiation, or the like, thereby peeling off the support substrate 9.

[0045] In the method for manufacturing the interposer 100 according to the first embodiment, the interposer 100 is formed by performing the first to seventh steps.

[0046] The manufacturing method of the interposer 100 according to the first embodiment utilizes the imprinting method, which eliminates the need for the photolithography and dry etching processes used in the semiconductor manufacturing process, thereby enabling the cost of the interposer 100 to be reduced.

[0047] (4) Advantages The interposer 100 according to the first embodiment includes a dielectric substrate 4 and a first capacitor 1, a second capacitor 2, and a third capacitor 3 embedded in the dielectric substrate 4. In the interposer 100, the first capacitor 1, the second capacitor 2, and the third capacitor 3 have different capacitances. In the interposer 100, the thickness T2 of the second dielectric portion 23 is thinner than the thickness T1 of the first dielectric portion 13, and the capacitance of the second capacitor 2 is greater than the capacitance of the first capacitor 1. Furthermore, in the interposer 100, the thickness T3 of the third dielectric portion 33 is thinner than the thickness T2 of the second dielectric portion 23, and the capacitance of the third capacitor 3 is greater than the capacitance of the second capacitor 2. This allows the interposer 100 according to the first embodiment to be miniaturized while including multiple capacitors (the first capacitor 1, the second capacitor 2, and the third capacitor 3) with different capacitances. More specifically, according to the interposer 100 of the first embodiment, the unit capacitances (capacitance per unit area) of the first capacitor 1, the second capacitor 2, and the third capacitor 3 are different from one another, which enables miniaturization compared to a case where the capacitances are made different by changing the areas of the first capacitor 1, the second capacitor 2, and the third capacitor 3 in a plan view from the thickness direction D1 of the dielectric substrate 4. Furthermore, in the interposer 100 of the first embodiment, the thickness T2 of the second dielectric portion 23 of the second capacitor 2 is thicker than the thickness T3 of the third dielectric portion 33 of the third capacitor 3, which enables the reliability of the second capacitor 2 to be improved more than that of the third capacitor 3. In other words, in the interposer 100 of the first embodiment, the thickness T2 of the second dielectric portion 23 of the second capacitor 2 is thicker than the thickness T3 of the third dielectric portion 33 of the third capacitor 3, which enables the time dependent dielectric breakdown (TDDB) of the second capacitor 2 to be longer than that of the third capacitor 3. Furthermore, in the interposer 100 of embodiment 1, the thickness T1 of the first dielectric portion 13 of the first capacitor 1 is thicker than the thickness T2 of the second dielectric portion 23 of the second capacitor 2, so that the reliability of the first capacitor 1 can be improved more than the reliability of the second capacitor 2.In other words, in the interposer 100 of embodiment 1, the thickness T1 of the first dielectric portion 13 of the first capacitor 1 is thicker than the thickness T2 of the second dielectric portion 23 of the second capacitor 2, so it is possible to make the TDDB of the first capacitor 1 longer than the TDDB of the second capacitor 2.

[0048] An interposer 101 according to a second embodiment will be described with reference to Fig. 4. Regarding the interposer 101 according to the second embodiment, components similar to those of the interposer 100 according to the first embodiment (see Fig. 1) are designated by the same reference numerals and descriptions thereof will be omitted.

[0049] (1) Configuration The interposer 101 according to the second embodiment differs from the interposer 100 according to the first embodiment in that the dielectric substrate 4 further includes a third dielectric layer 43 .

[0050] The third dielectric layer 43 is interposed between the first dielectric layer 41 and the second dielectric layer 42 in the thickness direction D1 of the dielectric substrate 4. That is, in the interposer 101 according to the second embodiment, the second dielectric layer 42 is stacked on the first dielectric layer 41 via the third dielectric layer 43. In the interposer 101 according to the second embodiment, the material of the first dielectric portion 13, the material of the second dielectric portion 23, and the material of the second dielectric layer 42 include an organic material. The material of the third dielectric layer 43 is an inorganic material. The inorganic material includes, for example, silicon nitride or silicon oxynitride.

[0051] In the interposer 101 according to the second embodiment, the first dielectric portion 13 includes a first portion 131 formed integrally with the third dielectric layer 43 and a second portion 132 formed integrally with the second dielectric layer 42. In the first dielectric portion 13, the first portion 131 and the second portion 132 overlap with each other in the thickness direction D1 of the dielectric substrate 4. The dielectric constant of the first portion 131 of the first dielectric portion 13 is greater than the dielectric constant of the second portion 132.

[0052] The second dielectric portion 23 includes a third portion 231 formed integrally with the third dielectric layer 43 and a fourth portion 232 formed integrally with the second dielectric layer 42. In the second dielectric portion 23, the third portion 231 and the fourth portion 232 overlap with each other in the thickness direction D1 of the dielectric substrate 4. The dielectric constant of the third portion 231 of the second dielectric portion 23 is greater than the dielectric constant of the fourth portion 232.

[0053] The third dielectric portion 33 is formed integrally with the third dielectric layer 43. The thickness T3 of the third dielectric portion 33 is the same as the thickness of the third dielectric layer 43. The dielectric constant of the third dielectric portion 33 is greater than the dielectric constant of the fourth portion 232 of the second dielectric portion 23.

[0054] In the interposer 101 according to the second embodiment, similar to the interposer 100 according to the first embodiment, the thickness T2 of the second dielectric portion 23 is thinner than the thickness T1 of the first dielectric portion 13, and the capacitance of the second capacitor 2 is greater than the capacitance of the first capacitor 1. Also, in the interposer 101 according to the second embodiment, similar to the interposer 100 according to the first embodiment, the thickness T3 of the third dielectric portion 33 is thinner than the thickness T2 of the second dielectric portion 23, and the capacitance of the third capacitor 3 is greater than the capacitance of the second capacitor 2.

[0055] (2) Manufacturing Method A manufacturing method for the interposer 101 according to the second embodiment will be described with reference to Figures 5A to 7B. The manufacturing method for the interposer 101 according to the second embodiment is substantially the same as the manufacturing method for the interposer 100 according to the first embodiment, but differs from the manufacturing method for the interposer 100 according to the first embodiment in that the third dielectric layer 43 is formed. With regard to the manufacturing method for the interposer 101 according to the second embodiment, the description of the same steps as those in the manufacturing method for the interposer 100 according to the first embodiment will be omitted as appropriate.

[0056] In the manufacturing method of the interposer 101, the first to ninth steps are sequentially performed after preparing the support substrate 9. The support substrate 9 is, for example, an organic film, a silicon substrate, a glass substrate, or a metal substrate.

[0057] 5A , in the first step, a first resin layer 44, which will be the basis for the first dielectric layer 41, is formed on the support substrate 9. The thickness of the first resin layer 44 is greater than the thickness of the first dielectric layer 41. In the first step, a solution containing the organic material of the first resin layer 44 is applied onto the support substrate 9 using a coater (e.g., a spin coater) or a dispenser, and the solution is pre-baked to form the first resin layer 44.

[0058] 5B , in the second step, a first recess 441, a second recess 442, a third recess 443, and a plurality of fourth recesses 444 are formed in the first resin layer 44, which define regions where the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51 are to be formed, respectively. Here, in the second step, the first recess 441, the second recess 442, the third recess 443, and the plurality of fourth recesses 444 are formed in the first resin layer 44 by an imprinting method (for example, a thermal imprinting method).

[0059] In the third step, as shown in FIG. 5C , the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51 are formed. More specifically, the third step includes, for example, a first step, a second step, and a third step. In the first step, a seed layer covering the surface of the first resin layer 44 is formed by, for example, sputtering. In the second step, a first metal portion that will become the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51 is formed by, for example, electrolytic plating. In the third step, the first metal portion is subjected to CMP until it reaches the thickness of the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51, thereby forming the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51.

[0060] In the fourth step, as shown in FIG. 5D , a third dielectric layer 43 is formed, for example, by a CVD method, so as to cover the upper surfaces of the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductor portions 51, as well as the main surface 440 of the first resin layer 44.

[0061] 6A , in the fifth step, a second resin layer 45, which is the basis of the second dielectric layer 42, is formed so as to cover the third dielectric layer 43. In the fifth step, a solution containing the organic material of the second resin layer 45 is applied by a coater (e.g., a spin coater) or a dispenser so as to cover the third dielectric layer 43, and pre-baking is performed to form the second resin layer 45.

[0062] 6B , in the sixth step, a first recess 451, a second recess 452, a third recess 453, and a plurality of fifth recesses 4541 are formed in the second resin layer 45, which define regions where the second electrode 12, the fourth electrode 22, the sixth electrode 32, and the plurality of second conductors 52 are to be formed, respectively. Here, in the sixth step, the first recess 451, the second recess 452, the third recess 453, and the plurality of fifth recesses 4541 are formed in the second resin layer 45 by an imprinting method (e.g., thermal imprinting). In the sixth step, the third dielectric layer 43 functions as a stopper that limits the depth of the third recess 453 formed by the second mold.

[0063] 6C , in the seventh step, via holes 4542 corresponding to each of the plurality of via conductors 53 are formed in the second resin layer 45 and the third dielectric layer 43 by laser processing or the like. The fourth recess 454, which defines a region where a conductor including the second conductor 52 and the via conductor 53 is to be formed, includes a fifth recess 4541 and a via hole 4542.

[0064] In the eighth step, as shown in FIG. 7A , the second electrode 12, the fourth electrode 22, the sixth electrode 32, the plurality of via conductors 53, and the plurality of second conductors 52 are formed. More specifically, the eighth step includes, for example, a first step, a second step, and a third step. In the first step, a seed layer covering the surface of the second resin layer 45 is formed by, for example, sputtering. The material of the seed layer is the same as the material of the second electrode 12, the fourth electrode 22, the sixth electrode 32, the plurality of via conductors 53, and the plurality of second conductors 52, such as copper, but is not limited thereto and may be, for example, a copper alloy, aluminum, or titanium. In the second step, a second metal portion that will become the second electrode 12, the fourth electrode 22, the sixth electrode 32, the plurality of via conductors 53, and the plurality of second conductors 52 is formed by, for example, electrolytic plating. The material of the second metal portion is, for example, copper, but is not limited thereto and may be, for example, a copper alloy, aluminum, or titanium. In the third step, the second metal portion is subjected to CMP until it has the same thickness as the second electrode 12, the fourth electrode 22, the sixth electrode 32, and the plurality of second conductors 52, thereby forming the second electrode 12, the fourth electrode 22, the sixth electrode 32, the plurality of via conductors 53, and the plurality of second conductors 52. In the third step, the second resin layer 45 is also subjected to CMP so that the upper surfaces of the second electrode 12, the fourth electrode 22, the sixth electrode 32, and the plurality of second conductors 52 are exposed, and the main surface 450 of the second resin layer 45 is approximately flush with the upper surfaces of the second electrode 12, the fourth electrode 22, the sixth electrode 32, and the plurality of second conductors 52. As a result, the second resin layer 45 after CMP constitutes the second dielectric layer 42.

[0065] In the ninth step, the support substrate 9 and a portion of the first resin layer 44 are subjected to CMP from the main surface 92 of the support substrate 9 opposite the first resin layer 44 side, thereby forming a first dielectric layer 41 consisting of the remaining portion of the first resin layer 44 (see FIG. 7B ). Note that in the ninth step, the first resin layer 44 is also subjected to CMP so that the lower surfaces of the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51 are exposed and the lower surface of the first resin layer 44 is approximately flush with the lower surfaces of the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51. In the ninth step, it is essential that the lower surfaces of the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51 are exposed, but it is not essential that the lower surface of the first resin layer 44 be approximately flush with the lower surfaces of the first electrode 11, the third electrode 21, the fifth electrode 31, and the plurality of first conductors 51.

[0066] In the method for manufacturing the interposer 101 according to the second embodiment, the interposer 101 is formed by performing the first to ninth steps.

[0067] (3) Advantages In the interposer 101 according to the second embodiment, similar to the interposer 100 according to the first embodiment, the first capacitor 1, the second capacitor 2, and the third capacitor 3 have different capacitances. Also, in the interposer 101 according to the second embodiment, similar to the interposer 100 according to the first embodiment, the thickness T2 of the second dielectric portion 23 is thinner than the thickness T1 of the first dielectric portion 13, and the capacitance of the second capacitor 2 is greater than the capacitance of the first capacitor 1. Also, in the interposer 100, the thickness T3 of the third dielectric portion 33 is thinner than the thickness T2 of the second dielectric portion 23, and the capacitance of the third capacitor 3 is greater than the capacitance of the second capacitor 2. As a result, similar to the interposer 100 according to the first embodiment, the interposer 101 according to the second embodiment can be miniaturized while including multiple capacitors (the first capacitor 1, the second capacitor 2, and the third capacitor 3) with different capacitances.

[0068] Furthermore, in the interposer 101 according to the second embodiment, the dielectric substrate 4 has the third dielectric layer 43 having a larger dielectric constant than the first dielectric layer 41 and the second dielectric layer 42, so it is possible to make the capacitances of the first capacitor 1, the second capacitor 2, and the third capacitor 3 larger than the respective capacitances of the first capacitor 1, the second capacitor 2, and the third capacitor 3 in the interposer 100 according to the first embodiment. Furthermore, the interposer 101 according to the second embodiment can reduce the variation in the thickness of the third dielectric portion 33, and it is possible to reduce the variation in the capacitance of the third capacitor 3.

[0069] Furthermore, in the interposer 101 according to the second embodiment, the material of the third dielectric layer 43 contains silicon nitride or silicon oxynitride (in other words, the third dielectric layer 43 is composed of a silicon nitride layer or a silicon oxynitride layer), which can suppress the diffusion of copper contained in the constituent elements of the first electrode 11, the third electrode 21, and the fifth electrode 31, thereby enabling at least one of improved electromigration resistance and an extended TDDB time. Note that the material of the third dielectric layer 43 is not limited to silicon nitride or silicon oxynitride, as long as it is an inorganic material.

[0070] (Modifications) The above-described first and second embodiments are merely examples of various embodiments of the present disclosure. The above-described first and second embodiments can be modified in various ways depending on the design, etc., as long as the object of the present disclosure can be achieved.

[0071] For example, the interposers 100 and 101 may include the third capacitor 3, but may not include the third capacitor 3. Furthermore, the interposers 100 and 101 may include a plurality of capacitors including at least the first capacitor 1 and the second capacitor 2, and may not include the third capacitor 3, or may include four or more capacitors, including the first capacitor 1 and the second capacitor 2, whose dielectric portions have different thicknesses and whose capacitances are different from one another. Furthermore, the plurality of capacitors may include two capacitors having the same capacitance.

[0072] Furthermore, in the manufacturing method of the interposers 100 and 101, multiple insulating pillars 46 may be provided that penetrate the first electrode 11, as shown in FIGS. 8A and 8B . In the manufacturing method of the interposers 100 and 101, for example, if the area of ​​the first electrode 11 is increased, dishing may occur due to CMP in the third step, resulting in a decrease in flatness, as shown in FIG. 9 . In response to this, by providing multiple insulating pillars 46 that penetrate the first electrode 11 before the third step, dishing during CMP can be suppressed, thereby reducing variation in the capacitance of the first capacitor 1. Note that, although FIGS. 8A and 8B illustrate only the first electrode 11 among the first electrode 11, the third electrode 21, and the fifth electrode 31, multiple insulating pillars 46 may also be provided on each of the third electrode 21 and the fifth electrode 31.

[0073] The material of the insulating pillars 46 is, for example, the same as the material of the first resin layer 44. The insulating pillars 46 are formed integrally with the first resin layer 44. Therefore, in the interposers 100 and 101, the material of the insulating pillars 46 is the same as the material of the first dielectric layer 41.

[0074] The interposers 100 and 101 may also include a support substrate 9. In this case, the first resin layer 44 (see FIGS. 3B and 7A) may constitute the first dielectric layer 41, and the support substrate 9 may be provided with a plurality of through wiring portions connected one-to-one to the first capacitor 1, the second capacitor 2, the third capacitor 3, and each wiring portion 5, for example.

[0075] Furthermore, in the interposer 100, the material of each of the first dielectric layer 41 and the second dielectric layer 42 is not limited to an organic material, and may be, for example, an inorganic material (such as ceramic).

[0076] In the interposer 100, the dielectric substrate 4 may have one or more dielectric layers in addition to the first dielectric layer 41 and the second dielectric layer 42. In the interposer 100, the dielectric substrate 4 may have one or more dielectric layers in addition to the first dielectric layer 41, the second dielectric layer 42, and the third dielectric layer 43.

[0077] Furthermore, in the interposers 100 and 101, the dielectric substrate 4 has a plurality of dielectric layers, but it is not essential that the dielectric substrate 4 has a plurality of dielectric layers.

[0078] In addition, in the interposer 101, the material of the third dielectric layer 43 may be an organic material having a higher Young's modulus than the material of the first dielectric portion 13, the material of the second dielectric portion 23, and the material of the second dielectric layer 42.

[0079] (Aspects) The following aspects are disclosed in this specification.

[0080] The interposer (100; 101) according to the first aspect comprises a dielectric substrate (4), a wiring portion (5), a first capacitor (1), and a second capacitor (2). The dielectric substrate (4) has a first main surface (401) and a second main surface (402) opposite the first main surface (401). The wiring portion (5) penetrates the dielectric substrate (4). The first capacitor (1) and the second capacitor (2) are built into the dielectric substrate (4). The first capacitor (1) and the second capacitor (2) have different capacitances. The first capacitor (1) has a first electrode (11), a second electrode (12), and a first dielectric portion (13). The first electrode (11) and the second electrode (12) face each other in the thickness direction (D1) of the dielectric substrate (4). The first dielectric portion (13) is interposed between the first electrode (11) and the second electrode (12). The second capacitor (2) has a third electrode (21), a fourth electrode (22), and a second dielectric portion (23). The third electrode (21) and the fourth electrode (22) face each other in the thickness direction (D1) of the dielectric substrate (4). The second dielectric portion (23) is interposed between the third electrode (21) and the fourth electrode (22). The thickness (T2) of the second dielectric portion (23) is thinner than the thickness (T1) of the first dielectric portion (13), and the capacitance of the second capacitor (2) is greater than the capacitance of the first capacitor (1).

[0081] According to this aspect, it is possible to achieve miniaturization while providing a plurality of capacitors (first capacitor 1 and second capacitor 2) with different capacitances.

[0082] In the interposer (100; 101) according to the second aspect, in the first aspect, the dielectric substrate (4) has a first dielectric layer (41) and a second dielectric layer (42). The second dielectric layer (42) is laminated on the first dielectric layer (41). The first electrode (11) and the third electrode (21) are embedded in the first dielectric layer (41). The second electrode (12) and the fourth electrode (22) are embedded in the second dielectric layer (42).

[0083] In the interposer (100; 101) according to the third aspect, in the second aspect, the first dielectric portion (13) and the second dielectric portion (23) overlap the second dielectric layer (42) in a direction perpendicular to the thickness direction (D1) of the dielectric substrate (4). The material of the first dielectric portion (13), the material of the second dielectric portion (23), and the material of the second dielectric layer (42) include an organic material.

[0084] In the interposer (100; 101) according to the fourth aspect, in the second or third aspect, the material of the first dielectric layer (41) is the same as the material of the second dielectric layer (42).

[0085] According to this embodiment, it is possible to improve the adhesion between the first dielectric layer (41) and the second dielectric layer (42).

[0086] In the interposer (101) according to the fifth aspect, in the second aspect, the dielectric substrate (4) further includes a third dielectric layer (43). The third dielectric layer (43) is interposed between the first dielectric layer (41) and the second dielectric layer (42). The material of the first dielectric portion (13), the material of the second dielectric portion (23), and the material of the second dielectric layer (42) include an organic material. The material of the third dielectric layer (43) is an organic material having a higher Young's modulus than the materials of the first dielectric portion (13), the material of the second dielectric portion (23), and the material of the second dielectric layer (42). The first dielectric portion (13) includes a first portion (131) formed integrally with the third dielectric layer (43) and a second portion (132) formed integrally with the second dielectric layer (42). The second dielectric portion (23) includes a third portion (231) formed integrally with the third dielectric layer (43).

[0087] In the interposer (101) according to the sixth aspect, the dielectric substrate (4) of the second aspect further includes a third dielectric layer (43). The third dielectric layer (43) is interposed between the first dielectric layer (41) and the second dielectric layer (42). The material of the third dielectric layer (43) is an inorganic material.

[0088] In an interposer (100; 101) according to a seventh aspect, in any one of the second to sixth aspects, the wiring portion (5) includes a first conductor portion (51), a second conductor portion (52), and a via conductor portion (53). The first conductor portion (51) penetrates the first dielectric layer (41). The second conductor portion (52) is embedded in the second dielectric layer (42). The second conductor portion (52) is thinner than the thickness of the second dielectric layer (42) and is exposed from the second main surface (402) of the dielectric substrate (4). The via conductor portion (53) is embedded in the second dielectric layer (42) and connects the first conductor portion (51) and the second conductor portion (52).

[0089] In the interposer (100; 101) of the eighth aspect, in any one of the first to seventh aspects, the first electrode (11), the second electrode (12), the third electrode (21), the fourth electrode (22) and the wiring portion (5) contain the same metal.

[0090] According to this aspect, it is possible to reduce costs.

[0091] 1 First capacitor 11 First electrode 12 Second electrode 13 First dielectric portion 131 First portion 132 Second portion 2 Second capacitor 21 Third electrode 22 Fourth electrode 23 Second dielectric portion 231 Third portion 232 Fourth portion 3 Third capacitor 31 Fifth electrode 32 Sixth electrode 33 Third dielectric portion 4 Dielectric substrate 41 First dielectric layer 42 Second dielectric layer 43 Third dielectric layer 401 First main surface 402 Second main surface 5 Wiring portion 51 First conductor portion 52 Second conductor portion 53 Via conductor portion 100, 101 Interposer D1 Thickness direction T1 Thickness T2 Thickness T3 Thickness

Claims

1. a dielectric substrate having a first main surface and a second main surface opposite to the first main surface; a wiring portion penetrating the dielectric substrate; a first capacitor and a second capacitor having different capacitances and embedded in the dielectric substrate; The first capacitor is a first electrode and a second electrode facing each other in a thickness direction of the dielectric substrate; a first dielectric portion interposed between the first electrode and the second electrode, The second capacitor is a third electrode and a fourth electrode facing each other in the thickness direction of the dielectric substrate; a second dielectric portion interposed between the third electrode and the fourth electrode, The thickness of the second dielectric portion is smaller than the thickness of the first dielectric portion, The capacitance of the second capacitor is greater than the capacitance of the first capacitor. Interposer.

2. The dielectric substrate is a first dielectric layer; a second dielectric layer laminated on the first dielectric layer, the first electrode and the third electrode are embedded in the first dielectric layer; the second electrode and the fourth electrode are embedded in the second dielectric layer; The interposer of claim 1 .

3. the first dielectric portion and the second dielectric portion overlap the second dielectric layer in a direction perpendicular to the thickness direction of the dielectric substrate, a material of the first dielectric portion, a material of the second dielectric portion, and a material of the second dielectric layer include an organic material; The interposer of claim 2 .

4. The material of the first dielectric layer is the same as the material of the second dielectric layer.

4. An interposer according to claim 2 or 3.

5. The dielectric substrate is a third dielectric layer interposed between the first dielectric layer and the second dielectric layer; a material of the first dielectric portion, a material of the second dielectric portion, and a material of the second dielectric layer include an organic material; a material of the third dielectric layer is an organic material having a higher Young's modulus than a material of the first dielectric portion, a material of the second dielectric portion, and a material of the second dielectric layer; The first dielectric portion is a first portion integrally formed with the third dielectric layer; a second portion integrally formed with the second dielectric layer; The second dielectric portion is a third portion integrally formed with the third dielectric layer; The interposer of claim 2 .

6. The dielectric substrate is a third dielectric layer interposed between the first dielectric layer and the second dielectric layer; the material of the third dielectric layer is an inorganic material; The interposer of claim 2 .

7. The wiring portion is a first conductor portion penetrating the first dielectric layer; a second conductor portion embedded in the second dielectric layer, thinner than the thickness of the second dielectric layer, and exposed from the second main surface of the dielectric substrate; a via conductor portion embedded in the second dielectric layer and connecting the first conductor portion and the second conductor portion, 4. An interposer according to claim 2 or 3.

8. the first electrode, the second electrode, the third electrode, the fourth electrode, and the wiring portion contain the same metal; An interposer according to any one of claims 1 to 3, 5 and 6.