Semiconductor device and semiconductor device manufacturing method

Abstract

Provided is a semiconductor device having a MOS gate structure, the semiconductor device comprising: a base layer provided on the front surface of a semiconductor substrate or above the semiconductor substrate; an interlayer insulating film provided above the base layer; a contact hole provided in the interlayer insulating film and reaching the base layer from the upper surface of the interlayer insulating film; a first alloy layer provided on the bottom part of the contact hole; and a second alloy layer provided on the side wall of the contact hole. Further provided is a semiconductor device manufacturing method comprising: a step for forming an initial polycrystalline film and a first initial metal film on the inner wall of the contact hole; and a step for heating the semiconductor substrate to form a first alloy layer on the bottom part of the contact hole, and to form a second alloy layer on the side wall of the contact hole.

Description

Semiconductor device and method for manufacturing the same

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Patent Document 1 describes a semiconductor device in which a "silicide layer" is provided in a "contact hole." [Prior Art Documents] [Patent Documents] Patent Document 1: Japanese Patent Laid-Open Publication No. 2003-318396 Problem to be solved

[0003] It is preferable to improve the reliability on the front surface side of the semiconductor device. General disclosure

[0004] In a first aspect of the present invention, there is provided a semiconductor device having a MOS gate structure, comprising: an underlayer provided on a front surface of a semiconductor substrate or above the semiconductor substrate; an interlayer insulating film provided above the underlayer; a first contact hole provided in the interlayer insulating film and extending from the upper surface of the interlayer insulating film to the underlayer; a first alloy layer provided at the bottom of the contact hole; and a second alloy layer provided on a side wall of the contact hole.

[0005] The first alloy layer may include an alloy layer formed by reacting a polycrystal deposited inside the first contact hole.

[0006] The second alloy layer may be an alloy layer formed by reacting polycrystal deposited inside the first contact hole.

[0007] The thickness of the second alloy layer may be 0.01 μm or more and 0.2 μm or less.

[0008] The semiconductor device may further include a first barrier metal layer provided inside the contact hole and on the inner side of the first alloy layer and the second alloy layer.

[0009] The first barrier metal layer may include a layer.

[0010] The semiconductor device may further include a tungsten plug layer provided in the first contact hole in contact with the first barrier metal layer.

[0011] The semiconductor substrate may have a transistor portion and a diode portion.

[0012] The interlayer insulating film may further have a second contact hole extending from the upper surface of the interlayer insulating film to the underlayer, and the second contact hole may not have the second alloy layer on its sidewall.

[0013] The semiconductor device may include an impurity-doped polycrystalline layer provided in contact with the first alloy layer.

[0014] The semiconductor device may include at least an impurity-doped polycrystalline layer provided between the lower surface of the first alloy layer and the underlayer, and the underlayer and the impurity-doped polycrystalline layer may have the same conductivity type.

[0015] A second barrier metal layer may be provided on the sidewall of the second contact hole in contact with the interlayer insulating film.

[0016] The semiconductor substrate may have a recess provided in the underlayer below the first contact hole, and the first alloy layer may be provided in the recess.

[0017] The semiconductor substrate may have, at least in part on the front surface side of the semiconductor substrate, a lifetime control region including a lifetime killer.

[0018] The semiconductor substrate may have a transistor portion and a diode portion, the transistor portion having a main region spaced from the diode portion and a boundary region between the main region and the diode portion, and the lifetime control region may be provided in the diode portion and the boundary region.

[0019] In a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of: forming a MOS gate structure on a front surface of a semiconductor substrate; forming an interlayer insulating film on the front surface of the semiconductor substrate or above an underlying layer provided above the semiconductor substrate; forming a first contact hole in the interlayer insulating film above the underlying layer, the first contact hole extending from the upper surface of the interlayer insulating film to the underlying layer; depositing an initial polycrystalline film and a first initial metal film on the inner wall of the contact hole; and heating the semiconductor substrate to form a first alloy layer at the bottom of the first contact hole and a second alloy layer on the side wall of the first contact hole.

[0020] The initial polycrystalline film may be deposited before depositing the first initial metal film.

[0021] The initial polycrystalline film may be deposited after depositing the first initial metal film.

[0022] The method for manufacturing a semiconductor device may include forming a first barrier metal layer on the first alloy layer and the second alloy layer.

[0023] The method for manufacturing a semiconductor device may include a step of depositing a second initial metal film before heating the semiconductor substrate.

[0024] In a third aspect of the present invention, there is provided a semiconductor device having a MOS gate structure, comprising: an underlayer provided on the front surface of a semiconductor substrate or above the semiconductor substrate; an interlayer insulating film provided above the underlayer; a second contact hole provided in the interlayer insulating film, the second contact hole extending from the upper surface of the interlayer insulating film to the underlayer; a third alloy layer provided at the bottom of the second contact hole; and a second alloy layer provided on the upper surface of the interlayer insulating film.

[0025] The third alloy layer may include an alloy layer obtained by reacting the underlayer.

[0026] A second barrier metal layer may be provided on the sidewall of the second contact hole in contact with the interlayer insulating film.

[0027] The second barrier metal layer may include a Ti layer in contact with the interlayer insulating film on the sidewall of the second contact hole, and a TiN layer stacked on the Ti layer.

[0028] The semiconductor device may include a first barrier metal layer provided on an upper surface of the third alloy layer.

[0029] The first barrier metal layer may include a TiN layer provided on the third alloy layer.

[0030] The semiconductor device may include a first barrier metal layer provided on an upper surface of the second alloy layer.

[0031] The first barrier metal layer may include a TiN layer provided on the second alloy layer.

[0032] In a fourth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of: forming a MOS gate structure on a front surface of a semiconductor substrate; forming an interlayer insulating film on the front surface of the semiconductor substrate or above an underlying layer provided above the semiconductor substrate; depositing an initial polycrystalline film on the upper surface of the interlayer insulating film; forming a second contact hole in the interlayer insulating film from the upper surface of the interlayer insulating film to reach the underlying layer; depositing a first metal film on the inner wall of the second contact hole and on the upper surface of the initial polycrystalline film; and heating the semiconductor substrate to form a third alloy layer at the bottom of the second contact hole and a second alloy layer on the upper surface of the interlayer insulating film.

[0033] The method for manufacturing a semiconductor device may include a step of depositing a second initial metal film on the first initial metal film.

[0034] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0035] 1A shows an example of a top view of the semiconductor device 100. FIG. 1B shows an example of a cross section taken along a-a' in FIG. 1A. FIG. 1B shows a top view of a modified example of the semiconductor device 100. FIG. 1C shows a top view of a modified example of the semiconductor device 100. FIG. 1D shows a cross section taken along a-b' in FIG. 1A. FIG. 1E shows a cross section of a modified example of the semiconductor device 100. FIG. 1F shows an enlarged cross section of the semiconductor device 100. FIG. 1G shows an enlarged cross section of the semiconductor device 100. FIG. 1H shows an enlarged cross section of the semiconductor device 100. FIG. 1I shows an enlarged cross section of the semiconductor device 100. FIG. 1J shows an enlarged cross section of the semiconductor device 100. FIG. 1J shows an enlarged cross section of the semiconductor device 100. FIG. 1J shows an enlarged cross section of the semiconductor device 100. FIG. 1J shows another example of the cross section taken along a-b' in FIG. 1B. FIG. 1J shows a flowchart showing an example of a manufacturing process of the semiconductor device 100. FIG. 1I shows an example of a manufacturing process of the semiconductor device 100. FIG. 1I shows an example of a manufacturing process of the semiconductor device 100. FIG. 1I shows an example of a manufacturing process of the semiconductor device 100. FIG. 1J shows an enlarged cross section of a modified example of the semiconductor device 100. 1 is an enlarged cross-sectional view of a modified example of the semiconductor device 100. FIG. 2 is an enlarged cross-sectional view of a modified example of the semiconductor device 100. FIG. 3 is an enlarged cross-sectional view of a modified example of the semiconductor device 100. FIG. 4 is an enlarged cross-sectional view of a modified example of the semiconductor device 100. FIG. 5 is an enlarged cross-sectional view of a modified example of the semiconductor device 100. FIG. 6 is an enlarged cross-sectional view of a semiconductor device 200. FIG. 7 is an enlarged cross-sectional view of a modified example of the semiconductor device 200. FIG. 8 is an enlarged cross-sectional view of a modified example of the semiconductor device 200.

[0036] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0037] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0038] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0039] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0040] In this specification, when P+ type or N+ type is used, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is used, it means that the doping concentration is lower than that of P type or N type.

[0041] 1A shows an example of a top view of a semiconductor device 100. The semiconductor device 100 of this example is a semiconductor chip including a transistor section 70. The semiconductor device 100 is not limited to a transistor, as long as it is a semiconductor element having a MOS gate structure on a semiconductor substrate 10.

[0042] The transistor section 70 is a region obtained by projecting a collector region 22 provided on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region 22 will be described later. The transistor section 70 includes a transistor such as an IGBT. In this example, the transistor section 70 is an IGBT. However, the transistor section 70 may be another transistor such as a MOSFET.

[0043] In this figure, the region around the active portion of the semiconductor device 100 is shown, and other regions are omitted. For example, an edge termination structure may be provided in the region on the negative side of the Y-axis direction of the semiconductor device 100 in this example. The edge termination structure relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure may have, for example, a guard ring, a field plate, a resurf, or a structure combining these. Note that, for convenience, this example describes the edge on the negative side of the Y-axis direction, but the same applies to other edges of the semiconductor device 100.

[0044] The semiconductor substrate 10 is a substrate made of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate or a silicon carbide substrate. The semiconductor substrate 10 may be made of a III-V compound such as GaN, Ga ２ O ３ , or C. The semiconductor substrate 10 in this example is a silicon substrate. In this specification, the term "top view" simply refers to a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 has a front surface 21 and a back surface 23, as described below.

[0045] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are examples of a front surface side metal layer. The gate trench portion 40 is an example of a MOS gate structure included in the semiconductor device 100. Note that although the semiconductor device 100 of this example is a transistor with a MOS gate structure, it may also be a diode with a MOS gate structure.

[0046] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. The gate metal layer 50 is provided above the connection portion 25 and the well region 17.

[0047] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al) or copper (Cu), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al) or copper (Cu), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0048] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with an interlayer insulating film 38 sandwiched therebetween. The interlayer insulating film 38 is omitted in Fig. 1A. A contact hole 54, a contact hole 55, and a contact hole 56 are provided to penetrate the interlayer insulating film 38.

[0049] The contact hole 55 electrically connects the gate metal layer 50 and the gate conductive portion in the transistor portion 70 via the connection portion 25. A plug layer made of tungsten, copper, or the like may be provided inside the contact hole 55. The plug layer will be described later.

[0050] The contact hole 56 connects the emitter electrode 52 and the dummy conductive portion in the dummy trench portion 30. A plug layer made of tungsten, copper, or the like may be provided inside the contact hole 56.

[0051] The connection portion 25 is connected to a front surface side metal layer such as the emitter electrode 52 or the gate metal layer 50. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. In this example, the connection portion 25 is provided extending in the X-axis direction and electrically connected to the gate conductive portion. The connection portion 25 may also be provided between the emitter electrode 52 and the dummy conductive portion. In this example, the connection portion 25 is not provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0052] The gate trench portion 40 is an example of a plurality of trench portions extending in a predetermined extension direction on the front surface 21 side of the semiconductor substrate 10. The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate trench portion 40 of this example may have two extension portions 41 extending along an extension direction (in this example, the Y-axis direction) that is parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 43 that connects the two extension portions 41.

[0053] It is preferable that at least a portion of the connection portion 43 be curved. By connecting the ends of the two extension portions 41 of the gate trench portion 40, electric field concentration at the end of the extension portion 41 can be alleviated. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be electrically connected to the gate conductive portion via the connection portion 25. In another example, without providing the connection portion 25, a contact hole 55 may be provided directly above the extension portion 41 or the connection portion 43 to connect the gate metal layer 50 to the gate conductive portion. Alternatively, the gate metal layer 50 may not be provided within the scope of FIG. 1A, and the gate metal layer 50 or a gate pad (described later) may be connected to the connection portion 25 via the contact hole 55 outside the scope of FIG. 1A.

[0054] The dummy trench portion 30 is an example of a plurality of trench portions extending in a predetermined extension direction on the front surface 21 side of the semiconductor substrate 10. The dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. Like the gate trench portion 40, the dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example). The dummy trench portion 30 in this example has an I-shape on the front surface 21 of the semiconductor substrate 10, but may also have a U-shape on the front surface 21 of the semiconductor substrate 10, like the gate trench portion 40. That is, the dummy trench portion 30 may have two extension portions extending along the extension direction and a connection portion connecting the two extension portions.

[0055] The transistor section 70 of this example has a structure in which two gate trench sections 40 and two dummy trench sections 30 are repeatedly arranged. That is, the transistor section 70 of this example has gate trench sections 40 and dummy trench sections 30 in a 1:1 ratio. For example, the transistor section 70 has one dummy trench section 30 between two extension sections 41.

[0056] However, the ratio of the gate trench portions 40 to the dummy trench portions 30 is not limited to this example. The ratio of the gate trench portions 40 may be greater than the ratio of the dummy trench portions 30, or the ratio of the dummy trench portions 30 may be greater than the ratio of the gate trench portions 40. The ratio of the gate trench portions 40 to the dummy trench portions 30 may be 2:3 or 2:4. Furthermore, the transistor portion 70 may have all the trench portions as gate trench portions 40 and no dummy trench portions 30. In another example, the trench portions may be provided discretely. In yet another example, the trench portions may have intersections in the active portion 120. Distributed trench portions may mean, for example, circular trench portions with no extensions in a top view are provided discretely. In this case, the shape of the trench portions in a top view may be rectangular, hexagonal, or another shape. Alternatively, the trench portions may be provided discretely, with the extension portions connected all the way around. The arrangement of the trench portions in a top view may be a square, a hexagon, or the like. The trench portions having an intersection in the active portion 120 may mean that the conductors inside the trenches are electrically connected.

[0057] The well region 17 is a second conductivity type region provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18, which will be described later. The well region 17 is an example of a well region provided on the peripheral side of the active portion 120. The active portion 120 will be described later. The well region 17 is, for example, P+ type. The well region 17 is provided within a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. Part of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side are provided in the well region 17. The bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction may be covered by the well region 17.

[0058] The contact holes 54 are provided above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 54 are not provided above the well regions 17 provided at both ends in the Y-axis direction. In this manner, one or more contact holes 54 are provided in the interlayer insulating film. The one or more contact holes 54 may be provided extending in the extension direction.

[0059] The mesa portion 71 is a mesa portion provided adjacent to a trench portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion extending from the front surface 21 of the semiconductor substrate 10 to the deepest bottom of each trench portion. The extension portion of each trench portion may be considered as one trench portion. In other words, the region sandwiched between the two extension portions may be considered as a mesa portion.

[0060] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, the emitter regions 12 and the contact regions 15 are provided alternately in the extension direction in the mesa portion 71. In another example, in the mesa portion 71, the emitter region 12 may be arranged in contact with the trench portion, and the contact region 15 may be arranged in contact with the emitter region 12 and spaced apart from the trench portion.

[0061] The base region 14 is a region of a second conductivity type provided on the front surface 21 side of the semiconductor substrate 10. The base region 14 is, for example, a P-type. The base region 14 may be provided on the front surface 21 of the semiconductor substrate 10 at both ends of the mesa portion 71 in the Y-axis direction. Note that FIG. 1A shows only one end of the base region 14 in the Y-axis direction.

[0062] The emitter region 12 is a region of the first conductivity type having a higher doping concentration than the drift region 18. In this example, the emitter region 12 is, for example, N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface 21 of the mesa portion 71, in contact with the gate trench portion 40. The emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54.

[0063] The emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0064] The contact region 15 is provided above the base region 14 and is a second conductivity type region having a higher doping concentration than the base region 14. In this example, the contact region 15 is P+ type, for example. The contact region 15 in this example is provided on the front surface 21 of the mesa portion 71. The contact region 15 may be provided in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. The contact region 15 in this example is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54.

[0065] 1B shows an example of the aa' cross section in FIG. 1A. The aa' cross section is an XZ plane passing through the emitter region 12 in the transistor section 70. In the aa' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The collector electrode 24 is an example of a back-side metal layer provided in contact with the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 is provided above the semiconductor substrate 10 and the interlayer insulating film 38.

[0066] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.

[0067] The buffer region 20 is a region of a first conductivity type provided closer to the back surface 23 of the semiconductor substrate 10 than the drift region 18. In this example, the buffer region 20 is, for example, N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type. Note that the buffer region 20 may be omitted.

[0068] The collector region 22 is provided below the buffer region 20 in the transistor section 70. The collector region 22 has the second conductivity type. In this example, the collector region 22 is, for example, a P+ type.

[0069] The collector electrode 24 is provided on the rear surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as a metal. The material of the collector electrode 24 may be the same as or different from the material of the emitter electrode 52.

[0070] The base region 14 is a region of the second conductivity type provided above the drift region 18. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0071] The emitter region 12 is provided above the base region 14. The emitter region 12 is provided between the base region 14 and the front surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0072] The accumulation region 16 is a region of a first conductivity type that is provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18. The accumulation region 16 in this example is, for example, an N+ type. However, the accumulation region 16 does not necessarily have to be provided.

[0073] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. The dose of ion implantation into the accumulation region 16 is 1.0E+12 cm －２ Above, 1.0E+13cm －２ The ion implantation dose of the accumulation region 16 may be 3.0E+12 cm －２ Above, 6.0E + 12cm －２ By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the transistor section 70 can be reduced.

[0074] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16 is provided, each trench also penetrates these regions to reach the drift region 18. The trenches penetrating the doped regions do not necessarily mean that the trenches are formed in the order of forming the doped regions and then the trenches. The trenches penetrating the doped regions also include trenches formed in the order of forming the doped regions and then the trenches.

[0075] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench, further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 with an interlayer insulating film 38. The upper end of the gate conductive portion 44 may be at the same height as the front surface 21, or may be located below or above the front surface 21.

[0076] The gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side across the gate insulating film 42 in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0077] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed more inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 may be covered with an interlayer insulating film 38 on the front surface 21. The upper end of the dummy conductive portion 34 may be at the same height as the front surface 21, or may be located below the front surface 21, or may be located above the front surface 21.

[0078] The interlayer insulating film 38 is provided above the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 of this example is provided in contact with the front surface 21 of the semiconductor substrate 10. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more contact holes 54 are provided in the interlayer insulating film 38 to electrically connect the emitter electrode 52 and the semiconductor substrate 10. Contact holes 55 and 56 may also be provided penetrating the interlayer insulating film 38. The thickness of the interlayer insulating film 38 is, for example, 1.0 μm, but is not limited to this.

[0079] The interlayer insulating film 38 may be a silicon oxide film. The interlayer insulating film 38 may be a borophosphosilicate glass (BPSG) film, a borosilicate glass (BSG) film, or a phosphosilicate glass (PSG) film. The interlayer insulating film 38 may include a high temperature silicon oxide (HTO) film.

[0080] The back side lifetime control region 151 may be provided in the transistor portion 70. However, the back side lifetime control region 151 may be omitted. The back side lifetime control region 151 is a region in which a lifetime killer is intentionally formed by, for example, injecting impurities into the semiconductor substrate 10. In one example, the back side lifetime control region 151 is formed by injecting helium into the semiconductor substrate 10. The back side lifetime control region 151 may also be formed by injecting protons. By providing the back side lifetime control region 151, it is possible to reduce the turn-off time and suppress the tail current, thereby reducing losses during switching.

[0081] The lifetime killer is a carrier recombination center. The lifetime killer may be a lattice defect. For example, the lifetime killer may be a vacancy, a divacancy, a complex defect of these with an element constituting the semiconductor substrate 10, or a dislocation. The lifetime killer may also be a rare gas element such as helium or neon, or a metal element such as platinum. Electron beams or protons may be used to form the lattice defects.

[0082] The lifetime killer concentration is the concentration of carrier recombination centers. The lifetime killer concentration may be the concentration of lattice defects. For example, the lifetime killer concentration may be the concentration of vacancies such as vacancies and divacancies, the concentration of complex defects formed between these vacancies and elements constituting the semiconductor substrate 10, or the concentration of dislocations. The lifetime killer concentration may also be the chemical concentration of a rare gas element such as helium or neon, or the chemical concentration of a metal element such as platinum.

[0083] The back surface side lifetime control region 151 is provided closer to the back surface 23 than the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The back surface side lifetime control region 151 in this example is provided in the buffer region 20. The back surface side lifetime control region 151 in this example is provided over the entire surface of the semiconductor substrate 10 in the XY plane, and can be formed without using a mask. The back surface side lifetime control region 151 may be provided in a part of the semiconductor substrate 10 in the XY plane. The dose of impurities for forming the back surface side lifetime control region 151 is 0.5E+10 cm －２ Above, 1.0E+14cm －２ Even if it is less than 5.0E+10cm －２ Above, 1.0E+13cm －２ It may be the following:

[0084] The back side lifetime control region 151 may be formed by implantation from the back side 23 of the semiconductor substrate 10. This makes it easier to avoid any influence on the front surface 21 of the semiconductor substrate 10. For example, the back side lifetime control region 151 is formed by irradiating helium or protons from the back side 23 of the semiconductor substrate 10. Here, whether the back side lifetime control region 151 is formed by implantation from the front surface 21 of the semiconductor substrate 10 or from the back side 23 of the semiconductor substrate 10 can be determined by obtaining the state of the front surface 21 by the SR method or by measuring leakage current.

[0085] 2A shows a top view of a modified example of the semiconductor device 100. In this example, only some of the components of the semiconductor device 100 are shown, and some components are omitted.

[0086] The semiconductor substrate 10 has edges 102 in a top view. The semiconductor substrate 10 of this example has two pairs of edges 102 that face each other in a top view. In this example, the X-axis and the Y-axis are parallel to either of the edges 102.

[0087] An active portion 120 is provided on the semiconductor substrate 10. The active portion 120 is a region through which a main current flows in the depth direction between the front surface 21 and the back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode 52 is provided above the active portion 120, but is not shown in the figure.

[0088] The active section 120 is provided with at least one of a transistor section 70 including a transistor element such as an IGBT and a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of FIG. 2A , the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the front surface 21 of the semiconductor substrate 10. In another example, the active section 120 may be provided with only one of the transistor section 70 and the diode section 80.

[0089] In this example, the region where the transistor section 70 is arranged is marked with the symbol "I," and the region where the diode section 80 is arranged is marked with the symbol "F." The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section, which will be described later.

[0090] The diode section 80 is a region obtained by projecting a cathode region 82 provided on the back surface 23 side of the semiconductor substrate 10 onto the front surface 21 of the semiconductor substrate 10. The cathode region 82 will be described later. A P+ type collector region 22 may be provided in a region of the back surface 23 of the semiconductor substrate 10 other than the cathode region 82. In this specification, an extension region 85 obtained by extending the diode section 80 in the Y-axis direction to a gate wiring described later may also be included in the diode section 80. The collector region 22 may be provided on the back surface 23 of the extension region 85.

[0091] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 112. The semiconductor device 100 may also have pads such as an anode pad and a cathode pad. Each pad is disposed near an edge 102. The vicinity of the edge 102 refers to the region between the edge 102 and the emitter electrode 52 in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0092] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the gate conductive portion 44 of the gate trench portion 40 in the active portion 120. The semiconductor device 100 includes a gate wiring that connects the gate pad 112 and the gate trench portion 40. In FIG. 2A , the gate wiring is indicated by diagonal hatching.

[0093] The gate wiring in this example includes a peripheral gate wiring 130 and an inter-active portion gate wiring 131. The gate wiring may be configured using either a gate metal layer 50 or a connection portion 25, or an appropriate combination of both. The peripheral gate wiring 130 and the inter-active portion gate wiring 131 may have the same configuration or different configurations. The peripheral gate wiring 130 is disposed between the active portion 120 and the edge 102 of the semiconductor substrate 10 in a top view. The peripheral gate wiring 130 in this example surrounds the active portion 120 in a top view. The area surrounded by the peripheral gate wiring 130 in a top view may also be the active portion 120. The peripheral gate wiring 130 is connected to the gate pad 112. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be configured using a gate metal layer 50 and a connection portion 25.

[0094] The inter-active portion gate wiring 131 is provided between the multiple active portions 120. In Fig. 2A, two active portions 120 are arranged side by side in the Y-axis direction. By providing the inter-active portion gate wiring 131 between the multiple active portions 120 inside the semiconductor substrate 10, it is possible to reduce variations in wiring length from the gate pad 112 for each region of the semiconductor substrate 10.

[0095] The inter-active portion gate wiring 131 is connected to the gate trench portion of the active portion 120. The inter-active portion gate wiring 131 is disposed above the semiconductor substrate 10. In this example, the inter-active portion gate wiring 131 is composed of a gate metal layer 50 and a connection portion 25. The gate metal layer 50 may be a metal layer containing aluminum or the like.

[0096] The inter-active portion gate wiring 131 may be connected to the peripheral gate wiring 130. In this example, the inter-active portion gate wiring 131 is provided extending in the X-axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 at approximately the center in the Y-axis direction, so as to cross the active portion 120. When the active portion 120 is divided by the inter-active portion gate wiring 131, the transistor portions 70 and the diode portions 80 may be arranged alternately in the X-axis direction in each divided region.

[0097] The edge termination structure 140 is provided on the front surface 21 of the semiconductor substrate 10. In a top view, the edge termination structure 140 is provided between the active section 120 and the edge 102. In this example, the edge termination structure 140 is disposed between the peripheral gate wiring 130 and the edge 102. The edge termination structure 140 relieves electric field concentration on the front surface 21 side of the semiconductor substrate 10. The edge termination structure 140 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active section 120.

[0098] 2B shows a top view of a modified example of the semiconductor device 100. The semiconductor device 100 of this example includes a transistor section 70 and a diode section 80. This figure is an enlarged view of the top surface of region A in FIG. 2A.

[0099] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17, which are provided inside the front surface 21 side of the semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion.

[0100] The dummy trench portion 30 of this example may have a U-shape on the front surface 21 of the semiconductor substrate 10, similar to the gate trench portion 40. That is, the dummy trench portion 30 may have two extension portions 31 extending along the extension direction and a connection portion 33 connecting the two extension portions 31.

[0101] The semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other. The transistor section 70 of this example includes a boundary region 90 located at the boundary between the transistor section 70 and the diode section 80. The region of the transistor section 70 other than the boundary region 90, i.e., the region separated from the diode section 80, may be referred to as a main region.

[0102] The boundary region 90 is a region provided between the main region of the transistor portion 70 and the diode portion 80, and is adjacent to the diode portion 80. The boundary region 90 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. In one example, the trench portion of the boundary region 90 includes a gate trench portion 40 and a dummy trench portion 30. In this example, the boundary region 90 is arranged so that both ends in the X-axis direction are the dummy trench portion 30, but in another example, the boundary region 90 may be arranged so that one end in the X-axis direction is the dummy trench portion 30 and the other end is the gate trench portion 40.

[0103] The contact holes 54 are provided above the base region 14 in the diode section 80. The contact holes 54 are provided above the contact regions 15 in the boundary region 90. None of the contact holes 54 are provided above the well regions 17 provided at both ends in the Y-axis direction.

[0104] The mesa portion 91 is provided in the boundary region 90. The mesa portion 91 has an emitter region 12 and a contact region 15 on the front surface 21 of the semiconductor substrate 10, similar to the main region of the transistor portion 70. The boundary region 90 may have a buffer structure different from that of the main region to achieve compatibility between the structures of the transistor portion 70 and the diode portion 80. As an example of the buffer structure, the mesa portion 91 closest to the diode portion 80 may not have an emitter region 12. Furthermore, the base region 14 may be exposed on the front surface 21 of the semiconductor substrate 10 across multiple mesas 91. The mesa portion 91 of this example has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0105] The mesa portion 81 is provided in a region of the diode portion 80 that is sandwiched between adjacent dummy trench portions 30. The mesa portion 81 has a base region 14 on the front surface 21 of the semiconductor substrate 10. The mesa portion 81 of this example has a well region 17 on the negative side in the Y-axis direction.

[0106] The emitter region 12 is provided in the mesa portion 71, but does not have to be provided in the mesa portion 81 or the mesa portion 91 closest to the diode portion 80. The contact region 15 is provided in the mesa portion 71 and the mesa portion 91, but does not have to be provided in the mesa portion 81.

[0107] 2C shows a cross section taken along the line bb' of a modified example of semiconductor device 100. This figure corresponds to the cross section taken along the line bb' of FIG. 2B. Semiconductor device 100 of this example includes a back-side lifetime control region 151 and a front-side lifetime control region 152. However, semiconductor device 100 does not necessarily have to include either back-side lifetime control region 151 or front-side lifetime control region 152. Semiconductor device 100 of this example includes collector region 22 and cathode region 82 on the lower surface side of buffer region 20, i.e., on the back surface 23 side of semiconductor substrate 10.

[0108] The emitter region 12 is provided above the base region 14 in the mesa portion 71. The emitter region 12 is provided in contact with the gate trench portion 40 in the mesa portion 71. In other cross sections, the emitter region 12 may be provided on the front surface 21 of the mesa portion 71.

[0109] The contact region 15 is provided above the base region 14 in the mesa portion 91. The contact region 15 is provided in contact with the dummy trench portion 30 in the mesa portion 91. In other cross sections, the contact region 15 may be provided on the front surface 21 of the mesa portion 71.

[0110] The accumulation region 16 is provided in the transistor section 70 and the diode section 80. In this example, the accumulation region 16 is provided on the entire surface of the transistor section 70 and the diode section 80. However, the accumulation region 16 does not have to be provided in the diode section 80.

[0111] The cathode region 82 is provided below the buffer region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80. That is, the collector region 22 is provided below the boundary region 90 in this example.

[0112] The back side lifetime control region 151 is provided in both the transistor portion 70 and the diode portion 80. This allows the semiconductor device 100 of this example to speed up recovery in the diode portion 80 and further improve switching loss. The back side lifetime control region 151 may be formed by a method similar to that used for the back side lifetime control region 151 of the other embodiments.

[0113] The front surface side lifetime control region 152 is provided closer to the front surface 21 than the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this example, the front surface side lifetime control region 152 is provided in the drift region 18. The front surface side lifetime control region 152 is provided in both the transistor portion 70 and the diode portion 80. The front surface side lifetime control region 152 is provided in the diode portion 80 and the boundary region 90, and may not be provided in a portion of the transistor portion 70. In another example, the front surface side lifetime control region 152 may be provided over the entire surface of the transistor portion 70, or may not be provided over the entire surface of the transistor portion 70, or may not be provided over a portion or the entire surface of the diode portion 80. The front surface side lifetime control region 152 can suppress hole injection from the base region 14 of the diode portion 80 and the contact region 15 of the transistor portion 70, thereby reducing reverse recovery loss.

[0114] The front-side lifetime control region 152 may be formed by any of the methods for forming the back-side lifetime control region 151. The elements and dose amounts for forming the back-side lifetime control region 151 and the front-side lifetime control region 152 may be the same or different. A case in which the lifetime is adjusted over the entire region in the Z-axis direction of the semiconductor substrate 10, such as by electron beam irradiation, may also be considered an example of forming the front-side lifetime control region 152.

[0115] The front surface side lifetime control region 152 in this example is provided extending from the diode portion 80 to the boundary region 90. The front surface side lifetime control region 152 may be formed by irradiation from the front surface 21 of the semiconductor substrate 10. The front surface side lifetime control region 152 may be formed by irradiation from the back surface 23 side of the semiconductor substrate 10. The front surface side lifetime control region 152 in this example is provided below the gate trench portion 40. When a particle beam or the like for forming the front surface side lifetime control region 152 passes through the MOS gate structure of the semiconductor device 100, defects may occur at the interface between the gate oxide film and the semiconductor substrate.

[0116] The semiconductor device 100 may be a power semiconductor device for controlling power, etc. The semiconductor device 100 of this example may have a vertical semiconductor structure including a backside metal layer on the backside 23 side of the semiconductor substrate 10.

[0117] In this example, an RC-IGBT with a trench gate structure is described as an example of the semiconductor device 100. However, the semiconductor device 100 may be a semiconductor device with a planar gate structure, or may be another semiconductor device such as a diode. The semiconductor device 100 may include an N-channel MOSFET or a P-channel MOSFET.

[0118] 3A is an enlarged view of a cross section of the semiconductor device 100. In this example, an enlarged view of a cross section in the vicinity of a contact hole 54A is shown. The contact hole 54A is an example of a contact hole 54. The cross section in this example is an XZ cross section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. The contact hole 54A (contact hole 54) has a bottom 54b and a sidewall 54w. A first barrier metal layer 60, a first alloy layer 62, a second alloy layer 63, and a plug layer 64 are provided in the contact hole 54A. The contact hole 54A is an example of a first contact hole.

[0119] For convenience, in this specification, the inner wall of contact hole 54, the portion above front surface 21 of semiconductor substrate 10, is referred to as sidewall 54w, and the portion below front surface 21 of semiconductor substrate 10 is referred to as bottom 54b. Although the structure in the vicinity of contact hole 54 is sometimes described using contact hole 54 in this specification, a similar structure may also be applied to other contact holes such as contact hole 55 and contact hole 56. That is, first barrier metal layer 60, first alloy layer 62, second alloy layer 63, and plug layer 64 may be provided in other contact holes such as contact hole 55 and contact hole 56.

[0120] The first alloy layer 62 is provided to cover the bottom 54b of the contact hole 54A. In this example, the first alloy layer 62 is an alloy layer formed by reacting polycrystals. Providing the first alloy layer 62 provides good contact. For example, the first alloy layer 62 is a TiSi (Ti alloy) layer formed by annealing an initial polycrystalline film, which is polysilicon, and a first initial metal film, which is titanium (Ti), formed on the bottom 54b of the contact hole 54A. ２ is.

[0121] The second alloy layer 63 is provided to cover the sidewall 54w of the contact hole 54A. The second alloy layer 63 in this example is an alloy layer formed by reacting polycrystals, similar to the first alloy layer 62. For example, the second alloy layer 63 is a TiSi (Ti alloy) layer formed by annealing an initial polycrystalline film, which is polysilicon, formed on the sidewall 54w of the contact hole 54A and a first initial metal film, which is titanium (Ti). ２ The first alloy layer 62 and the second alloy layer 63 may be formed by the same deposition and annealing process.

[0122] The second alloy layer 63 may be continuous with the first alloy layer 62 at its lower end. That is, the inner wall of the contact hole 54A may be covered with the first alloy layer 62 and the second alloy layer 63. Although the first alloy layer 62 and the second alloy layer 63 are clearly shown as distinct in the drawings, this is merely for convenience. Of the alloy layers integrally formed in the same process, the portion on the bottom 54b of the contact hole 54 may be referred to as the first alloy layer 62, and the portion on the sidewall 54w may be referred to as the second alloy layer 63.

[0123] In this example, the thickness T of the second alloy layer 63 is 0.01 μm or more and 0.2 μm or less. Here, the thickness T of the second alloy layer 63 is the distance in the direction perpendicular to the sidewall 54w of the contact hole 54A, and may be the film thickness at the thickest position.

[0124] The first barrier metal layer 60 is provided inside the first alloy layer 62 and the second alloy layer 63 in the contact hole 54A. The first barrier metal layer 60 contains at least one of titanium (Ti), cobalt (Co), magnesium (Mg), vanadium (V), lanthanum (La), palladium (Pd), tantalum (Ta), and zirconium (Zr). In this example, the first barrier metal layer 60 is formed by sputtering TiN as the second initial metal film, or by annealing the sputtered TiN. The first barrier metal layer 60 may be formed by the same annealing process as the first alloy layer 62 and the second alloy layer 63. Alternatively, the first barrier metal layer 60 may include a layer in which the Ti film formed as the first initial metal film remains or a layer nitrided by the annealing process.

[0125] The plug layer 64 is provided in contact with the first barrier metal layer 60 in the contact hole 54A. For example, the material of the plug layer 64 is tungsten. By using tungsten, which has good embedding properties, the front surface element structure can be miniaturized. Furthermore, by providing the first barrier metal layer 60, it is possible to prevent the interlayer insulating film 38, the first alloy layer 62, and the second alloy layer 63 from being eroded by gases during the formation of the plug layer 64.

[0126] The bottom 54b of the contact hole 54A may be located below the front surface 21 of the semiconductor substrate 10. That is, the semiconductor substrate 10 may have a recess 27 located in the emitter region 12 below the contact hole 54A, and the first alloy layer 62 may be located so as to be accommodated in the recess 27. The emitter region 12 is an example of an underlayer located on the front surface 21 of the semiconductor substrate 10 or above the semiconductor substrate 10. In this example, the upper surface of the underlayer is located at the same height as the front surface 21. The upper surface of the underlayer may be located at the same height as the front surface 21, below the front surface 21, or above the front surface 21. Examples of underlayers whose upper surfaces are located below the front surface 21 include the plug region 19 of the trench contact portion 65 of the mesa portion, the gate conductive portion 44, and the dummy conductive portion 34, as will be described later. Examples of the upper surface of the underlayer located above front surface 21 include connection portion 25, which will be described later, and the field plate of a temperature sensitive diode or edge termination structure 140. The upper surface of first alloy layer 62 may protrude from within recess 27, i.e., may be located above front surface 21 of semiconductor substrate 10.

[0127] The interlayer insulating film 38 has a contact hole 54A and is provided above the semiconductor substrate 10. The interlayer insulating film 38 has one insulating layer provided above the front surface 21, but may also have a plurality of stacked insulating layers. The interlayer insulating film 38 may be a silicon oxide film such as BPSG.

[0128] Here, when electron beams, particle beams, etc. for forming a lifetime control region pass through the MOS gate structure, defects may occur near the interface between the oxide film of the MOS gate structure and the semiconductor layer. Furthermore, if a metal such as Ti, which has a hydrogen absorption effect, is present near the MOS gate structure, it may absorb hydrogen diffusing into the gate portion, inhibiting hydrogen termination of dangling bonds in the MOS gate structure and causing fluctuations in threshold voltage. Conventionally, a silicide layer provided at the bottom of a contact hole is formed by bonding a first initial metal film such as Ti with silicon of a semiconductor substrate, so that unreacted first initial metal film with a hydrogen absorption effect may remain on the upper and lower surfaces of the silicide layer. Furthermore, because elements of the semiconductor substrate that react with the first initial metal film are not present on the side surfaces of the contact hole, unreacted first initial metal film may remain.

[0129] In the semiconductor device 100 of this example, the initial polycrystalline film formed to form the first alloy layer 62 and the second alloy layer 63 bonds with the first initial metal film, thereby preventing the first initial metal film, which has a hydrogen absorption effect, from remaining or reducing the amount of the remaining first initial metal film. This suppresses the influence of the hydrogen absorption effect and promotes hydrogen termination of dangling bonds in the MOS gate structure. This suppresses fluctuations in the threshold voltage.

[0130] The electron beam and particle beam used to form the lifetime control region have a greater effect on the MOS gate structure when irradiated from the front surface 21 side of the semiconductor substrate 10, but can also affect the MOS gate structure when irradiated from the back surface 23 side of the semiconductor substrate 10. Therefore, the semiconductor device 100 can recover damage to the MOS gate structure and suppress fluctuations in threshold voltage even when irradiated from the back surface 23 side. When irradiating the semiconductor substrate 10 with a particle beam or the like from the back surface 23 side, the acceleration voltage increases and the device becomes larger. However, in the semiconductor device 100 of this example, the effect of irradiating the particle beam or the like from the front surface 21 can be suppressed, so the lifetime control region can be formed using a smaller device.

[0131] The first initial metal film may not completely react with the initial polycrystalline film, but may remain on the upper or lower surface of the second alloy layer 63 as is or as a product of reaction with the annealing atmosphere, and may constitute part of the first barrier metal layer 60. When the first initial metal film is formed on the initial polycrystalline film, the first initial metal film may remain on the upper surface of the second alloy layer 63. When the initial polycrystalline film is formed on the first initial metal film, the first initial metal film may remain on the lower surface of the second alloy layer 63. The same applies to the bottom 54b of the contact hole 54A. Even when the first initial metal film remains, the initial polycrystalline film bonds with the first initial metal film, thereby reducing the first initial metal film having a hydrogen storage effect and suppressing fluctuations in the threshold voltage.

[0132] When the first initial metal film remains on the upper surface of the second alloy layer 63, or when the first initial metal film remains on the upper surface of the first alloy layer 62, an enlarged view of the cross section of the semiconductor device 100 passing through the emitter region 12 may be as shown in FIG. 3A, and the layer derived from the first initial metal film may be stacked with the layer derived from the second initial metal film to form part of the first barrier metal layer 60.

[0133] On the other hand, when the first initial metal film remains on the underside of the second alloy layer 63, an enlarged cross-section of the semiconductor device 100 passing through the emitter region 12 is as shown in FIG. 3B . On the sidewall 54w of the contact hole, from the top side, a first barrier metal layer 60 derived from the second initial metal film, a second alloy layer 63 formed by a reaction between the initial polycrystalline film and the first initial metal film, and the first barrier metal layer 60 derived from the first initial metal film are formed. Similarly, on the bottom 54b of the contact hole, from the top side, a first barrier metal layer 60 derived from the second initial metal film, a first alloy layer 62 formed by a reaction between the initial polycrystalline film and the first initial metal film, the first barrier metal layer 60 derived from the first initial metal film, and the first alloy layer 62 formed by a reaction between the silicon of the mesa portion 71 and the first initial metal film may be formed. The stacked structure may be formed on either or both of the sidewall 54w and the bottom 54b of the contact hole.

[0134] 3B and subsequent examples of the first barrier metal layer 60, a layer derived from the first initial metal film may be formed on the sidewall 54w of the contact hole or, as will be described later, on the upper surface of the interlayer insulating film 38, on the lower surface of the second alloy layer 63. Furthermore, at the bottom 54b of the contact hole, the first barrier metal layer 60 may mutually form a layer with the first alloy layer 62 or a third alloy layer 68, which will be described later.

[0135] Furthermore, as shown in FIG. 3C , the second alloy layer 63 may also be formed on the upper surface of the interlayer insulating film 38 outside the contact hole 54A. The second alloy layer 63 on the upper surface of the interlayer insulating film 38 may be formed integrally with the second alloy layer 63 formed on the sidewall 54w of the contact hole 54A. The first barrier metal layer 60 does not have to be formed on the upper surface of the interlayer insulating film 38 outside the contact hole 54A. The contact hole 54A shown in this example is fabricated by forming the second alloy layer 63 integrally with the first barrier metal layer 60 formed on the upper surface of the sidewall 54w of the contact hole 54A, and then etching back the first barrier metal layer 60 only on the upper surface of the interlayer insulating film 38. In the examples shown in FIG. 3C and subsequent figures, even if an example is described in which the second alloy layer 63 is not formed on the upper surface of the interlayer insulating film 38 outside the contact hole, the second alloy layer 63 may be formed on the upper surface of the interlayer insulating film 38 as in this example.

[0136] Fig. 3D is an enlarged view of a cross section of the semiconductor device 100. The cross section of this example differs from the cross section of Fig. 3A in that it passes through the contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, the differences from Fig. 3A will be particularly described.

[0137] A P+ type plug region 19 having a doping concentration higher than that of the contact region 15 may be provided below the contact hole 54A. The plug region 19 is an example of an underlayer provided on the front surface 21 of the semiconductor substrate 10 or above the semiconductor substrate 10. The plug region 19 may be provided below the contact hole 54A and above the contact region 15. The lower end of the plug region 19 may be shallower than the lower end of the contact region 15. Holes are extracted from the contact region 15 and the plug region 19 via the contact hole 54A. The plug region 19 improves the contact resistance between the first barrier metal layer 60 of the contact hole 54A and the contact region 15, thereby improving latch-up resistance.

[0138] The plug region 19 may be provided below the contact hole 54A and above the base region 14. The plug region 19 may be provided in the mesa portion 71 and the mesa portion 91. The plug region 19 may be provided below the contact hole 54A and not above the emitter region 12. In this case, the plug regions 19 may be provided discretely along the contact hole 54A in the mesa portion 71 and the mesa portion 91 in accordance with the repeated structure of the emitter region 12 and the contact region 15.

[0139] When the contact hole 54A is provided in the mesa portion 81, the plug region 19 is provided below the contact hole 54A. This improves the contact resistance between the base region 14 and the first alloy layer 62. The plug region 19 may not be provided over the entire contact region 15 or the base region 14, but may be provided partially or discretely. In the area where the plug region 19 is not formed, the contact region 15 or the base region 14 may be an example of an underlayer provided on the front surface 21 of the semiconductor substrate 10 or above the semiconductor substrate 10. This suppresses hole injection into the semiconductor substrate 10 when the diode portion 80 is conductive in the area where the plug region 19 is not formed. When the contact hole 54A is provided in the mesa portion 81, the second alloy layer 63 is provided on the sidewall 54w of the contact hole, and the first alloy layer 62 is provided on the bottom 54b. The Ti layer included in the first barrier metal layer 60 is removed or reduced, thereby suppressing fluctuations in the threshold voltages of the mesa portions 71 and 91.

[0140] 4A is an enlarged view of a cross section of the semiconductor device 100. In this example, an enlarged view of a cross section in the vicinity of the contact hole 54A is shown. The cross section in this example is an XZ cross section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. This example differs from the example in FIG. 3A in that an impurity-introduced polycrystalline layer 66 is provided on the lower surface of the second alloy layer 63 in the contact hole 54A.

[0141] In this example, the impurity-doped polycrystalline layer 66 is provided on the lower surface of the first alloy layer 62, i.e., sandwiched between the bottom 54b and the first alloy layer 62. The impurity-doped polycrystalline layer 66 is also provided on the lower surface of the second alloy layer 63, i.e., between the sidewall 54w and the second alloy layer 63. When the second alloy layer 63 is also formed on the upper surface of the interlayer insulating film 38, the impurity-doped polycrystalline layer 66 may be provided on both the upper surface of the interlayer insulating film 38 and the lower surface of the second alloy layer 63.

[0142] The impurity-introduced polycrystalline layer 66 may be provided on the lower surface of the first alloy layer 62, but not on the lower surface of the second alloy layer 63. The impurity-introduced polycrystalline layer 66 may not be provided on the lower surface of the first alloy layer 62, but may be provided on the lower surface of the second alloy layer 63. The impurity-introduced polycrystalline layer 66 may be provided partially on the lower surfaces of the first alloy layer 62 and the second alloy layer 63.

[0143] The impurity-introduced polycrystalline layer 66 is formed by introducing impurities into the initial polycrystalline film formed to form the first alloy layer 62 and the second alloy layer 63 when the initial polycrystalline film remains without bonding with the first initial metal film. The impurities may be doped during film formation or may be introduced by ion implantation after film formation. The impurity-introduced polycrystalline layer 66N is an example of the impurity-introduced polycrystalline layer 66. The impurity-introduced polycrystalline layer 66N provided above the emitter region 12 is N-type.

[0144] 4B is an enlarged view of a cross section of the semiconductor device 100. In this example, an enlarged view of a cross section in the vicinity of the contact hole 54A is shown. The cross section in this example is an XZ cross section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. This example differs from the example in FIG. 4A in that an impurity-introduced polycrystalline layer 66N is provided on the upper surface of the second alloy layer 63 in the contact hole 54A.

[0145] In this example, the impurity-doped polycrystalline layer 66N is provided on the upper surface of the first alloy layer 62, i.e., sandwiched between the first barrier metal layer 60 and the first alloy layer 62. The impurity-doped polycrystalline layer 66N is also provided on the upper surface of the second alloy layer 63, i.e., between the first barrier metal layer 60 and the second alloy layer 63.

[0146] The impurity-doped polycrystalline layer 66N is provided on the upper surfaces of the first alloy layer 62 and the second alloy layer 63. The impurity-doped polycrystalline layer 66N may be provided on the upper surface of the first alloy layer 62, but not on the upper surface of the second alloy layer 63. The impurity-doped polycrystalline layer 66N may not be provided on the upper surface of the first alloy layer 62, but may be provided on the upper surface of the second alloy layer 63. The impurity-doped polycrystalline layer 66N may be provided partially on the upper surfaces of the first alloy layer 62 and the second alloy layer 63.

[0147] 4C is an enlarged view of a cross section of the semiconductor device 100. The cross section of this example differs from the cross section of FIG. 4A in that it passes through the contact region 15 on the front surface 21. The impurity-doped polycrystalline layer 66P is an example of the impurity-doped polycrystalline layer 66. The impurity-doped polycrystalline layer 66P provided above the contact region 15 is of P-type.

[0148] In this way, by providing the impurity-doped polycrystalline layer 66 on the lower surface of the first alloy layer 62, it is possible to suppress an increase in resistance due to the remaining initial polycrystalline film and to prevent interference with charge migration. In Figures 4A, 4B, and 4C, the impurity-doped polycrystalline layer 66 is provided entirely on the lower or upper surfaces of both the first alloy layer 62 and the second alloy layer 63. However, it may be provided only partially on the lower or upper surface of either one of them. The polarity of the impurity-doped polycrystalline layer 66 on the lower surface of the first alloy layer 62 only needs to be at least partially the same as the polarity of the emitter region 12, contact region 15, or plug region 19 at the contact points, and it does not have to be the same as the polarity of the impurity-doped polycrystalline layer 66 on the lower surface of the second alloy layer 63. Furthermore, even if the initial polycrystalline film remains on the lower surface of the second alloy layer 63, it is not necessary to dope the impurity.

[0149] 5A is an enlarged view of a cross section of the semiconductor device 100. In this example, an enlarged view of a cross section in the vicinity of contact hole 54B is shown. The cross section in this example is an XZ cross section passing through emitter region 12 on the front surface 21 of the semiconductor substrate 10. Contact hole 54B is an example of a contact hole 54. In this example, differences from contact hole 54A in FIGS. 3A to 4C will be particularly described.

[0150] In contact hole 54B, a third alloy layer 68 is provided on the bottom 54b, a second barrier metal layer 74 is provided on the sidewall 54w, and a first barrier metal layer 60 is provided on the third alloy layer 68. The third alloy layer 68 is not provided on the sidewall 54w of contact hole 54B. That is, in contact hole 54B, the third alloy layer 68 is provided instead of the first alloy layer 62 of contact hole 54A, and the second alloy layer 63 is not provided. Contact hole 54B is an example of a second contact hole.

[0151] The third alloy layer 68 is formed by annealing a first initial metal film such as Ti. In this example, the emitter region 15, which is an example of an underlayer, reacts with the first initial metal film to form the third alloy layer 68. In this example, the third alloy layer 68 is a TiSi film formed by bonding Ti, which is formed as the first initial metal film on the bottom 54b of the contact hole 54B, with silicon in the semiconductor substrate 10. ２ is.

[0152] In this example, the second barrier metal layer 74 may have a stacked structure in which a TiN film is formed as a second initial metal film by sputtering on a Ti film of the first initial metal film formed on the sidewall 54w of the contact hole 54B. Alternatively, the second barrier metal layer 74 may include a TiN film formed by annealing the Ti of the first initial metal film in a nitrogen atmosphere. In the contact hole 54B, a high proportion of unreacted first initial metal film with a hydrogen absorption effect may remain, particularly on the sidewall 54w. Therefore, the contact hole 54B may be provided in a region, area, or extent in which the remaining unreacted first initial metal film does not affect the threshold voltage.

[0153] 5B is an enlarged view of a cross section of the semiconductor device 100. In this example, an enlarged view of a cross section in the vicinity of contact hole 54B is shown. The cross section of this example differs from the cross section of FIG. 5A in that it passes through contact region 15 on front surface 21 of semiconductor substrate 10. In this example, the differences from FIG. 5A will be particularly described.

[0154] 3D and 4C , a P+ type plug region 19 having a doping concentration higher than that of the contact region 15 may be provided below the contact hole 54B. In this example, the plug region 19, which is an example of an underlayer, reacts with the first initial metal film to form a third alloy layer 68.

[0155] In the diode section 80, a contact hole 54B may be provided in the mesa section 81 in which the plug region 19 is formed. As described above, the contact hole 54B has a third alloy layer 68 instead of the first alloy layer 62 and the second alloy layer 63. Because no initial polycrystalline film is formed in the contact hole 54B, titanium reacts only with silicon in the mesa section 81 to form the third alloy layer 68. Therefore, compared to when titanium reacts with the initial polycrystalline film to form the first alloy layer 62, the P+ type plug region 19 with a high doping concentration is reduced. Therefore, by providing the contact hole 54B in the mesa section 81 in which the plug region 19 is formed, hole injection from the plug region 19 can be suppressed. Note that in areas where the plug region 19 is not provided, the contact region 15 and base region 14, which are examples of an underlayer, react with the first initial metal film to form the third alloy layer 68.

[0156] 6 is an enlarged view of a cross section of the semiconductor device 100. In this example, an enlarged view of a cross section in the vicinity of the contact hole 54A is shown. The cross section in this example is an XZ cross section passing through the contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, differences from the contact hole 54A in FIGS. 3A to 4C will be particularly described.

[0157] The contact hole 54A in this example has a trench contact portion 65 extending in the depth direction from the front surface 21 of the semiconductor substrate 10. That is, the contact hole 54A has a region extending from the upper surface of the interlayer insulating film 38 to the front surface 21 of the semiconductor substrate 10, and a region (trench contact portion 65) extending in the depth direction from the front surface 21 of the semiconductor substrate 10. The bottom 54b of the contact hole 54A is the lower end of the trench contact portion 65, and the sidewall 54w of the contact hole 54A is the region of the inner wall of the contact hole 54A from the upper surface of the interlayer insulating film 38 to the front surface 21 of the semiconductor substrate 10, and the bottom 54b is the inner wall of the trench contact portion 65.

[0158] The lower end of the trench contact portion 65 in this example is shallower than the lower end of the contact region 15. The lower end of the trench contact portion 65 may be deeper than the lower end of the contact region 15. The lower end of the trench contact portion 65 in this example is shallower than the upper end of the gate conductive portion 44. The lower end of the trench contact portion 65 may be deeper than the upper end of the gate conductive portion 44.

[0159] In this way, by providing the contact hole 54A having the trench contact portion 65, the semiconductor device 100 of this example can increase the contact area with the semiconductor substrate 10 and reduce the contact resistance, and can reduce the resistance of the hole current by shortening the distance from the base region 14 to the plug layer 64. By providing the contact hole 54A in the transistor portion 70, holes can be easily extracted, thereby suppressing latch-up.

[0160] 3A except for the presence of a trench contact portion 65. The lower end of the trench contact portion 65 in this example is shallower than the lower end of the emitter region 12. The lower end of the trench contact portion 65 may be deeper than the lower end of the emitter region 12. The lower end of the trench contact portion 65 in this example is shallower than the upper end of the gate conductive portion 44. The lower end of the trench contact portion 65 may be deeper than the upper end of the gate conductive portion 44. A plug region 19 common to the contact region 15 may be provided at the lower end of the trench contact portion 65. The structure having the trench contact portion 65 may also be applied to the contact hole 54B.

[0161] 7 shows an example of a cross section taken along the line bb' in FIG. 2B. The semiconductor device 100 of this example includes a transistor portion 70 and a diode portion 80. The semiconductor device 100 of this example also includes a back surface-side lifetime control region 151 and a front surface-side lifetime control region 152.

[0162] In the semiconductor device 100 of this example, the contact hole 54 provided in the main region of the transistor section 70 is the contact hole 54B shown in Figures 5A and 5B, and the contact hole 54 provided in the diode section 80 and the boundary region 90 is the contact hole 54A shown in Figures 3A and 3D. The contact hole 54A may be the one shown in Figures 4A to 4C (having an impurity-introduced polycrystalline layer 66). Furthermore, the contact holes 54A and 54B may be provided with trench contact portions 65 as shown in Figure 6.

[0163] That is, in the semiconductor device 100 of this example, the contact holes 54A are provided only in the diode section 80 and the boundary region 90, where the front-side lifetime control region 152 is provided. As a result, in the region through which the electron beam and particle beam pass to form the front-side lifetime control region 152, the unreacted first initial metal film having a hydrogen absorption effect is replaced with the first alloy layer and the second alloy layer, thereby suppressing fluctuations in the threshold voltage due to the influence of the hydrogen absorption effect. Furthermore, because the highly doped P+ type plug region 19 remains in the boundary region 90, holes are easily extracted even when current concentrates during turn-off, and this can prevent problems even if a decrease in the threshold voltage is not completely suppressed.

[0164] Fig. 8 shows another example of the cross section taken along the line bb' in Fig. 2B. In this example, differences from Fig. 7 will be particularly described.

[0165] In the semiconductor device 100 of this example, the contact hole 54 provided in the main region of the transistor section 70 is the contact hole 54A shown in Figures 3A and 3D, and the contact hole 54 provided in the diode section 80 and the boundary region 90 is the contact hole 54B shown in Figures 5A and 5B.

[0166] That is, in semiconductor device 100 of this example, contact hole 54A is provided only in the main region of transistor portion 70 that is not provided with front surface side lifetime control region 152. When the area of ​​the main region of transistor portion 70 that is not provided with front surface side lifetime control region 152 is larger than the area of ​​diode portion 80 and boundary region 90 that are provided with front surface side lifetime control region 152, by replacing the unreacted first initial metal film that has a hydrogen absorption effect with the first alloy layer and the second alloy layer in this way in the main region of transistor portion 70 that has a high area ratio, it is possible to suppress fluctuations in threshold voltage due to the influence of the hydrogen absorption effect.

[0167] Furthermore, in the main region of the transistor section 70, an initial polycrystalline film is formed on the bottom 54b of the contact hole 54A, so that titanium does not bond with the silicon of the mesa section 71, and the highly doped P+ type plug region 19 remains. Therefore, although the front-side lifetime control region 152 is not provided and holes tend to accumulate, the holes are easily extracted during turn-off, thereby suppressing latch-up. Meanwhile, in the boundary region 90, titanium bonds with the silicon of the mesa section 91, and the highly doped P+ type plug region 19 is reduced. Therefore, hole injection from the plug region 19 and contact region 15 of the mesa section 91 can be suppressed during diode operation.

[0168] 7 and 8 , the boundary region 90 and the diode section 80 have the same contact hole 54B aligned with the boundary of the front-side lifetime control region 152, while the main region of the transistor section 70 has a different contact hole 54A. However, this is not limited to this. The manner in which the contact holes 54A and 54B are provided in each region may be appropriately selected to balance the suppression of threshold voltage reduction by reducing the amount of unreacted first initial metal film that has a hydrogen storage effect with the concentration of holes in the mesa section. The boundary of the front-side lifetime control region 152 and the transition between the contact holes 54A and 54B do not have to coincide. Even when the front-side lifetime control region 152 is provided over the entire surface of the semiconductor device, or when it is not provided over the entire surface, or when it is provided in multiple regions, the contact holes 54A and 54B may be appropriately provided in the transistor section 70 and the diode section 80.

[0169] Fig. 9 is a flowchart showing an example of a manufacturing process for the semiconductor device 100. Figs. 10A to 10C are diagrams showing an example of a manufacturing process for the semiconductor device 100. Here, an example of the manufacturing process for the semiconductor device 100 will be described with appropriate reference to the diagrams of the respective processes shown in Figs. 10A to 10C.

[0170] In step S100, an element structure is formed on the front surface 21 side of the semiconductor substrate 10. Step S100 may include a step of forming a dummy trench portion 30 and a gate trench portion 40 as the element structure on the front surface 21 side. Step S100 may include a step of forming a base region 14, an emitter region 12, a contact region 15, and the like by ion implantation into the semiconductor substrate 10 as the element structure on the front surface 21 side.

[0171] In step S102, an interlayer insulating film 38 is formed above the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 may be a silicon oxide film such as BPSG. The interlayer insulating film 38 may be formed by stacking a plurality of insulating films.

[0172] In step S104, the interlayer insulating film 38 is etched to form a contact hole. Here, over-etching is performed on the front surface 21 of the semiconductor substrate 10, thereby forming a recess 27. In other words, after reaching the front surface 21 of the semiconductor substrate 10, etching is continued until the recess 27 is formed, thereby forming a contact hole 54 of sufficient dimensions. A trench contact portion 65 may also be formed. Furthermore, a plug region 19 may be formed between steps S104 and S106.

[0173] In step S104, contact holes such as contact hole 54, contact hole 55, and contact hole 56 may be formed in the interlayer insulating film 38. Here, the contact hole 54 will be described using the contact hole 54A shown in FIGS. 3A and 3D as an example of the contact hole 54.

[0174] In step S106, an initial polycrystalline film 61 is formed to cover the bottom 54b and sidewall 54w of the contact hole 54A. The initial polycrystalline film 61 may also be formed on the upper surface of the interlayer insulating film 38. At the bottom 54b of the contact hole 54A, the initial polycrystalline film 61 may be formed within the recess 27; that is, the upper surface of the initial polycrystalline film 61 formed at the bottom 54b of the contact hole 54A may be lower than the front surface 21 of the semiconductor substrate 10. The initial polycrystalline film 61 is preferably formed to a thickness such that the first initial metal film 67 does not remain on the sidewall 54w of the contact hole 54A after step S110, which will be described later.

[0175] In step S108, a first initial metal film 67 is formed on the initial polycrystalline film 61 in the contact hole 54A. The first initial metal film 67 may also be formed above the interlayer insulating film 38. For example, the first initial metal film 67 is a Ti film formed by sputtering. Note that the order of steps S106 and S108 may be reversed, and the initial polycrystalline film 61 may be formed on the first initial metal film 67.

[0176] In step S110, a second initial metal film 69 is formed on the first initial metal film 67. The second initial metal film 69 may also be formed on the upper surface of the interlayer insulating film 38. For example, the second initial metal film 69 is a TiN film formed by sputtering. The second initial metal film 69 may be formed continuously using the same apparatus as the first initial metal film 67 in step S108.

[0177] In step S112, the semiconductor substrate 10 is annealed in a nitrogen atmosphere. This causes the initial polycrystalline film 61 and the first initial metal film 67 to react with each other, forming a first alloy layer 62 at the bottom 54b of the contact hole 54A, and a first barrier metal layer 60 in contact with the upper surface of the first alloy layer 62. A second alloy layer 63 is formed on the sidewall 54w of the contact hole 54A and on the upper surface of the interlayer insulating film 38, and the first barrier metal layer 60 is formed in contact with the upper surface of the second alloy layer 63. In this example, the first alloy layer 62 and the second alloy layer 63 are TiSi layers formed by the first initial metal film 67 of Ti reacting with the initial polycrystalline film 61 of polysilicon to form a silicide. ２ is.

[0178] The Ti of the first initial metal film 67 bonds with the initial polycrystalline film 61 and is replaced by a first alloy layer 62 and a second alloy layer 63. The thickness T of the second alloy layer 63 is 0.01 μm or more and 0.2 μm or less. Note that a portion of the first initial metal film 67 may also bond with the semiconductor substrate 10 to form the first alloy layer 62.

[0179] After step S112, unreacted polycrystalline film may remain, particularly on the sidewall 54w of the contact hole 54A. Therefore, after step S106, impurities may be implanted into the initial polycrystalline film 61, and / or impurities may be introduced into the initial polycrystalline film 61 while being deposited in step S106, thereby forming impurity-introduced polycrystalline layers 66 shown in Figures 4A to 4C between the first alloy layer 62 and the bottom 54b and between the second alloy layer 63 and the sidewall 54w.

[0180] The first barrier metal layer 60 may be the second initial metal film 69. Furthermore, by the annealing in step S112, the first initial metal film 67 that has not bonded to the initial polycrystalline film 61 on the bottom 54b, sidewall 54w, and upper surface of the interlayer insulating film 38 may be nitrided to form a TiN film, which may constitute part of the first barrier metal layer 60. Furthermore, part of the first initial metal film 67 formed on the bottom 54b, sidewall 54w, and upper surface of the interlayer insulating film 38 may remain without bonding to the initial polycrystalline film 61, nitrogen, etc., and may constitute part of the first barrier metal layer 60.

[0181] It is also possible to omit step S110 and form the first barrier metal layer 60 using only a TiN film formed by nitriding the first initial metal film 67. A TiN film formed by annealing has a denser structure than a TiN film formed by sputtering, and therefore can more reliably protect the interlayer insulating film 38 and the first alloy layer 62 from gases used during the formation of the plug layer 64, which will be described later.

[0182] The annealing of the semiconductor substrate 10 in a nitrogen atmosphere may be performed separately in two steps: after step S110 and in step S112. The former is an annealing step for forming the first alloy layer 62 and the second alloy layer 63 and for nitriding the remaining first initial metal film 67, and the latter is an annealing step for improving the adhesion of the second initial metal film 69. The conditions for the respective annealing steps may be the same or different. In another example, only the former annealing step before step S110 may be performed, and the latter annealing step after step S110 may not be performed. The annealing step may be performed before forming the plug layer 64.

[0183] In step S114, the plug layer 64 is formed. In this example, the tungsten plug layer 64 is formed by filling the contact hole 54 by a chemical vapor deposition (CVD) method, and is also laminated on the interlayer insulating film 38.

[0184] In step S116, the plug layer 64 is etched back, thereby removing unnecessary tungsten film outside the contact hole 54. The etch back may be performed by dry etching or CMP (Chemical Mechanical Polishing).

[0185] The second alloy layer 63 and the first barrier metal layer 60 on the upper surface of the interlayer insulating film 38 may be removed by etching back after etching back the plug layer 64. After steps S108, S110, and S112, the initial polycrystalline film 61, the first initial metal film 67, the second initial metal film 69, the second alloy layer 63, and the first barrier metal layer 60 on the upper surface of the interlayer insulating film 38 may be removed.

[0186] It is to be noted that step S116 may be omitted, leaving the plug layer 64 outside the contact hole 54. Furthermore, steps S114 and S116 may be omitted, and the plug layer 64 may not be formed.

[0187] After step S116, an emitter electrode 52 may be formed above the semiconductor substrate 10. Furthermore, after step S116, components on the back surface 23 side, such as a collector electrode 24, may be formed. After step S116, a back surface-side lifetime control region 151 and a front surface-side lifetime control region 152 may be formed.

[0188] 11A, 11B, and 11C are enlarged cross-sectional views of modified examples of the semiconductor device 100. In the examples of FIGS. 11A, 11B, and 11C, the configurations of the first barrier metal layer 60 and the second alloy layer 63 differ from those of FIGS. 3A to 4C. FIGS. 11A, 11B, and 11C are enlarged cross-sectional views of the vicinity of the contact hole 54A. The cross-sections of FIGS. 11A, 11B, and 11C are XZ cross-sections passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. The XZ cross-section passing through the contact region 15 on the front surface 21 of the semiconductor substrate 10 is the same as the XZ cross-sections of FIGS. 11A, 11B, and 11C except that the contact region 15 is provided instead of the emitter region 12 in FIGS. 11A, 11B, and 11C, and is therefore not shown.

[0189] 11A differs from FIGS. 3A to 4C in that the first barrier metal layer 60 and the second alloy layer 63 are provided outside the contact hole 54A and above the interlayer insulating film 38. The second alloy layer 63 may be provided outside the contact hole 54A in contact with the upper surface of the interlayer insulating film 38. This second alloy layer 63 may not be removed by etch-back in step S116 of FIG. 10C and may remain on the upper surface of the interlayer insulating film 38.

[0190] The first barrier metal layer 60 may be provided outside the contact hole 54A in contact with the upper surface of the second alloy layer 63. This first barrier metal layer 60 may not be removed by etch-back in step S116 of Fig. 10C, but may remain above the interlayer insulating film 38. By forming the first barrier metal layer 60 also on the interlayer insulating film 38, reliability during mounting, such as wire bonding and resin sealing, can be improved.

[0191] 11B differs from FIG. 11A in that the plug layer 64 is provided outside the contact hole 54A and above the interlayer insulating film 38. The plug layer 64 may be provided outside the contact hole 54A, above the interlayer insulating film 38, and in contact with the first barrier metal layer 60. Providing the plug layer 64 also above the interlayer insulating film can further improve reliability during mounting, such as wire bonding and resin sealing.

[0192] 11C differs from FIG. 11A in that a plug layer 64 is not provided in the contact hole 54A, and an emitter electrode 52 is provided instead. The emitter electrode 52 is connected to the front surface 21 of the semiconductor substrate 10 via the contact hole 54A. When the mesa width is wide and the contact hole width is made wide, the emitter electrode can be directly filled without providing a plug layer. Even in such a case, the first barrier metal layer 60 is also formed on the interlayer insulating film 38, thereby improving reliability during assembly, such as wire bonding and resin sealing.

[0193] The example of FIG. 11D differs from that of FIG. 11A in that the first barrier metal layer 60 and the second alloy layer 63 are not provided on the upper surface of the interlayer insulating film 38, but instead a second barrier metal layer 74 is provided. After step S106 of the manufacturing process shown in FIGS. 9 and 10A to 10C, the initial polycrystalline film 61 on the upper surface of the interlayer insulating film 38 around the contact hole 54A is removed, thereby forming a second barrier metal layer 74 on the upper surface of the interlayer insulating film 38. By providing the second barrier metal layer 74 on the upper surface of the interlayer insulating film 38, in which a larger amount of the first initial metal film 67 remains than the first barrier metal layer 60, the ion resistance can be improved compared to the example shown in FIG. 11A. Note that the second barrier metal layer 74 may be provided in this manner when the plug layer 64 is left above the interlayer insulating film 38 as shown in FIG. 11B. Alternatively, the second barrier metal layer 74 may be provided in this manner when the emitter electrode is embedded in the contact hole 54A without forming a plug layer as shown in FIG. 11C.

[0194] 12 is an enlarged view of a cross section of a modified example of the semiconductor device 100. The semiconductor device 100 of this example has a gate electrode 240 with a planar structure instead of the gate trench portion 40. The cross section of this example is an XZ cross section passing through the source electrode 252, the interlayer insulating film 38, the first conductivity type source region 212, the second conductivity type base region 214, the second conductivity type contact region 215, the second conductivity type plug region 219, and the gate electrode 240 on the front surface 21 of the semiconductor substrate 10. A first barrier metal layer 60, a first alloy layer 62, and a second alloy layer 63 are provided in the contact hole 54A.

[0195] The semiconductor device 100 of this example does not need to have the plug layer 64. Since the planar structure allows a wider pitch than the trench structure, the contact hole 54A may be filled with the source electrode 252.

[0196] 11C , a first barrier metal layer 60 and a second alloy layer 63 may be provided outside the contact hole 54A above the interlayer insulating film 38. In another example, the second alloy layer 63, the first barrier metal layer 60, and the plug layer 64 may be provided above the interlayer insulating film 38 or on the sidewall as in the contact hole 54A described with reference to FIGS. 3A to 11B , and a gate trench portion 40 may be provided instead of a gate electrode 240 having a planar structure.

[0197] 13A is an enlarged view of a cross section of the semiconductor device 200. The semiconductor device 200 has a structure common to the semiconductor device 100 except for the structure in the vicinity of the contact hole 54, and therefore common elements are denoted by common reference numerals, and the following description will focus on the differences.

[0198] The cross section in this example is an XZ cross section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. In the contact hole 54B, a third alloy layer 68, a first barrier metal layer 60, a second barrier metal layer 74, and a plug layer 64 are provided. In addition, a second alloy layer 63 and a first barrier metal layer 60 are provided above the interlayer insulating film 38.

[0199] First, the structure inside the contact hole 54B will be described. The third alloy layer 68 is provided to cover the bottom 54b of the contact hole 54B. In this example, the third alloy layer 68 is formed when Ti, which is formed as the first initial metal film 67 on the bottom 54b of the contact hole 54B, bonds with the silicon of the semiconductor substrate 10. By providing the third alloy layer 68, good contact can be obtained. For example, the third alloy layer 68 can be formed of TiSi ２ is.

[0200] On the sidewall 54w of the contact hole 54B, the second barrier metal layer 74 is provided in contact with the interlayer insulating film 38. The second barrier metal layer 74 may have a laminated structure including a first initial metal film 67 for forming the third alloy layer 68 that is deposited on the sidewall 54w of the contact hole 54B and remains without bonding with nitrogen or the like, and a TiN film formed by sputtering as the second initial metal film 69. The second barrier metal layer 74 may further include a TiN film formed by annealing the Ti film deposited on the sidewall 54w of the contact hole 54B as the first initial metal film 67 in a nitrogen atmosphere.

[0201] At the bottom 54b of the contact hole 54B, the first barrier metal layer 60 is provided laminated on the third alloy layer 68. The first barrier metal layer 60 may be a TiN film formed by sputtering as a second initial metal film 69. Furthermore, the first barrier metal layer 60 may further include a first initial metal film 67 for forming the third alloy layer 68 that is formed at the bottom 54b of the contact hole 54B and remains without bonding with the semiconductor substrate 10, nitrogen, or the like, or a TiN film formed by annealing Ti formed at the bottom 54b of the contact hole 54B as the first initial metal film 67 in a nitrogen atmosphere.

[0202] The plug layer 64 is provided in contact with the first barrier metal layer 60 and the second barrier metal layer 74 in the contact hole 54B. For example, the material of the plug layer 64 is tungsten. By using tungsten, which has good embedding properties, the front surface element structure can be miniaturized. The plug layer 64 may also be provided above the interlayer insulating film 38.

[0203] Providing the first barrier metal layer 60 and the second barrier metal layer 74 in the contact hole 54B can improve the adhesion of the plug layer 64. Furthermore, providing the first barrier metal layer 60 and the second barrier metal layer 74 can prevent the interlayer insulating film 38 and the third alloy layer 68 from being eroded by gases generated during the formation of the plug layer 64.

[0204] Next, the structure of the upper surface of the interlayer insulating film 38 near the contact hole 54B will be described. A second alloy layer 63 is provided on the upper surface of the interlayer insulating film 38. In this example, the second alloy layer 63 is an alloy layer formed by reacting polycrystals. For example, the second alloy layer 63 is a TiSi alloy layer formed by annealing an initial polycrystalline film 61 made of polysilicon and a first initial metal film 67 made of Ti, both of which are formed on the upper surface of the interlayer insulating film 38. ２ The third alloy layer 68 and the second alloy layer 63 may be formed by the same annealing process.

[0205] The first barrier metal layer 60 is provided by being laminated on the second alloy layer 63. The first barrier metal layer 60 may be a TiN film formed by sputtering as a second initial metal film 69. Furthermore, the first initial metal film 67 for forming the second alloy layer 63 may be formed on the upper surface of the interlayer insulating film 38 and may include a portion that remains without bonding with the initial polycrystalline film 61, nitrogen, or the like, or a TiN film formed by annealing Ti formed on the upper surface of the interlayer insulating film 38 as the first initial metal film 67 in a nitrogen atmosphere. By providing the first barrier metal layer 60 on the upper surface of the interlayer insulating film 38, it is possible to improve ion permeation resistance.

[0206] In the semiconductor device 200 of this example, the initial polycrystalline film 61 formed above the interlayer insulating film 38 to form the second alloy layer 63 bonds with the first initial metal film 67, thereby preventing the first initial metal film 67, which has a hydrogen absorption effect, from remaining and reducing the amount of remaining first initial metal film 67. This suppresses the influence of the hydrogen absorption effect and promotes hydrogen termination of dangling bonds in the MOS gate structure. This suppresses fluctuations in the threshold voltage.

[0207] Fig. 13B is an enlarged view of a cross section of the semiconductor device 200. The cross section of this example differs from the cross section of Fig. 13A in that it passes through the contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, the differences from Fig. 13A will be particularly described.

[0208] A P+ type plug region 19 having a doping concentration higher than that of the contact region 15 may be provided below the contact hole 54B. The plug region 19 may be provided below the contact hole 54B and above the contact region 15. The lower end of the plug region 19 may be provided shallower than the lower end of the contact region 15. Holes are extracted from the contact region 15 and the plug region 19 via the contact hole 54B. The plug region 19 improves the contact resistance between the third alloy layer 68 in the contact hole 54B and the contact region 15, thereby improving latch-up resistance.

[0209] The plug region 19 may be provided below the contact hole 54B and above the base region 14. The plug region 19 may be provided in the mesa portion 71 and the mesa portion 91. The plug region 19 may be provided below the contact hole 54 and not above the emitter region 12. In this case, the plug regions 19 may be provided discretely along the contact hole 54B in the mesa portion 71 and the mesa portion 91 in accordance with the repeated structure of the emitter region 12 and the contact region 15.

[0210] When the contact hole 54B is provided in the mesa portion 81, the plug region 19 is provided below the contact hole 54B. This improves the contact resistance between the base region 14 and the first alloy layer 62. Note that the plug region 19 may not be provided over the entire contact region 15 and the base region 14, but may be provided partially or discretely. This suppresses hole injection into the semiconductor substrate 10 in the region where the plug region 19 is not formed when the diode portion 80 is conductive.

[0211] Fig. 14 is a flowchart showing an example of the manufacturing process of the semiconductor device 200. Figs. 15A to 15C are diagrams showing an example of the manufacturing process of the semiconductor device 200. Here, an example of the manufacturing process of the semiconductor device 200 will be described with appropriate reference to the diagrams of each process shown in Figs. 15A to 15C.

[0212] In step S200, an element structure is formed on the front surface 21 side of the semiconductor substrate 10. Step S200 may include a step of forming a dummy trench portion 30 and a gate trench portion 40 as the element structure on the front surface 21 side. Step S200 may include a step of forming a base region 14, an emitter region 12, a contact region 15, and the like by ion implantation into the semiconductor substrate 10 as the element structure on the front surface 21 side.

[0213] In step S202, an interlayer insulating film 38 is formed above the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 may be a silicon oxide film such as BPSG. The interlayer insulating film 38 may be formed by stacking a plurality of insulating films.

[0214] In step S204, an initial polycrystalline film 61 is formed on the upper surface of the interlayer insulating film 38. The initial polycrystalline film 61 is preferably formed to a thickness such that the first initial metal film 67 does not remain on the upper surface of the interlayer insulating film 38 after step S212, which will be described later.

[0215] In step S206, the interlayer insulating film 38 is etched to form a contact hole. Here, over-etching is performed on the front surface 21 of the semiconductor substrate 10, thereby forming a recess 27. In other words, after reaching the front surface 21 of the semiconductor substrate 10, etching is continued until the recess 27 is formed, thereby forming a contact hole 54B of sufficient dimensions. A trench contact portion 65 may also be formed. Furthermore, a plug region 19 may be formed between steps S206 and S208.

[0216] Step S206 is performed after step S204. That is, upon completion of step S206, the silicon of the semiconductor substrate 10 and the interlayer insulating film 38 are exposed at the bottom 54b and sidewall 54w of the contact hole 54B, respectively, and the initial polycrystalline film 61 remains only on the upper surface of the interlayer insulating film 38 surrounding the contact hole 54B. Also, in step S206, contact holes such as contact hole 54B, contact hole 55, and contact hole 56 may be formed in the interlayer insulating film 38.

[0217] In step S208, a first initial metal film 67 is formed on the inner wall of the contact hole 54B and above the interlayer insulating film 38. For example, the first initial metal film 67 is a Ti film formed by sputtering. The first initial metal film 67 is formed in contact with the silicon of the semiconductor substrate 10 and the interlayer insulating film 38 at the bottom 54b and sidewall 54w of the contact hole 54B, respectively. The first initial metal film 67 is formed above the interlayer insulating film 38 in contact with the upper surface of the initial polycrystalline film 61.

[0218] In step S210, a second initial metal film 69 is formed on the first initial metal film 67 in the contact hole 54B and above the interlayer insulating film 38. For example, the second initial metal film 69 is a TiN film formed by sputtering. The second initial metal film 69 is formed by stacking on the first initial metal film 67.

[0219] In step S212, the semiconductor substrate 10 is annealed in a nitrogen atmosphere. As a result, the silicon of the semiconductor substrate 10 and the first initial metal film 67 are silicided at the bottom 54b of the contact hole 54B, forming a third alloy layer 68. In this example, the third alloy layer 68 is made of TiSi ２ The first initial metal film 67 formed on the bottom 54b of the contact hole 54B bonds with the silicon of the semiconductor substrate 10 and is replaced by a third alloy layer 68. The third alloy layer 68 is formed on the bottom 54b of the contact hole 54B in contact with the front surface 21 of the semiconductor substrate 10, and the first barrier metal layer 60 is formed in contact with the upper surface of the third alloy layer 68.

[0220] Furthermore, the annealing in step S212 nitrides the first initial metal film 67 on the sidewall 54w of the contact hole 54B, forming a TiN film. A portion of the first initial metal film 67 formed on the sidewall 54w of the contact hole 54B may remain without bonding with nitrogen or the like. A stacked structure of a Ti layer and a TiN layer may be formed on the sidewall 54w of the contact hole 54B. The Ti layer is the remaining first initial metal film 67 and is provided in contact with the interlayer insulating film 38. The TiN layer may have a stacked structure of a second initial metal film 69 and a TiN film formed by nitriding the first initial metal film 67. The Ti layer and TiN layer in the contact hole 54B are an example of a second barrier metal layer 74.

[0221] It is also possible to omit step S210 and form the second barrier metal layer 74 using only a TiN film formed by nitriding the first initial metal film 67. A TiN film formed by annealing has a denser structure than a TiN film formed by sputtering, and therefore can more reliably protect the interlayer insulating film 38 and the third alloy layer 68 from gases used during the formation of the plug layer 64, which will be described later.

[0222] Furthermore, by the annealing in step S212, the initial polycrystalline film 61 and the first initial metal film 67 are silicided on the upper surface of the interlayer insulating film 38, forming a second alloy layer 63. In this example, the second alloy layer 63 is made of TiSi ２ Above the interlayer insulating film 38, the first initial metal film 67 bonds with the initial polycrystalline film 61 and is replaced by the second alloy layer 63. Therefore, no first initial metal film 67 remains above the interlayer insulating film 38, or only a small amount remains, so that the influence of the hydrogen absorption effect of the first initial metal film 67 can be suppressed and hydrogen termination of dangling bonds in the MOS gate structure can be promoted. This makes it possible to suppress fluctuations in the threshold voltage.

[0223] Furthermore, by the annealing in step S212, a first barrier metal layer 60 is provided on the upper surface of the interlayer insulating film 38, stacked on the second alloy layer 63. The first barrier metal layer 60 may be a TiN film formed by sputtering as a second initial metal film 69. Furthermore, the first initial metal film 67 for forming the second alloy layer 63 may be formed on the upper surface of the interlayer insulating film 38 and may include a portion that remains without bonding with the initial polycrystalline film 61, nitrogen, or the like, or a TiN film formed by annealing Ti formed on the upper surface of the interlayer insulating film 38 as the first initial metal film 67 in a nitrogen atmosphere. By providing the first barrier metal layer 60 on the upper surface of the interlayer insulating film 38, it is possible to improve ion permeation resistance.

[0224] The semiconductor substrate 10 may also be annealed before step S210. In this case, the annealing step may be performed twice, once after the formation of the first initial metal film 67 and once after the formation of the second initial metal film 69. The former is an annealing step for forming the third alloy layer 68 and the second alloy layer 63 and for nitriding the remaining first initial metal film 67, and the latter is an annealing step for improving the adhesion of the second initial metal film 69. The conditions for these annealing steps may be the same or different. In another example, only the former annealing step before step S210 may be performed, and the latter annealing step after S210 may not be performed. The annealing step may be performed before the formation of the plug layer 64.

[0225] In step S214, the plug layer 64 is formed. In this example, the tungsten plug layer 64 is formed by CVD (Chemical Vapor Deposition) so as to fill the inside of the contact hole 54B. As described above, the second barrier metal layer 74 and the first barrier metal layer 60 are provided on the inner wall of the contact hole 54, so that the interlayer insulating film 38 and the third alloy layer 68 can be prevented from being eroded by gases during the formation of the plug layer 64.

[0226] In step S216, the plug layer 64 is etched back. This may remove unnecessary tungsten film outside the contact hole 54B. The etch back may be performed by dry etching or CMP (Chemical Mechanical Polishing). Note that step S216 may be omitted, leaving the plug layer 64 outside the contact hole 54B.

[0227] After step S216, the emitter electrode 52 may be formed above the semiconductor substrate 10. Also, after step S216, components on the back surface 23 side, such as the collector electrode 24, may be formed. After step S216, the back surface-side lifetime control region 151 and the front surface-side lifetime control region 152 may be formed. Note that step S216 may be omitted, and the plug layer 64 may be left outside the contact hole 54B. Also, steps S214 and S216 may be omitted, and the plug layer 64 may not be formed.

[0228] As described above, according to the manufacturing method of the semiconductor device 200, the second barrier metal layer 74 and the first barrier metal layer 60, each having a Ti layer and a TiN layer, are formed in the contact hole 54B, thereby improving the resistance to ion permeation. Furthermore, by forming the second barrier metal layer 74 and the first barrier metal layer 60, it is possible to prevent the interlayer insulating film 38 and the third alloy layer 68 from being corroded by gases generated during the formation of the plug layer 64.

[0229] Furthermore, according to the manufacturing method of the semiconductor device 200, by forming the initial polycrystalline film 61 on the upper surface of the interlayer insulating film 38 before forming the contact hole 54B, the first initial metal film 67 formed above the interlayer insulating film 38 is bonded to the initial polycrystalline film 61 and replaced with the second alloy layer 63. Therefore, a Ti layer is formed in the contact hole 54 to enhance the ion permeation resistance provided by the second barrier metal layer 74, while Ti is removed from above the interlayer insulating film 38 to suppress the influence of the hydrogen absorption effect of Ti, promoting hydrogen termination of dangling bonds in the MOS gate structure, and enhancing the ion permeation resistance provided by the first barrier metal layer 60. This makes it possible to suppress fluctuations in the threshold voltage.

[0230] 16A, 16B, and 16C are enlarged views of a cross section of a modified example of the semiconductor device 200. In the examples of Figures 16A, 16B, and 16C, the configuration of the plug layer 64 differs from that of Figures 13A and 13B. Figures 16A, 16B, and 16C show enlarged views of a cross section in the vicinity of the contact hole 54B.

[0231] The cross section of Figure 16A is an XZ cross section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. The example of Figure 16A differs from Figure 13A in that the plug layer 64 is provided above the interlayer insulating film 38 outside the contact hole 54B. The plug layer 64 may be provided above the interlayer insulating film 38 outside the contact hole 54B in contact with the first barrier metal layer 60. Note that the XZ cross section passing through the contact region 15 on the front surface 21 of the semiconductor substrate 10 is the same as the XZ cross section of Figure 16A except that the contact region 15 is provided instead of the emitter region 12 in Figure 16A, and therefore is not shown.

[0232] The cross section of Figure 16B is an XZ cross section passing through emitter region 12 on front surface 21 of semiconductor substrate 10. The example of Figure 16B differs from that of Figure 13A in that plug layer 64 is not provided in contact hole 54B, and instead, emitter electrode 52 is provided. Emitter electrode 52 is connected to front surface 21 of semiconductor substrate 10 via contact hole 54B. Note that an XZ cross section passing through contact region 15 on front surface 21 of semiconductor substrate 10 is the same as the XZ cross section of Figure 16B except that contact region 15 is provided instead of emitter region 12 in Figure 16B, and therefore is not shown.

[0233] 16C , a gate electrode 240 having a planar structure is provided instead of the gate trench portion 40. The cross section of this example is an XZ cross section passing through the source electrode 252, the interlayer insulating film 38, the first conductivity type source region 212, the second conductivity type base region 214, the second conductivity type contact region 215, the second conductivity type plug region 219, and the gate electrode 240 on the front surface 21 of the semiconductor substrate 10. In the contact hole 54B, a third alloy layer 68 and a first barrier metal layer 60 are provided on the bottom 54b, and a second barrier metal layer 74 is provided on the sidewall 54w. In addition, a second alloy layer 63 and a first barrier metal layer 60 are provided above the interlayer insulating film 38.

[0234] The semiconductor device 200 of this example does not need to have the plug layer 64. Since the planar structure allows for a wider pitch than the trench structure, the contact hole 54B may be filled with the source electrode 252. In another example, the second alloy layer 63, the first barrier metal layer 60, the second barrier metal layer 74, and the plug layer 64 above or on the sidewall of the interlayer insulating film 38 may be provided as in the contact hole 54B described with reference to FIGS. 13A to 16A, and a gate trench portion 40 may be provided instead of the gate electrode 240 of the planar structure.

[0235] In this way, the structure inside the contact hole 54B and on the upper surface of the interlayer insulating film 38 described with reference to FIGS. 13A and 13B can also be applied to the semiconductor device 200 of this example.

[0236] 13A and 13B can also be fabricated by, in the manufacturing process for fabricating the semiconductor device 100 shown in FIGS. 9 and 10A-10C , opening the contact hole 54 in step S104, depositing the initial polycrystalline film 61 in step S106, then removing the initial polycrystalline film 61 from inside the contact hole 54B and leaving it only on the upper surface of the interlayer insulating film 38, and then performing the processes from step S108 onward. When fabricating the contact hole 54B using this manufacturing process, the initial polycrystalline film 61 may not be left on the entire upper surface of the interlayer insulating film 38, but may be partially removed. For example, the boundary of the remaining initial polycrystalline film 61 may not coincide with the opening of the contact hole 54B, and the boundaries between the second barrier metal layer 74 and the first barrier metal layer 60 and the second alloy layer 63 may be present on the upper surface of the interlayer insulating film 38. In this way, the semiconductor device 100 having the contact holes 54A and 54B may be manufactured by a manufacturing process that partially removes the initial polycrystalline film 61 that was formed after the opening of the contact hole 54. For example, the example in Fig. 7 has been described with the contact hole 54A shown in Fig. 3A and the contact hole 54B shown in Fig. 5A, but this is not limiting, and the semiconductor device 100 may have, for example, the contact hole 54A shown in Fig. 11A and the contact hole 54B shown in Fig. 13A, or the contact hole 54B having the second barrier metal layer 74 on the upper surface of the interlayer insulating film 38.

[0237] Furthermore, the semiconductor device 200 may be manufactured having only the contact hole 54B by the manufacturing process of partially removing the initial polycrystalline film 61 formed after the opening of the contact hole 54. The semiconductor device 200 may have only the contact hole 54B shown in Figures 13A and 13B manufactured in this manner, or may have other contact holes 54B with different structures, such as the contact hole 54B shown in Figures 5A and 5B or a contact hole 54B having a second barrier metal layer 74 on the upper surface of the interlayer insulating film 38.

[0238] 9 and 10A-10C, the semiconductor device 100 having the contact holes 54A and 54B can also be fabricated by opening the contact hole 54A in step S104, and after forming the initial polycrystalline film 61 in step S106, opening the contact hole 54B in the interlayer insulating film 38 on which the initial polycrystalline film 61 has been formed, and then performing steps 108 and beyond. The fabrication process for the contact hole 54B is the same as the fabrication process for the semiconductor device 200 shown in FIG. 14 and 15A-15C. In this way, the semiconductor device 100 having the contact holes 54A and 54B can be fabricated without removing the initial polycrystalline film 61 midway. That is, if the emitter electrode 52 is formed after step S116, the semiconductor device 100 having the contact hole 54A shown in FIG. 11A and the contact hole 54B shown in FIG. 13A can be obtained. If the first barrier metal layer 60 and the second alloy layer 63 are further removed after step S116 and the emitter electrode 52 is formed, the semiconductor device 100 having the contact hole 54A shown in FIG. 3A and the contact hole 54B shown in FIG. 5A can be obtained. If the emitter electrode 52 is formed without performing step S116, the semiconductor device 100 having the contact hole 54A shown in FIG. 11B and the contact hole 54B shown in FIG. 16A can be obtained. If the emitter electrode 52 is formed without performing step S114, the semiconductor device 100 having the contact hole 54A shown in FIG. 11C and the contact hole 54B shown in FIG. 16B can be obtained.

[0239] In the above-described embodiments, the first alloy layer 62 at the bottom 54b of the contact hole 54A is formed from the initial polycrystalline film 61 at the bottom 54b, which is formed after the contact hole is opened. However, this is not limited to this. Alternatively, the initial polycrystalline film 61 at only the bottom 54b of the contact hole in step S106 shown in FIGS. 9 and 10B may be removed, and the first alloy layer 62 may be formed from the silicon of the mesa portion at the bottom 54b of the contact hole, i.e., the underlying layer. Even in this case, the formation of the second alloy layer 63 on the sidewall 54w of the contact hole removes or thins the first initial metal film 67 of the first barrier metal layer 60 at the sidewall 54w of the contact hole, thereby suppressing threshold fluctuations. Furthermore, regarding carrier injection through the bottom 54b of the contact hole, the amount of silicon in the mesa portion that changes to silicide increases, reducing the high-concentration region, allowing for adjustments different from those described in the above-described embodiments.

[0240] Meanwhile, in the previous embodiments, the third alloy layer 68 at the bottom 54b of the contact hole 54B was formed from the silicon of the mesa portion at the bottom 54b of the contact hole, i.e., the base layer. However, this is not limited to this. The initial polycrystalline film 61 at the sidewall 54w of the contact hole in step S106 shown in FIGS. 9 and 10B may be removed, and the third alloy layer 68 may be formed from the initial polycrystalline film 61 at the bottom 54b. Even in this case, when the second alloy layer 63 is formed on the upper surface of the interlayer insulating film 38 around the contact hole 54B, the first initial metal film 67 of the first barrier metal layer 60 is removed or thinned on the upper surface of the interlayer insulating film 38, thereby suppressing threshold fluctuations. Furthermore, with regard to carrier injection through the bottom 54b of the contact hole, the amount of silicon in the mesa portion that changes to silicide is reduced, leaving a high-concentration region. Furthermore, since the impurity-doped polycrystalline layer 66 may be provided, adjustments different from those described in the previous embodiments can be made.

[0241] Furthermore, contact holes such as contact hole 55 and contact hole 56 formed in active portion 120 other than those connecting emitter electrode 52 to underlying layers such as emitter region 12, contact region 15, base region 14, and plug region 19 may also have a structure similar to that of contact holes 54A and 54B described in the previous embodiments. In the case of a contact hole 55 provided on the connection portion 25, which is the base layer as shown in Figures 1A and 2B, or on the gate conductive portion 44, which is an example different from Figures 1A and 2B, a contact hole 56 provided on the dummy conductive portion 34, which is shown in Figures 1A and 2B, or on the connection portion 25, which is an example different from Figures 1A and 2B, or a contact hole provided on a polysilicon diode of a temperature-sensitive diode (not shown), or on a field plate or guard ring of an edge termination structure portion 140, when a second alloy layer 63 is formed on the upper surface of the interlayer insulating film 38 or on the side wall of the contact hole, the first initial metal film 67 of the first barrier metal layer 60 provided in contact with the second alloy layer 63 can be removed or thinned, thereby suppressing fluctuations in the threshold voltage of the active portion 120.

[0242] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0243] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0244] 10...Semiconductor substrate, 12...Emitter region, 14...Base region, 15...Contact region, 16...Accumulation region, 17...Well region, 18...Drift region, 19...Plug region, 20...Buffer region, 21...Front surface, 22...Collector region, 23...Back surface, 24...Collector electrode, 25...Connection portion, 27...Concave portion, 30...Dummy trench portion, 31...Extended portion, 32...Dummy insulating film, 33...Connection portion, 34...Dummy conductive portion, 38...Interlayer insulating film, 40...Gate trench portion, 41...Extended portion, 42...Gate insulating film, 43...Connection portion, 44...Gate conductive portion, 50...Gate metal layer, 52...Emitter electrode, 54...Contact hole, 55...Contact hole, 56...Contact hole, 60...First barrier metal layer, 61...Initial polycrystalline film, 62... First alloy layer, 63: Second alloy layer, 64: Plug layer, 65: Trench contact portion, 66: Impurity-doped polycrystalline layer, 67: First initial metal film, 68: Third alloy layer, 69: Second initial metal film, 70: Transistor portion, 71: Mesa portion, 74: Second barrier metal layer, 80: Diode portion, 81: Mesa portion, 82: Cathode region, 85: Extension region, 90: Boundary region, 91: Mesa portion, 100: Semiconductor device, 102: Edge, 112: Gate pad, 120: Active portion, 130: Peripheral gate wiring, 131: Gate wiring between active portions, 140: Edge termination structure, 151: Back surface side lifetime control region, 152: Front surface side lifetime control region, 212: Source region, 214: Base region, 219: Plug region, 240: Gate electrode, 252: Source electrode

Claims

1. A semiconductor device having a MOS gate structure, a base layer provided on a front surface of a semiconductor substrate or above the semiconductor substrate; an interlayer insulating film provided above the underlayer; a first contact hole provided in the interlayer insulating film, the first contact hole extending from an upper surface of the interlayer insulating film to the base layer; a first alloy layer provided at the bottom of the first contact hole; a second alloy layer provided on a sidewall of the first contact hole; Equipped with the first contact hole is filled with a conductive material; At least one of the first alloy layer and the second alloy layer is an alloy layer formed by reacting a polycrystal deposited inside the first contact hole.

2. the first alloy layer includes an alloy layer formed by reacting a polycrystal deposited inside the first contact hole; The semiconductor device according to claim 1 .

3. the second alloy layer is an alloy layer obtained by reacting a polycrystal deposited inside the first contact hole; The semiconductor device according to claim 1 .

4. The thickness of the second alloy layer is 0.01 μm or more and 0.2 μm or less. The semiconductor device according to claim 1 .

5. a first barrier metal layer provided inside the first contact hole and on the inside of the first alloy layer and the second alloy layer; The semiconductor device according to claim 1 .

6. The first barrier metal layer includes a TiN layer. The semiconductor device according to claim 5 .

7. a tungsten plug layer provided in the first contact hole in contact with the first barrier metal layer; The semiconductor device according to claim 6.

8. the semiconductor substrate has a transistor portion and a diode portion; The semiconductor device according to claim 1 .

9. the interlayer insulating film further has a second contact hole extending from the upper surface of the interlayer insulating film to the base layer; the second contact hole does not have the second alloy layer on a side wall; The semiconductor device according to claim 1 .

10. a doped polycrystalline layer provided in contact with the first alloy layer; The semiconductor device according to claim 1 .

11. a doped polycrystalline layer provided between a lower surface of the first alloy layer and the underlayer, the doped polycrystalline layer having the same conductivity type as the underlayer; The semiconductor device according to claim 1 .

12. a second barrier metal layer is provided on a side wall of the second contact hole in contact with the interlayer insulating film; The semiconductor device according to claim 9.

13. the semiconductor substrate has a recess provided in the underlayer below the first contact hole, and the first alloy layer is provided in the recess; The semiconductor device according to claim 1 .

14. The semiconductor substrate has at least a portion of a lifetime control region including a lifetime killer on a front surface side of the semiconductor substrate. The semiconductor device according to claim 1 .

15. the semiconductor substrate has a transistor portion and a diode portion, the transistor portion has a main region spaced from the diode portion and a boundary region between the main region and the diode portion, and the lifetime control region is provided in the diode portion and the boundary region. The semiconductor device according to claim 14.

16. forming a MOS gate structure on a front surface of a semiconductor substrate; forming an interlayer insulating film on a front surface of the semiconductor substrate or on an underlayer provided above the semiconductor substrate; forming a first contact hole in the interlayer insulating film above the underlayer, the first contact hole extending from an upper surface of the interlayer insulating film to the underlayer; forming an initial polycrystalline film and a first initial metal film on an inner wall of the first contact hole; heating the semiconductor substrate to form a first alloy layer at a bottom of the first contact hole and a second alloy layer on a sidewall of the first contact hole; filling the first contact hole with a conductive material; Equipped with At least one of the first alloy layer and the second alloy layer is an alloy layer formed by reacting a polycrystal deposited inside the first contact hole.

17. the initial polycrystalline film is deposited prior to depositing the first initial metal film; The method for manufacturing a semiconductor device according to claim 16.

18. the initial polycrystalline film is deposited after depositing the first initial metal film; The method for manufacturing a semiconductor device according to claim 16.

19. forming a first barrier metal layer on the first alloy layer and the second alloy layer; The method for manufacturing a semiconductor device according to claim 16.

20. depositing a second initial metal film prior to heating the semiconductor substrate; The method for manufacturing a semiconductor device according to claim 16.

21. A semiconductor device having a MOS gate structure, a base layer provided on a front surface of a semiconductor substrate or above the semiconductor substrate; an interlayer insulating film provided above the underlayer; a second contact hole provided in the interlayer insulating film, the second contact hole extending from an upper surface of the interlayer insulating film to the base layer; a third alloy layer provided at the bottom of the second contact hole; a second alloy layer provided on an upper surface of the interlayer insulating film; Equipped with the second alloy layer is an alloy layer formed by reacting a polycrystal deposited on the upper surface of the interlayer insulating film, and the third alloy layer includes an alloy layer formed by reacting the underlayer, which is the front surface of the semiconductor substrate; Semiconductor device.

22. A semiconductor device having a MOS gate structure, comprising: a base layer provided on a front surface of a semiconductor substrate or above the semiconductor substrate; an interlayer insulating film provided above the underlayer; a second contact hole provided in the interlayer insulating film, the second contact hole extending from an upper surface of the interlayer insulating film to the base layer; a third alloy layer provided at the bottom of the second contact hole; a second alloy layer provided on an upper surface of the interlayer insulating film; Equipped with a second barrier metal layer is provided on a side wall of the second contact hole in contact with the interlayer insulating film; Semiconductor device.

23. The second barrier metal layer is a Ti layer in contact with the interlayer insulating film on a side wall of the second contact hole; a TiN layer laminated on the Ti layer; have The semiconductor device according to claim 22.

24. 22. The semiconductor device of claim 21, further comprising a first barrier metal layer provided on an upper surface of the third alloy layer.

25. A semiconductor device having a MOS gate structure, comprising: a base layer provided on a front surface of a semiconductor substrate or above the semiconductor substrate; an interlayer insulating film provided above the underlayer; a second contact hole provided in the interlayer insulating film, the second contact hole extending from an upper surface of the interlayer insulating film to the base layer; a third alloy layer provided at the bottom of the second contact hole; a second alloy layer provided on an upper surface of the interlayer insulating film; a first barrier metal layer provided on an upper surface of the third alloy layer; Equipped with the third alloy layer includes an alloy layer obtained by reacting the underlayer, the first barrier metal layer has a TiN layer provided on the third alloy layer; Semiconductor device.

26. a first barrier metal layer provided on an upper surface of the second alloy layer; The semiconductor device according to claim 21.

27. A semiconductor device having a MOS gate structure, comprising: a base layer provided on a front surface of a semiconductor substrate or above the semiconductor substrate; an interlayer insulating film provided above the underlayer; a second contact hole provided in the interlayer insulating film, the second contact hole extending from an upper surface of the interlayer insulating film to the base layer; a third alloy layer provided at the bottom of the second contact hole; a second alloy layer provided on an upper surface of the interlayer insulating film; a first barrier metal layer provided on an upper surface of the second alloy layer; Equipped with the third alloy layer includes an alloy layer obtained by reacting the underlayer, the first barrier metal layer has a TiN layer provided on the second alloy layer; Semiconductor device.

28. forming a MOS gate structure on a front surface of a semiconductor substrate; forming an interlayer insulating film on a front surface of the semiconductor substrate or on an underlayer provided above the semiconductor substrate; forming an initial polycrystalline film on an upper surface of the interlayer insulating film; forming a second contact hole in the interlayer insulating film from an upper surface of the interlayer insulating film to the underlayer; forming a first initial metal film on an inner wall of the second contact hole and on an upper surface of the initial polycrystalline film; heating the semiconductor substrate to form a third alloy layer at the bottom of the second contact hole and a second alloy layer on an upper surface of the interlayer insulating film; A method for manufacturing a semiconductor device comprising the steps of:

29. depositing a second initial metal film on the first initial metal film; The method for manufacturing a semiconductor device according to claim 28.

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