Method for manufacturing semiconductor device

Abstract

In a method for manufacturing a semiconductor device according to the present disclosure, a forward voltage is applied to a pn junction of a semiconductor chip, light emitted from the pn junction is detected, and the magnitude of the main current of the semiconductor chip is detected from the intensity of the detected light.

Description

Semiconductor device manufacturing method

[0001] The present disclosure relates to a method for manufacturing a semiconductor device.

[0002] Patent Document 1 discloses a method for inspecting bipolar transistors. When a collector voltage is not applied properly due to poor contact of the collector electrode or other reasons, amplification does not occur and current flows only between the base and emitter. In this case, a forward bias is applied to the pn junction between the emitter and base, and light hν with a wavelength corresponding to the bandgap of the pn junction is emitted. By detecting this light, malfunctions can be easily and reliably detected.

[0003] Japanese Patent Application Laid-Open No. 2001-274170

[0004] In Patent Document 1, malfunctions are detected by detecting light emission generated near the pn junction of a bipolar transistor. However, this inspection method cannot be applied to the characteristic inspection of semiconductor chips that do not have malfunctions.

[0005] An object of the present disclosure is to provide a method for manufacturing a semiconductor device that can inspect the characteristics of a semiconductor chip.

[0006] The method for manufacturing a semiconductor device according to the present disclosure applies a forward voltage to a pn junction of a semiconductor chip, detects light emitted from the pn junction, and detects the magnitude of the main current of the semiconductor chip from the intensity of the detected light.

[0007] In the method for manufacturing a semiconductor device according to the present disclosure, the magnitude of the main current of the semiconductor chip is detected from the intensity of the detected light, thereby making it possible to inspect the characteristics of the semiconductor chip.

[0008] FIG. 1 is a cross-sectional view of a semiconductor chip according to embodiment 1. FIG. 2 is a flowchart showing a method for manufacturing a semiconductor device according to embodiment 1. FIG. 3 is a diagram explaining a base process according to embodiment 1. FIG. 4 is a diagram explaining a wire bonding process according to embodiment 1. FIG. 5 is a diagram explaining an electrode bonding process according to embodiment 1. FIG. 6 is a diagram explaining an optical emission inspection process according to embodiment 1. FIG. 7 is a diagram explaining a case attachment process according to embodiment 1. FIG. 8 is a diagram explaining an optical emission inspection process according to embodiment 2. FIG. 9 is a flowchart showing a method for manufacturing a semiconductor device according to embodiment 3. FIG. 10 is a plan view explaining a die bonding process according to embodiment 3. FIG. 11 is a side view explaining the die bonding process according to embodiment 3. FIG. 12 is a plan view of a semi-finished product according to embodiment 3. FIG. 13 is a diagram explaining an optical emission inspection process according to embodiment 3.

[0009] The method for manufacturing a semiconductor device according to each embodiment will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and repeated description may be omitted.

[0010] First Embodiment. FIG. 1 is a cross-sectional view of a semiconductor chip 10 according to a first embodiment. FIG. 1 shows the structure of the semiconductor chip 10 included in a semiconductor device that is the subject of inspection in this embodiment. The semiconductor chip 10 is, for example, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The semiconductor chip 10 includes a substrate 12 formed of SiC. The substrate 12 has a drain portion and a source portion. A drain electrode 16 is connected to the drain portion, and a source electrode 14 is connected to the source portion. An insulating layer 17 is formed by ion implantation and is stacked near a p-layer region having a channel function. A gate electrode 18 is connected to the p-layer region via the insulating layer 17.

[0011] The semiconductor chip 10 includes a pn junction 20 where a p-layer region and an n-layer region are in contact. In the example shown in FIG. 1 , the pn junction 20 is a body diode parasitic on the SiC-MOSFET. When a forward voltage is applied to the pn junction 20, light is generated with a wavelength corresponding to the bandgap of the pn junction 20. As a result, a bipolar current I flows through the substrate 12. The emission intensity at this time depends on the magnitude of the main current flowing through the semiconductor chip 10 when the semiconductor device is in use. Specifically, the emission intensity and the main current are proportional. In this embodiment, the emission intensity is measured during the semiconductor device manufacturing process to detect the magnitude of the main current of the semiconductor device.

[0012] FIG. 2 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment. In the method for manufacturing a semiconductor device according to the present embodiment, after the introduction of components (S1), a base step is carried out (S2). FIG. 3 is a diagram illustrating the base step according to the first embodiment. In the base step, an insulating substrate 32 is mounted on a base plate 30. A semiconductor chip 10 is mounted on the insulating substrate 32. Next, a wire bonding step is carried out (S3). FIG. 4 is a diagram illustrating the wire bonding step according to the first embodiment. In the wire bonding step, a circuit pattern on the insulating substrate 32 and a circuit pattern on an electrode mounting substrate 33 are connected by wires 34.

[0013] Next, an electrode bonding step is carried out (S4). Figure 5 is a diagram illustrating the electrode bonding step according to the first embodiment. In the electrode bonding step, an electrode 36 made of metal for applying a forward voltage to the semiconductor chip 10 is bonded to the insulating substrate 32 and the electrode mounting substrate 33. The electrode 36 is electrically connected to the source electrode 14 and the drain electrode 16 of the semiconductor chip 10 via a wire 34 and circuit patterns provided on the insulating substrate 32 and the electrode mounting substrate 33.

[0014] Next, an optical emission inspection process is performed (S5). FIG. 6 is a diagram illustrating the optical emission inspection process according to the first embodiment. The optical emission inspection process is performed after the semiconductor chip 10 is electrically connected to electrodes 36 for supplying electricity to the semiconductor chip 10 from outside the semiconductor device. In the optical emission inspection process, a forward voltage is applied to the pn junction 20 of the semiconductor chip 10, and light L1 emitted from the pn junction 20 is detected. Specifically, a voltage is applied to the semiconductor chip 10 via the electrodes 36, and light L1 emitted from the pn junction 20 is detected.

[0015] A power supply 50 is connected between the electrodes 36. In the light emission inspection process, a voltage equal to or greater than the built-in potential must be applied between the source and drain of the semiconductor chip 10 to pass a current through the pn junction 20. The voltage applied between the source and drain varies depending on the semiconductor material forming the semiconductor chip 10, but is, for example, on the order of several volts. It is preferable to apply a negative bias of several volts to the gate electrode 18 in order to keep the MOSFET off. The light L1 emitted from the pn junction 20 in this manner is detected by the light receiving device 52. In the light emission inspection process, the magnitude of the main current of the semiconductor chip 10 is detected from the intensity of the detected light L1.

[0016] Next, the encasing and gel sealing process is carried out (S6). FIG. 7 is a diagram illustrating the encasing process according to the first embodiment. In the encasing process, the case 38 is attached to the base plate 30. In the gel sealing process, the inside of the case is sealed with gel. Instead of the encasing process, a molding process may be employed in which the semiconductor chip 10, insulating substrate 32, etc. are sealed with molding resin. Thereafter, a final inspection (S7) and packaging / shipping (S8) are carried out. The semiconductor device 100 is manufactured in this manner.

[0017] In this embodiment, light emitted when current is applied to the pn junction 20 is detected and measured. By performing an optical emission inspection of the semiconductor chip 10 during the manufacture of the semiconductor device 100, it is possible to obtain optical emission information of the semiconductor chip 10. The magnitude of the main current of the semiconductor chip 10 can be detected from the optical emission information. Therefore, it is possible to inspect the characteristics of the semiconductor chip 10, and screening of the semiconductor chip 10 becomes possible. In other words, in this embodiment, by inspecting the characteristics of a normal semiconductor chip 10, it is possible to provide a highly reliable semiconductor device 100.

[0018] The semiconductor device 100 is a power module used, for example, in motor control for electric railways, automobiles, industrial equipment, etc. Although one semiconductor chip 10 is shown in Fig. 7, a plurality of semiconductor chips 10 may be connected in parallel on an insulating substrate 32 in the semiconductor device 100. The number of semiconductor chips 10 included in the semiconductor device 100 may be one or more. Furthermore, the semiconductor chip 10 is not limited to a MOSFET, and may be a pn diode.

[0019] In this embodiment, an example has been shown in which the semiconductor chip 10 is made of silicon carbide, but the semiconductor chip 10 may be made of a wide bandgap semiconductor such as a gallium nitride material or diamond. The semiconductor chip 10 may also be made of a direct transition semiconductor material, which makes it easier to obtain light emission information. The semiconductor chip 10 may also be made of silicon.

[0020] The above-described modifications can be appropriately applied to the manufacturing methods of semiconductor devices according to the following embodiments. Note that the manufacturing methods of semiconductor devices according to the following embodiments have many points in common with the first embodiment, so the following description will focus on the differences from the first embodiment.

[0021] Second Embodiment Figure 8 is a diagram illustrating an optical emission inspection process according to a second embodiment. In the semiconductor device 100 of this embodiment, a plurality of semiconductor chips 10 are connected in parallel. In the optical emission inspection process, light emitted from the pn junction 20 is detected while the plurality of semiconductor chips 10 are connected in parallel. A plurality of light receiving devices 52 are provided corresponding to the plurality of semiconductor chips 10.

[0022] In this embodiment, light emitted from the pn junction 20 can be detected in a state where a plurality of semiconductor chips 10 are connected in parallel, similar to the state where the semiconductor device 100 is actually used.

[0023] For example, semiconductor devices used to control motors in electric railways, automobiles, industrial equipment, and the like are required to handle high voltages and large currents. In such applications, semiconductor devices incorporating multiple semiconductor chips are sometimes used. Generally, multiple semiconductor chips 10 have variations in characteristics. Therefore, when multiple semiconductor chips are incorporated into the same semiconductor device, even if each semiconductor chip operates normally as a single unit, the semiconductor device as a whole may behave differently from when it is alone. In addition, the behavior of the semiconductor chips may change depending on the internal structure, such as the parallel connection method of the semiconductor chips, chip arrangement, and electrode arrangement.

[0024] In contrast, in the present embodiment, it is possible to acquire light emission information after combining multiple semiconductor chips 10 as in an actual use state. This makes it possible to reflect the behavior of the semiconductor chips 10 when connected in parallel in the manufacture of the semiconductor device 100. Therefore, it is possible to manufacture the semiconductor device 100 so that uniform stress is applied to the multiple semiconductor chips 10 when the semiconductor device 100 including the multiple semiconductor chips 10 connected in parallel actually operates.

[0025] In particular, by acquiring light emission information of each semiconductor chip 10, it becomes possible to screen the semiconductor device 100 in a state where a plurality of semiconductor chips 10 are assembled. For example, screening may be performed in accordance with the intensity of light detected in the light emission inspection so that the variation in the main current flowing through the plurality of semiconductor chips 10 included in the semiconductor device 100 during operation of the semiconductor device 100 is kept below a predetermined value.

[0026] Specifically, if the results of the light emission inspection show that there is a large variation in the characteristics of the multiple semiconductor chips 10, the semiconductor device 100 including the multiple semiconductor chips 10 may be discarded. This prevents current from concentrating on a specific semiconductor chip 10 during operation of the semiconductor device 100. Therefore, the risk of the semiconductor device 100 failing before its expected product lifespan can be reduced, and a highly reliable semiconductor device 100 can be manufactured. Alternatively, for example, if the wire bonds and chip bonding material can be cleanly removed, a semiconductor device 100 with large variations may be disassembled and reassembled to reduce the variations.

[0027] 9 is a flowchart showing a manufacturing method of a semiconductor device 100 according to a third embodiment. This embodiment differs from the first embodiment in that the light emission inspection process is performed on a semi-finished product. In this embodiment, first, a die bonding process is performed in which the semiconductor chip 10 is mounted on the insulating substrate 32 (S11).

[0028] 10A is a plan view illustrating the die bonding process according to embodiment 3. FIG. 10B is a side view illustrating the die bonding process according to embodiment 3. Insulating substrate 32 has front electrode pattern 32a as a circuit pattern on its upper surface. Insulating substrate 32 also has back electrode pattern 32b on its back surface. In the die bonding process, multiple semiconductor chips 10 are bonded to front electrode pattern 32a of insulating substrate 32 with bonding material 31.

[0029] Next, a wire bonding step (S12) is carried out, thereby producing a semi-finished product. Fig. 11 is a plan view of the semi-finished product according to the third embodiment. In the wire bonding step, electrodes on the upper surfaces of the plurality of semiconductor chips 10 are electrically connected to the surface electrode patterns 32a by wires 35.

[0030] Next, an optical emission inspection step is carried out (S13). Fig. 12 is a diagram illustrating the optical emission inspection step according to the third embodiment. In this embodiment, a voltage is applied to the semiconductor chip 10 via the circuit pattern of the insulating substrate 32, and light L1 emitted from the pn junction 20 is detected. The method of applying a voltage to the semiconductor chip 10 and the method of detecting light L1 are the same as those in the first embodiment.

[0031] The subsequent steps are the same as those of the first embodiment, except that the light emission inspection step is not performed after the electrode bonding step (S4). In this manner, in the present embodiment, after the light emission inspection step, the semiconductor chip 10 is electrically connected to the electrodes 36 for supplying electricity to the semiconductor chip 10 from outside the semiconductor device 100.

[0032] A semiconductor device 100 that handles high voltages and large currents may be equipped with multiple insulating substrates 32. In this case, a component may be manufactured in which a semiconductor chip 10 is bonded to an insulating substrate 32. This component is called a semi-finished product. For example, the semiconductor device shown in FIG. 8 has two semi-finished products mounted thereon. The light emission inspection process can also be performed on semi-finished products. In this manner, screening may be performed in a process upstream of that in the first embodiment. This can improve the manufacturing efficiency of the semiconductor device 100. For example, if disposal or reassembly is performed depending on the screening results, screening in an upstream process eliminates the need to discard or reassemble the finished product, allowing for more efficient manufacturing.

[0033] The technical features described in each embodiment may be used in appropriate combination.

[0034] 10 Semiconductor chip, 12 Substrate, 14 Source electrode, 16 Drain electrode, 17 Insulating layer, 18 Gate electrode, 20 pn junction, 30 Base plate, 31 Bonding material, 32 Insulating substrate, 32a Surface electrode pattern, 32b Back electrode pattern, 33 Electrode mounting substrate, 34, 35 Wire, 36 Electrode, 38 Case, 50 Power supply, 52 Light receiving device, 100 Semiconductor device

Claims

1. A forward voltage is applied to a pn junction of a semiconductor chip, light emitted from the pn junction is detected, and a magnitude of a main current of the semiconductor chip is detected from an intensity of the detected light, wherein the method is for manufacturing a semiconductor device.

2. A plurality of the semiconductor chips are connected in parallel, and the light is detected in a state where the plurality of semiconductor chips are connected in parallel, wherein the method is for manufacturing a semiconductor device according to claim 1.

3. The light is detected in a state where the plurality of semiconductor chips are connected in parallel, in a similar usage state as that of the semiconductor device including the plurality of semiconductor chips, wherein the method is for manufacturing a semiconductor device according to claim 2.

4. Screening is performed so that a variation in a main current flowing through the plurality of semiconductor chips during operation of the semiconductor device becomes equal to or less than a predetermined value according to an intensity of the detected light, wherein the method is for manufacturing a semiconductor device according to claim 2 or 3.

5. After electrically connecting the semiconductor chip and an electrode for energizing the semiconductor chip from outside the semiconductor device, a voltage is applied to the semiconductor chip via the electrode, and the light is detected, wherein the method is for manufacturing a semiconductor device according to any one of claims 1 to 3.

6. The semiconductor chip is mounted on an insulating substrate, a voltage is applied to the semiconductor chip via a circuit pattern of the insulating substrate to detect the light, and after detecting the light, the semiconductor chip and an electrode for energizing the semiconductor chip from outside the semiconductor device are electrically connected, wherein the method is for manufacturing a semiconductor device according to any one of claims 1 to 3.

7. The semiconductor chip is a MOSFET, and the pn junction is a body diode, wherein the method is for manufacturing a semiconductor device according to any one of claims 1 to 3.

8. The semiconductor chip is formed of a wide bandgap semiconductor, wherein the method is for manufacturing a semiconductor device according to any one of claims 1 to 3.

9. The wide bandgap semiconductor is silicon carbide, a gallium nitride-based material, or diamond, wherein the method is for manufacturing a semiconductor device according to claim 8.