Semiconductor device

Abstract

Provided is a highly reliable semiconductor device. In this semiconductor device, a plurality of semiconductor elements are electrically connected. The semiconductor elements each have a bonding region in which a bonding contact that bonds semiconductor elements to each other and electrically connects the semiconductor elements to each other and a dummy bonding contact that bonds semiconductor elements to each other to non-conductively connect the semiconductor elements to each other are arranged. The dummy bonding contact is continuously provided along the outer periphery of the bonding region of each semiconductor element. The semiconductor elements are arranged in such a manner that the bonding regions thereof face each other, and the bonding contacts are bonded with each other, and the dummy bonding contacts are bonded with each other.

Description

semiconductor devices

[0001] The present invention relates to a semiconductor device in which a plurality of semiconductor elements are stacked and electrically connected, and in particular to a semiconductor device that bonds semiconductor elements having bonding contacts that electrically connect the semiconductor elements to each other and dummy bonding contacts that do not electrically connect the semiconductor elements to each other.

[0002] Currently, various connection forms have been proposed for connecting semiconductor elements to each other, or between a semiconductor element and a substrate, etc., such as wafer-on-wafer, chip-on-wafer, or chip-on-chip. Hybrid bonding is a method for joining semiconductor elements to each other, or between a semiconductor element and a substrate, etc.

[0003] For example, U.S. Patent Publication No. 2005 / 0129999 and U.S. Patent Publication No. 2005 / 0129999 describe hybrid-bonded semiconductor devices. The semiconductor device of U.S. Patent Publication No. 2005 / 0129999 includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between a first bonding layer and a second bonding layer. The first semiconductor structure includes a first interconnect layer including first interconnect portions, and a first bonding layer including first bonding contacts. At least one first interconnect portion is a first dummy interconnect portion. Each first interconnect portion is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnect portions, and a second bonding layer including second bonding contacts. At least one second interconnect portion is a second dummy interconnect portion. Each second interconnect portion is in contact with a respective second bonding contact. Each first bonding contact is in contact with a respective second bonding contact at the bonding interface.

[0004] The semiconductor device of Patent Document 2 includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between a first bonding layer and a second bonding layer. In the first semiconductor structure, each first interconnect is in contact with a respective first bonding contact. In the second semiconductor structure, at least one second bonding contact is in contact with each second interconnect. At least one other second bonding contact is separated from the second interconnect. Each first bonding contact is in contact with one of the second bonding contacts at the bonding interface.

[0005] JP 2022-511451 A JP 2022-509249 A

[0006] Because chip-on-wafer and chip-on-chip structures are difficult to clean after singulation, it is more difficult to reduce the number of particles and other foreign particles of a few nanometers that cause bonding defects compared to wafer-on-wafer structures. This increases the likelihood that particles and other foreign particles will cause bonding defects at the bonding surface of the semiconductor device, and also increases the likelihood that oxygen, moisture, and other foreign particles will penetrate through the bonding surface. This makes it difficult to ensure the reliability of the semiconductor device. The above-mentioned Patent Documents 1 and 2 include the bonding interface between the first bonding layer and the second bonding layer, i.e., the bonding surface. Therefore, even in the semiconductor devices of Patent Documents 1 and 2, it is difficult to ensure reliability due to particles and other foreign particles, as described above.

[0007] An object of the present invention is to provide a highly reliable semiconductor device.

[0008] In order to achieve the above-mentioned object, invention [1] is a semiconductor device in which a plurality of semiconductor elements are stacked and electrically connected, the semiconductor elements have bonding regions in which bonding contacts that bond the semiconductor elements together and electrically connect the semiconductor elements together, and dummy bonding contacts that bond the semiconductor elements together and connect the semiconductor elements together in a non-conductive manner are arranged, the dummy bonding contacts are provided continuously along the periphery of the bonding regions of the semiconductor elements, and the semiconductor elements are bonded to each other with their bonding regions facing each other, and the dummy bonding contacts are bonded to each other.

[0009] Invention [2] is the semiconductor device according to Invention [1], in which the bonding contacts of the multiple semiconductor elements are directly bonded to each other and the dummy bonding contacts are directly bonded to each other with their bonding regions facing each other. Invention [3] is the semiconductor device according to Invention [1], in which an anisotropically conductive member having conductivity in the stacking direction of the semiconductor elements is disposed between the bonding regions of the multiple semiconductor elements, electrically connecting the bonding contacts to each other and electrically connecting the dummy bonding contacts to each other. Invention [4] is the semiconductor device according to Invention [3], in which the anisotropically conductive member has an electrically insulating base material and a plurality of conductive paths that penetrate the insulating base material in the thickness direction and are electrically insulated from each other.

[0010] Invention [5] is the semiconductor device according to any one of Inventions [1] to [4], in which the Vickers hardness of the dummy bonding contact is 1 / 10 or less of the Vickers hardness of the region other than the bonding and dummy bonding contact in the bonding region. Invention [6] is the semiconductor device according to any one of Inventions [1] to [5], in which the dummy bonding contact is made of aluminum or copper, or an alloy containing aluminum or copper.

[0011] According to the present invention, a highly reliable semiconductor device can be provided.

[0012] FIG. 1 is a schematic perspective view showing an example of a semiconductor element used in a semiconductor device according to an embodiment of the present invention; FIG. 2 is a schematic cross-sectional view showing a first example of a semiconductor device according to an embodiment of the present invention; FIG. 3 is a schematic cross-sectional view showing an example of a method for manufacturing the first example of a semiconductor device according to an embodiment of the present invention; FIG. 4 is a schematic cross-sectional view showing a second example of a semiconductor device according to an embodiment of the present invention; FIG. 5 is a schematic cross-sectional view showing an example of a method for manufacturing the second example of a semiconductor device according to an embodiment of the present invention; FIG. 6 is a schematic cross-sectional view showing an example of an anisotropically conductive member of the second example of a semiconductor device according to an embodiment of the present invention; and FIG. 7 is a schematic plan view showing an example of an anisotropically conductive member of the second example of a semiconductor device according to an embodiment of the present invention.

[0013] The semiconductor device of the present invention will be described in detail below based on preferred embodiments shown in the accompanying drawings. Note that the drawings described below are merely illustrative for explaining the present invention, and the present invention is not limited to the drawings shown below. Note that in the following, the term "to" indicating a range of values ​​includes the values ​​written on both sides. For example, when ε is a value ε α ~Number ε β That is, the range of ε is the number ε α and the number ε β The range includes ε α ≦ε≦ε β Unless otherwise specified, the term "parallel" includes a generally accepted error range in the relevant technical field. Unless otherwise specified, the term "same" also includes a generally accepted error range in the relevant technical field.

[0014] [First Example of Semiconductor Device] FIG. 1 is a schematic perspective view showing an example of a semiconductor element used in a semiconductor device according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view showing a first example of a semiconductor device according to an embodiment of the present invention. Note that, although two semiconductor elements 12 are shown in FIG. 1, one of the two semiconductor elements 12 is shown imaginarily. In FIG. 2, the same components as those in the semiconductor element 12 shown in FIG. 1 are given the same reference numerals, and detailed descriptions thereof will be omitted. The semiconductor element 12 shown in FIG. 1 constitutes a semiconductor device in which a plurality of semiconductor elements are stacked and electrically connected. As described above, FIG. 1 shows two semiconductor elements 12.

[0015] The semiconductor element 12 has, for example, a rectangular outer shape in a plan view and a flat surface 12a. The flat surface 12a also has a rectangular outer shape in a plan view. The semiconductor element 12 has a bonding region Aj on the flat surface 12a. The bonding region Aj has, for example, a rectangular outer shape in a plan view. The outer shape of the bonding region Aj is similar to the outer shape of the flat surface 12a. The bonding region Aj is provided with bonding contacts 20 that bond the semiconductor elements 12 together and electrically connect the semiconductor elements 12 together, and dummy bonding contacts 22 that bond the semiconductor elements 12 together and connect the semiconductor elements 12 together in a non-conductive manner. In the semiconductor element 12 before bonding, the surfaces of the bonding contacts 20 and the dummy bonding contacts 22 do not protrude beyond the flat surface 12a and are flush with the flat surface 12a. The dummy bonding contacts 22 are provided continuously along the outer periphery of the bonding region Aj of the semiconductor element 12. More specifically, the dummy bonding contacts 22 are strip-shaped in plan view and are provided continuously and uninterruptedly in a ring shape along the outer periphery. For example, the outer and inner shapes of the dummy bonding contacts 22 are quadrangular in plan view. The outer and inner shapes of the dummy bonding contacts 22 are similar shapes.

[0016] The bonding contacts 20 are arranged in an area Ad surrounded by the dummy bonding contacts 22. The area Ad has a rectangular outer shape in a plan view. The bonding contacts 20 are conductive and electrically connect the semiconductor elements 12. The bonding contacts 20 enable the exchange of electrical signals between the semiconductor elements 12. The bonding contacts 20 correspond to electrodes or terminals. For example, the bonding contacts 20 have a circular outer shape in a plan view, but this is not limited thereto and may also be a rectangular shape. The dummy bonding contacts 22 are conductive and connect the semiconductor elements 12 to each other in a non-conductive manner. In other words, the dummy bonding contacts 22 join the semiconductor elements 12 to each other but do not electrically connect them. The dummy bonding contacts 22 do not contribute to the exchange of electrical signals between the semiconductor elements 12. The dummy bonding contacts 22 bond together to seal the periphery of the bonding contacts 20 of the semiconductor device 10, isolating and protecting the bonding contacts 20 from the outside. The dummy bonding contacts 22 can prevent oxygen, moisture, and the like from penetrating the bonding contacts 20, thereby increasing the reliability of the semiconductor device 10. Furthermore, the dummy bonding contacts 22 increase the bonding surface, thereby maintaining the bonding strength of the semiconductor device 10.

[0017] As described above, the bonding contacts 20 and dummy bonding contacts 22 are arranged in the bonding region Aj. When the semiconductor device 10 is composed of two semiconductor elements 12, the two semiconductor elements 12 are bonded together with their bonding contacts 20 and dummy bonding contacts 22 bonded together with their flat surfaces 12a facing each other and their bonding regions Aj facing each other. This results in a highly reliable semiconductor device. Note that as long as the bonding regions Aj are the same in size and shape, the semiconductor elements 12 can be bonded together even if the flat surfaces 12a of the semiconductor elements 12 are different in size, and a semiconductor device can be obtained.

[0018] The semiconductor device 10 will be described in more detail. The semiconductor device 10 shown in FIG. 2 is composed of two semiconductor elements. The semiconductor device 10 is, for example, a first semiconductor element 13 and a second semiconductor element 14 that are stacked in a stacking direction Ds, bonded, and electrically connected. For example, the first semiconductor element 13 and the second semiconductor element 14 have different sizes in a plan view, with the first semiconductor element 13 being larger than the second semiconductor element 14.

[0019] Similar to the semiconductor element 12 shown in FIG. 1 , the first semiconductor element 13 has, for example, a rectangular outer shape in a plan view, a flat surface 13a, and a bonding region (not shown) on the flat surface 13a. The flat surface 13a and the bonding region both have rectangular outer shapes in a plan view. Bonding contacts 20 and dummy bonding contacts 22 are arranged in the bonding region. The first semiconductor element 13 has a first insulating layer 23. The surface 23a of the first insulating layer 23 is the flat surface 13a of the first semiconductor element 13. The above-mentioned bonding contacts 20 and dummy bonding contacts 22 are provided on the first insulating layer 23. The surfaces of the bonding contacts 20 and the dummy bonding contacts 22 do not protrude beyond the surface 23a of the first insulating layer 23, but are flush with the surface 23a of the first insulating layer 23.

[0020] In FIG. 2 , a second insulating layer 24 is provided as a lower layer on the side of the first insulating layer 23 opposite the flat surface 13a of the first semiconductor element 13. A conductive connection portion 25 is provided on the second insulating layer 24 in contact with the lower surface 20b of the bonding contact 20. The connection portion 25 is electrically connected to the bonding contact 20. Note that no connection portion 25 is provided for the dummy bonding contact 22. A third insulating layer 26 is provided as a lower layer on the side of the second insulating layer 24 opposite the flat surface 13a of the first semiconductor element 13. A wiring layer 27 is provided on the third insulating layer 26. The wiring layer 27 is composed of a plurality of wirings 27a. Of the wirings 27a, the wirings 27a arranged below the connection portions 25 are electrically connected to the connection portions 25.

[0021] A fourth insulating layer 28 is provided as a lower layer on the side of the third insulating layer 26 opposite the flat surface 13a of the first semiconductor element 13. A through electrode 29 is provided in the fourth insulating layer 28. The through electrode 29 is provided in contact with a wiring 27a electrically connected to the bonding contact 20. The through electrode 29 is electrically connected to the wiring 27a. The first insulating layer 23, the second insulating layer 24, the third insulating layer 26, and the fourth insulating layer 28 described above all have electrical insulating properties and are made of, for example, silicon, silicon oxide, silicon nitride, silicon oxynitride, a low-dielectric-constant dielectric, or any combination thereof.

[0022] Similar to the semiconductor element 12 shown in FIG. 1 , the second semiconductor element 14 has, for example, a rectangular outer shape in a plan view, a flat surface 14a, and a bonding region (not shown) on the flat surface 14a. Both the flat surface 14a and the bonding region have rectangular outer shapes in a plan view. Bonding contacts 20 and dummy bonding contacts 22 are arranged in the bonding region. The second semiconductor element 14 has a first insulating layer 30. The surface 30a of the first insulating layer 30 is the flat surface 14a of the second semiconductor element 14. The above-mentioned bonding contacts 20 and dummy bonding contacts 22 are provided on the first insulating layer 30. The surfaces of the bonding contacts 20 and the dummy bonding contacts 22 do not protrude beyond the surface of the first insulating layer 30, but are flush with the surface 30a of the first insulating layer 30.

[0023] In FIG. 2 , a second insulating layer 31 is provided as an upper layer on the side of the first insulating layer 30 opposite the flat surface 14a of the second semiconductor element 14. A conductive connection portion 32 is provided on the second insulating layer 31 in contact with the lower surface 20b of the bonding contact 20. The connection portion 32 is electrically connected to the bonding contact 20. Note that no connection portion 32 is provided for the dummy bonding contact 22. A third insulating layer 33 is provided as an upper layer on the side of the second insulating layer 31 opposite the flat surface 14a of the second semiconductor element 14. A wiring layer 34 is provided on the third insulating layer 33. The wiring layer 34 is composed of a plurality of wirings 34a. Of the wirings 34a, the wirings 34a arranged above the connection portions 32 are electrically connected to the connection portions 32.

[0024] A fourth insulating layer 35 is provided as an upper layer on the third insulating layer 33, opposite the flat surface 14a of the second semiconductor element 14. A through electrode 36 is provided in the fourth insulating layer 35. The through electrode 36 is provided in contact with the wiring 34a electrically connected to the bonding contact 20. The through electrode 36 is electrically connected to the wiring 34a. A fifth insulating layer 37 is provided as an upper layer on the fourth insulating layer 35, opposite the flat surface 14a of the second semiconductor element 14. A wiring layer 38 is provided on the fifth insulating layer 37. The wiring layer 38 is composed of a plurality of wirings 38a. Of the wirings 38a, the wiring 38a arranged above the through electrode 36 is electrically connected to the through electrode 36. A sixth insulating layer 39 is provided as an upper layer on the fifth insulating layer 37, opposite the flat surface 14a of the second semiconductor element 14. A conductive connection portion 40 is provided on the sixth insulating layer 39 so as to contact the upper surface 38b of the wiring 38a electrically connected to the through electrode 36. The connection portion 40 is electrically connected to the wiring 38a.

[0025] A seventh insulating layer 41 is provided as an upper layer on the opposite side of the sixth insulating layer 39 from the flat surface 14a of the second semiconductor element 14. The above-mentioned bonding contacts 20 and dummy bonding contacts 22 are provided on the seventh insulating layer 41. The bonding contacts 20 are provided in contact with the upper surface 40a of the connecting portion 40. The bonding contacts 20 are electrically connected to the connecting portion 40. Note that no connecting portion 40 is provided for the dummy bonding contacts 22. The above-mentioned first insulating layer 30, second insulating layer 31, third insulating layer 33, fourth insulating layer 35, fifth insulating layer 37, sixth insulating layer 39, and seventh insulating layer 41 all have electrical insulating properties and are made of, for example, silicon, silicon oxide, silicon nitride, silicon oxynitride, low-dielectric-constant dielectrics, or any combination thereof. The fourth insulating layer 28 provided with the through electrode 29 and the fourth insulating layer 35 provided with the through electrode 36 each have a structure similar to a TSV (Through Silicon Via), and can be made of silicon.

[0026] In the first semiconductor element 13 and the second semiconductor element 14, the bonding contact 20, dummy bonding contact 22, connecting portions 25, 32, 40, wiring layers 27, 34, 38, and through electrodes 29, 36 are all conductive and made of, for example, tungsten, cobalt, copper, aluminum, silicide, or a combination thereof. Materials used for terminals or electrode pads in the semiconductor element field can also be used as appropriate. The dummy bonding contact 22 is preferably made of a metal or alloy that is more easily deformed during bonding than semiconductors, oxides, and nitrides, and is more preferably made of aluminum or copper, or an alloy containing aluminum or copper.

[0027] In the semiconductor device 10, the first semiconductor element 13 and the second semiconductor element 14 are electrically connected by directly bonding their bonding contacts 20. This establishes electrical continuity between the bonding contacts 20, connection portions 40, wiring layer 38, through electrodes 36, wiring layer 34, and connection portions 32 of the second semiconductor element 14 and the bonding contacts 20, connection portions 25, wiring layer 27, and through electrodes 29 of the first semiconductor element 13, allowing electrical signals to be exchanged between the first semiconductor element 13 and the second semiconductor element 14.

[0028] In a semiconductor device, the Vickers hardness of the dummy bonding contacts 22 of the semiconductor element 12 (see FIG. 1) is preferably 1 / 10 or less of the Vickers hardness of the region As (see FIG. 1) other than the bonding contacts 20 (see FIG. 1) and dummy bonding contacts 22 (see FIG. 1) in the bonding region Aj (see FIG. 1). In this case, because the dummy bonding contacts 22 are softer than the region As, even if particles or other foreign matter are present, they are sandwiched between the dummy bonding contacts 22 without any gaps and bonded. This ensures that the periphery of the bonding contacts 20 of the semiconductor device 10 is sealed reliably even if particles or other foreign matter are present, thereby suppressing bonding obstruction at the bonding surface Bc of the semiconductor device 10. This further increases the reliability of the semiconductor device 10. The above-mentioned region As corresponds to the plane 14a of the first semiconductor element 13, i.e., the surface 23a of the first insulating layer 23, and corresponds to the plane 14a of the second semiconductor element 14, i.e., the surface 30a of the first insulating layer 30. The Vickers hardness of single crystal Si is 10.6 GPa, and that of SiO ２ The Vickers hardness of copper (Cu) is 9.7 GPa, that of copper (Cu) is 0.80 GPa, and that of aluminum (Al) is 0.50 GPa. The Vickers hardness is measured based on JIS (Japanese Industrial Standards) Z 2255:2003.

[0029] In the semiconductor device 10, the interface between the flat surface 13a of the first semiconductor element 13 and the flat surface 14a of the second semiconductor element 14 is the bonding surface Bc. At the bonding surface Bc, the bonding contacts 20 are directly bonded to each other, and the dummy bonding contacts 22 are directly bonded to each other. As described above, the dummy bonding contacts 22 are arranged surrounding the bonding contacts 20. Therefore, the dummy bonding contacts 22 prevent oxygen, moisture, and the like from penetrating the bonding contacts 20. This results in a highly reliable semiconductor device 10. Here, direct bonding means bonding without using an intermediate layer such as solder or adhesive.

[0030] Although the semiconductor device 10 has a stacked configuration of two semiconductor elements, the first semiconductor element 13 and the second semiconductor element 14, the number of semiconductor elements may be any number and is not limited to two. Furthermore, in the semiconductor device 10, a semiconductor element (not shown) having the above-described bonding contacts 20 and dummy bonding contacts 22 may be stacked on the surface 41a of the seventh insulating layer 41 opposite the flat surface 14a of the second semiconductor element 14. In this case, the number of stacked semiconductor elements is not particularly limited. The second semiconductor element 14 shown in FIG. 2 has a layer structure symmetrical with respect to the fourth insulating layer 35 in the stacking direction Ds. The second semiconductor element 14 has the above-described bonding contacts 20 and dummy bonding contacts 22 arranged on the flat surface 14a and the surface 41a of the seventh insulating layer 41. Therefore, a plurality of second semiconductor elements 14 can be stacked in the stacking direction, with the bonding contacts 20 electrically connected to each other and the dummy bonding contacts 22 electrically connected to each other, thereby stacking a plurality of second semiconductor elements 14. In this case, if the second semiconductor elements 14 are memories, this becomes a memory stack. Note that there is no particular limit to the number of stacked second semiconductor elements 14. Note that both the first semiconductor element 13 and the second semiconductor element 14 described above can be manufactured by a known manufacturing method used to manufacture semiconductor elements.

[0031] [First Example of Manufacturing Method of Semiconductor Device] Fig. 3 is a schematic cross-sectional view showing an example of a first example of a manufacturing method of a semiconductor device according to an embodiment of the present invention. In Fig. 3, the same components as those of the first semiconductor element 13 and the second semiconductor element 14 shown in Fig. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0032] 3, the flat surface 13a of the first semiconductor element 13 and the flat surface 14a of the second semiconductor element 14 are placed opposite each other with their bonding regions facing each other. In this case, the first semiconductor element 13 and the second semiconductor element 14 are aligned so that the bonding contacts 20 and dummy bonding contacts 22 of the first semiconductor element 13 face the bonding contacts 20 and dummy bonding contacts 22 of the second semiconductor element 14. In this state, the flat surface 13a of the first semiconductor element 13 and the flat surface 14a of the second semiconductor element 14 are brought into contact with each other, so that the bonding contacts 20 are directly bonded to each other and the dummy bonding contacts 22 are directly bonded to each other.

[0033] The method for bonding semiconductor elements together is not particularly limited, and for example, a bonding method used for hybrid bonding can be used. Furthermore, examples of bonding methods that can be used include DBI (Direct Bond Interconnect) and SAB (Surface Activated Bond). The DBI technique involves stacking a silicon oxide film on a semiconductor element and performing chemical mechanical polishing. The silicon oxide film interface is then activated by plasma treatment, and the semiconductor elements are brought into contact with each other to bond them together. The SAB technique involves surface-treating and activating each bonding surface of the semiconductor element in a vacuum. In this state, the semiconductor elements are brought into contact with each other in a room-temperature environment to bond them together. Ion irradiation of an inert gas such as argon, or neutral atom beam irradiation, is used for the surface treatment. In addition, a conductive relay material such as solder may be provided between the bonding contacts 20 and dummy bonding contacts 22 of the first semiconductor element 13 and the bonding contacts 20 and dummy bonding contacts 22 of the second semiconductor element 14, and the first semiconductor element 13 and the second semiconductor element 14 may be joined to form a semiconductor device.

[0034] [Second Example of Semiconductor Device] Figure 4 is a schematic cross-sectional view showing a second example of a semiconductor device according to an embodiment of the present invention. In Figure 4, components identical to those of the first semiconductor element 13 and the second semiconductor element 14 shown in Figure 2 are designated by the same reference numerals, and detailed descriptions thereof will be omitted. The semiconductor device 10a shown in Figure 4 differs from the semiconductor device 10 shown in Figure 2 in that an anisotropically conductive member 16 having conductivity in the stacking direction Ds of the semiconductor elements is disposed between the bonding regions of multiple semiconductor elements. The bonding surface Bc of the semiconductor device 10a is the interface between the flat surface 13a of the first semiconductor element 13 and the back surface 16b of the anisotropically conductive member 16, and is the interface between the flat surface 14a of the second semiconductor element 14 and the front surface 16a of the anisotropically conductive member 16. Other configurations are the same as those of the semiconductor device 10 shown in Figure 2.

[0035] 4 is disposed such that the flat surface 13a of the first semiconductor element 13 faces the back surface 16b of the anisotropically conductive member 16, and the flat surface 14a of the second semiconductor element 14 faces the front surface 16a of the anisotropically conductive member 16. In the semiconductor device 10a, the bonding contacts 20 are electrically connected to each other by the anisotropically conductive member 16, and the dummy bonding contacts 22 are electrically connected to each other. In this manner, in the semiconductor device 10a, the bonding contacts 20 and the dummy bonding contacts 22 are not directly bonded to each other.

[0036] In the semiconductor device 10a, the first semiconductor element 13 and the second semiconductor element 14 are electrically connected by bonding contacts 20 bonded to each other via an anisotropic conductive member 16. This establishes electrical continuity between the bonding contacts 20, connection portions 40, wiring layer 38, through electrodes 36, wiring layer 34, and connection portions 32 of the second semiconductor element 14 and the bonding contacts 20, connection portions 25, wiring layer 27, and through electrodes 29 of the first semiconductor element 13, allowing electrical signals to be exchanged between the first semiconductor element 13 and the second semiconductor element 14. In the semiconductor device 10a, as in the semiconductor device 10 shown in FIG. 2, the dummy bonding contacts 22 are arranged surrounding the bonding contacts 20. This prevents oxygen, moisture, and the like from penetrating the bonding contacts 20. This results in a highly reliable semiconductor device 10a.

[0037] The semiconductor device 10a has a configuration in which two semiconductor elements, a first semiconductor element 13 and a second semiconductor element 14, are stacked, similarly to the semiconductor device 10 shown in FIG. 2 . However, the number of semiconductor elements may be any number and is not limited to two. Furthermore, in the semiconductor device 10a, similarly to the semiconductor device 10 shown in FIG. 2 , a semiconductor element (not shown) having the above-described bonding contacts 20 and dummy bonding contacts 22 may be stacked on the surface 41a of the seventh insulating layer 41 of the second semiconductor element 14 via the anisotropic conductive member 16. In this case, the number of layers is not particularly limited. Furthermore, when bonding a semiconductor element to the surface 41a of the seventh insulating layer 41 of the second semiconductor element 14, the second semiconductor element 14 and the semiconductor element may be linearly bonded without providing the anisotropic conductive member 16. Furthermore, in the semiconductor device 10a, multiple second semiconductor elements 14 can be stacked in the stacking direction via anisotropic conductive members 16, electrically connecting the bonding contacts 20 and electrically connecting the dummy bonding contacts 22, thereby stacking multiple second semiconductor elements 14. In this case, if the second semiconductor elements 14 are memories, this becomes a memory stack. Note that the number of stacked second semiconductor elements 14 is not particularly limited.

[0038] In both the semiconductor device 10 and the semiconductor device 10a described above, the bonding contacts 20 and the dummy bonding contacts 22 are arranged in the same layer. This allows the dummy bonding contacts 22 to be formed in the same process as the bonding contacts 20, thereby not complicating the manufacturing process of the semiconductor element. When the bonding contacts 20 and the dummy bonding contacts 22 are arranged in the same layer, they are formed in the same process, so for example, the bonding contacts 20 and the dummy bonding contacts 22 are made of the same metal or alloy. Note that forming them in the same process means forming them in a single film formation process, such as a plating process, a sputtering process, or a CVD (Chemical Vapor Deposition) process.

[0039] [Second Example Manufacturing Method of Semiconductor Device] Figure 5 is a schematic cross-sectional view showing an example of a second example manufacturing method of a semiconductor device according to an embodiment of the present invention. In Figure 5, the same components as the first semiconductor element 13, the second semiconductor element 14, and the anisotropically conductive member 16 shown in Figure 4 are designated by the same reference numerals, and detailed description thereof will be omitted. For example, as shown in Figure 5, the flat surface 13a of the first semiconductor element 13 and the flat surface 14a of the second semiconductor element 14 are arranged opposite each other, with their bonding regions facing each other. In this case, the first semiconductor element 13 and the second semiconductor element 14 are aligned so that the bonding contacts 20 and dummy bonding contacts 22 of the first semiconductor element 13 face the bonding contacts 20 and dummy bonding contacts 22 of the second semiconductor element 14.

[0040] Furthermore, an anisotropically conductive member 16 is disposed between the flat surface 13a of the first semiconductor element 13 and the flat surface 14a of the second semiconductor element 14, with the back surface 16b of the anisotropically conductive member 16 facing the flat surface 13a of the first semiconductor element 13 and the front surface 16a of the anisotropically conductive member 16 facing the flat surface 14a of the second semiconductor element 14. In this state, the flat surface 13a of the first semiconductor element 13 is brought into contact with the back surface 16b of the anisotropically conductive member 16, and the flat surface 14a of the second semiconductor element 14 is brought into contact with the front surface 16a of the anisotropically conductive member 16, thereby bonding the bonding contacts 20 together and bonding the dummy bonding contacts 22 together using the anisotropically conductive member 16. The method for bonding the semiconductor elements together is not particularly limited, and for example, a bonding method used for hybrid bonding can be used. Alternatively, the above-mentioned DBI or SAB can be used as the bonding method. In addition, a semiconductor device may be formed by providing solder between the bonding contacts 20 and dummy bonding contacts 22 of the first semiconductor element 13 and the back surface 16b of the anisotropically conductive member 16, and providing solder between the bonding contacts 20 and dummy bonding contacts 22 of the second semiconductor element 14 and the front surface 16a of the anisotropically conductive member 16, and joining the first semiconductor element 13, the anisotropically conductive member 16, and the second semiconductor element 14.

[0041] (Anisotropically Conductive Member) FIG. 6 is a schematic cross-sectional view showing an example of an anisotropically conductive member of a second example of a semiconductor device according to an embodiment of the present invention. FIG. 7 is a schematic plan view showing an example of an anisotropically conductive member of a second example of a semiconductor device according to an embodiment of the present invention. FIG. 7 is a plan view of FIG. 6 as viewed from the surface side of the anodic oxide film, showing a state without the resin layer 54. The anisotropically conductive member 16 shown in FIG. 6 is conductive in the stacking direction Ds (see FIG. 2) of the semiconductor element described above. The anisotropically conductive member 16 includes an electrically insulating insulating substrate 50, a plurality of conductive paths 52 that penetrate the insulating substrate 50 in the thickness direction Dt and are electrically insulated from each other, and a resin layer 54 that covers at least one surface of the insulating substrate 50. The anisotropically conductive member 16 is disposed between the first semiconductor element 13 and the second semiconductor element 14, with the thickness direction Dt and the stacking direction Ds parallel to each other.

[0042] The plurality of conductive paths 52 are provided in the insulating substrate 50 while being electrically insulated from one another. In this case, for example, the insulating substrate 50 has a plurality of pores 51 penetrating in the thickness direction Dt. The conductive paths 52 are provided in the plurality of pores 51. The conductive paths 52 protrude from the front surface 50a of the insulating substrate 50. Alternatively, the conductive paths 52 protrude from the back surface 50b of the insulating substrate 50. The conductive paths 52 may protrude from one surface of the insulating substrate 50 in the thickness direction Dt. In this case, it is preferable to provide a resin layer 54 on the surface of the insulating substrate 50 from which the conductive paths 52 protrude. The resin layer 54 covers the protruding portions 52a of the conductive paths 52, and the protruding portions 52a are embedded in the resin layer 54. Alternatively, the resin layer 54 covers the protruding portions 52b of the conductive paths 52, and the protruding portions 52b are embedded in the resin layer 54. The insulating substrate 50 is formed, for example, of an anodized film. The front surface 50a of the insulating substrate 50 and the back surface 50b of the insulating substrate 50 are surfaces that face each other in the thickness direction Dt of the insulating substrate 50.

[0043] The anisotropically conductive member 16 has anisotropic conductivity and is conductive in the thickness direction Dt, but has sufficiently low conductivity in a direction parallel to the surface 50a of the insulating substrate 50. As shown in FIG. 7 , the anisotropically conductive member 16 has, for example, a rectangular outer shape. The outer shape and size of the anisotropically conductive member 16 are determined appropriately according to the outer shape and size of the bonding region of the semiconductor element. For example, the anisotropically conductive member 16 is bonded without the resin layer 54, or with the resin layer 54 present but with nothing on the surface 54a.

[0044] The structure of the anisotropically conductive member will be described in more detail below. The anisotropically conductive member has a structure similar to that of the structure described in, for example, WO 2022 / 163260 and can be manufactured in a manner similar to that of the structure described above. <Insulating Substrate> The insulating substrate 50 is made of a conductor and electrically insulates a plurality of conductive paths 52 from one another. The insulating substrate 50 has electrical insulation properties. The insulating substrate 50 also has a plurality of pores 51 in which the conductive paths 52 are formed. The composition of the insulating substrate 50 will be described later. The length of the insulating substrate 50 in the thickness direction Dt, i.e., the thickness ht of the insulating substrate 50, is preferably within the range of 1 to 1000 μm, more preferably within the range of 5 to 500 μm, and even more preferably within the range of 10 to 300 μm. When the thickness ht of the insulating substrate 50 is within this range, the insulating substrate 50 is easy to handle. From the viewpoint of ease of winding, the thickness ht of the insulating substrate 50 is preferably 30 μm or less, and more preferably 5 to 20 μm.

[0045] The thickness of the insulating substrate is a value calculated as an average value of 10 measurements taken at 10 points after cutting the insulating substrate in the thickness direction Dt using a focused ion beam (FIB) and taking surface photographs (magnification: 50,000 times) of the cross section using a scanning electron microscope (SEM).

[0046] <Average Diameter of Pores> The average diameter of the pores 51 is preferably 1 μm or less, more preferably 5 to 500 nm, even more preferably 20 to 400 nm, even more preferably 40 to 200 nm, and most preferably 50 to 100 nm. When the average diameter d of the pores 51 is 1 μm or less and within the above-mentioned range, conductive paths 52 having the above-mentioned average diameter can be obtained. The average diameter of the pores 51 is measured by photographing the surface of the insulating substrate 50 from directly above using a scanning electron microscope (SEM) at a magnification of 100 to 10,000 times. At least 20 pores with a circular periphery are extracted from the captured image, and their diameters are measured to determine the opening diameter. The average of these opening diameters is calculated as the average diameter of the pores. The magnification can be appropriately selected within the above-mentioned range so as to obtain an image in which 20 or more pores can be extracted. The opening diameter is measured by measuring the maximum distance between the ends of the pore portions. In other words, since the shape of the opening of the pore is not limited to a substantially circular shape, when the opening shape is non-circular, the maximum value of the distance between the ends of the pore portion is taken as the opening diameter. Therefore, even when a pore has a shape in which two or more pores are integrated, this is considered to be a single pore, and the maximum value of the distance between the ends of the pore portion is taken as the opening diameter.

[0047] <Conductive Path> As described above, the multiple conductive paths 52 are provided in the insulating substrate 50, e.g., an anodized film, while being electrically insulated from one another. The multiple conductive paths 52 are electrically conductive. The conductive paths are made of a conductive material. The conductive material is not particularly limited, and examples thereof include metals. Specific examples of metals include gold (Au), silver (Ag), copper (Cu), aluminum (Al), magnesium (Mg), nickel (Ni), zinc (Zn), and cobalt (Co). From the viewpoint of electrical conductivity, copper, gold, aluminum, nickel, and cobalt are preferred, copper and gold are more preferred, and copper is most preferred. Metals have superior ductility and other properties compared to oxide conductors, making them more easily deformable, even when compressed during bonding. Therefore, the conductive paths are preferably made of metal. The height of the conductive paths 52 in the thickness direction Dt is preferably 10 to 300 μm, and more preferably 20 to 30 μm.

[0048] <<Shape of Conductive Paths>> The average diameter d of the conductive paths 52 is preferably 1 μm or less, more preferably 5 to 500 nm, even more preferably 20 to 400 nm, still more preferably 40 to 200 nm, and most preferably 50 to 100 nm. The density of the conductive paths 52 is 20,000 pieces / mm 2 It is preferable that the density is 2 million / mm or more. 2 More preferably, it is 10 million particles / mm or more. 2 More preferably, it is 50 million particles / mm or more. 2 It is particularly preferable that the number of particles is 100 million / mm or more. 2 Furthermore, the center-to-center distance p between adjacent conductive paths 52 is preferably 20 nm to 500 nm, more preferably 40 nm to 200 nm, and even more preferably 50 nm to 140 nm.

[0049] The average diameter of the conductive paths is determined by photographing the surface of the insulating substrate from directly above at a magnification of 100 to 10,000 times using a scanning electron microscope. At least 20 conductive paths with a circular periphery are extracted from the image, and their diameters are measured to determine the opening diameter. The average of these opening diameters is then calculated as the average diameter of the conductive paths. The magnification can be appropriately selected within the above-mentioned range so as to obtain an image that can extract at least 20 conductive paths. Furthermore, when the opening shape is non-circular, the maximum distance between the ends of the conductive path portion is taken as the opening diameter. Therefore, for example, even when two or more conductive paths are integrated, this is considered as a single conductive path, and the maximum distance between the ends of the conductive path portion is taken as the opening diameter. The average diameter d of the conductive paths 52 is the same as the average diameter of the protrusions. The center-to-center distance p of adjacent conductive paths 52 is determined by further identifying the center positions (not shown) of the identified conductive paths in the image of the insulating substrate 50 obtained as described above. The distance between the centers of adjacent conductive paths was determined at 10 locations. This average value was set as the center-to-center distance p between adjacent conductive paths 52. The center position is the center position of the region in the captured image that corresponds to conductive path 52. Note that a known image analysis method is used to calculate the center position of the region in the captured image.

[0050] <<Protrusions>> The protrusions are part of the conductive paths and are columnar. The protrusions are preferably cylindrical because this increases the contact area with the object to be joined. The average protrusion length ha of the protrusions 52a and the average length hb of the protrusions 52b are preferably 10 nm to 1000 nm, more preferably 50 nm to 500 nm. When the average protrusion length ha and the average length hb are 10 nm to 1000 nm, the adhesion between the resin layer 54 and the insulating substrate 50 is improved. The average protrusion length ha of the protrusions 52a and the average length hb of the protrusions 52b are calculated by obtaining cross-sectional images of the protrusions using a scanning electron microscope as described above, and measuring the heights of the protrusions at 10 points on the cross-sectional images.

[0051] The distance between adjacent protrusions of the conductive paths 52 is preferably 20 nm to 200 nm, and more preferably 40 nm to 100 nm. When the distance between adjacent protrusions is within the above range, the distance between the conductive paths 52 can be maintained on the front surface 50a or the back surface 50b of the insulating substrate 50 of the conductive paths 52. This prevents short circuits in the conductive paths 52 when the semiconductor device is bonded, further increasing reliability during bonding.

[0052] <<Resin Layer>> As described above, the resin layer covers at least one of the front and back surfaces of the insulating substrate and protects the insulating substrate and the conductive paths. For example, if the conductive paths have protrusions, the resin layer buries the protrusions. That is, the resin layer covers the ends of the conductive paths protruding from the insulating substrate and protects the protrusions. To achieve the above-described functions, the resin layer preferably exhibits fluidity in a temperature range of 50°C to 200°C and hardens at 200°C or higher. The resin layer is a thermoplastic layer made of, for example, a thermoplastic resin, which will be described in detail later. The average thickness hm of the resin layer 54 is preferably 10 μm or less, more preferably 5 μm or less, and even more preferably 1 μm or less. When the average thickness hm of the resin layer 54 is 10 μm or less, it can fully protect the protrusions of the conductive paths 52 and fill the periphery of the electrodes during bonding of semiconductor devices. The average thickness hm of the resin layer 54 is the average distance from the surface 50a of the insulating substrate 50 or the average distance from the back surface 50b of the insulating substrate 50. The resin layer is cut in the thickness direction Dt of the anisotropically conductive member 16, and the cut surface is observed using a scanning electron microscope. The average thickness hm of the resin layer 54 is the average value of 10 measured values ​​obtained by measuring the distance from the surface 50a of the insulating substrate 50 at 10 locations corresponding to the resin layer. The average thickness hm of the resin layer 54 is also the average value of 10 measured values ​​obtained by measuring the distance from the back surface 50b of the insulating substrate 50 at 10 locations corresponding to the resin layer.

[0053] The resin layer may have the following composition. The composition of the resin layer will be described below. For example, the resin layer contains a polymer material and may also contain an antioxidant material. Specific examples of the resin material constituting the resin layer include thermoplastic resins such as ethylene copolymers, polyamide resins, polyester resins, polyurethane resins, polyolefin resins, acrylic resins, acrylonitrile resins, and cellulose resins. Polyacrylonitrile can also be used as the resin material constituting the resin layer 54. In addition to the above-mentioned resin layers, for example, a resin layer containing a main composition including an acrylic polymer, an acrylic monomer, and a maleimide compound, as described in International Publication No. 2022 / 163260, can be used.

[0054] [Example of a Semiconductor Element] In a semiconductor element, the functions of the semiconductor element are distinguished by the operation of the semiconductor element. Examples of semiconductor functions include calculations such as a central processing unit (CPU) or a graphics processing unit (GPU), storage such as a memory, conversion such as a converter, filtering, and sensing. Furthermore, when these functions are integrated into a single chip or unit, the functions are identified in the integrated state. If the identified functions are different, the semiconductor elements are different.

[0055] The semiconductor element is not particularly limited as long as it has the above-mentioned bonding contacts 20 and dummy bonding contacts 22 . More specifically, examples of semiconductor elements include logic LSIs (Large Scale Integration), ASICs (Application Specific Integrated Circuits), FPGAs (Field Programmable Gate Arrays), ASSPs (Application Specific Standard Products), etc.), microprocessors (e.g., CPUs, GPUs, etc.), memories (e.g., DRAMs (Dynamic Random Access Memory), SRAMs (Static Random Access Memory), HMCs (Hybrid Memory Cubes), MRAMs (Magnetic RAMs), PCMs (Phase-Change Memory), ReRAMs (Resistive RAMs), FeRAMs (Ferroelectric RAMs), flash memories, etc.), LEDs (Light Emitting Diodes), power devices, analog ICs (Integrated Circuits), e.g., DC (Direct Current)-DC (Direct Current) converters, insulated gate bipolar transistors (IGBTs), MEMS (Micro Electro Mechanical Systems) such as acceleration sensors, pressure sensors, vibrators, and gyro sensors, e.g., GPS (Global Positioning System), FM (Frequency Modulation), etc. Modulation), NFC (Near field communication), RFEM (RF Expansion Module), MMIC (Monolithic Microwave Integrated Circuit), WLAN (Wireless Local Area Network), Discrete elements, BSI (Back Side Illumination), CIS (Contact Image Sensor), Camera modules, Passive devices, SAW (Surface Acoustic Wave) filters, RF (RadioExamples of such filters include RF filters (Radio Frequency Integrated Passive Devices), RFIPDs (Radio Frequency Integrated Passive Devices), and BB (Broadband).

[0056] The composition of the semiconductor constituting the semiconductor element is not particularly limited, and examples of the semiconductor composition include diamond, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide, and silicon-on-insulator (SOI).

[0057] [Semiconductor Device] As described above, a semiconductor device is a device in which multiple semiconductor elements are stacked and electrically connected. A semiconductor device is a device in which multiple semiconductor elements are assembled to perform a specific function, but also includes devices that simply transmit electrical signals. A semiconductor device may be, for example, a logic device with a two-dimensional (2D), two-and-a-half-dimensional (2.5D), or three-dimensional (3D) architecture. Furthermore, a semiconductor device may be, for example, a DRAM stack in which multiple DRAMs are stacked, or a configuration in which a DRAM stack and a logic LSI are stacked.

[0058] The semiconductor device may also have a configuration including a printed wiring board, a heat sink, etc. The semiconductor device may have digital, analog, or mixed-signal peripheral circuits in addition to the semiconductor elements described above. More specifically, the semiconductor device may have a peripheral device layer including one or more of a page buffer, a row decoder, a column decoder, a sense amplifier, a driver, a charge pump, a transistor, a diode, a resistor, or a capacitor.

[0059] Furthermore, the semiconductor device may have an element region in addition to the semiconductor element described above. The element region is a region in which various element component circuits, etc., for functioning as electronic elements are formed. The element region may include, for example, a region in which a memory circuit such as a flash memory, a logic circuit such as a microprocessor and an FPGA (field-programmable gate array), etc., is formed, and a region in which a communication module such as a wireless tag and wiring are formed. In addition to the above, a MEMS may be formed in the element region. Examples of MEMS include sensors, actuators, and antennas. Examples of sensors include various sensors for acceleration, sound, light, etc.

[0060] The present invention is basically configured as described above. Although the semiconductor device of the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and various improvements and modifications may be made without departing from the spirit and scope of the present invention.

[0061] 10, 10a Semiconductor device 12 Semiconductor element 12a, 13a, 14a Plane 13 First semiconductor element 14 Second semiconductor element 16 Anisotropically conductive member 16a, 23a, 30a, 41a, 50a, 54a Front surface 16b, 50b Back surface 20 Bonding contact 20b Lower surface 22 Dummy bonding contact 23, 30 First insulating layer 24, 31 Second insulating layer 25, 32, 40 Connection portion 26, 33 Third insulating layer 27, 34, 38 Wiring layer 27a, 34a, 38a Wiring 28, 35 Fourth insulating layer 29, 36 Through electrode 37 Fifth insulating layer 38b, 40a Upper surface 39 Sixth insulating layer 41 Seventh insulating layer 50 Insulating base material 51 Pore 52 Conductive path 52a, 52b Protrusion 54 Resin layer Ad Region Aj Bonding region As Region Bc Bonding surface Ds Stacking direction Dt Thickness direction d Average diameter hm Average thickness ht Thickness p Center-to-center distance

Claims

1. A semiconductor device in which a plurality of semiconductor elements are stacked and electrically connected, The semiconductor element is a bonding region in which bonding contacts that bond the semiconductor elements together and electrically connect the semiconductor elements together, and dummy bonding contacts that bond the semiconductor elements together and non-conductively connect the semiconductor elements together are arranged; the dummy bonding contact is provided continuously along the periphery of the bonding region of the semiconductor element, The semiconductor element has the bonding contacts bonded to each other and the dummy bonding contacts bonded to each other with the bonding regions facing each other.

2. 2. The semiconductor device according to claim 1, wherein the bonding contacts of the plurality of semiconductor elements are directly bonded to each other and the dummy bonding contacts are directly bonded to each other with the bonding regions facing each other.

3. 2. The semiconductor device of claim 1, wherein an anisotropic conductive member having conductivity in the stacking direction of the semiconductor elements is arranged between the bonding regions of the plurality of semiconductor elements, electrically connecting the bonding contacts to each other and electrically connecting the dummy bonding contacts to each other.

4. 4. The semiconductor device according to claim 3, wherein the anisotropically conductive member has an insulating base material having electrical insulation properties and a plurality of conductive paths that penetrate the insulating base material in a thickness direction and are electrically insulated from each other.

5. 5. The semiconductor device according to claim 1, wherein the Vickers hardness of the dummy bonding contact is 1 / 10 or less of the Vickers hardness of the region other than the bonding contact and the dummy bonding contact in the bonding region.

6. 5. The semiconductor device according to claim 1, wherein the dummy bonding contact is made of aluminum or copper, or an alloy containing aluminum or copper.