Semiconductor light-emitting element and method for manufacturing semiconductor light-emitting element

Abstract

This method for manufacturing a semiconductor light emitting element comprises: a growth step for growing a semiconductor laminate (1S) on a main surface of a wafer (10M); a ridge groove formation step for forming a plurality of projection sections (P1) and a plurality of ridges (R1) extending in a first direction parallel to the main surface of the wafer (10M) by forming, in the semiconductor laminate (1S), a plurality of ridge grooves (T3) extending in the first direction; a transverse groove formation step for forming, in the semiconductor laminate (1S), a plurality of transverse grooves (T1) that are deeper than the plurality of ridge grooves (T3); a cleavage step for forming a plurality of bar-shaped substrates (10Mb) by cleaving the wafer (10M) at a plurality of cleavage lines (L1) parallel to a second direction that is parallel to the main surface of the wafer (10M) and perpendicular to the first direction; and a separation step for individually dividing the plurality of bar-shaped substrates (10Mb) at a plurality of division lines (L2) parallel to the first direction.

Description

Semiconductor light emitting element and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor light emitting device and a method for manufacturing the same.

[0002] Semiconductor light-emitting elements such as semiconductor laser elements have advantages such as long life, high efficiency, and small size, and are therefore used as light sources for a variety of products such as projectors, optical discs, vehicle headlamps, lighting devices, laser processing devices, etc. In recent years, research and development has been progressing on nitride-based semiconductor light-emitting elements that can cover wavelength bands from ultraviolet to blue (see, for example, Patent Document 1).

[0003] A semiconductor light-emitting element can be produced by cleaving a semiconductor laminate substrate, which has multiple semiconductor layers stacked on a wafer, to cut out multiple bar-shaped substrates, and then dividing these bar-shaped substrates into multiple individual pieces.

[0004] Japanese Patent Application Laid-Open No. 2005-142546

[0005] However, in the cleaving step, the wafer may warp due to the difference in lattice constant between the wafer and the semiconductor layer, which may cause problems such as the wafer being cleaved at a position other than the intended cleavage position.

[0006] The present disclosure has been made to solve such problems, and has an object to provide a semiconductor light-emitting device with good cleavage properties and a method for manufacturing the same.

[0007] In order to achieve the above object, one aspect of a method for manufacturing a semiconductor light-emitting element according to the present disclosure includes a growth step of growing a semiconductor laminate on a main surface of a wafer; a ridge groove forming step of forming a plurality of ridge grooves in the semiconductor laminate extending in a first direction parallel to the main surface of the wafer, thereby forming a plurality of protrusions and a plurality of ridges extending in the first direction; a transverse groove forming step of forming a plurality of transverse grooves in the semiconductor laminate that are deeper than the plurality of ridge grooves; and a step of forming a plurality of cleavage lines parallel to the second direction, the plurality of cleavage lines being parallel to the second direction, the plurality of cleavage lines being perpendicular to the first direction. The method includes a cleaving step of forming a plurality of bar-shaped substrates by cleaving a wafer, and a singulation step of dividing the plurality of bar-shaped substrates along a plurality of parting lines parallel to the first direction, wherein the semiconductor laminate has an n-side semiconductor layer disposed above the wafer, an active layer disposed above the n-side semiconductor layer, and a p-side semiconductor layer disposed above the active layer, the plurality of ridge grooves are formed only in the p-side semiconductor layer of the semiconductor laminate, and heights of the plurality of protrusions from the main surface of the wafer are equal to heights of the plurality of ridges from the main surface of the wafer. each of the plurality of ridges is adjacent to one of the plurality of protrusions via one of the plurality of ridge grooves; each of the plurality of transverse grooves is continuously formed from a position of one of the plurality of parting lines in the second direction to a position of one of the plurality of parting lines adjacent to the one of the plurality of parting lines in the second direction; the plurality of cleavage lines include a first cleavage line, and second and third cleavage lines adjacent to the first cleavage line; the plurality of parting lines extend from the first cleavage line to the second cleavage line and are aligned in the second direction; the semiconductor laminate includes a first parting line and a second parting line which are two adjacent parting lines, and a third parting line and a fourth parting line which extend from the first cleavage line to the third cleavage line and are two adjacent parting lines in the second direction, the semiconductor laminate includes a first region surrounded by the first parting line, the second parting line, the first cleavage line, and the second cleavage line, and a second region surrounded by the third parting line, the fourth parting line, the first cleavage line, and the third cleavage line, the first region adjacent to the second region in the first direction, and the plurality of ridges include a first ridge and a second ridge,The plurality of transverse grooves include a first transverse groove intersecting the first cleavage line, the first ridge intersecting the first cleavage line and the second cleavage line and being continuously formed between the first cleavage line and the second cleavage line and at least a portion of the first ridge being disposed in the second region, the second ridge intersecting the first cleavage line and the third cleavage line and being at least a portion of the second ridge being disposed in the first region, and the first transverse groove intersecting the first cleavage line between the first ridge and the second ridge.

[0008] Another aspect of the method for manufacturing a semiconductor light-emitting element according to the present disclosure includes a growing step of growing a semiconductor laminate on a main surface of a wafer; a ridge groove forming step of forming a plurality of ridge grooves in the semiconductor laminate extending in a first direction parallel to the main surface of the wafer, thereby forming a plurality of protrusions and a plurality of ridges extending in the first direction; a transverse groove forming step of forming a plurality of transverse grooves in the semiconductor laminate that are deeper than the plurality of ridge grooves; and a step of cleaving the wafer at a plurality of cleavage lines parallel to a second direction that is parallel to the main surface of the wafer and perpendicular to the first direction. and a singulation step of dividing the plurality of bar-shaped substrates along a plurality of parting lines parallel to the first direction, wherein the semiconductor laminate has an n-side semiconductor layer disposed above the wafer, an active layer disposed above the n-side semiconductor layer, and a p-side semiconductor layer disposed above the active layer, the plurality of ridge grooves are formed only in the p-side semiconductor layer of the semiconductor laminate, the heights of the plurality of protrusions from the main surface of the wafer are equal to the heights of the plurality of ridges from the main surface of the wafer, and the plurality of each of the ridges is adjacent to one of the plurality of protruding portions via one of the plurality of ridge grooves, the plurality of cleavage lines includes a first cleavage line, and a second cleavage line and a third cleavage line adjacent to the first cleavage line, the plurality of parting lines includes a first parting line and a second parting line which extend from the first cleavage line to the second cleavage line and are two parting lines adjacent to each other in the second direction, and a third parting line and a fourth parting line which extend from the first cleavage line to the third cleavage line and are two parting lines adjacent to each other in the second direction, the body includes a first region surrounded by the first parting line, the second parting line, the first cleavage line, and the second cleavage line, and a second region surrounded by the third parting line, the fourth parting line, the first cleavage line, and the third cleavage line, the first region adjacent to the second region in the first direction, the plurality of ridges including a first ridge and a second ridge, the plurality of transverse grooves including a first transverse groove intersecting the first cleavage line, the first ridge intersecting the first cleavage line and the second cleavage line and being continuously formed between the first cleavage line and the second cleavage line, andat least a portion of the second ridge is disposed in the second region, the second ridge intersects the first cleavage line and the third cleavage line and is at least a portion of the first region, the first transverse groove intersects the first cleavage line between the first ridge and the second ridge and is disposed between the first ridge and the third cleavage line, the second ridge intersects the first cleavage line and the third cleavage line and is formed continuously between the first cleavage line and the third cleavage line, and the first transverse groove is disposed between the second ridge and the second cleavage line.

[0009] Furthermore, one aspect of the semiconductor light-emitting device according to the present disclosure includes an n-type substrate and a semiconductor laminate disposed on a major surface of the substrate, the semiconductor laminate having an n-side semiconductor layer disposed above the substrate, an active layer disposed above the n-side semiconductor layer, and a p-side semiconductor layer disposed above the active layer, the semiconductor laminate having a front end face and a rear end face disposed at one end and the other end, respectively, in a first direction parallel to the major surface of the substrate, and a first laminate side face and a second laminate side face disposed at one end and the other end, respectively, in a second direction parallel to the major surface of the substrate and perpendicular to the first direction, a ridge disposed between two adjacent ridge grooves of the plurality of ridge grooves and to which a current is supplied; a protrusion disposed adjacent to the ridge via one of the two ridge grooves; a first dummy ridge disposed between two other ridge grooves of the plurality of ridge grooves other than the two ridge grooves and to which no current is supplied; and a first transverse groove formed continuously between one of the front end face and the rear end face and a side surface of the first stack and deeper than the plurality of ridge grooves, wherein the height of the protrusion from the substrate is equal to the height of the ridge from the substrate.

[0010] According to the present disclosure, a semiconductor light emitting device with good cleavage properties and a method for manufacturing the same can be obtained.

[0011] 1 is a schematic top view showing an overall configuration of a semiconductor light emitting device according to an embodiment. FIG. 2 is a schematic cross-sectional view showing an overall configuration of a semiconductor light emitting device according to an embodiment. FIG. 3 is a schematic first cross-sectional view showing a shape of a semiconductor stack of a semiconductor light emitting device according to an embodiment. FIG. 4 is a schematic cross-sectional view showing a shape of a semiconductor stack of a semiconductor light emitting device according to an embodiment. FIG. 5 is a schematic cross-sectional view showing a shape of a semiconductor stack of a semiconductor light emitting device according to an embodiment. FIG. 6 is a schematic top view showing a wafer according to an embodiment. FIG. 7 is a schematic cross-sectional view showing a first step of a method for manufacturing a semiconductor light emitting device according to an embodiment. FIG. 8 is a schematic cross-sectional view showing a second step of a method for manufacturing a semiconductor light emitting device according to an embodiment. FIG. 9 is a schematic cross-sectional view showing a third step of a method for manufacturing a semiconductor light emitting device according to an embodiment. FIG. 10 is a schematic cross-sectional view showing a third step of a method for manufacturing a semiconductor light emitting device according to an embodiment. FIG. 11 is a top view for explaining the configuration of each groove and each ridge in a manufacturing process of a semiconductor light emitting device according to an embodiment. FIG. 12 is a schematic top view showing a fourth step of a method for manufacturing a semiconductor light emitting device according to an embodiment. FIG. 1 is a schematic cross-sectional view showing a fourth step of the method for manufacturing a semiconductor light-emitting element according to an embodiment. FIG. 2 is a schematic cross-sectional view showing a fifth step of the method for manufacturing a semiconductor light-emitting element according to an embodiment. FIG. 3 is a schematic top view showing a sixth step of the method for manufacturing a semiconductor light-emitting element according to an embodiment. FIG. 4 is a schematic cross-sectional view showing a sixth step of the method for manufacturing a semiconductor light-emitting element according to an embodiment. FIG. 5 is a schematic cross-sectional view showing a seventh step of the method for manufacturing a semiconductor light-emitting element according to an embodiment. FIG. 6 is a schematic top view showing an eighth step of the method for manufacturing a semiconductor light-emitting element according to an embodiment. FIG. 7 is a schematic top view showing a ninth step of the method for manufacturing a semiconductor light-emitting element according to an embodiment. FIG. 8 is a schematic top view showing a transverse groove and a cleavage line in a method for manufacturing a semiconductor light-emitting element of Comparative Example 1. FIG. 9 is a schematic top view showing a transverse groove and a cleavage line in a method for manufacturing a semiconductor light-emitting element of Comparative Example 2. FIG. 10 is a schematic top view of a wafer showing the configuration of a transverse groove according to Modification 1 of the embodiment. FIG. 11 is a schematic top view of a wafer showing the configuration of a transverse groove according to Modification 2 of the embodiment.FIG. 1 is a schematic top view of a wafer showing a configuration example 1 of modified example 2 of the embodiment; FIG. 2 is a schematic top view of a wafer showing a configuration example 2 of modified example 2 of the embodiment; FIG. 3 is a schematic top view of a wafer showing a configuration example 3 of modified example 2 of the embodiment; FIG. 4 is a schematic top view of a wafer showing a configuration example 4 of modified example 2 of the embodiment; FIG. 5 is a schematic top view of a wafer showing a configuration example 5 of modified example 2 of the embodiment; FIG. 6 is a schematic top view of a wafer showing a configuration of a transverse groove according to modified example 3 of the embodiment; FIG. 7 is a schematic top view of a wafer showing a configuration of a transverse groove according to modified example 4 of the embodiment; FIG. 8 is a schematic top view of a wafer showing a configuration of a transverse groove according to modified example 5 of the embodiment; FIG. 9 is a schematic top view of a wafer showing a configuration of a transverse groove according to modified example 6 of the embodiment; FIG. 10 is a schematic top view of a wafer showing a configuration of a transverse groove according to modified example 7 of the embodiment; FIG. 11 is a schematic top view of a wafer showing a configuration of an end face groove according to modified example 8 of the embodiment; FIG. 12 is a schematic top view of a wafer showing another configuration of the end face groove according to modified example 8 of the embodiment; Fig. 13 is a schematic top view of a wafer according to a modified example 10 of the embodiment. Fig. 14 is a schematic top view of a wafer according to a modified example 11 of the embodiment. Fig. 15 is a schematic top view of a wafer according to a modified example 12 of the embodiment. Fig. 16 is a schematic top view of a wafer according to a modified example 13 of the embodiment. Fig. 17 is a schematic top view of a wafer according to another configuration example of the modified example 13 of the embodiment. Fig. 18 is a schematic top view of a wafer according to a modified example 14 of the embodiment.

[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that each of the embodiments described below represents a specific example of the present disclosure. Therefore, the numerical values, shapes, materials, components, arrangement and connection of the components, steps (processes), and order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure.

[0013] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, the scales and the like do not necessarily match in each figure. In each figure, the same reference numerals are used to denote substantially the same components, and redundant explanations will be omitted or simplified.

[0014] Furthermore, in this specification, terms indicating the relationship between elements, such as "equal," terms indicating the shape of elements, such as "parallel" and "perpendicular," and numerical ranges are not expressions that only express a strict meaning, but are expressions that mean a substantially equivalent range, for example, including a difference of about a few percent.

[0015] In this specification, the terms "above" and "below" do not refer to vertically above and below in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. The terms "above" and "below" are used not only when two components are arranged with a gap between them and another component is present between them, but also when two components are arranged in contact with each other.

[0016] (Embodiment) A semiconductor light emitting device and a manufacturing method thereof according to an embodiment will be described.

[0017] [1. Overall Configuration of Semiconductor Light-Emitting Device] The overall configuration of the semiconductor light-emitting device according to this embodiment will be described with reference to FIGS. 1 to 6. FIGS. 1 and 2 are a schematic top view and a cross-sectional view, respectively, illustrating the overall configuration of the semiconductor light-emitting device 1 according to this embodiment. FIG. 2 shows a cross section taken along line II-II in FIG. 1. FIGS. 3 to 6 are schematic cross-sectional views illustrating the shape of the semiconductor laminate 1S of the semiconductor light-emitting device 1 according to this embodiment. FIGS. 3, 4, 5, and 6 show cross sections of the semiconductor laminate 1S taken along lines III-III, IV-IV, V-V, and VI-VI in FIG. 1, respectively. Note that FIGS. 3 to 6 also show a cross section of the substrate 10. Each figure also shows mutually orthogonal X-, Y-, and Z-axes. The X-, Y-, and Z-axes are in a right-handed Cartesian coordinate system. The stacking direction of the semiconductor light-emitting device 1 is parallel to the Z-axis, and the main emission direction of light (laser light) is parallel to the X-axis.

[0018] As shown in FIG. 2 , the semiconductor light-emitting device 1 according to this embodiment is an edge-emitting semiconductor light-emitting device that includes a semiconductor laminate 1S and emits light from a front end facet 1F (see FIG. 1 ) perpendicular to the stacking direction (i.e., the Z-axis direction) of the semiconductor laminate 1S. In this embodiment, the semiconductor light-emitting device 1 is a semiconductor laser device including a nitride-based semiconductor and having a front end facet 1F and a rear end facet 1R that form a resonator. The front end facet 1F is a front end face that emits laser light, and the rear end facet 1R is a rear end facet with a higher reflectivity than the front end facet 1F. The semiconductor light-emitting device 1 also has an optical waveguide formed between the front end facet 1F and the rear end facet 1R. The reflectivities of the front end facet 1F and the rear end facet 1R are not particularly limited, but are 16% and 95%, respectively, in this embodiment. The resonator length of the semiconductor light-emitting device 1 according to this embodiment (i.e., the distance between the front end facet 1F and the rear end facet 1R) is approximately 800 μm. The width (dimension in the Y-axis direction) of the semiconductor light emitting element 1 is about 150 μm.

[0019] The peak wavelength of light emitted by the semiconductor light emitting element 1 is less than 400 nm. The semiconductor light emitting element 1 emits ultraviolet light having a peak wavelength in the 375 nm band, for example. The semiconductor light emitting element 1 may also emit ultraviolet light having a peak wavelength in a band other than the 375 nm band.

[0020] As shown in FIG. 2, the semiconductor light emitting device 1 includes a substrate 10, a semiconductor laminate 1S, a current blocking layer 50, a p-side electrode 62, a pad electrode 66, and an n-side electrode .

[0021] The substrate 10 is a plate-like member made of a nitride-based semiconductor, which serves as a base for the semiconductor light-emitting device 1. The substrate 10 has main surfaces 10a and 10b. In this embodiment, the substrate 10 is disposed below the n-type cladding layer 23 and is made of n-type GaN. More specifically, the substrate 10 has an average concentration of 1.4×10 １８ cm －３ The substrate is a GaN substrate doped with Si and having a thickness of 85 μm.

[0022] The semiconductor laminate 1S has an n-side semiconductor layer 20 arranged above the substrate 10, an active layer 30 arranged above the n-side semiconductor layer 20, and a p-side semiconductor layer 40 arranged above the active layer 30. As shown in Fig. 1 , the semiconductor laminate 1S has a front end face 1F and a rear end face 1R (see Fig. 1 ) arranged at one end and the other end, respectively, in a first direction (i.e., the X-axis direction) parallel to the major surface 10a of the substrate 10, and has a first laminate side face 1Sa and a second laminate side face 1Sb arranged at one end and the other end, respectively, in a second direction (i.e., the Y-axis direction) parallel to the major surface 10a of the substrate 10 and perpendicular to the first direction.

[0023] The n-side semiconductor layer 20 is disposed above the substrate 10 and is a semiconductor layer containing an n-type semiconductor. The n-side semiconductor layer 20 is disposed between the substrate 10 and the active layer 30. The n-side semiconductor layer 20 has an underlayer 21, a buffer layer 22, an n-type cladding layer 23, and an n-side optical guide layer 24.

[0024] The underlayer 21 is an n-type semiconductor layer disposed on the major surface 10a of the substrate 10. In this embodiment, the underlayer 21 is an n-type AlGaN layer, and may have an average Al composition ratio smaller than that of the n-type cladding layer 23. In this embodiment, the underlayer 21 is an n-type AlGaN layer disposed on the major surface 10a of the substrate 10, and may have an average Al composition ratio of 1.0×10 １８ cm －３ Si-doped n-type Al with a thickness of 1000 nm ０．０２ Ga ０．９８ This is the N layer.

[0025] In the present disclosure, the average impurity concentration of each layer (i.e., average impurity concentration) refers to the value of the impurity concentration obtained by integrating the magnitude of the impurity concentration at a certain position in the stacking direction of the layer in the stacking direction from the position of the interface on the side closer to the substrate 10 in the stacking direction of the layer to the position of the interface on the side farther from the substrate 10, and dividing the result by the film thickness of the layer (the distance between the interface on the side closer to the substrate 10 and the interface on the side farther from the substrate 10). In an n-type semiconductor layer, the impurity refers to an impurity doped to obtain n-type conductivity, and in a p-type semiconductor layer, it refers to an impurity doped to obtain p-type conductivity.

[0026] In addition, in the present disclosure, the average Al composition ratio of a certain layer refers to the value of the Al composition ratio obtained by integrating the magnitude of the Al composition ratio at a certain position in the stacking direction of the layer in the stacking direction from the position of the interface closer to the substrate 10 in the stacking direction of the layer to the position of the interface farther from the substrate 10 in the stacking direction of the layer, and dividing the result by the film thickness of the layer.

[0027] The buffer layer 22 is an n-type semiconductor layer disposed between the substrate 10 and the n-type cladding layer 23. In this embodiment, the buffer layer 22 is an InGaN layer disposed on the underlayer 21. The buffer layer 22 may function as a stray light absorption layer. In other words, the buffer layer 22 may prevent light generated in the active layer 30 from reaching the substrate 10. This can reduce substrate mode light propagating through the substrate 10. In this embodiment, the buffer layer 22 has an average concentration of 1.0×10 １８ cm －３ Si-doped n-type In ０．０４ Ga ０．９６ This is the N layer.

[0028] The n-type cladding layer 23 is an n-type semiconductor layer disposed above the substrate 10. In this embodiment, the n-type cladding layer 23 is an AlGaN layer disposed on the buffer layer 22. The n-type cladding layer 23 has an average refractive index smaller than that of the active layer 30. The n-type cladding layer 23 also has an average refractive index smaller than that of the n-side optical guide layer 24. The average Al composition ratio of the n-type cladding layer 23 is larger than that of the n-side optical guide layer 24. In this embodiment, the n-type cladding layer 23 has an average concentration of 1.0×10 １８ cm －３ Si-doped n-type Al film with a thickness of 900 nm ０．０７ Ga ０．９３ This is the N layer.

[0029] Here, in the present disclosure, the average refractive index of a certain layer refers to the refractive index value obtained by integrating the magnitude of the refractive index at a certain position in the stacking direction of the layer from the position of the interface closer to the substrate 10 in the stacking direction of the layer to the position of the interface farther from the substrate 10 in the stacking direction of the layer, and dividing the result by the film thickness of the layer.

[0030] The n-side optical guide layer 24 is disposed above the n-type cladding layer 23 and is a semiconductor layer having a larger average refractive index than the n-type cladding layer 23. In this embodiment, the n-side optical guide layer 24 is an AlGaN layer disposed between the n-type cladding layer 23 and the active layer 30. The n-side optical guide layer 24 has an average concentration of 1.0×10 １８ cm －３ Si-doped n-type Al with a thickness of 130 nm ０．０３ Ga ０．９７ An N layer and an undoped Al layer with a thickness of 80 nm arranged above the N layer. ０．０３ Ga ０．９７ In the present disclosure, an undoped layer is an N layer having an impurity concentration of 1.0×10 １８ cm －３ It means a semiconductor layer that is less than

[0031] The active layer 30 is a light-emitting layer disposed between the n-side semiconductor layer 20 and the p-side semiconductor layer 40. In this embodiment, the active layer 30 includes barrier layers 31 and 33 and a well layer 32.

[0032] The barrier layers 31 and 33 are semiconductor layers disposed above the n-side optical guide layer 24 and function as barriers of the quantum well structure. In this embodiment, the barrier layer 31 is an AlGaN layer disposed between the n-side optical guide layer 24 and the well layer 32. The barrier layer 33 is an AlGaN layer disposed between the well layer 32 and the p-side semiconductor layer 40. The average band gap energy of each of the barrier layers 31 and 33 is larger than the average band gap energy of the well layer 32. In this embodiment, the barrier layer 31 is a 7-nm-thick undoped AlGaN layer. ０．０４ Ga ０．９６ The barrier layer 33 is an undoped AlN layer with a thickness of 14 nm. ０．０４ Ga ０．９６ N layer and a layer with an average density of 2.0×10 １８ cm －３ Mg-doped undoped Al film with a thickness of 3 nm ０．０４ Ga ０．９６ N layers.

[0033] Here, in the present disclosure, the average band gap energy of a certain layer refers to the value of the band gap energy obtained by integrating the magnitude of the band gap energy at a certain position in the stacking direction of the layer in the stacking direction from the interface position on the side closer to the substrate 10 in the stacking direction of the layer to the interface position on the side farther from the substrate 10 in the stacking direction of the layer, and dividing the result by the film thickness of the layer.

[0034] The well layer 32 is a semiconductor layer disposed between the barrier layer 31 and the barrier layer 33 and functions as a well of the quantum well structure. In this embodiment, the well layer 32 is an undoped In layer having a thickness of 18 nm. ０．０１ Ga ０．９９ In the present embodiment, an example is shown in which the active layer 30 has a single quantum well structure having a single well layer 32, but the active layer 30 may have a multiple quantum well structure having a plurality of well layers.

[0035] The p-side semiconductor layer 40 is disposed above the active layer 30 and is a semiconductor layer including a p-type semiconductor layer. In this embodiment, the p-side semiconductor layer 40 has an electron barrier layer 41, a first p-side optical guiding layer 42, a second p-side optical guiding layer 43, a p-type cladding layer 44, and a contact layer 45.

[0036] The electron barrier layer 41 is a p-type semiconductor layer disposed above the active layer 30. In this embodiment, the electron barrier layer 41 is an AlGaN layer disposed between the active layer 30 and the first p-side optical guide layer 42. The average band gap energy of the electron barrier layer 41 is larger than the average band gap energy of the barrier layer 33. This makes it possible to suppress leakage of electrons from the active layer 30 to the p-type cladding layer 44. The average band gap energy of the electron barrier layer 41 is larger than the average band gap energy of each of the first p-side optical guide layer 42 and the p-type cladding layer 44. The average impurity concentration of the electron barrier layer 41 is higher than the average impurity concentration of the first p-side optical guide layer 42. In this embodiment, the electron barrier layer 41 has an average concentration of 1.5×10 １９ cm －３ p-type Al doped with Mg having a thickness of 2 nm ０．３６ Ga ０．６４ This is the N layer.

[0037] The first p-side optical guiding layer 42 is a p-type semiconductor layer disposed above the active layer 30. In this embodiment, it is an AlGaN layer disposed between the electron barrier layer 41 and the second p-side optical guiding layer 43. The first p-side optical guiding layer 42 has a larger average refractive index than the p-type cladding layer 44. In this embodiment, the first p-side optical guiding layer 42 has an average concentration of 4.0×10 １８ cm －３ p-type Al doped with Mg having a thickness of 60 nm ０．０５ Ga ０．９５ The Mg doped into the first p-side light guiding layer 42 may be Mg intentionally doped during the crystal growth of the first p-side light guiding layer 42, or Mg mixed into the first p-side light guiding layer 42 that has been crystal-grown as an undoped AlGaN layer by diffusion from at least one of the electron barrier layer 41 and the p-type cladding layer 44, both of which are doped with Mg.

[0038] The second p-side light guiding layer 43 is a p-type semiconductor layer disposed above the active layer 30. In this embodiment, the second p-side light guiding layer 43 is an AlGaN layer disposed between the first p-side light guiding layer 42 and the p-type cladding layer 44. The second p-side light guiding layer 43 has a larger average refractive index than the p-type cladding layer 44. In this embodiment, the second p-side light guiding layer 43 has an average concentration of 2.0×10 １８ cm －３ p-type Al doped with Mg having a thickness of 110 nm ０．０３ Ga ０．９７ The Mg doped into the second p-side light guiding layer 43 may be Mg intentionally doped during the crystal growth of the second p-side light guiding layer 43, or Mg mixed into the second p-side light guiding layer 43 that has been crystal-grown as an undoped AlGaN layer by diffusion from at least one of the electron barrier layer 41 and the p-type cladding layer 44, both of which are doped with Mg.

[0039] The p-type cladding layer 44 is a p-type semiconductor layer disposed above the active layer 30. In this embodiment, the p-type cladding layer 44 is an AlGaN layer disposed between the second p-side optical guide layer 43 and the contact layer 45. The p-type cladding layer 44 has an average refractive index smaller than those of the active layer 30, the first p-side optical guide layer 42, and the second p-side optical guide layer 43. The average bandgap energy of the p-type cladding layer 44 is smaller than that of the electron barrier layer 41. The impurity concentration at the end of the p-type cladding layer 44 closer to the active layer 30 may be lower than the impurity concentration at the end farther from the active layer 30. This allows the impurity concentration in the p-type cladding layer 44 in a region where the light intensity is high to be reduced, thereby reducing free carrier loss of light due to impurities. In this embodiment, the p-type cladding layer 44 has an average concentration of 2.0×10 １８ cm －３ p-type Al doped with Mg having a thickness of 170 nm ０．０７ Ga ０．９３ N layers and an average density of 1.0×10 １９ cm －３ p-type Al doped with Mg having a thickness of 300 nm ０．０７ Ga ０．９３ N layers.

[0040] The p-type cladding layer 44 may have a superlattice structure. For example, the p-type cladding layer 44 may be a p-type Al 1.5 nm thick layer. ０．０９ Ga ０．９１ N layer and p-type Al with a thickness of 1.5 nm ０．０５ Ga ０．９５ In this case, Mg may be doped into each layer, or Al may be doped into each layer. ０．０９ Ga ０．９１ N layer and p-type Al ０．０５ Ga ０．９５ Only one of the N layers may be selectively doped.

[0041] The contact layer 45 is a p-type semiconductor layer disposed above the p-type cladding layer 44. In this embodiment, the contact layer 45 is a GaN layer that is in ohmic contact with the p-side electrode 62. In this embodiment, the contact layer 45 has an average concentration of 2.0×10 １９cm －３ A p-type GaN layer having a thickness of 50 nm and doped with Mg of 2.0×10 ２０ cm －３ and a 10 nm-thick p-type GaN layer doped with Mg. The contact layer 45 may be an AlGaN layer having a band gap energy equal to or lower than that of the p-type cladding layer 44. The current blocking layer 50 is disposed above the p-type cladding layer 44 and is an insulating layer that is transparent to light from the active layer 30. The current blocking layer 50 is disposed in a region of the upper surface of the semiconductor laminate 1S other than the opening 50a. The opening 50a is disposed above the ridge R1. In this embodiment, the opening 50a is disposed in a partial region above the ridge R1. In this embodiment, the current blocking layer 50 is a 300 nm-thick SiO ２ It is a layer.

[0042] The p-side electrode 62 is a conductive layer disposed above the contact layer 45. In this embodiment, the p-side electrode 62 is disposed in the opening 50a of the current blocking layer 50 and is in contact with the contact layer 45. The p-side electrode 62 is, for example, a single-layer film or a multilayer film formed of at least one of Cr, Ti, Ni, Pd, Pt, Ag, and Au. Furthermore, by using Ag, which has a low refractive index for light in the 375 nm wavelength band, for at least a portion of the p-side electrode 62, it is possible to reduce the leakage of light propagating through the optical waveguide into the p-side electrode 62, thereby reducing the waveguide loss generated in the p-side electrode 62. Ag has a refractive index of 0.5 or less in the wavelength range of 325 nm to 1500 nm and a refractive index of 0.2 or less in the wavelength range of 360 nm to 950 nm. In this case, it is possible to reduce the leakage of light into the p-side electrode 62, thereby suppressing an increase in waveguide loss while reducing the series resistance of the semiconductor light-emitting device 1. As a result, the operating voltage and operating current can be reduced. In this embodiment, the p-side electrode 62 has a Pd layer with a thickness of 40 nm and a Pt layer with a thickness of 100 nm disposed on the Pd layer.

[0043] The pad electrode 66 is a pad-shaped electrode disposed above the p-side electrode 62. In this embodiment, the pad electrode 66 is an Au layer with a film thickness of 2.0 μm. The pad electrode 66 does not need to be formed near the front end face 1F, the rear end face 1R, the first laminate body side face 1Sa, or the second laminate body side face 1Sb. In this embodiment, the pad electrode 66 is not formed in regions within 12 μm from each of the front end face 1F and the rear end face 1R, and in regions within 5 μm from each of the first laminate body side face 1Sa and the second laminate body side face 1Sb, as viewed from above. An adhesion layer may be provided between the pad electrode 66 and the current blocking layer 50 to enhance adhesion between the pad electrode 66 and the current blocking layer 50. The adhesion layer may be disposed on the p-side electrode 62. For example, the adhesion layer may include a 10 nm thick Ti layer disposed on the current blocking layer 50 and a 100 nm thick Pt layer disposed on the Ti layer.

[0044] The n-side electrode 70 is a conductive layer disposed below the major surface 10b of the substrate 10 (i.e., on the major surface 10b of the substrate 10 opposite to the major surface 10a on which the semiconductor stack 1S is disposed). The n-side electrode 70 is, for example, a single-layer film or a multilayer film formed of at least one of Cr, Ti, Ni, Pd, Pt, and Au. In this embodiment, the n-side electrode 70 has, stacked in this order from the substrate 10 side, a 10-nm-thick Ti layer, a 50-nm-thick Pt layer, and a 300-nm-thick Au film.

[0045] Next, the detailed structure of the semiconductor laminate 1S will be described.

[0046] 1 and 2, the semiconductor stack 1S has a ridge groove T3, a ridge R1, a protrusion P1, a dummy ridge R2, and a crossing groove T1. In this embodiment, the semiconductor stack 1S further has a dividing groove T2.

[0047] As shown in FIGS. 2 to 6 , the ridge groove T3 is a groove formed only in the p-side semiconductor layer 40 of the semiconductor laminate 1S and extending in the first direction. In other words, the ridge groove T3 is a groove formed in the upper surface of the semiconductor laminate 1S and extending in the first direction, and the depth of the ridge groove T3 (the dimension in the Z-axis direction) is equal to or less than the thickness of the p-side semiconductor layer 40. In this embodiment, the bottom of the ridge groove T3 is located in the first p-side light guiding layer 42. The width of the ridge groove T3 may be equal to or greater than 3 μm and equal to or less than 10 μm. In this embodiment, the width of the ridge groove T3 is approximately 7 μm.

[0048] As shown in FIG. 1 , the semiconductor laminate 1S has two ridge grooves T3 extending from the front end face 1F to the rear end face 1R, two ridge grooves T3 extending from the front end face 1F in a first direction, and two other ridge grooves T3 extending from the rear end face 1R in the first direction. The semiconductor laminate 1S also has two other ridge grooves T3 extending in a second direction. The two ridge grooves T3 extending in the first direction from the front end face 1F are connected at their ends on the rear end face 1R side by a ridge groove T3 extending in the second direction. Furthermore, the two ridge grooves T3 extending in the first direction from the rear end face 1R are connected at their ends on the front end face 1F side by a ridge groove T3 extending in the second direction. Note that, although the semiconductor laminate 1S has two ridge grooves T3 extending in the second direction in this embodiment, the semiconductor laminate 1S does not necessarily have to have two ridge grooves T3 extending in the second direction.

[0049] The ridge R1 is a convex portion disposed between two adjacent ridge grooves T3 among the multiple ridge grooves T3, and a current is supplied to the ridge R1. As shown in FIGS. 1 and 2 , an opening 50a is formed in the current blocking layer 50 above the ridge R1, and a current is supplied to the ridge R1 from the p-side electrode 62 disposed in the opening 50a. The ridge R1 is disposed between two ridge grooves T3 extending from the front end facet 1F to the rear end facet 1R. That is, the ridge R1 is formed continuously between the front end facet 1F and the rear end facet 1R. In other words, the ridge R1 extends continuously without interruption between the front end facet 1F and the rear end facet 1R.

[0050] Light is emitted from the active layer 30 located below the ridge R1. In this embodiment, the center of the ridge R1 in the second direction is located at a position that divides the width of the semiconductor light emitting element 1 in the second direction at a ratio of 3:1. In other words, the distance from the center of the ridge R1 in the second direction to the center of the semiconductor light emitting element 1 in the second direction is ¼ of the width of the semiconductor light emitting element 1 in the second direction.

[0051] The width of the ridge R1 in the second direction (i.e., the dimension in the Y-axis direction) is uniform and is 60 μm or less. In this embodiment, the width of the ridge R1 in the second direction is 15 μm.

[0052] As shown in FIG. 1 , the dummy ridge R2 is a convex portion that is arranged between two ridge grooves other than the two ridge grooves T3 adjacent to the ridge R1, among the multiple ridge grooves T3. As shown in FIG. 2 , the dummy ridge R2 is covered with a current blocking layer 50, and no current is supplied to the dummy ridge R2. In this embodiment, the semiconductor stack 1S has two dummy ridges R2, as shown in FIG. 1 . Each of the two dummy ridges R2 is arranged between the first stack side surface 1Sa and the ridge R1. One dummy ridge R2 is an example of a first dummy ridge and is arranged between the front end face 1F and the transverse groove T1, and the other dummy ridge R2 is an example of a second dummy ridge and is arranged between the rear end face 1R and the transverse groove T1. In this embodiment, the center of the dummy ridge R2 in the second direction is arranged at a position that divides the width of the semiconductor light emitting element 1 in the second direction at a ratio of 1:3. In other words, the distance from the center of the dummy ridge R2 in the second direction to the center of the semiconductor light-emitting element 1 in the second direction is ¼ of the width of the semiconductor light-emitting element 1 in the second direction. The width of the dummy ridge R2 in the second direction is equal to the width of the ridge R1 in the second direction. The length of each dummy ridge R2 in the first direction may be 25% or less of the cavity length of the semiconductor light-emitting element 1 (i.e., the distance between the front end facet 1F and the rear end facet 1R). In this embodiment, the length of each dummy ridge R2 in the first direction is approximately 150 μm. The lengths of the dummy ridges R2 located near the front end facet 1F and the dummy ridges R2 located near the rear end facet 1R may or may not be equal.

[0053] As shown in FIG. 1 , the protrusion P1 is a convex portion located adjacent to the ridge R1 with one of the two ridge grooves T3 interposed therebetween. As shown in FIGS. 2 to 6 , the height of the protrusion P1 from the substrate 10 is equal to the height of the ridge R1 from the substrate 10. In other words, the protrusion P1, like the ridge R1 (and the dummy ridge R2), is a region in which no groove is formed. This protrusion P1 distributes stress applied to the semiconductor laminate 1S, for example, when the semiconductor light-emitting element 1 is junction-down mounted on a mounting substrate or the like (i.e., when the top surface of the semiconductor laminate 1S is mounted facing the mounting substrate), between the ridge R1 (and the dummy ridge R2) and the protrusion P1. This reduces the stress applied to the ridge R1 due to mounting.

[0054] Furthermore, the width in the second direction of the protrusion P1 adjacent to the ridge R1 with the ridge groove T3 interposed therebetween may be 4 μm or more. This allows current confinement in the second direction to be effectively achieved in the ridge R1. In this embodiment, the protrusion P1 is also disposed at a position adjacent to the dummy ridge R2 with the ridge groove T3 interposed therebetween.

[0055] As shown in FIG. 1 , the transverse groove T1 is a groove continuously formed between the front end face 1F or the rear end face 1R and the first stack side surface 1Sa. The transverse groove T1 is connected to the front end face 1F or the rear end face 1R between the ridge R1 and the dummy ridge R2. As shown in FIGS. 2 to 5 , the transverse groove T1 is deeper than the ridge groove T3. The depth of the transverse groove T1 is greater than the distance from the upper surface of the semiconductor stack 1S to the upper surface of the n-type cladding layer 23. The depth of the transverse groove T1 may also be greater than the distance from the upper surface of the semiconductor stack 1S to the lower surface of the n-type cladding layer 23. In this embodiment, the bottom of the transverse groove T1 is located in the underlayer 21 of the n-side semiconductor layer 20.

[0056] As shown in FIG. 1 , the transverse groove T1 has a first portion extending in a first direction from the front end face 1F, a second portion extending in a second direction from an end of the first portion on the rear end face 1R side to the first stack side face 1Sa, a third portion extending in the first direction from the rear end face 1R, and a fourth portion extending in the second direction from an end of the third portion on the front end face 1F side to the first stack side face 1Sa. The first and second portions are examples of a first transverse groove, and the third and fourth portions are examples of a fourth transverse groove. The position of the transverse groove T1 in the second direction on the front end face 1F or the rear end face 1R may be the center of the semiconductor light emitting device 1 in the second direction. The position of the transverse groove T1 in the first direction on the first stack side face 1Sa may be a position that divides the length of the semiconductor light emitting device 1 in the first direction at a ratio of 1:3. In this specification, when the transverse groove T1 is formed in a direction intersecting the second direction up to the front end face 1F or the rear end face 1R, such as the first and third portions of the transverse groove T1, it is said that the transverse groove T1 intersects with the front end face 1F or the rear end face 1R. The transverse groove T1 is connected to the dividing groove T2 on the first stack side surface 1Sa. The width of the transverse groove T1 may be 3 μm or more and 10 μm or less. In this embodiment, the width of the transverse groove T1 is about 5 μm.

[0057] By arranging such transverse grooves T1 near the front end facet 1F and the rear end facet 1R, stress (stress due to the difference in lattice constant between the substrate 10 and the semiconductor laminate 1S) applied to the semiconductor layer separated by the transverse grooves T1 is also separated. Therefore, by arranging the transverse grooves T1 having portions extending in the second direction near the front end facet 1F and the rear end facet 1R, stress in the first direction near the front end facet 1F and the rear end facet 1R can be reduced. This improves the cleavage properties of the substrate 10 at the front end facet 1F and the rear end facet 1R. In particular, in a semiconductor light-emitting device 1 including a GaN substrate 10 and a nitride-based semiconductor laminate 1S as in the present embodiment, the Al composition ratio of each cladding layer made of AlGaN tends to increase as wavelengths become shorter, thereby increasing stress due to the difference in lattice constant between the substrate 10 and the semiconductor laminate 1S. Furthermore, this stress increases as each cladding layer made of AlGaN becomes thicker to increase the output of the semiconductor light-emitting device 1. Therefore, as wavelengths become shorter and outputs become higher, the effect of reducing stress due to the transverse groove T1 becomes more pronounced.

[0058] As shown in FIG. 1, the division grooves T2 are grooves that extend in a first direction along the first stack side surface 1Sa and the second stack side surface 1Sb. The division grooves T2 extend from the front end face 1F to the rear end face 1R. Such division grooves T2 can reduce stress in a second direction caused by the difference in lattice constant between the substrate 10 and the semiconductor stack 1S. In this embodiment, as shown in FIGS. 2 to 6, the division grooves T2 are deeper than the ridge grooves T3. The depth of the division grooves T2 is equal to the depth of the transverse grooves T1. The width of the division grooves T2 may also be equal to the width of the transverse grooves T1. In this embodiment, the width of the division grooves T2 is approximately 5 μm.

[0059] At least a part of the dividing groove T2 connected to the transverse groove T1 may also be a part of the transverse groove T1. That is, at least a part of the dividing groove T2 connected to the transverse groove T1 may also serve as a part of the transverse groove T1. For example, the part of the dividing groove T2 from the connection point with the transverse groove T1 to either the front end face 1F or the rear end face 1R, whichever of the front end face 1F and the rear end face 1R is connected to the transverse groove T1, may also be a part of the transverse groove T1.

[0060] The division groove T2 does not have to be formed continuously along the first direction. The division groove T2 does not have to be formed at all.

[0061] [2. Manufacturing Method of Semiconductor Light-Emitting Device] A manufacturing method of a semiconductor light-emitting device according to this embodiment will be described with reference to FIGS. 7 to 21. FIG. 7 is a schematic top view showing a wafer 10M according to this embodiment. FIGS. 8, 10, 12, 15, 16, 18, and 19 are schematic cross-sectional views showing each step of the manufacturing method of the semiconductor light-emitting device 1 according to this embodiment. FIGS. 9, 11, 14, 17, 20, and 21 are schematic top views showing each step of the manufacturing method of the semiconductor light-emitting device 1 according to this embodiment.

[0062] First, as shown in FIG. 7 , a wafer 10M, which is the base material of the substrate 10, is prepared (preparation step). In this embodiment, the wafer 10M is made of n-type GaN with a C-plane ((0001) plane) as its main surface, and an orientation flat (OF) is formed parallel to the Y-axis direction. The wafer 10M is positioned so that the m-axis of the GaN crystal constituting the wafer 10M is parallel to the X-axis direction and the a-axis is parallel to the Y-axis direction. FIG. 7 shows multiple cleavage lines L1 (dotted lines shown in FIG. 7 ) and multiple division lines L2 (dashed lines shown in FIG. 7 ). The multiple cleavage lines L1 are imaginary line segments parallel to the second direction and indicate positions where cleavage will be performed in the cleaving step described below. The multiple division lines L2 are imaginary line segments parallel to the first direction and indicate positions where division will be performed in the division step described below. The multiple cleavage lines L1 are periodically arranged in the first direction. The period of the arrangement of the multiple cleavage lines L1 in the first direction is equal to the length of the semiconductor light emitting device 1 in the first direction (i.e., the resonator length). The multiple parting lines L2 are arranged periodically in the second direction. The period of the arrangement of the multiple parting lines L2 in the second direction is equal to the width of the semiconductor light emitting device 1 (the dimension in the second direction). In the following, for simplicity of the drawings, a top view of the interior of the dashed frame FD in FIG. 7 and a portion of the cross section taken along line VIII-VIII are shown. In the region other than the dashed frame FD in FIG. 7, the same configuration as the region within the dashed frame FD is formed periodically.

[0063] Next, as shown in FIG. 8 , a semiconductor laminate 1S is grown on one main surface of the wafer 10M (growth step). Note that FIG. 8 only shows a cross section between two adjacent parting lines L2 among the cross sections taken along line VIII-VIII in FIG. 7 . The semiconductor laminate 1S has an n-side semiconductor layer 20 disposed above the wafer 10M, an active layer 30 disposed above the n-side semiconductor layer 20, and a p-side semiconductor layer 40 disposed above the active layer 30. Specifically, the n-side semiconductor layer 20 is grown by epitaxially growing a base layer 21, a buffer layer 22, an n-type cladding layer 23, and an n-side light guide layer 24 in this order on one main surface of the wafer 10M using a metalorganic chemical vapor deposition (MOCVD) method or the like. Next, the barrier layer 31, the well layer 32, and the barrier layer 33 are epitaxially grown in this order on the n-side semiconductor layer 20 by using a method such as MOCVD, thereby growing the active layer 30. Next, the electron barrier layer 41, the first p-side light guide layer 42, the second p-side light guide layer 43, the p-type cladding layer 44, and the contact layer 45 are epitaxially grown in this order on the active layer 30 by using a method such as MOCVD, thereby growing the p-side semiconductor layer 40.

[0064] 9 and 10, multiple transverse grooves T1 are formed in the semiconductor laminate 1S (transverse groove forming step). As shown in FIG. 9, each of the multiple transverse grooves T1 is formed continuously from the position of one of the multiple parting lines L2 in the second direction to the position of one of the parting lines L2 adjacent to that parting line L2 in the second direction, and intersects one of the multiple cleavage lines L1 between one parting line L2 and the other parting line L2 adjacent to that parting line L2 in the second direction. Also, in this embodiment, in the transverse groove forming step, multiple division grooves T2 are formed in the semiconductor laminate 1S along the multiple parting lines L2 (division groove forming step). Each of the multiple division grooves T2 is formed continuously along the multiple parting lines L2. Note that each of the multiple division grooves T2 does not have to be formed continuously along the multiple parting lines L2. In other words, each of the multiple division grooves T2 may be interrupted along the way.

[0065] Furthermore, at least some of the division grooves T2 may also be parts of the transverse grooves T1. That is, at least some of the division grooves T2 may also serve as parts of the transverse grooves T1. For example, a portion of the division groove T2 from a connection point between the transverse groove T1 intersecting with one cleavage line L1 and the division groove T2 to the one cleavage line L1 may also be part of the transverse groove T1.

[0066] For example, each groove is formed by photolithography and etching. Specifically, first, a SiO 2 film is formed on the entire upper surface of the semiconductor laminated body 1S. ２ Then, a SiO ２ A resist is applied onto the film. Then, exposure and development are performed to place the resist only in the areas where neither the transverse groove T1 nor the dividing groove T2 is to be formed. Then, SiO ２ The region of the film that is not covered with the resist is removed by dry etching. ２ Dry etching is performed on the regions not covered with the film. As a result, the transverse trench T1 and the division trench T2 are formed as shown in FIGS. 9 and 10. In this embodiment, the depths of the transverse trench T1 and the division trench T2 formed in this step are shallower than the final depths of these trenches. In this embodiment, the SiO ２ The film remains after the crossing groove forming step and the dividing groove forming step, but in FIGS. 9 and 10, the SiO ２ In this embodiment, the division groove forming step is performed simultaneously with the transverse groove forming step, thereby reducing the number of steps and time required for manufacturing compared to when the division groove forming step and the transverse groove forming step are performed separately. Note that the division groove forming step and the transverse groove forming step may also be performed separately.

[0067] In this embodiment, by forming a plurality of division grooves T2 along a plurality of division lines L2, it is possible to reduce the stress in the second direction, which is caused by the difference in lattice constant between the wafer 10M and the semiconductor laminate 1S, and therefore it is possible to reduce the warpage of the wafer 10M in the second direction.

[0068] Furthermore, in this embodiment, two adjacent transverse grooves T1 among the plurality of transverse grooves T1 and two adjacent division grooves T2 among the plurality of division grooves T2 form closed regions. In this way, at least some layers of the semiconductor laminate 1S are divided into closed regions, so that the stress applied to the semiconductor laminate 1S is also divided into closed regions. Therefore, the stress applied to each closed region can be reduced. This reduces the stress in the entire wafer 10M, and therefore reduces warpage of the wafer 10M.

[0069] Furthermore, in this embodiment, by continuously forming the transverse groove T1 from one parting line L2 to the adjacent parting line L2, it is possible to reduce the stress in the direction perpendicular to the parting line L2 (i.e., the first direction) caused by the difference in lattice constant between the wafer 10M and the semiconductor laminate 1S, thereby suppressing warping of the wafer 10M in the first direction and cracking of the wafer 10M.

[0070] Furthermore, since each of the transverse trenches T1 intersects one of the cleavage lines L1, stress in the first direction caused by the difference in lattice constant between the substrate 10 and the semiconductor laminate 1S can be reduced near the cleavage lines L1, thereby improving the cleavage properties of the wafer 10M at the cleavage lines L1.

[0071] 11 and 12 , multiple ridge grooves T3 extending in the first direction are formed in the semiconductor laminate 1S, thereby forming multiple protrusions P1 and multiple ridges R1 extending in the first direction (ridge groove forming process). The multiple ridge grooves T3 are formed only in the p-side semiconductor layer 40 of the semiconductor laminate 1S. Two or more of the multiple ridges R1 are arranged in a region surrounded by two adjacent parting lines L2 of the multiple parting lines L2 and two adjacent cleavage lines L1 of the multiple cleavage lines L1. The height of the multiple protrusions P1 from the main surface of the wafer 10M is equal to the height of the multiple ridges R1 from the main surface of the wafer 10M. Each of the multiple ridges R1 is adjacent to one of the multiple protrusions P1 via one of the multiple ridge grooves T3.

[0072] The ridge groove T3 is formed by, for example, photolithography and etching. ２ A resist is applied to the film. Then, exposure and development are performed to place the resist only in the region where the transverse groove T1, the dividing groove T2, and the ridge groove T3 are not to be formed. Then, SiO ２ The region of the film that is not covered with the resist (i.e., the region corresponding to the region where the ridge groove T3 is to be formed) is removed by dry etching. ２ Dry etching is performed on the area not covered with the film. This forms the ridge groove T3 as shown in FIGS. 11 and 12. This forms the ridge R1 and the protrusion P1. Next, SiO ２ Remove the film. ２ The film can be removed, for example, by etching.

[0073] In this embodiment, the depth of the transverse groove T1 and the division grooves T2 is increased by further etching these grooves in this step. In other words, this step is also part of the transverse groove forming step and the division groove forming step. In this way, by further etching the transverse groove T1 and the division grooves T2 in the ridge groove forming step, the time required for etching can be shortened compared to when the transverse groove T1 and the division grooves T2 are formed only in the transverse groove forming step and the division groove forming step. Furthermore, the depth of the transverse groove T1 and the division grooves T2 can be made deeper than the ridge groove T3. This further enhances the effect of reducing stress caused by the transverse groove T1 and the division grooves T2.

[0074] In this embodiment, the crossing groove T1 and the dividing groove T2 are further etched in the ridge groove forming step, but the crossing groove T1 and the dividing groove T2 may be formed only in the crossing groove forming step and the dividing groove forming step without etching them in the ridge groove forming step. In this case, at the beginning of the ridge groove forming step, the SiO 2 remaining in the previous step is removed. ２ The film is removed once, and the entire upper surface of the semiconductor laminate 1S is covered with SiO ２ The membrane is reformed.

[0075] Furthermore, the sum of the area of ​​the upper surfaces of the multiple ridges R1 and the area of ​​the upper surfaces of the multiple protrusions P1 may be 80% or more of the area of ​​the upper surface of the semiconductor laminate 1S. In other words, the area of ​​the etched region of the upper surface of the semiconductor laminate 1S may be 20% or less of the area of ​​the upper surface of the semiconductor laminate 1S. By reducing the etched region in this way, it is possible to reduce adhesion of debris generated during etching to the surfaces of the wafer 10M and the semiconductor laminate 1S.

[0076] The configuration of each groove and each ridge will now be described in detail with reference to Fig. 13. Fig. 13 is a top view for explaining the configuration of each groove and each ridge in the manufacturing process of the semiconductor light emitting device 1 according to this embodiment. Fig. 13 corresponds to an enlarged view of the region between two adjacent parting lines L2 in Fig. 11.

[0077] 13 , the multiple cleavage lines L1 include a first cleavage line L11, a second cleavage line L12 and a third cleavage line L13 adjacent to the first cleavage line L11, and a fourth cleavage line L14 adjacent to the second cleavage line L12. The multiple parting lines L2 extend from the first cleavage line L11 to the second cleavage line L12 and include a first parting line L21 and a second parting line L22, which are two parting lines L2 adjacent to each other in the second direction, and a third parting line L23 and a fourth parting line L24, which are two parting lines L2 adjacent to each other in the second direction, and extend from the first cleavage line L11 to the third cleavage line L13. In the present embodiment, the plurality of parting lines L2 extend from the second cleavage line L12 to the fourth cleavage line L14 and further include a fifth parting line L25 and a sixth parting line L26, which are two parting lines L2 adjacent to each other in the second direction. The third parting line L23 and the fifth parting line L25 are adjacent to the first parting line L21 in the first direction, and the fourth parting line L24 and the sixth parting line L26 are adjacent to the second parting line L22 in the first direction.

[0078] The semiconductor laminate 1S includes a first region AR1 surrounded by a first parting line L21, a second parting line L22, a first cleavage line L11, and a second cleavage line L12, a second region AR2 surrounded by a third parting line L23, a fourth parting line L24, the first cleavage line L11, and a third cleavage line L13, and a third region AR3 surrounded by a fifth parting line L25, a sixth parting line L26, the second cleavage line L12, and a fourth cleavage line L14. The first region AR1 is adjacent to the second region AR2 and the third region AR3 in the first direction.

[0079] The multiple ridges R1 include a first ridge R11, a second ridge R12, and a third ridge R13, at least portions of which are disposed in the first region AR1. The multiple ridges R1 also include a first ridge R11, a second ridge R12, and a fourth ridge R14, at least portions of which are disposed in the second region AR2. The multiple ridges R1 also include a first ridge R11, a third ridge R13, and a fifth ridge R15, at least portions of which are disposed in the third region AR3. The first ridge R11, the fourth ridge R14, and the fifth ridge R15 are positioned at the same position in the second direction. The second ridge R12 and the third ridge R13 are positioned at the same position in the second direction.

[0080] The multiple transverse trenches T1 include a first transverse trench T11 intersecting the first cleavage line L11, a second transverse trench T12 intersecting the second cleavage line L12, a third transverse trench T13 intersecting the third cleavage line L13, and a fourth transverse trench T14 intersecting the fourth cleavage line L14.

[0081] The first ridge R11 intersects the first cleavage line L11 and the second cleavage line L12 and is continuously formed between the first cleavage line L11 and the second cleavage line L12, and at least a portion of the first ridge R11 is disposed in the second region AR2. The second ridge R12 intersects the first cleavage line L11 and the third cleavage line L13 and is continuously formed between the first cleavage line L11 and the third cleavage line L13 and is at least a portion of the second ridge R12 is disposed in the first region AR1. The third ridge R13 intersects the second cleavage line L12 and the fourth cleavage line L14 and is continuously formed between the second cleavage line L12 and the fourth cleavage line L14 and is at least a portion of the third ridge R13 is disposed in the first region AR1. The fourth ridge R14 intersects with the third cleavage line L13 and has at least a portion located in the second region AR2. The fifth ridge R15 intersects with the fourth cleavage line L14 and has at least a portion located in the third region AR3.

[0082] The first transverse trench T11 intersects the first cleavage line L11 between the first ridge R11 and the second ridge R12. The second transverse trench T12 intersects the second cleavage line L12 between the first ridge R11 and the third ridge R13. The third transverse trench T13 intersects the third cleavage line L13 between the second ridge R12 and the fourth ridge R14. The fourth transverse trench T14 intersects the fourth cleavage line L14 between the third ridge R13 and the fifth ridge R15.

[0083] In the first region AR1, the third ridge R13 intersects the second cleavage line L12, and a first transverse groove T11 is disposed between the second ridge R12 and the third ridge R13, which are positioned at the same position in the second direction. At least one of the multiple protrusions P1 is disposed in at least one of the region between the first transverse groove T11 and the second ridge R12 and the region between the first transverse groove T11 and the third ridge R13. Here, the second ridge R12 and the third ridge R13 become dummy ridges R2 of the semiconductor light emitting device 1 manufactured using the first region AR1 of the semiconductor laminate 1S. Therefore, by providing the protrusion P1 between the second ridge R12 and the third ridge R13, which become the dummy ridge R2, and the first transverse groove T11, the proportion of the area occupied by the protrusion P1 in the first region AR1 can be increased. In other words, the etched area in the first region AR1 can be reduced, thereby reducing adhesion of debris generated during etching to the surfaces of the wafer 10M and the semiconductor laminate 1S.

[0084] The first transverse trench T11 intersects the second parting line L22 in the first region AR1. In this way, the first transverse trench T11 intersects the first cleavage line L11 between the first ridge R11 and the second ridge R12, and also intersects the second parting line L22 in the first region AR1. This makes it possible to form the first transverse trench T11 so that the second ridge R12 is not divided by the first transverse trench T11 in the second region AR2. This makes it possible to form the second ridge R12 continuously from the first cleavage line L11 to the third cleavage line L13 in the second region AR2, while continuously forming the first transverse trench T11 between the third parting line L23 and the second parting line L22.

[0085] The second transverse trench T12 intersects the second parting line L22 in the first region AR1. In this way, the second transverse trench T12 intersects the second cleavage line L12 between the first ridge R11 and the third ridge R13, and also intersects the second parting line L22 in the first region AR1. This makes it possible to form the second transverse trench T12 so that the first ridge R11 is not divided by the second transverse trench T12 in the first region AR1. This makes it possible to form the first ridge R11 continuously from the first cleavage line L11 to the second cleavage line L12 in the first region AR1, while continuously forming the second transverse trench T12 between the first parting line L21 and the second parting line L22.

[0086] The first transverse trench T11 intersects the third parting line L23 in the second region AR2. In this way, the first transverse trench T11 intersects the first cleavage line L11 between the first ridge R11 and the second ridge R12, and also intersects the third parting line L23 in the second region AR2. This makes it possible to form the first transverse trench T11 so that the first ridge R11 is not divided by the first transverse trench T11 in the first region AR1. This makes it possible to form the first ridge R11 continuously from the first cleavage line L11 to the second cleavage line L12 in the first region AR1, while continuously forming the first transverse trench T11 between the third parting line L23 and the second parting line L22.

[0087] The second transverse trench T12 intersects with the fifth parting line L25 in the third region AR3. In this way, the second transverse trench T12 intersects with the second cleavage line L12 between the first ridge R11 and the third ridge R13, and also intersects with the fifth parting line L25 in the third region AR3. This makes it possible to form the second transverse trench T12 so that the first ridge R11 is not divided by the second transverse trench T12 in the first region AR1. This makes it possible to form the first ridge R11 continuously from the first cleavage line L11 to the second cleavage line L12 in the first region AR1, while continuously forming the second transverse trench T12 between the fifth parting line L25 and the second parting line L22.

[0088] The third transverse trench T13 intersects with the third parting line L23 in the second region AR2. In this way, the third transverse trench T13 intersects with the third cleavage line L13 between the second ridge R12 and the fourth ridge R14, and also intersects with the third parting line L23 in the second region AR2. This makes it possible to form the third transverse trench T13 so that the second ridge R12 is not divided by the third transverse trench T13 in the second region AR2.

[0089] The fourth transverse trench T14 intersects with the fifth parting line L25 in the third region AR3. In this way, the fourth transverse trench T14 intersects with the third cleavage line L13 between the third ridge R13 and the fifth ridge R15, and also intersects with the fifth parting line L25 in the third region AR3. This makes it possible to form the fourth transverse trench T14 so that the third ridge R13 is not divided by the fourth transverse trench T14 in the third region AR3.

[0090] The first transverse trench T11 is disposed between the first ridge R11 and the third cleavage line L13. This prevents the first ridge R11 from being divided by the first transverse trench T11. Furthermore, the first transverse trench T11 is disposed between the second ridge R12 and the second cleavage line L12. This prevents the second ridge R12 from being divided by the first transverse trench T11.

[0091] The second transverse trench T12 is disposed between the first ridge R11 and the fourth cleavage line L14. This prevents the first ridge R11 from being divided by the second transverse trench T12. Furthermore, the second transverse trench T12 is disposed between the third ridge R13 and the first cleavage line L11. This prevents the third ridge R13 from being divided by the second transverse trench T12. Furthermore, the first transverse trench T11 and the third transverse trench T13 are disposed between the fourth ridge R14 and the first cleavage line L11. This prevents the fourth ridge R14 from being divided by the first transverse trench T11 and the third transverse trench T13. Furthermore, the second transverse trench T12 and the fourth transverse trench T14 are disposed between the fifth ridge R15 and the second cleavage line L12. This prevents the fifth ridge R15 from being divided by the second transverse trench T12 and the fourth transverse trench T14.

[0092] As described above, the first ridge R11 intersects the first cleavage line L11 and the second cleavage line L12 and is formed continuously between the first cleavage line L11 and the second cleavage line L12. This allows the first ridge R11 to be used as the ridge R1 to which current is supplied in the semiconductor light emitting device 1 manufactured using the first region AR1 of the semiconductor laminate 1S.

[0093] As described above, the second ridge R12 intersects the first cleavage line L11 and the third cleavage line L13 and is formed continuously between the first cleavage line L11 and the third cleavage line L13. This allows the second ridge R12 to be used as the ridge R1 to which current is supplied in the semiconductor light emitting element 1 manufactured using the second region AR2 of the semiconductor laminate 1S.

[0094] As described above, the third ridge R13 intersects the second cleavage line L12 and the fourth cleavage line L14 and is formed continuously between the second cleavage line L12 and the fourth cleavage line L14. This allows the third ridge R13 to be used as the ridge R1 to which current is supplied in the semiconductor light emitting element 1 manufactured using the third region AR3 of the semiconductor laminate 1S.

[0095] 14 and 15, a current blocking layer 50 is formed on the upper surface of the semiconductor laminated body 1S (current blocking layer forming step). In this embodiment, the current blocking layer 50 is formed of, for example, SiO ２ A film is formed by chemical vapor deposition (CVD) or the like. Then, an opening 50a is formed on the ridge R1 of the current blocking layer 50. Specifically, a mask is formed on the current blocking layer 50 in a region other than the region corresponding to the opening 50a. Then, the region of the current blocking layer 50 corresponding to the opening 50a is etched, for example, to form the opening 50a. As shown in FIG. 14 , the opening 50a is formed above the ridge R1 that is continuously formed between two adjacent cleavage lines L1.

[0096] 16 , a p-side electrode 62 is formed on the ridge R1 (p-side electrode forming step). The p-side electrode 62 is formed at least in the opening 50a of the current blocking layer 50. In this embodiment, the p-side electrode 62 may also be formed on the current blocking layer 50. The p-side electrode 62 is formed using, for example, photolithography and vapor deposition.

[0097] 17 and 18 , a pad electrode 66 is formed above the p-side electrode 62. The pad electrode 66 is formed at least above the opening 50a of the current blocking layer 50. In this embodiment, the pad electrode 66 is formed by, for example, a plating method using a mask, a vapor deposition method, a sputtering method, or the like.

[0098] 19, an n-side electrode 70 is formed on the underside of the wafer 10M (the main surface of the wafer 10M behind the main surface on which the semiconductor laminate 1S is laminated). The underside of the wafer 10M may be polished before forming the n-side electrode 70. The n-side electrode 70 is formed at least in a position facing the opening 50a of the current blocking layer 50. The n-side electrode 70 is formed using, for example, photolithography and vapor deposition.

[0099] 20, the wafer 10M is cleaved along the cleavage lines L1 to form a plurality of bar-shaped substrates 10Mb (cleavage step). Specifically, for example, cleavage guide grooves are formed near the edges of the wafer 10M along the cleavage lines L1, and the cleavage is performed by using a Teflon (registered trademark) blade or the like to press the backside of the wafer 10M where the cleavage guide grooves are formed, using the cleavage guide grooves as guide grooves. The cleavage guide grooves are formed by, for example, laser scribing using a laser such as a YAG laser or point scribing using a diamond cutter.

[0100] Here, the portion of the ridge R1 that does not extend from the front end facet 1F to the rear end facet 1R has its upper surface covered with the current blocking layer 50, and serves as a dummy ridge R2 to which no current is supplied.

[0101] Next, an end face protection film (not shown) is formed on the cleavage planes of the plurality of bar-shaped substrates 10Mb. For example, an end face protection film is first formed on the cleavage plane corresponding to the front end face 1F, and then an end face protection film is formed on the cleavage plane corresponding to the rear end face 1R. For example, a dielectric multilayer film or the like can be used as the end face protection film.

[0102] 21, the bar-shaped substrates 10Mb are divided along the division lines L2 (singulation process). Specifically, the division is performed by, for example, pressing the backside of the division grooves T2 of the bar-shaped substrates 10Mb with a blade or the like. Note that, in the singulation process, grooves may be formed along the division lines L2 using a laser scriber or the like. This further prevents the bar-shaped substrates 10Mb from being divided at positions other than the division lines L2.

[0103] By the manufacturing method described above, the semiconductor light emitting device 1 according to this embodiment can be manufactured.

[0104] [3. Effects, etc.] As described above, the semiconductor light-emitting element 1 according to the present embodiment includes an n-type substrate 10 and a semiconductor laminate 1S disposed on the major surface 10a of the substrate 10. The semiconductor laminate 1S has an n-side semiconductor layer 20 disposed above the substrate 10, an active layer 30 disposed above the n-side semiconductor layer 20, and a p-side semiconductor layer 40 disposed above the active layer 30. The semiconductor laminate 1S has a front end face 1F and a rear end face 1R disposed at one end and the other end, respectively, in a first direction parallel to the major surface 10a of the substrate 10, and a first laminate side face 1Sa and a second laminate side face 1Sb disposed at one end and the other end, respectively, in a second direction parallel to the major surface 10a of the substrate 10 and perpendicular to the first direction. The semiconductor laminate 1S includes: a plurality of ridge grooves T3 formed only in the p-side semiconductor layer 40 of the semiconductor laminate 1S and extending in a first direction; a ridge R1 disposed between two adjacent ridge grooves T3 of the plurality of ridge grooves T3 and supplied with current; a protrusion P1 disposed adjacent to the ridge R1 via one of the two ridge grooves T3; a dummy ridge R2 (first dummy ridge) disposed between two other ridge grooves T3 of the plurality of ridge grooves T3 and not supplied with current; and a transverse groove T1 (first transverse groove) formed continuously between the front end face 1F or the rear end face 1R and the first laminate side surface 1Sa and deeper than the plurality of ridge grooves T3. The height of the protrusion P1 from the substrate 10 is equal to the height of the ridge R1 from the substrate 10.

[0105] In this way, by arranging the transverse groove T1 having a portion extending in the second direction near one of the front end facet 1F and the rear end facet 1R, it is possible to reduce stress in the first direction caused by the difference in lattice constant between the substrate 10 and the semiconductor laminate 1S near one of the front end facet 1F and the rear end facet 1R, thereby improving the cleavability of the substrate 10 at one of the front end facet 1F and the rear end facet 1R.

[0106] Furthermore, by forming the transverse groove T1, when the semiconductor light-emitting element 1 is junction-down mounted on a mounting substrate or the like, the air located between the mounting substrate and the semiconductor laminate 1S can be released through the transverse groove T1, making it easier for the air to escape.

[0107] Furthermore, by forming the transverse groove T1, the surface area of ​​the semiconductor laminated body 1S can be increased, and therefore the heat dissipation properties of the semiconductor laminated body 1S can be improved.

[0108] In the semiconductor light emitting device 1 according to this embodiment, the ridge R1 may be formed continuously between the front end facet 1F and the rear end facet 1R.

[0109] Such a ridge R1 makes it possible to form an optical waveguide that extends over the entire length of the resonator formed by the front end facet 1F and the rear end facet 1R.

[0110] In the semiconductor light emitting device 1 according to this embodiment, the semiconductor stack 1S may have dividing grooves T2 extending in the first direction along the first stack side surface 1Sa and the second stack side surface 1Sb.

[0111] Such dividing grooves T2 can reduce the stress in the second direction caused by the difference in lattice constant between the substrate 10 and the semiconductor laminated body 1S.

[0112] In the semiconductor light emitting device 1 according to this embodiment, the center of the ridge R1 in the second direction may be located at a position that divides the width of the semiconductor light emitting device 1 in the second direction at a ratio of 3:1.

[0113] In the semiconductor light emitting element 1 according to this embodiment, the width of the protrusion P1 in the second direction may be 4 μm or more.

[0114] This makes it possible to effectively confine the current in the second direction in the ridge R1.

[0115] In the semiconductor light emitting device 1 according to this embodiment, the transverse trench T1 may be connected to the front end facet 1F or the rear end facet 1R between the ridge R1 and the dummy ridge R2.

[0116] In the semiconductor light emitting device 1 according to this embodiment, the dummy ridge R2 may be disposed between the first stacked body side surface 1Sa and the ridge R1.

[0117] In the semiconductor light-emitting element 1 according to this embodiment, the semiconductor laminate 1S may have a dummy ridge R2 (second dummy ridge) that is arranged between two other ridge grooves T3 among the multiple ridge grooves T3 other than the two ridge grooves T3 and to which no current is supplied, and a transverse groove T1 (second transverse groove) that is formed continuously between the other of the front end face 1F and the rear end face 1R and the first laminate side face 1Sa and is deeper than the multiple ridge grooves T3.

[0118] In this way, by arranging the transverse groove T1 having a portion extending in the second direction near the other of the front end facet 1F and the rear end facet 1R, it is possible to reduce stress in the first direction caused by the difference in lattice constant between the substrate 10 and the semiconductor laminate 1S near the other of the front end facet 1F and the rear end facet 1R, thereby improving the cleavability of the substrate 10 near the other of the front end facet 1F and the rear end facet 1R.

[0119] The manufacturing method of the semiconductor light-emitting element 1 according to this embodiment includes a growth process for growing a semiconductor laminate 1S on the main surface of a wafer 10M; a ridge groove formation process for forming a plurality of ridge grooves T3 extending in a first direction parallel to the main surface of the wafer 10M in the semiconductor laminate 1S, thereby forming a plurality of protrusions P1 and a plurality of ridges R1 extending in the first direction; a transverse groove formation process for forming a plurality of transverse grooves T1 deeper than the plurality of ridge grooves T3 in the semiconductor laminate 1S; a cleavage process for forming a plurality of bar-shaped substrates 10Mb by cleaving the wafer 10M along a plurality of cleavage lines L1 parallel to a second direction, the second direction being a direction parallel to the main surface of the wafer 10M and perpendicular to the first direction; and a singulation process for dividing the plurality of bar-shaped substrates 10Mb along a plurality of parting lines L2 parallel to the first direction. The semiconductor laminate 1S has an n-side semiconductor layer 20 disposed above the wafer 10M, an active layer 30 disposed above the n-side semiconductor layer 20, and a p-side semiconductor layer 40 disposed above the active layer 30. The multiple ridge grooves T3 are formed only in the p-side semiconductor layer 40 of the semiconductor laminate 1S. The height of the multiple protrusions P1 from the main surface of the wafer 10M is equal to the height of the multiple ridges R1 from the main surface of the wafer 10M. Each of the multiple ridges R1 is adjacent to one of the multiple protrusions P1 via one of the multiple ridge grooves T3. Each of the multiple transverse grooves T1 is formed continuously from the position of one of the multiple parting lines L2 in the second direction to the position of one of the parting lines L2 adjacent to the parting line L2 in the second direction. The multiple cleavage lines L1 include a first cleavage line L11, and a second cleavage line L12 and a third cleavage line L13 adjacent to the first cleavage line L11. The multiple parting lines L2 include a first parting line L21 and a second parting line L22 that extend from the first cleavage line L11 to the second cleavage line L12 and are two parting lines L2 adjacent to each other in the second direction, and a third parting line L23 and a fourth parting line L24 that extend from the first cleavage line L11 to the third cleavage line L13 and are two parting lines L2 adjacent to each other in the second direction. The semiconductor laminate 1S includes a first region AR1 surrounded by a first parting line L21, a second parting line L22, a first cleavage line L11, and a second cleavage line L12, and a second region AR2 surrounded by a third parting line L23, a fourth parting line L24, the first cleavage line L11, and a third cleavage line L13.The first region AR1 is adjacent to the second region AR2 in the first direction. The multiple ridges R1 include a first ridge R11 and a second ridge R12. The multiple transverse trenches T1 include a first transverse trench T11 that intersects with the first cleavage line L11. The first ridge R11 intersects with the first cleavage line L11 and the second cleavage line L12, is continuously formed between the first cleavage line L11 and the second cleavage line L12, and has at least a portion located in the second region AR2. The second ridge R12 intersects with the first cleavage line L11 and the third cleavage line L13, and has at least a portion located in the first region AR1. The first transverse trench T11 intersects with the first cleavage line L11 between the first ridge R11 and the second cleavage line R12.

[0120] In this way, by continuously forming the transverse groove T1 from one parting line L2 to the parting line L2 adjacent to that parting line L2 in the second direction, stress in the direction perpendicular to the parting line L2 (i.e., the first direction) caused by the difference in lattice constants between the wafer 10M and the semiconductor laminate 1S can be reduced. Therefore, warping of the wafer 10M in the first direction and cracking of the wafer 10M can be suppressed. Furthermore, since warping of the wafer 10M can be suppressed, cracks can be suppressed during crystal growth and heat treatment of the semiconductor laminate 1S. Furthermore, since exposure focus deviation caused by warping of the wafer 10M can be reduced, deterioration in the quality of each layer formed on the wafer 10M can be reduced. Furthermore, since warping of the wafer 10M can be reduced, deviation of the cleavage position during cleavage can be suppressed. Furthermore, even if the cleavage position deviates from the cleavage line L1, the cleavage can be stopped by the transverse groove T1, so that the occurrence of defective products due to deviation of the cleavage position can be reduced.

[0121] Note that reducing stress in the direction perpendicular to the parting line L2 of the wafer 10M (i.e., the first direction) can also be achieved by, for example, forming a linear transverse groove extending in the second direction. A semiconductor stack and wafer of a comparative example having such a configuration will be described using FIGS. 22A and 22B. FIGS. 22A and 22B are schematic top views showing the transverse groove T101 and cleavage line L1 in the manufacturing methods of semiconductor light-emitting devices of Comparative Examples 1 and 2, respectively. Similar to FIG. 13 , FIGS. 22A and 22B show top views of the wafer 10M after the semiconductor stack has been formed on the wafer 10M and after the grooves have been formed.

[0122] 22A and 22B , similar to the present embodiment, transverse grooves T101 and T102 deeper than the ridge groove T3 are formed. Similar to the first transverse groove T11 of the present embodiment, the transverse groove T101 of comparative example 1 and the transverse groove T102 of comparative example 2 are formed continuously from the third parting line L23 to the second parting line L22, and intersect with the first cleavage line L11 between the third parting line L23 and the second parting line L22.

[0123] The transverse trench T101 of Comparative Example 1 and the transverse trench T102 of Comparative Example 2 differ from the first transverse trench T11 of the present embodiment in that they do not intersect with the first cleavage line L11 between the first ridge R11 and the second ridge R12. The transverse trench T101 of Comparative Example 1 intersects with the first cleavage line L11 between the first ridge R11 and the first parting line L21 and the third parting line L23. The transverse trench T102 of Comparative Example 2 intersects with the first cleavage line L11 between the second ridge R12 and the second parting line L22 and the fourth parting line L24.

[0124] It is possible to reduce the stress in the first direction of the wafer 10M in the manufacturing methods of the semiconductor light-emitting element according to Comparative Example 1 and Comparative Example 2. However, the manufacturing methods of the semiconductor light-emitting element according to Comparative Example 1 and Comparative Example 2 have low utilization efficiency of the wafer 10M.

[0125] For example, in the manufacturing method of the semiconductor light-emitting device of Comparative Example 1, the second ridge R12 is formed continuously from the first cleavage line L11 to the third cleavage line L13 in the second region AR2, so that a semiconductor light-emitting device using the second ridge R12 as a current supply region can be formed using the second region AR2. However, in the first region AR1, the transverse trench T101 intersects with the first ridge R11, so that the first ridge R11 cannot be formed continuously from the first cleavage line L11 to the second cleavage line L12. In other words, a ridge cannot be formed continuously from the first cleavage line L11 to the second cleavage line L12 in the first region AR1. Therefore, a semiconductor light-emitting device cannot be formed using the first region AR1.

[0126] Furthermore, in the manufacturing method of the semiconductor light-emitting device of Comparative Example 2, the first ridge R11 is formed continuously from the first cleavage line L11 to the second cleavage line L12 in the first region AR1, so that a semiconductor light-emitting device can be formed using the first region AR1, with the first ridge R11 serving as a current supply region (in other words, an optical waveguide region). However, in the second region AR2, the transverse trench T101 intersects with the second ridge R12, so that the second ridge R12 cannot be formed continuously from the first cleavage line L11 to the third cleavage line L13. In other words, a ridge cannot be formed continuously from the first cleavage line L11 to the third cleavage line L13 in the second region AR2. Therefore, a semiconductor light-emitting device cannot be formed using the second region AR2. In contrast, in this embodiment, each transverse trench T1 is formed continuously between two adjacent parting lines L2, and each transverse trench T1 intersects the cleavage line L1 between two adjacent ridges in the second direction while intersecting the cleavage line L1 without intersecting the multiple ridges R1. Such multiple transverse trenches T1 can reduce stress in the first direction, as described above. Furthermore, because the transverse trenches T1 do not intersect the ridges R1, ridges R1 can be formed continuously between adjacent cleavage lines L1 in each region of the wafer 10M. In other words, since ridges R1 that can be used as current supply regions can be formed in each region, semiconductor light-emitting devices can be formed using each region. For example, in the example shown in FIG. 13, semiconductor light-emitting devices can be formed using all of the first region AR1 to the third region AR3. As such, this embodiment can improve the utilization efficiency of the wafer 10M compared to the comparative examples.

[0127] Furthermore, since each of the transverse trenches T1 intersects one of the cleavage lines L1, stress in the first direction caused by the difference in lattice constant between the substrate 10 and the semiconductor laminate 1S can be reduced near the cleavage lines L1, thereby improving the cleavage properties of the wafer 10M at the cleavage lines L1.

[0128] In addition, the manufacturing method of the semiconductor light-emitting element 1 according to this embodiment includes a growth process for growing a semiconductor laminate 1S on the main surface of the wafer 10M, a ridge groove formation process for forming a plurality of ridge grooves T3 extending in a first direction parallel to the main surface of the wafer 10M in the semiconductor laminate 1S, thereby forming a plurality of protrusions P1 and a plurality of ridges R1 extending in the first direction, a transverse groove formation process for forming a plurality of transverse grooves T1 deeper than the plurality of ridge grooves T3 in the semiconductor laminate 1S, a cleavage process for forming a plurality of bar-shaped substrates 10Mb by cleaving the wafer 10M along a plurality of cleavage lines L1 parallel to a second direction, the second direction being a direction parallel to the main surface of the wafer 10M and perpendicular to the first direction, and a singulation process for dividing the plurality of bar-shaped substrates 10Mb along a plurality of parting lines L2 parallel to the first direction. The semiconductor laminate 1S has an n-side semiconductor layer 20 disposed above the wafer 10M, an active layer 30 disposed above the n-side semiconductor layer 20, and a p-side semiconductor layer 40 disposed above the active layer 30. The multiple ridge grooves T3 are formed only in the p-side semiconductor layer 40 of the semiconductor laminate 1S. The height of the multiple protrusions P1 from the main surface of the wafer 10M is equal to the height of the multiple ridges R1 from the main surface of the wafer 10M. Each of the multiple ridges R1 is adjacent to one of the multiple protrusions P1 via one of the multiple ridge grooves T3. The multiple cleavage lines L1 include a first cleavage line L11, and a second cleavage line L12 and a third cleavage line L13 adjacent to the first cleavage line L11. The multiple parting lines L2 extend from the first cleavage line L11 to the second cleavage line L12 and include a first parting line L21 and a second parting line L22 that are two parting lines L2 adjacent to each other in the second direction, and a third parting line L23 and a fourth parting line L24 that extend from the first cleavage line L11 to the third cleavage line L13 and are two parting lines L2 adjacent to each other in the second direction. The semiconductor laminate 1S includes a first region AR1 surrounded by the first parting line L21, the second parting line L22, the first cleavage line L11, and the second cleavage line L12, and a second region AR2 surrounded by the third parting line L23, the fourth parting line L24, the first cleavage line L11, and the third cleavage line L13. The first region AR1 is adjacent to the second region AR2 in the first direction. The multiple ridges R1 include a first ridge R11 and a second ridge R12.The multiple transverse trenches T1 include a first transverse trench T11 that intersects with the first cleavage line L11. The first ridge R11 intersects with the first cleavage line L11 and the second cleavage line L12, is continuously formed between the first cleavage line L11 and the second cleavage line L12, and has at least a portion located in the second region AR2. The second ridge R12 intersects with the first cleavage line L11 and the third cleavage line L13, and has at least a portion located in the first region AR1. The first transverse trench T11 intersects with the first cleavage line L11 between the first ridge R11 and the second ridge R12. The first transverse trench T11 is located between the first ridge R11 and the third cleavage line L13. The second ridge R12 intersects the first cleavage line L11 and the third cleavage line L13 and is formed continuously between the first cleavage line L11 and the third cleavage line L13. A first transverse trench T11 is disposed between the second ridge R12 and the second cleavage line L12.

[0129] In this way, the first transverse grooves T11 intersect the first cleavage line L11 between the first ridge R11 and the second ridge R12, and are disposed between the first ridge R11 and the third cleavage line, and between the second ridge R12 and the second cleavage line L12. That is, the first transverse grooves T11 are formed in at least three locations in the second direction between two adjacent parting lines L2. This reduces stress in the direction perpendicular to the parting line L2 (i.e., the first direction) that is caused by the difference in lattice constants between the wafer 10M and the semiconductor laminate 1S. Therefore, warping of the wafer 10M in the first direction and cracking of the wafer 10M can be suppressed.

[0130] In addition, in this embodiment, each transverse trench T1 can intersect the cleavage line L1 between two ridges adjacent to each other in the second direction without intersecting with the plurality of ridges R1, so that the utilization efficiency of the wafer 10M can be improved compared to the comparative examples shown in FIGS.

[0131] Furthermore, since each of the transverse trenches T1 intersects one of the cleavage lines L1, stress in the first direction caused by the difference in lattice constant between the substrate 10 and the semiconductor laminate 1S can be reduced near the cleavage lines L1, thereby improving the cleavage properties of the wafer 10M at the cleavage lines L1.

[0132] In the method for manufacturing the semiconductor light emitting device 1 according to this embodiment, the plurality of parting lines L2 may be periodically arranged, and the plurality of cleavage lines L1 may be periodically arranged.

[0133] This allows a large number of semiconductor light emitting devices 1 of the same size to be manufactured at the same time.

[0134] The manufacturing method of the semiconductor light-emitting element 1 according to this embodiment further includes a split groove forming step of forming multiple split grooves T2 in the semiconductor laminate 1S along multiple split lines L2, and the multiple split grooves T2 may be deeper than the multiple ridge grooves T3.

[0135] By forming such division grooves T2, it is possible to reduce the stress in the second direction caused by the difference in lattice constant between the wafer 10M and the semiconductor laminate 1S.

[0136] In the method for manufacturing the semiconductor light emitting element 1 according to this embodiment, two adjacent transverse grooves T1 among the plurality of transverse grooves T1 and two adjacent division grooves T2 among the plurality of division grooves T2 may form a closed region.

[0137] In this way, since at least some of the layers of the semiconductor laminate 1S are divided into closed regions, the stress applied to the semiconductor laminate 1S is also divided into closed regions. Therefore, the stress applied to each closed region can be reduced. This reduces the stress in the entire wafer 10M, and therefore reduces warpage of the wafer 10M.

[0138] In the manufacturing method of the semiconductor light-emitting element 1 according to this embodiment, the sum of the area of ​​the upper surfaces of the multiple ridges R1 and the area of ​​the upper surfaces of the multiple protrusions P1 may be 80% or more of the area of ​​the upper surface of the semiconductor laminate 1S.

[0139] By reducing the area to be etched in this way, it is possible to reduce the amount of debris generated during etching that adheres to the surfaces of the wafer 10M and the semiconductor laminate 1S.

[0140] In the method for manufacturing the semiconductor light emitting element 1 according to this embodiment, the depth of the multiple transverse trenches T1 may be greater than the thickness of the p-side semiconductor layer 40 .

[0141] This allows the p-side semiconductor layer 40 to be divided by the transverse trench T1, thereby reducing the stress caused by the p-side semiconductor layer 40.

[0142] In the method for manufacturing the semiconductor light emitting element 1 according to this embodiment, the depth of the multiple transverse trenches T1 may be greater than the thickness of the semiconductor laminate 1S.

[0143] This allows the entire semiconductor laminate 1S to be divided by the transverse trench T1, thereby reducing stress caused by the semiconductor laminate 1S.

[0144] In the method for manufacturing the semiconductor light emitting element 1 according to this embodiment, the depth of the plurality of dividing grooves T2 may be greater than the thickness of the p-side semiconductor layer 40 .

[0145] This allows the p-side semiconductor layer 40 to be divided by the dividing grooves T2, thereby reducing the stress caused by the p-side semiconductor layer 40.

[0146] In the method for manufacturing the semiconductor light emitting element 1 according to this embodiment, the depth of the plurality of division grooves T2 may be greater than the thickness of the semiconductor laminate 1S.

[0147] This allows the entire semiconductor laminate 1S to be divided by the dividing grooves T2, thereby reducing stress caused by the semiconductor laminate 1S.

[0148] In the method for manufacturing the semiconductor light emitting element 1 according to this embodiment, the multiple ridges R1 may be arranged at equal intervals in the second direction.

[0149] As a result, the ridges R1 are arranged at equal intervals along the cleavage line L1. In this case, the ridges R1 are arranged evenly at the cleavage position, which improves the cleavage property at the cleavage position.

[0150] In the method for manufacturing the semiconductor light emitting element 1 according to the present embodiment, the width of each of the plurality of protrusions P1 in the second direction may be 4 μm or more.

[0151] This makes it possible to effectively confine the current in the second direction in the ridge R1 of the semiconductor light emitting element 1.

[0152] In the method for manufacturing the semiconductor light emitting device 1 according to the present embodiment, the wafer 10M may contain GaN, and the n-side semiconductor layer 20 and the p-side semiconductor layer 40 may contain AlGaN.

[0153] In this case, tensile strain occurs in the semiconductor laminate 1S due to the difference in lattice constant with the wafer 10M, so the effect of reducing stress due to the formation of the transverse trench T1 according to this embodiment becomes even more pronounced.

[0154] In the manufacturing method of the semiconductor light emitting element 1 according to this embodiment, the integrated stress of the semiconductor laminate 1S on the wafer 10M may be -500 Pa m or less (that is, the tensile integrated stress of the semiconductor laminate 1S may be 500 Pa m or more). Here, compressive stress on the wafer 10M is represented by a positive (plus) value, and tensile stress is represented by a negative (minus) value. The integrated stress is a value obtained by integrating the stress of each layer of the semiconductor laminate 1S on the wafer 10M in the stacking direction.

[0155] Even when the integrated stress (that is, strain) in the semiconductor laminate 1S is large, the stress can be reduced by forming the transverse trench T1 according to this embodiment, and therefore warpage of the wafer 10M can be reduced.

[0156] In the method for manufacturing the semiconductor light emitting device 1 according to this embodiment, a first transverse trench T11 may be disposed between the second ridge R12 and the second cleavage line L12.

[0157] This makes it possible to prevent the second ridge R12 from being divided by the first transverse trench T11.

[0158] In the method for manufacturing the semiconductor light emitting element 1 according to the present embodiment, the plurality of ridges R1 include a third ridge R13 at least a portion of which is disposed in the first region AR1, and in the first region AR1, the third ridge R13 intersects the second cleavage line L12, and a first transverse groove T11 is disposed between the second ridge R12 and the third ridge R13, which are positioned at the same position in the second direction. At least one of the plurality of protrusions P1 may be disposed in at least one of the region between the first transverse groove T11 and the second ridge R12 and the region between the first transverse groove T11 and the third ridge R13.

[0159] Here, the second ridge R12 and the third ridge R13 become dummy ridges R2 of the semiconductor light emitting device 1 manufactured using the first region AR1 of the semiconductor laminate 1S. Therefore, by providing protrusions P1 between the first transverse groove T11 and the second ridges R12 and third ridges R13 that become dummy ridges R2, it is possible to increase the proportion of the area in the first region AR1 that is occupied by the protrusions P1. In other words, since the area to be etched in the first region AR1 can be reduced, it is possible to reduce adhesion of debris generated during etching to the surfaces of the wafer 10M and the semiconductor laminate 1S.

[0160] In the manufacturing method of the semiconductor light emitting device 1 according to this embodiment, the multiple cleavage lines L1 may include a fourth cleavage line L14 adjacent to the second cleavage line L12, and the multiple parting lines L2 may include a fifth parting line L25 and a sixth parting line L26 extending from the second cleavage line L12 to the fourth cleavage line L14 and adjacent to each other in the second direction. The semiconductor laminate 1S may include a third region AR3 surrounded by the fifth parting line L25, the sixth parting line L26, the second cleavage line L12, and the fourth cleavage line L14. The first region AR1 may be adjacent to the third region AR3 in the first direction. The multiple transverse grooves T1 may include a second transverse groove T12 intersecting the second cleavage line L12. At least a portion of the first ridge R11 is arranged in the third region AR3, a second transverse trench T12 is arranged between the first ridge R11 and the fourth cleavage line L14, and a second transverse trench T12 is arranged between the third ridge R13 and the first cleavage line L11, and the second transverse trench T12 may intersect with the second cleavage line L12 between the first ridge R11 and the third ridge R13.

[0161] This allows the second transverse trench T12 to be formed without dividing the first ridge R11 and the third ridge R13 by the second transverse trench T12. Therefore, in the third region AR3, the third ridge R13 can be formed continuously from the second cleavage line L12 to the fourth cleavage line L14, and therefore a semiconductor light emitting element can be formed using the third region AR3, with the third ridge R13 serving as a current supply region.

[0162] In the method for manufacturing the semiconductor light emitting element 1 according to this embodiment, the first transverse trench T11 may intersect with the second parting line L22.

[0163] In this way, the first transverse trench T11 intersects the first cleavage line L11 between the first ridge R11 and the second ridge R12, and also intersects the second parting line L22 in the first region AR1. This makes it possible to form the first transverse trench T11 so that the second ridge R12 is not divided by the first transverse trench T11 in the second region AR2. This makes it possible to form the second ridge R12 continuously from the first cleavage line L11 to the third cleavage line L13 in the second region AR2, while continuously forming the first transverse trench T11 between the first parting line L21 and the second parting line L22.

[0164] In the manufacturing method of the semiconductor light-emitting device 1 according to this embodiment, the multiple transverse trenches T1 include a second transverse trench T12 that intersects with the second cleavage line L12, and the second transverse trench T12 may intersect with the second dividing line L22.

[0165] In this way, the second transverse trench T12 intersects the second cleavage line L12 between the first ridge R11 and the third ridge R13, and also intersects the second parting line L22 in the first region AR1. This makes it possible to form the second transverse trench T12 so that the first ridge R11 is not divided by the second transverse trench T12 in the first region AR1. This makes it possible to form the first ridge R11 continuously from the first cleavage line L11 to the second cleavage line L12 in the first region AR1, while continuously forming the second transverse trench T12 between the first parting line L21 and the second parting line L22.

[0166] In the method for manufacturing the semiconductor light emitting element 1 according to this embodiment, the first transverse trench T11 may intersect with the third parting line L23.

[0167] In this way, the first transverse trench T11 intersects the first cleavage line L11 between the first ridge R11 and the second ridge R12, and also intersects the first parting line L21 in the second region AR2. This makes it possible to form the first transverse trench T11 so that the first ridge R11 is not divided by the first transverse trench T11 in the first region AR1. This makes it possible to form the first ridge R11 continuously from the first cleavage line L11 to the second cleavage line L12 in the first region AR1, and to form the first transverse trench T11 continuously between the first parting line L21 and the second parting line L22.

[0168] In the method for manufacturing the semiconductor light emitting device 1 according to this embodiment, a first transverse trench T11 may be disposed between the first ridge R11 and the third cleavage line L13.

[0169] This makes it possible to prevent the first ridge R11 from being divided by the first transverse trench T11.

[0170] In the manufacturing method of the semiconductor light-emitting element 1 according to this embodiment, the second ridge R12 may intersect the first cleavage line L11 and the third cleavage line L13 and may be formed continuously between the first cleavage line L11 and the third cleavage line L13.

[0171] This allows the second ridge R12 to be used as the ridge R1 to which current is supplied in the semiconductor light emitting device 1 manufactured using the second region AR2 of the semiconductor laminate 1S.

[0172] [4. Modifications] Modifications of the present embodiment will be described.

[0173] [4-1. Modification 1] A semiconductor light emitting device and a manufacturing method thereof according to Modification 1 of the present embodiment will be described with reference to Fig. 23. Fig. 23 is a schematic top view of a wafer 10M showing the configuration of a transverse groove T1 according to this modification. Fig. 23 shows only a region corresponding to one semiconductor light emitting device 1 in the top view of the wafer 10M on which the semiconductor laminate 1S is stacked.

[0174] 23 , in a top view of the wafer 10M, the width of each of the transverse grooves T1 may be greater in the portion extending in the second direction than in the portion extending in the first direction. For example, the width of the portion extending in the second direction of each of the transverse grooves T1 may be 1.5 times or more and 2.5 times or less the width of the portion extending in the first direction of each of the transverse grooves T1. Furthermore, the width of the portion extending in the second direction of each of the transverse grooves T1 may be approximately twice the width of the portion extending in the first direction of each of the transverse grooves T1.

[0175] Increasing the width of the portion of the transverse trench T1 extending in the second direction in this manner makes it possible to further reduce the stress in the first direction of the semiconductor laminate 1S, and therefore further reduce the warpage of the wafer 10M in the first direction.

[0176] Furthermore, in the semiconductor light emitting device 1 manufactured from such a wafer 10M, stress near the front end face 1F and the rear end face 1R can be further reduced.

[0177] [4-2. Modification 2] A semiconductor light emitting device and a manufacturing method thereof according to Modification 2 of the present embodiment will be described with reference to Fig. 24. Fig. 24 is a schematic top view of a wafer 10M showing the configuration of a transverse groove T1 according to this modification. Fig. 24 shows only a region corresponding to one semiconductor light emitting device 1 in the top view of the wafer 10M on which the semiconductor laminate 1S is stacked.

[0178] 24, each of the transverse grooves T1 may have no corners when viewed from above the wafer 10M. In other words, each of the transverse grooves T1 may have a curved shape when viewed from above the wafer 10M.

[0179] When the transverse trench T1 has a corner, the semiconductor laminate 1S adjacent to the transverse trench T1 also has a corner, and cracks are likely to occur at the corner. In contrast, in this modification, each of the multiple transverse trenches T1 does not have a corner, and therefore the number of corners in the semiconductor laminate 1S can be reduced. Therefore, the occurrence of cracks in the semiconductor laminate 1S can be reduced.

[0180] Furthermore, the configuration of the cornerless transverse groove T1 is not limited to the example shown in Fig. 24. Other configuration examples of this modified example will be described below with reference to Figs. 25 to 29. Figs. 25 to 29 are schematic top views of a wafer 10M showing other configuration examples of this modified example. Figs. 25 to 29 show only a region corresponding to one semiconductor light emitting element 1 in the top view of the wafer 10M on which the semiconductor laminate 1S is laminated.

[0181] As shown in Figure 25, the shape of the crossing groove T1 without corners may be a semicircular shape as shown in Figure 25. In this case, between two adjacent parting lines, the crossing groove T1 intersects with the cleavage line L1 at two points. This increases the portion of the crossing groove T1 that is close to the cleavage line L1. This further reduces the stress in the semiconductor laminate 1S near the cleavage line L1.

[0182] As shown in FIG. 26 , in a top view of the wafer 10M, the edges of the multiple protrusions P1 facing the intersections Tc where the multiple transverse grooves T1 and the multiple division grooves T2 intersect may have a curved shape. This reduces the occurrence of cracks near the edges of the protrusions P1 facing the intersections Tc. Note that the shape of the edges of the multiple protrusions P1 facing the intersections Tc in a top view of the wafer 10M is not limited to a curved shape. For example, in a top view of the wafer 10M, the interior angles of the edges of the multiple protrusions P1 facing the intersections Tc where the multiple transverse grooves T1 and the multiple division grooves T2 intersect may be 90 degrees or greater. Even with this configuration, the occurrence of cracks near the edges of the protrusions P1 facing the intersections Tc can be reduced.

[0183] 26, only the edge of one protrusion P1 facing one intersection Tc has a curved shape, but as shown in Fig. 27, the edges of both protrusions P1 facing one intersection Tc may also have curved shapes, which further reduces the occurrence of cracks near the edges of the protrusions P1 facing the intersection Tc.

[0184] 28 and 29, in this modification, the width of the portion of the transverse groove T1 extending in the second direction may be increased, as in the modification 1. This provides the same effect as the modification 1.

[0185] [4-3. Modification 3] A semiconductor light emitting device and a manufacturing method thereof according to Modification 3 of the present embodiment will be described with reference to Fig. 30. Fig. 30 is a schematic top view of a wafer 10M showing the configuration of a transverse groove T1 according to this modification. Fig. 30 shows only a region corresponding to one semiconductor light emitting device 1 in the top view of the wafer 10M on which the semiconductor laminate 1S is stacked.

[0186] 30 , in a top view of the wafer 10M, each of the multiple transverse grooves T1 is made up of multiple connected linear segment grooves T1a-T1c, and the angle formed by any two connected linear segment grooves among the multiple linear segment grooves T1a-T1c may be 90 degrees or more. Also, each of the multiple transverse grooves T1 of the semiconductor light emitting device 1 manufactured from such a wafer 10M is made up of multiple connected linear segment grooves T1a-T1c, and the angle formed by any two connected linear segment grooves among the multiple linear segment grooves T1a-T1c is 90 degrees or more.

[0187] In the example shown in FIG. 30, each of the multiple transverse grooves T1 has a linear groove T1a parallel to the first direction, a linear groove T1b parallel to the second direction, and a linear groove T1c connecting them and inclined with respect to the first direction and the second direction.

[0188] Because such a transverse groove T1 does not have an acute corner, the semiconductor laminate 1S adjacent to the corner also does not have an acute corner. Therefore, according to this modification, the occurrence of cracks in the semiconductor laminate 1S can be reduced. Furthermore, in the example shown in FIG. 30, the angle formed by the two connected linear grooves is greater than 90 degrees (i.e., an obtuse angle). This further reduces the occurrence of cracks in the semiconductor laminate 1S.

[0189] [4-4. Modification 4] A semiconductor light emitting device and a manufacturing method thereof according to Modification 4 of the present embodiment will be described with reference to Fig. 31. Fig. 31 is a schematic top view of a wafer 10M showing the configuration of a transverse groove T1 according to this modification. Fig. 31 shows only a portion of the top view of the wafer 10M on which a semiconductor laminate 1S is stacked.

[0190] 31 , the multiple cleavage lines L1 include a first cleavage line L11 and a second cleavage line L12 and a third cleavage line L13 adjacent to the first cleavage line L11. The multiple parting lines L2 extend from the first cleavage line L11 to the second cleavage line L12 and include a first parting line L21 and a second parting line L22, which are two parting lines L2 adjacent to each other in the second direction, and a third parting line L23 and a fourth parting line L24, which are two parting lines L2 adjacent to each other in the second direction, and a seventh parting line L27, which is adjacent to the first parting line L21 in the second direction and is located on the opposite side of the first parting line L21 from the second parting line L22. The multiple dividing lines L2 also include an eighth dividing line L28 that is adjacent to the third dividing line L23 in the second direction and is positioned on the opposite side of the third dividing line L23 from the fourth dividing line L24.

[0191] In this specification, the phrase "two parting lines L2 are adjacent in the second direction" means that the two parting lines L2 are adjacent over the entire range in the first direction between two adjacent cleavage lines L1. For example, the first parting line L21 and the third parting line L23 are not adjacent over the entire range in the first direction between two adjacent cleavage lines L1, and therefore are not included in the two parting lines adjacent in the second direction.

[0192] 31 , in this modification, the positions of the multiple parting lines L2 are alternately shifted for each region between two adjacent cleavage lines L1 (i.e., for each bar-shaped substrate 10 Mb) by half the width in the second direction of the semiconductor light emitting element 1. For example, the position of the third parting line L23 in the second direction is shifted from the position of the first parting line L21 in the second direction by half the width in the second direction of the semiconductor light emitting element 1 (i.e., the width of the first region AR1).

[0193] The semiconductor laminate 1S includes a first region AR1 surrounded by the first parting line L21, the second parting line L22, the first cleavage line L11, and the second cleavage line L12; a second region AR2 surrounded by the third parting line L23, the fourth parting line L24, the first cleavage line L11, and the third cleavage line L13; a fourth region AR4 surrounded by the first parting line L21, the seventh parting line L27, the first cleavage line L11, and the second cleavage line L12; and a fifth region AR5 surrounded by the third parting line L23, the eighth parting line L28, the first cleavage line L11, and the third cleavage line L13. The first region AR1 is adjacent to the second region AR2 and the fifth region AR5 in the first direction. The fourth region AR4 is adjacent to the fifth region AR5 in the first direction. The first region AR1 is adjacent to the fourth region AR4 in the second direction. The second region AR2 is adjacent to the fifth region AR5 in the second direction. In this modification, the positions in the second direction of two element regions adjacent in the first direction (e.g., the first region AR1 and the second region AR2) are shifted alternately between two adjacent cleavage lines L1 by half the width of the element region in the second direction. For example, the position of the second region AR2 in the second direction is shifted by half the width of the first region AR1 and the second region AR2 in the second direction relative to the position of the first region AR1 in the second direction. Furthermore, the position of the fifth region AR5 in the second direction is shifted by half the width of the fourth region AR4 and the fifth region AR5 in the second direction relative to the position of the fourth region AR4 in the second direction.

[0194] The multiple ridges R1 include a first ridge R11, a second ridge R12, and a third ridge R13, at least portions of which are disposed in the first region AR1. The multiple ridges R1 also include a second ridge R12, a sixth ridge R16, and a seventh ridge R17, at least portions of which are disposed in the second region AR2. The multiple ridges R1 also include an eighth ridge R18, a ninth ridge R19, and a tenth ridge R20, at least portions of which are disposed in the fourth region AR4. The multiple ridges R1 also include a first ridge R11, a ninth ridge R19, and a fourth ridge R14, at least portions of which are disposed in the fifth region AR5.

[0195] The first ridge R11 and the fourth ridge R14 are positioned at the same position in the second direction. The second ridge R12 and the third ridge R13 are positioned at the same position in the second direction. The sixth ridge R16 and the seventh ridge R17 are positioned at the same position in the second direction. The ninth ridge R19 and the tenth ridge R20 are positioned at the same position in the second direction.

[0196] The first ridge R11 intersects the first cleavage line L11 and the second cleavage line L12 and is continuously formed between the first cleavage line L11 and the second cleavage line L12, with at least a portion thereof disposed in the fifth region AR5. The second ridge R12 intersects the first cleavage line L11 and the third cleavage line L13 and is continuously formed between the first cleavage line L11 and the third cleavage line L13 and with at least a portion thereof disposed in the first region AR1. The third ridge R13 intersects the second cleavage line L12 and is at least a portion thereof disposed in the first region AR1. The fourth ridge R14 intersects the third cleavage line L13 and is at least a portion thereof disposed in the fifth region AR5. The sixth ridge R16 intersects the first cleavage line L11 and has at least a portion located in the second region AR2. The seventh ridge R17 intersects the third cleavage line L13 and has at least a portion located in the second region AR2. The eighth ridge R18 intersects the first cleavage line L11 and the second cleavage line L12 and is continuously formed between the first cleavage line L11 and the second cleavage line L12. The ninth ridge R19 intersects the first cleavage line L11 and the third cleavage line L13 and is continuously formed between the first cleavage line L11 and the third cleavage line L13 and has at least a portion located in the fourth region AR4. The tenth ridge R20 intersects the second cleavage line L12 and has at least a portion located in the fourth region AR4.

[0197] The multiple transverse grooves T1 include a first transverse groove T11 that intersects with the first cleavage line L11, a second transverse groove T12 that intersects with the second cleavage line L12, and a third transverse groove T13 that intersects with the third cleavage line L13. As in the manufacturing method of the semiconductor light emitting device according to the above embodiment, each of the multiple transverse grooves T1 is formed continuously from the position in the second direction of one of the multiple parting lines L2 to the position in the second direction of one of the parting lines adjacent to that parting line in the second direction.

[0198] The first transverse trench T11 intersects with the first cleavage line L11 between the sixth ridge R16 and the second ridge R12, between the second ridge R12 and the first ridge R11, between the first ridge R11 and the ninth ridge R19, and between the ninth ridge R19 and the eighth ridge R18. Here, the portion of the multiple dividing trenches T2 from the connection point with the first transverse trench T11 to the first cleavage line L11 also forms part of the first transverse trench T11.

[0199] The second transverse trench T12 intersects with the second cleavage line L12 between the third ridge R13 and the first ridge R11, and between the tenth ridge R20 and the eighth ridge R18. Here, of the multiple dividing trenches T2, the portion from the connection point with the second transverse trench T12 to the second cleavage line L12 also forms part of the second transverse trench T12. Therefore, the second transverse trench T12 intersects with the second cleavage line L12 also between the first ridge R11 and the tenth ridge R20, etc.

[0200] The third transverse trench T13 intersects the third cleavage line L13 between the second ridge R12 and the seventh ridge R17, and between the fourth ridge R14 and the ninth ridge R19. Here, of the multiple dividing trenches T2, the portion from the connection point with the third transverse trench T13 to the third cleavage line L13 also forms part of the third transverse trench T13. Therefore, the third transverse trench T13 intersects the third cleavage line L13 also between the second ridge R12 and the fourth ridge R14, etc.

[0201] In the first region AR1, the third ridge R13 intersects the second cleavage line L12, and a first transverse trench T11 is disposed between the second ridge R12 and the third ridge R13, which are positioned at the same position in the second direction. At least one of the multiple protrusions P1 is disposed in at least one of the region between the first transverse trench T11 and the second ridge R12 and the region between the first transverse trench T11 and the third ridge R13. The first transverse trench T11 also intersects the second parting line L22 in the first region AR1.

[0202] The second transverse trench T12 intersects with the second parting line L22 in the first region AR1. In this manner, the second transverse trench T12 intersects with the second cleavage line L12 between the first ridge R11 and the third ridge R13, and also intersects with the second parting line L22 in the first region AR1.

[0203] The first transverse trench T11 is disposed between the first ridge R11 and the third cleavage line L13. This prevents the first ridge R11 from being divided by the first transverse trench T11. The first transverse trench T11 is disposed between the second ridge R12 and the second cleavage line L12. This prevents the second ridge R12 from being divided by the first transverse trench T11. The second transverse trench T12 is disposed between the third ridge R13 and the first cleavage line L11. This prevents the third ridge R13 from being divided by the second transverse trench T12. The first transverse trench T11 and the third transverse trench T13 are disposed between the fourth ridge R14 and the first cleavage line L11. This prevents the fourth ridge R14 from being divided by the first transverse trench T11 and the third transverse trench T13. The first transverse trench T11 and the third transverse trench T13 are disposed between the sixth ridge R16 and the third cleavage line L13. This prevents the sixth ridge R16 from being divided by the first transverse trench T11 and the third transverse trench T13. Furthermore, the first transverse trench T11 and the third transverse trench T13 are disposed between the seventh ridge R17 and the first cleavage line L11. This prevents the seventh ridge R17 from being divided by the first transverse trench T11 and the third transverse trench T13.

[0204] As described above, the first ridge R11 intersects the first cleavage line L11 and the second cleavage line L12 and is formed continuously between the first cleavage line L11 and the second cleavage line L12. This allows the first ridge R11 to be used as the ridge R1 to which current is supplied in the semiconductor light emitting device 1 manufactured using the first region AR1 of the semiconductor laminate 1S.

[0205] As described above, the second ridge R12 intersects the first cleavage line L11 and the third cleavage line L13 and is formed continuously between the first cleavage line L11 and the third cleavage line L13. This allows the second ridge R12 to be used as the ridge R1 to which current is supplied in the semiconductor light emitting element 1 manufactured using the second region AR2 of the semiconductor laminate 1S.

[0206] As described above, the eighth ridge R18 intersects the first cleavage line L11 and the second cleavage line L12 and is formed continuously between the first cleavage line L11 and the second cleavage line L12. This allows the eighth ridge R18 to be used as the ridge R1 to which current is supplied in the semiconductor light emitting device 1 manufactured using the fourth region AR4 of the semiconductor laminate 1S.

[0207] As described above, the ninth ridge R19 intersects with the first cleavage line L11 and the third cleavage line L13 and is formed continuously between the first cleavage line L11 and the third cleavage line L13. This allows the ninth ridge R19 to be used as the ridge R1 to which current is supplied in the semiconductor light emitting element 1 manufactured using the fifth region AR5 of the semiconductor laminate 1S.

[0208] The semiconductor light emitting device and the method for manufacturing the same according to this modification also have the same effects as those of the semiconductor light emitting device 1 according to the present embodiment and the method for manufacturing the same.

[0209] [4-5. Modification 5] A semiconductor light emitting device and a method for manufacturing the same according to Modification 5 of the present embodiment will be described. The semiconductor light emitting device and a method for manufacturing the same according to this modification differ from the semiconductor light emitting device and a method for manufacturing the same according to Modification 4 in that the multiple transverse grooves T1 are spaced apart from the multiple parting lines L2 (or division grooves T2). The semiconductor light emitting device and a method for manufacturing the same according to this modification will be described below with reference to FIG. 32, focusing on the differences from the semiconductor light emitting device and a method for manufacturing the same according to Modification 4. FIG. 32 is a schematic top view of a wafer 10M showing the configuration of the transverse groove T1 according to this modification. FIG. 32 shows only a portion of the top view of a wafer 10M on which a semiconductor laminate 1S is stacked.

[0210] As in the manufacturing method of the semiconductor light-emitting device according to the above embodiment, each of the multiple transverse grooves T1 is continuously formed from the position in the second direction of one of the multiple parting lines L2 to the position in the second direction of one of the multiple parting lines L2 adjacent to the one of the multiple parting lines L2. In the semiconductor light-emitting device and its manufacturing method according to this modification, as shown in FIG. 32 , the multiple transverse grooves T1 include a first transverse groove T11, a second transverse groove T12, and a third transverse groove T13, and each of the multiple transverse grooves T1 is spaced apart from the multiple parting grooves T2. In this modification, as in Modification 4, the multiple parting grooves T2 are arranged along the multiple parting lines L2, respectively. Note that, as shown in FIG. 32 , the multiple parting grooves T2 may each extend onto an extension line of the multiple parting lines L2. This ensures that the parting grooves T2 intersect with the cleavage line L1. This prevents the parting grooves T2 from not reaching the cleavage line L1.

[0211] In this modified example, the first transverse grooves T11 are arranged to extend in the first direction between the dividing groove T2 including the fourth dividing line L24 and the sixth ridge R16, between the sixth ridge R16 (and the dividing groove T2 including the second dividing line L22) and the second ridge R12, between the second ridge R12 (and the dividing groove T2 including the third dividing line L23) and the first ridge R11, between the first ridge R11 (and the dividing groove T2 including the first dividing line L21) and the ninth ridge R19, and between the ninth ridge R19 (and the dividing groove T2 including the eighth dividing line L28) and the eighth ridge R18, and intersect with the first cleavage line L11.

[0212] In addition, the first transverse trench T11 is arranged to extend in the second direction between the sixth ridge R16 and the third cleavage line L13, between the second ridge R12 and the second cleavage line L12, between the first ridge R11 and the third cleavage line L13, and between the ninth ridge R19 and the second cleavage line L12.

[0213] In addition, the first transverse groove T11 is formed continuously from the point where the extension line of the second dividing line L22 in the first direction intersects with the first transverse groove T11 to the point where the extension line of the first dividing line L21 adjacent to the second dividing line L22 in the second direction intersects with the first transverse groove T11.

[0214] The second transverse trench T12 intersects with the second cleavage line L12 between the dividing trench T2 including the second dividing line L22 and the third ridge R13, between the third ridge R13 and the first ridge R11, between the first ridge R11 (and the dividing trench T2 including the first dividing line L21) and the tenth ridge R20, and between the tenth ridge R20 and the eighth ridge R18.

[0215] The second transverse trench T12 is disposed between the third ridge R13 and the first cleavage line L11, and between the tenth ridge R20 and the first cleavage line L11.

[0216] The third transverse trench T13 intersects with the third cleavage line L13 between the dividing trench T2 including the fourth dividing line L24 and the seventh ridge R17, between the seventh ridge R17 and the second ridge R12, between the second ridge R12 (and the dividing trench T2 including the third dividing line L23) and the fourth ridge R14, and between the fourth ridge R14 and the ninth ridge R19.

[0217] The third transverse trench T13 is disposed between the seventh ridge R17 and the first cleavage line L11, and between the fourth ridge R14 and the first cleavage line L11.

[0218] The semiconductor light emitting device and the method for manufacturing the same according to this modification also have the same effects as those of the semiconductor light emitting device 1 according to the present embodiment and the method for manufacturing the same.

[0219] [4-6. Modification 6] A semiconductor light emitting device and a method for manufacturing the same according to Modification 6 of the present embodiment will be described. The semiconductor light emitting device and a method for manufacturing the same according to this modification differ from the semiconductor light emitting device and a method for manufacturing the same according to Modification 5 in that the multiple transverse grooves T1 intersect with two or more adjacent cleavage lines L1. The semiconductor light emitting device and a method for manufacturing the same according to this modification will be described below with reference to FIG. 33, focusing on the differences from the semiconductor light emitting device and a method for manufacturing the same according to Modification 5. FIG. 33 is a schematic top view of a wafer 10M showing the configuration of the transverse groove T1 according to this modification. FIG. 33 shows only a portion of the top view of a wafer 10M on which a semiconductor laminate 1S is stacked.

[0220] In this modified example, as shown in FIG. 33, the multiple cleavage lines L1 include a first cleavage line L11, a second cleavage line L12 and a third cleavage line L13 adjacent to the first cleavage line L11, and a fourth cleavage line L14 adjacent to the second cleavage line L12. The multiple parting lines L2 include a first parting line L21 and a second parting line L22 that extend from the first cleavage line L11 to the second cleavage line L12 and are two parting lines L2 adjacent to each other in the second direction, a third parting line L23 and a fourth parting line L24 that extend from the first cleavage line L11 to the third cleavage line L13 and are two parting lines L2 adjacent to each other in the second direction, and a fifth parting line L25 and a sixth parting line L26 that extend from the second cleavage line L12 to the fourth cleavage line L14 and are two parting lines L2 adjacent to each other in the second direction.

[0221] The multiple dividing lines L2 also include a seventh dividing line L27 adjacent to the first dividing line L21 in the second direction and disposed on the opposite side of the second dividing line L22 from the first dividing line L21. The multiple dividing lines L2 also include an eighth dividing line L28 adjacent to the third dividing line L23 in the second direction and disposed on the opposite side of the fourth dividing line L24 from the third dividing line L23. The multiple dividing lines L2 also include a ninth dividing line L29 adjacent to the fifth dividing line L25 in the second direction and disposed on the opposite side of the sixth dividing line L26 from the fifth dividing line L25.

[0222] The semiconductor laminate 1S is divided into a first region AR1 surrounded by a first parting line L21, a second parting line L22, a first cleavage line L11, and a second cleavage line L12, a second region AR2 surrounded by a third parting line L23, a fourth parting line L24, the first cleavage line L11, and a third cleavage line L13, and a third region AR3 surrounded by a fifth parting line L25, a sixth parting line L26, the second cleavage line L12, and a fourth cleavage line L14. R3, a fourth region AR4 surrounded by the first parting line L21, the seventh parting line L27, the first cleavage line L11, and the second cleavage line L12, a fifth region AR5 surrounded by the third parting line L23, the eighth parting line L28, the first cleavage line L11, and the third cleavage line L13, and a sixth region AR6 surrounded by the fifth parting line L25, the ninth parting line L29, the second cleavage line L12, and the fourth cleavage line L14.

[0223] The first region AR1 is adjacent to the second region AR2, the third region AR3, and the fifth region AR5 in the first direction. The fourth region AR4 is adjacent to the fifth region AR5 and the sixth region AR6 in the first direction. The first region AR1 is adjacent to the fourth region AR4 in the second direction. The second region AR2 is adjacent to the fifth region AR5 in the second direction. The third region AR3 is adjacent to the sixth region AR6 in the second direction. In this modification, as in modification 5, the position of the second region AR2 in the second direction is shifted by half the width of the first region AR1 and the second region AR2 in the second direction relative to the position of the first region AR1 in the second direction. Furthermore, the position of the fifth region AR5 in the second direction is shifted by half the width of the fourth region AR4 and the fifth region AR5 in the second direction relative to the position of the fourth region AR4 in the second direction. In this modified example, the positions of the third region AR3 and the sixth region AR6 in the second direction coincide with the positions of the first region AR1 and the fourth region AR4 in the second direction, respectively.

[0224] The multiple ridges R1 include a first ridge R11 and a second ridge R12, at least portions of which are disposed in the first region AR1. The multiple ridges R1 also include a second ridge R12, a sixth ridge R16, and a seventh ridge R17, at least portions of which are disposed in the second region AR2. The multiple ridges R1 also include a first ridge R11, a second ridge R12, and a third ridge R13, at least portions of which are disposed in the third region AR3. The multiple ridges R1 also include an eighth ridge R18 and a ninth ridge R19, at least portions of which are disposed in the fourth region AR4. The multiple ridges R1 also include a first ridge R11, a ninth ridge R19, and a fourth ridge R14, at least portions of which are disposed in the fifth region AR5. The multiple ridges R1 also include an eighth ridge R18, a ninth ridge R19, and a tenth ridge R20, at least portions of which are disposed in the sixth region AR6.

[0225] The first ridge R11 and the fourth ridge R14 are positioned at the same position in the second direction. The second ridge R12 and the third ridge R13 are positioned at the same position in the second direction. The sixth ridge R16 and the seventh ridge R17 are positioned at the same position in the second direction. The ninth ridge R19 and the tenth ridge R20 are positioned at the same position in the second direction.

[0226] The first ridge R11 intersects the first cleavage line L11, the second cleavage line L12, and the fourth cleavage line L14, and is continuously formed between the first cleavage line L11 and the fourth cleavage line L14, with at least a portion thereof disposed in the fifth region AR5. The second ridge R12 intersects the first cleavage line L11, the second cleavage line L12, and the third cleavage line L13, and is continuously formed between the second cleavage line L12 and the third cleavage line L13, with at least a portion thereof disposed in the third region AR3. The third ridge R13 intersects the fourth cleavage line L14, and at least a portion thereof disposed in the third region AR3. The fourth ridge R14 intersects the third cleavage line L13, and at least a portion thereof disposed in the fifth region AR5. The sixth ridge R16 intersects the first cleavage line L11 and at least a portion thereof is disposed in the second region AR2. The seventh ridge R17 intersects the third cleavage line L13 and at least a portion thereof is disposed in the second region AR2. The eighth ridge R18 intersects the first cleavage line L11, the second cleavage line L12, and the fourth cleavage line L14 and is continuously formed between the first cleavage line L11 and the fourth cleavage line L14. The ninth ridge R19 intersects the first cleavage line L11, the second cleavage line L12, and the third cleavage line L13 and is continuously formed between the second cleavage line L12 and the third cleavage line L13 and at least a portion thereof is disposed in the sixth region AR6. The tenth ridge R20 intersects with the fourth cleavage line L14, and at least a portion of the tenth ridge R20 is disposed in the sixth region AR6.

[0227] As in the method for manufacturing a semiconductor light-emitting device according to the above embodiment, each of the multiple transverse grooves T1 is formed continuously from the position in the second direction of one of the multiple parting lines L2 to the position in the second direction of one of the multiple parting lines L2 adjacent to that parting line L2. The multiple transverse grooves T1 include a first transverse groove T11 intersecting the first cleavage line L11 and the second cleavage line L12, a third transverse groove T13 intersecting the second cleavage line L12, and a fourth transverse groove T14 intersecting the fourth cleavage line L14, and each of the multiple transverse grooves T1 is spaced apart from the multiple parting grooves T2.

[0228] In this modified example, the first transverse groove T11 intersects the first cleavage line L11 between the dividing groove T2 including the fourth dividing line L24 and the sixth ridge R16, between the sixth ridge R16 (and the dividing groove T2 including the second dividing line L22) and the second ridge R12, between the second ridge R12 (and the dividing groove T2 including the third dividing line L23) and the first ridge R11, between the first ridge R11 (and the dividing groove T2 including the first dividing line L21) and the ninth ridge R19, and between the ninth ridge R19 (and the dividing groove T2 including the eighth dividing line L28) and the eighth ridge R18.

[0229] In addition, the first transverse trench T11 intersects with the second cleavage line L12 between the dividing trench T2 including the second dividing line L22 and the second ridge R12, between the second ridge R12 and the first ridge R11, between the first ridge R11 (and the dividing trench T2 including the first dividing line L21) and the ninth ridge R19, and between the ninth ridge R19 and the eighth ridge R18.

[0230] The third transverse trench T13 intersects with the third cleavage line L13 between the dividing trench T2 including the fourth dividing line L24 and the seventh ridge R17, between the seventh ridge R17 and the second ridge R12, between the second ridge R12 (and the dividing trench T2 including the third dividing line L23) and the fourth ridge R14, and between the fourth ridge R14 and the ninth ridge R19.

[0231] The fourth transverse trench T14 intersects with the fourth cleavage line L14 between the dividing trench T2 including the sixth dividing line L26 and the third ridge R13, between the third ridge R13 and the first ridge R11, between the first ridge R11 (and the dividing trench T2 including the fifth dividing line L25) and the tenth ridge R20, and between the tenth ridge R20 and the eighth ridge R18.

[0232] The first transverse trench T11 is disposed between the first ridge R11 and the third cleavage line L13. This prevents the first ridge R11 from being divided by the first transverse trench T11. Furthermore, the first transverse trench T11 is disposed between the second ridge R12 and the fourth cleavage line L14. This prevents the second ridge R12 from being divided by the first transverse trench T11. The first transverse trench T11 and the fourth transverse trench T14 are disposed between the third ridge R13 and the second cleavage line L12. This prevents the third ridge R13 from being divided by the first transverse trench T11 and the fourth transverse trench T14. Furthermore, the first transverse trench T11 and the third transverse trench T13 are disposed between the fourth ridge R14 and the first cleavage line L11. This prevents the fourth ridge R14 from being divided by the first transverse trench T11 and the third transverse trench T13. Furthermore, the first transverse trench T11 and the third transverse trench T13 are arranged between the sixth ridge R16 and the third cleavage line L13. This prevents the sixth ridge R16 from being divided by the first transverse trench T11 and the third transverse trench T13. Furthermore, the first transverse trench T11 and the third transverse trench T13 are arranged between the seventh ridge R17 and the first cleavage line L11. This prevents the seventh ridge R17 from being divided by the first transverse trench T11 and the third transverse trench T13. Furthermore, the first transverse trench T11 and the fourth transverse trench T14 are arranged between the ninth ridge R19 and the fourth cleavage line L14. This prevents the ninth ridge R19 from being divided by the first transverse trench T11 and the fourth transverse trench T14. The first transverse trench T11 and the fourth transverse trench T14 are arranged between the tenth ridge R20 and the second cleavage line L12. This makes it possible to prevent the tenth ridge R20 from being divided by the first transverse trench T11 and the fourth transverse trench T14.

[0233] As described above, the first ridge R11 and the second ridge R12 intersect the first cleavage line L11 and the second cleavage line L12, and are formed continuously between the first cleavage line L11 and the second cleavage line L12. This allows at least one of the first ridge R11 and the second ridge R12 to be used as the ridge R1 to which current is supplied in the semiconductor light emitting device 1 manufactured using the first region AR1 of the semiconductor laminate 1S.

[0234] As described above, the second ridge R12 intersects the first cleavage line L11 and the third cleavage line L13 and is formed continuously between the first cleavage line L11 and the third cleavage line L13. This allows the second ridge R12 to be used as the ridge R1 to which current is supplied in the semiconductor light emitting element 1 manufactured using the second region AR2 of the semiconductor laminate 1S.

[0235] As described above, the first ridge R11 intersects the second cleavage line L12 and the fourth cleavage line L14, and is formed continuously between the second cleavage line L12 and the fourth cleavage line L14. This allows the first ridge R11 to be used as the ridge R1 to which current is supplied in the semiconductor light emitting element 1 manufactured using the third region AR3 of the semiconductor laminate 1S.

[0236] As described above, the eighth ridge R18 and the ninth ridge R19 intersect the first cleavage line L11 and the second cleavage line L12 and are formed continuously between the first cleavage line L11 and the second cleavage line L12. This allows at least one of the eighth ridge R18 and the ninth ridge R19 to be used as the ridge R1 to which current is supplied in the semiconductor light-emitting device 1 manufactured using the fourth region AR4 of the semiconductor laminate 1S.

[0237] As described above, the ninth ridge R19 intersects with the first cleavage line L11 and the third cleavage line L13 and is formed continuously between the first cleavage line L11 and the third cleavage line L13. This allows the ninth ridge R19 to be used as the ridge R1 to which current is supplied in the semiconductor light emitting element 1 manufactured using the fifth region AR5 of the semiconductor laminate 1S.

[0238] As described above, the eighth ridge R18 intersects the second cleavage line L12 and the fourth cleavage line L14, and is continuously formed between the second cleavage line L12 and the fourth cleavage line L14. This allows the eighth ridge R18 to be used as the ridge R1 to which current is supplied in the semiconductor light emitting device 1 manufactured using the sixth region AR6 of the semiconductor laminate 1S.

[0239] Even in a configuration in which each of the multiple transverse grooves T1 intersects two or more cleavage lines L1, as in the semiconductor light-emitting element and manufacturing method thereof according to this modified example, the same effects as those of the semiconductor light-emitting element 1 and manufacturing method thereof according to this embodiment can be achieved.

[0240] [4-7. Modification 7] A semiconductor light emitting device and a manufacturing method thereof according to Modification 7 of the present embodiment will be described with reference to Fig. 34. Fig. 34 is a schematic top view of a wafer 10M showing the configuration of a transverse groove T1 according to this modification. Fig. 34 shows only a region corresponding to one semiconductor light emitting device 1 in the top view of the wafer 10M on which the semiconductor laminate 1S is stacked.

[0241] 34 , in a top view of the wafer 10M, each of the transverse grooves T1 may have a portion that is continuously formed between two adjacent cleavage lines L1 among the plurality of cleavage lines L1. In this modification, the transverse groove T1 extends in the first direction between two adjacent cleavage lines L1 among the plurality of cleavage lines L1 and has a portion that is continuously formed. This can further reduce the stress in the second direction of the semiconductor laminate 1S.

[0242] [4-8. Modification 8] A semiconductor light emitting device and a manufacturing method thereof according to Modification 8 of the present embodiment will be described with reference to Fig. 35. Fig. 35 is a schematic top view of a wafer 10M showing the configuration of end surface grooves T4 according to this modification. Fig. 35 shows only a region corresponding to one semiconductor light emitting device 1 out of the top view of the wafer 10M on which semiconductor laminates 1S are stacked.

[0243] As shown in FIG. 35 , a plurality of end surface grooves T4 may be formed along the plurality of cleavage lines L1. That is, the manufacturing method of the semiconductor light emitting device 1 according to this embodiment may include an end surface groove forming step of forming a plurality of end surface grooves T4 along the plurality of cleavage lines L1. Each of the plurality of end surface grooves T4 is continuously formed between two adjacent ridges R1. Each of the plurality of end surface grooves T4 is formed in a region along the plurality of cleavage lines L1 other than the region where the plurality of ridges R1 are formed. The plurality of end surface grooves T4 may be shallower than the transverse grooves T1 and the dividing grooves T2. The plurality of end surface grooves T4 may have the same depth as the ridge groove T3. Note that the depth of the region where the end surface groove T4 intersects with the transverse groove T1 is the depth of the transverse groove T1. The end surface groove forming step may be performed simultaneously with the ridge groove forming step. That is, the plurality of end surface grooves T4 may be formed in the same step as the plurality of ridge grooves T3.

[0244] The width of the end surface groove T4 in the first direction may be 5 μm or more and 20 μm or less. In this modification, the width of the end surface groove T4 in the first direction is about 12 μm.

[0245] Since the plurality of end surface grooves T4 extend in the second direction, similar to the transverse groove T1, they have the effect of reducing stress in the first direction of the semiconductor laminate 1S, similar to the transverse groove T1.

[0246] Another configuration example of this modified example will be described with reference to Fig. 36. Fig. 36 is a schematic top view of a wafer 10M showing the configuration of an end surface groove T4 according to another configuration example of this modified example. Fig. 36 shows only a region corresponding to one semiconductor light emitting element 1 in the top view of the wafer 10M on which the semiconductor laminate 1S is laminated.

[0247] 36, in the region surrounded by the transverse groove T1, the division groove T2, and the cleavage line L1, the ridge groove T3 may not have a portion extending in the first direction. In the configuration example shown in FIG. 36, in this region, the ridge R1 is formed only in the region sandwiched between the two end surface grooves T4. In the semiconductor light-emitting element 1 manufactured from such a wafer 10M, the ridge R1 formed only in the region sandwiched between the two end surface grooves T4 in this region becomes a dummy ridge R2.

[0248] The width of the end surface groove T4 in the first direction may be 5 μm or more and 20 μm or less. Furthermore, the widths of the two end surface grooves T4 adjacent to the dummy ridge R2 in the first direction may be different from each other. In this configuration example, the width of the end surface groove T4 in the first direction is approximately 12 μm.

[0249] In the above-described configuration example, the stress in the first direction of the semiconductor laminated body 1S can also be reduced.

[0250] [4-9. Modification 9] A semiconductor light emitting device and a manufacturing method thereof according to Modification 9 of the present embodiment will be described with reference to Fig. 37. Fig. 37 is a schematic top view of a wafer 10M according to this modification. Fig. 37 shows only a partial region of the top view of the wafer 10M on which the semiconductor laminate 1S is laminated.

[0251] 37 , in this modification, the ridge R1 formed continuously between two adjacent cleavage lines L1 is positioned equidistant from two adjacent parting lines L2. In this case, the ridge R1 of the semiconductor light-emitting element 1 to be manufactured is positioned at the center of the semiconductor light-emitting element 1 in the second direction, and the center of the dummy ridge R2 in the second direction is positioned at a position that divides the width of the semiconductor light-emitting element 1 in the second direction at a ratio of 1:3. This makes the heat dissipation of the semiconductor light-emitting element 1 in the second direction symmetrical with respect to the ridge R1. This makes it possible to equalize the heat dissipation of the semiconductor light-emitting element 1 in the second direction.

[0252] The ridge R1 of the semiconductor light emitting element 1 does not have to be positioned exactly at the center in the second direction of the semiconductor light emitting element 1. For example, the distance from the center in the second direction of the ridge R1 to the center in the second direction of the semiconductor light emitting element 1 may be less than ¼ of the width in the second direction of the semiconductor light emitting element 1. Even with such a configuration, the heat dissipation properties of the semiconductor light emitting element 1 in the second direction can be made uniform.

[0253] In this modification, as shown in FIG. 37 , the spacing between the multiple ridges R1 alternates in the second direction. This configuration allows the ridge R1 of the semiconductor light-emitting device 1 to be manufactured to be positioned near the center of the semiconductor light-emitting device 1 in the second direction. Furthermore, the spacing between two adjacent ridges R1 sandwiching one of the multiple parting lines L2 is twice the spacing between two adjacent ridges R1 in the second direction between two adjacent parting lines L2. This configuration allows the ridge R1 of the semiconductor light-emitting device 1 to be manufactured to be positioned near the center of the semiconductor light-emitting device 1 in the second direction.

[0254] Furthermore, in the semiconductor light emitting device 1 manufactured by this modification, four transverse grooves T1 are arranged symmetrically with respect to the ridge R1. Each of the transverse grooves T1 is formed continuously between the front end face or the rear end face (corresponding to the position of the cleavage line L1 in FIG. 37) and the side surface of the first stack or the side surface of the second stack (corresponding to the position of the parting line L2 in FIG. 37). This further improves the cleavability of the semiconductor light emitting device 1.

[0255] [4-10. Modification 10] A semiconductor light emitting device and a manufacturing method thereof according to Modification 10 of the present embodiment will be described with reference to Fig. 38. Fig. 38 is a schematic top view of a wafer 10M according to this modification. Fig. 38 shows only a partial region of the top view of the wafer 10M on which the semiconductor laminate 1S is laminated.

[0256] 38 , in the method for manufacturing the semiconductor light-emitting element 1 according to the above-described ninth modification, a ridge R1d surrounded by a ridge groove T3 may be further formed within the closed region surrounded by the transverse groove T1 and the dividing groove T2. The length of this ridge R1d in the first direction is shorter than the distance between two adjacent cleavage lines L1. By forming such a ridge R1d, two dummy ridges R2 are formed symmetrically with respect to the ridge R1 in the manufactured semiconductor light-emitting element 1. This further enhances the symmetry of the semiconductor laminate 1S in the second direction with respect to the ridge R1. This further enhances the cleavage property of the semiconductor light-emitting element 1.

[0257] [4-11. Modification 11] A semiconductor light emitting device and a method for manufacturing the same according to Modification 11 of this embodiment will be described. The semiconductor light emitting device and a method for manufacturing the same according to this modification differ from the semiconductor light emitting device and a method for manufacturing the same according to the above embodiment in the configuration of the multiple transverse grooves T1. The semiconductor light emitting device and a method for manufacturing the same according to this modification will be described below with reference to FIG. 39, focusing on the differences from the semiconductor light emitting device and a method for manufacturing the same according to the above embodiment. FIG. 39 is a schematic top view of a wafer 10M according to this modification. FIG. 39 shows only a partial region of the top view of the wafer 10M on which the semiconductor stack 1S is stacked.

[0258] 39, the plurality of transverse grooves T1 are formed continuously from the position in the second direction of one of the plurality of parting lines L2 to the position in the second direction of one of the parting lines L2 adjacent to that parting line in the second direction, as in the manufacturing method of the semiconductor light-emitting device according to the above embodiment. In the semiconductor light-emitting device and its manufacturing method according to this modification, the plurality of transverse grooves T1 include a first transverse groove T11, a second transverse groove T12, and a third transverse groove T13, as shown in FIG.

[0259] Each of the transverse trenches T1 according to this modification has at least one straight line portion that overlaps one cleavage line L1 and extends in the second direction. In this modification, each of the at least one straight line portion does not intersect with each of the ridges.

[0260] For example, the first transverse trench T11 includes at least one straight line portion that overlaps the first cleavage line L11 and extends in the second direction between the first parting line L21 and the second parting line L22. The at least one straight line portion included in the first transverse trench T11 does not intersect with either the first ridge R11 or the second ridge R12.

[0261] At least one straight line portion included in the first transverse groove T11 includes a first straight line portion T11L1 arranged between the first ridge R11 and the second ridge R12, a second straight line portion T11L2 arranged between the first ridge R11 and the first parting line L21, and a third straight line portion T11L3 arranged between the second ridge R12 and the second parting line L22. Here, the distance between the first ridge R11 and the first parting line L21 is narrower than the distance between the second ridge R12 and the first parting line L21. The distance between the second ridge R12 and the second parting line L22 is narrower than the distance between the first ridge R11 and the second parting line L22.

[0262] Furthermore, each of the transverse grooves T1 according to this modification has at least one ridge dividing portion, and in this modification, each of the at least one ridge dividing portion does not intersect with each of the plurality of ridges.

[0263] For example, the first transverse trench T11 includes a first ridge division portion T11D1 arranged between the first cleavage line L11 and the third cleavage line L13, and a second ridge division portion T11D2 arranged between the first cleavage line L11 and the second cleavage line L12.

[0264] At least a portion of the first ridge divider T11D1 is disposed between the first ridge R11 and the third cleavage line L13. In this modification, the first ridge divider T11D1 has a U-shape, including a portion that is disposed between the position of the first ridge R11 in the second direction and the position of the first parting line L21, a portion that is disposed between the first ridge R11 and the third cleavage line L13 (and the fourth ridge R14) and extends in the second direction, and a portion that is disposed between the first ridge R11 and the second ridge R12 and extends in the first direction. The first ridge divider T11D1 is connected to the first linear portion T11L1 and the second linear portion T11L2. More specifically, the first ridge divider T11D1 is connected to the end of the first linear portion T11L1 that is closer to the first ridge R11, and is also connected to the end of the second linear portion T11L2 that is closer to the first ridge R11.

[0265] At least a portion of the second ridge divider T11D2 is disposed between the second ridge R12 and the second cleavage line L12. In this modification, the second ridge divider T11D2 has a U-shape, including a portion disposed between the second ridge R12 and the second parting line L22 and extending in the first direction, a portion disposed between the second ridge R12 and the second cleavage line L12 (and the third ridge R13) and extending in the second direction, and a portion disposed between the first ridge R11 and the second ridge R12 and extending in the first direction. The second ridge divider T11D2 is connected to the first linear portion T11L1 and the third linear portion T11L3. More specifically, the second ridge divider T11D2 is connected to the end of the first linear portion T11L1 closer to the second ridge R12, and is also connected to the end of the third linear portion T11L3 closer to the second ridge R12. In this way, the position where the first ridge divider T11D1 is connected to the first straight portion T11L1 differs from the position where the second ridge divider T11D2 is connected to the first straight portion T11L1.

[0266] Similarly, the transverse grooves T1 other than the first transverse groove T11 also have at least one straight portion and at least one ridge dividing portion.

[0267] In this modification, the same effects as those of the semiconductor light emitting device and the manufacturing method thereof according to the above embodiment can be achieved. Furthermore, in this modification, the linear portion included in the transverse groove functions as a cleavage guide, thereby improving the flatness of the cleavage plane.

[0268] Since each straight line portion included in the first transverse trench T11 does not intersect with the first ridge R11, the first ridge R11 can be formed continuously from the first cleavage line L11 to the second cleavage line L12. Similarly, the other ridges can also be formed continuously between adjacent cleavage lines L1.

[0269] In this modification, the first transverse groove T11 includes a first linear portion T11L1, a second linear portion T11L2, and a third linear portion T11L3, but the configuration of the first transverse groove T11 is not limited to this. For example, the first transverse groove T11 according to this modification may include at least one of the first linear portion T11L1, the second linear portion T11L2, and the third linear portion T11L3.

[0270] In this modified example, a dividing groove T2 is formed at the location where the first dividing line L21 and the second dividing line L22 overlap, but the dividing groove T2 does not have to be formed at the location where the first dividing line L21 and the second dividing line L22 overlap.

[0271] [4-12. Modification 12] A semiconductor light emitting device and a method for manufacturing the same according to Modification 12 of the present embodiment will be described. The semiconductor light emitting device and a method for manufacturing the same according to this modification differ from the semiconductor light emitting device and a method for manufacturing the same according to Modification 4 in the configuration of the multiple transverse grooves T1. The semiconductor light emitting device and a method for manufacturing the same according to this modification will be described below with reference to FIG. 40, focusing on the differences from the semiconductor light emitting device and a method for manufacturing the same according to Modification 4. FIG. 40 is a schematic top view of a wafer 10M according to this modification. FIG. 40 shows only a partial region of the top view of the wafer 10M on which the semiconductor stack 1S is stacked.

[0272] 40 , the multiple transverse grooves T1 are formed continuously from the position in the second direction of one of the multiple parting lines L2 to the position in the second direction of one of the parting lines L2 adjacent to that parting line in the second direction, as in the manufacturing method of the semiconductor light-emitting device according to the above-described modified example 4. In the semiconductor light-emitting device and its manufacturing method according to this modified example, the multiple transverse grooves T1 include a first transverse groove T11, a second transverse groove T12, and a third transverse groove T13, as shown in FIG.

[0273] Each of the transverse trenches T1 according to this modification has at least one straight line portion that overlaps one cleavage line L1 and extends in the second direction. In this modification, each of the at least one straight line portion does not intersect with each of the ridges.

[0274] For example, the first transverse trench T11 includes at least one straight line portion that overlaps the first cleavage line L11 and extends in the second direction between the first parting line L21 and the second parting line L22. The at least one straight line portion included in the first transverse trench T11 does not intersect with either the first ridge R11 or the second ridge R12.

[0275] At least one straight line portion included in the first transverse groove T11 includes a first straight line portion T11L1 arranged between the first ridge R11 and the second ridge R12, a second straight line portion T11L2 arranged between the first ridge R11 and the first parting line L21, and a third straight line portion T11L3 arranged between the second ridge R12 and the second parting line L22. Here, the distance between the first ridge R11 and the first parting line L21 is narrower than the distance between the second ridge R12 and the first parting line L21. The distance between the second ridge R12 and the second parting line L22 is narrower than the distance between the first ridge R11 and the second parting line L22.

[0276] Furthermore, each of the transverse grooves T1 according to this modification has at least one ridge dividing portion, and in this modification, each of the at least one ridge dividing portion does not intersect with each of the plurality of ridges.

[0277] For example, the first transverse trench T11 includes a first ridge division portion T11D1 arranged between the first cleavage line L11 and the third cleavage line L13, and a second ridge division portion T11D2 arranged between the first cleavage line L11 and the second cleavage line L12.

[0278] At least a portion of the first ridge divider T11D1 is disposed between the first ridge R11 and the third cleavage line L13. In this modification, the first ridge divider T11D1 has a U-shape, including a portion that is disposed between the position of the first ridge R11 in the second direction and the position of the first parting line L21, a portion that is disposed between the first ridge R11 and the third cleavage line L13 (and the fourth ridge R14) and extends in the second direction, and a portion that is disposed between the first ridge R11 and the second ridge R12 and extends in the first direction. The first ridge divider T11D1 is connected to the first linear portion T11L1 and the second linear portion T11L2. More specifically, the first ridge divider T11D1 is connected to the end of the first linear portion T11L1 that is closer to the first ridge R11, and is also connected to the end of the second linear portion T11L2 that is closer to the first ridge R11.

[0279] At least a portion of the second ridge divider T11D2 is disposed between the second ridge R12 and the second cleavage line L12. In this modification, the second ridge divider T11D2 has a U-shape, including a portion disposed between the second ridge R12 and the second parting line L22 and extending in the first direction, a portion disposed between the second ridge R12 and the second cleavage line L12 (and the third ridge R13) and extending in the second direction, and a portion disposed between the first ridge R11 and the second ridge R12 and extending in the first direction. The second ridge divider T11D2 is connected to the first linear portion T11L1 and the third linear portion T11L3. More specifically, the second ridge divider T11D2 is connected to the end of the first linear portion T11L1 closer to the second ridge R12, and is also connected to the end of the third linear portion T11L3 closer to the second ridge R12. In this way, the position where the first ridge divider T11D1 is connected to the first straight portion T11L1 differs from the position where the second ridge divider T11D2 is connected to the first straight portion T11L1.

[0280] Similarly to the first transverse groove T11, the transverse grooves T1 other than the first transverse groove T11 also have at least one straight portion and at least one ridge dividing portion.

[0281] In this modification, the same effects as those of the semiconductor light emitting device and the manufacturing method thereof according to the above embodiment can be achieved. Furthermore, in this modification, the linear portion included in the transverse groove functions as a cleavage guide, thereby improving the flatness of the cleavage plane.

[0282] Since each straight line portion included in the first transverse trench T11 does not intersect with the first ridge R11, the first ridge R11 can be formed continuously from the first cleavage line L11 to the second cleavage line L12. Similarly, the other ridges can also be formed continuously between adjacent cleavage lines L1.

[0283] In this modification, the dividing grooves T2 are formed at the locations overlapping the respective dividing lines, but the dividing grooves T2 may not be formed.

[0284] [4-13. Modification 13] A semiconductor light emitting device and a method for manufacturing the same according to Modification 13 of the present embodiment will be described. The semiconductor light emitting device and a method for manufacturing the same according to this modification differ from the semiconductor light emitting device and a method for manufacturing the same according to Modification 12 in the configuration of the multiple transverse grooves T1. The semiconductor light emitting device and a method for manufacturing the same according to this modification will be described below with reference to FIG. 41, focusing on the differences from the semiconductor light emitting device and a method for manufacturing the same according to Modification 12. FIG. 41 is a schematic top view of a wafer 10M according to this modification. FIG. 41 shows only a partial region of the top view of the wafer 10M on which the semiconductor stack 1S is stacked.

[0285] 41 , the multiple transverse grooves T1 are formed continuously from the position in the second direction of one of the multiple parting lines L2 to the position in the second direction of one of the parting lines L2 adjacent to that parting line in the second direction, as in the manufacturing method of the semiconductor light-emitting element according to the above-described modification 12. As shown in FIG. 41 , the multiple transverse grooves T1 include a first transverse groove T11, a second transverse groove T12, and a third transverse groove T13.

[0286] Each of the multiple transverse grooves T1 in this modified example differs from the multiple transverse grooves T1 in modified example 12 in that it does not have a straight portion located between the part of the multiple ridges R1 that becomes the dummy ridge R2 of the semiconductor light-emitting element 1 and the adjacent (i.e., nearest) dividing line.

[0287] For example, the first transverse groove T11 according to this modification includes a first straight portion T11L1 and a second straight portion T11L2, but does not have a straight portion corresponding to the third straight portion T11L3.

[0288] The first transverse trench T11 according to this modification includes a first ridge divider T11D1 and a second ridge divider T11D2, similar to the first transverse trench T11 according to modification 12, but the configuration of each ridge divider is different from the configuration of each ridge divider according to modification 12.

[0289] At least a portion of the first ridge divider T11D1 is disposed between the first ridge R11 and the third cleavage line L13. In this modification, the first ridge divider T11D1 has a U-shape, including a portion that is disposed between the position of the first ridge R11 in the second direction and the position of the first parting line L21, a portion that is disposed between the first ridge R11 and the third cleavage line L13 (and the fourth ridge R14) and extends in the second direction, and a portion that is disposed between the first ridge R11 and the second ridge R12 and extends in the first direction. The first ridge divider T11D1 is connected to the first linear portion T11L1 and the second linear portion T11L2. More specifically, the first ridge divider T11D1 is connected to the end of the first linear portion T11L1 that is closer to the first ridge R11, and is also connected to the end of the second linear portion T11L2 that is closer to the first ridge R11.

[0290] The first ridge divider T11D1 according to this modification differs from the first ridge divider T11D1 according to modification 12 in that a portion thereof that is disposed between the first ridge R11 and the second ridge R12 and extends in the first direction overlaps with the dividing groove T2 that is disposed on the third parting line L23. A portion of the first ridge divider T11D1 is also a portion of the dividing groove T2 that is disposed on the third parting line L23.

[0291] At least a portion of the second ridge divider T11D2 is disposed between the second ridge R12 and the second cleavage line L12. In this modification, the second ridge divider T11D2 has a U-shape, including a portion disposed between the second ridge R12 and the second parting line L22 and extending in the first direction, a portion disposed between the second ridge R12 and the second cleavage line L12 (and the third ridge R13) and extending in the second direction, and a portion disposed between the first ridge R11 and the second ridge R12 and extending in the first direction. The second ridge divider T11D2 is connected to the first linear portion T11L1. More specifically, the second ridge divider T11D2 is connected to the end of the first linear portion T11L1 closer to the second ridge R12. Thus, the position where the first ridge divider T11D1 is connected to the first linear portion T11L1 differs from the position where the second ridge divider T11D2 is connected to the first linear portion T11L1. In this modification, the second dividing portion T11D2 is connected to a straight portion of the transverse trench T11 that is disposed between the second ridge R12 and the sixth ridge R16 and overlaps with the first cleavage line L11.

[0292] Furthermore, the second ridge separator T11D2 according to this modification differs from the second ridge separator T11D2 according to modification 12 in that a portion thereof that is disposed between the first ridge R11 and the second ridge R12 and extends in the first direction overlaps with the separator groove T2 that is disposed on the second parting line L22. A portion of the second ridge separator T11D2 is also a portion of the separator groove T2 that is disposed on the second parting line L22.

[0293] Similarly to the first transverse trench T11, the transverse trenches T1 other than the first transverse trench T11 also have at least one straight line portion and at least one ridge dividing portion.

[0294] In this modification, the same effects as those of the twelfth modification are achieved.

[0295] In this modification, the division grooves T2 are formed at locations overlapping with the division lines, but the division grooves T2 may not be formed. Such an example will be described with reference to FIG. 42. FIG. 42 is a schematic top view of a wafer 10M according to another configuration example of this modification. FIG. 42 shows only a partial region of the top view of the wafer 10M on which the semiconductor laminate 1S is laminated.

[0296] As shown in Fig. 42, the dividing grooves T2 may not be formed. In this case, the dividing grooves T2 are not formed on the respective dividing lines, but the respective crossing grooves are formed.

[0297] [4-14. Modification 14] A semiconductor light emitting device and a method for manufacturing the same according to Modification 14 of the present embodiment will be described. The semiconductor light emitting device and a method for manufacturing the same according to this modification differ from the semiconductor light emitting device and a method for manufacturing the same according to Modification 12 in the configuration of the multiple transverse grooves T1. The semiconductor light emitting device and a method for manufacturing the same according to this modification will be described below with reference to FIG. 43, focusing on the differences from the semiconductor light emitting device and a method for manufacturing the same according to Modification 12. FIG. 43 is a schematic top view of a wafer 10M according to this modification. FIG. 43 shows only a partial region of the top view of the wafer 10M on which the semiconductor stack 1S is stacked.

[0298] 43 , the multiple transverse grooves T1 are formed continuously from the position in the second direction of one of the multiple parting lines L2 to the position in the second direction of one of the parting lines L2 adjacent to that parting line in the second direction, as in the manufacturing method of the semiconductor light-emitting element according to the above-described modification 12. As shown in FIG. 43 , the multiple transverse grooves T1 include a first transverse groove T11, a second transverse groove T12, and a third transverse groove T13.

[0299] Each of the multiple transverse grooves T1 in this modified example differs from the multiple transverse grooves T1 in modified example 12 in that it does not have a straight portion located between the part of the multiple ridges R1 that becomes the ridge R1 of the semiconductor light-emitting element 1 and the adjacent dividing line.

[0300] For example, the first transverse groove T11 according to this modification includes a first straight portion T11L1 and a third straight portion T11L3, but does not have a straight portion corresponding to the second straight portion T11L2.

[0301] The first transverse trench T11 according to this modification includes a first ridge divider T11D1 and a second ridge divider T11D2, similar to the first transverse trench T11 according to modification 12, but the configuration of each ridge divider is different from the configuration of each ridge divider according to modification 12.

[0302] At least a portion of the first ridge divider T11D1 is disposed between the first ridge R11 and the third cleavage line L13. In this modification, the first ridge divider T11D1 has a U-shape, including a portion that is disposed at the position of the first parting line L21 in the second direction and extends in the first direction, a portion that is disposed between the first ridge R11 and the third cleavage line L13 (and the fourth ridge R14) and extends in the second direction, and a portion that is disposed between the first ridge R11 and the second ridge R12 and extends in the first direction. The position in the second direction of the portion of the first ridge divider T11D1 that is disposed between the first ridge R11 and the ninth ridge R19 and extends in the first direction corresponds to the position in the second direction of the first parting line L21.

[0303] The first ridge divider T11D1 is connected to the first straight portion T11L1. More specifically, the first ridge divider T11D1 is connected to the end of the first straight portion T11L1 that is closer to the first ridge R11. The first ridge divider T11D1 is connected to the straight portion of the transverse trench T11 that is disposed between the first ridge R11 and the ninth ridge R19 and overlaps with the first cleavage line L11.

[0304] At least a portion of the second ridge divider T11D2 is disposed between the second ridge R12 and the second cleavage line L12. In this modification, the second ridge divider T11D2 has a U-shape, including a portion disposed between the second ridge R12 and the second parting line L22 and extending in the first direction, a portion disposed between the second ridge R12 and the second cleavage line L12 (and the third ridge R13) and extending in the second direction, and a portion disposed between the first ridge R11 and the second ridge R12 and extending in the first direction. The position in the second direction of the portion of the second ridge divider T11D2 disposed between the first ridge R11 and the second ridge R12 and extending in the first direction overlaps with the position of the third parting line L23 in the second direction. The position in the second direction of the portion of the second ridge divider T11D2 disposed between the first ridge R11 and the second ridge R12 and extending in the first direction corresponds to the position of the third parting line L23 in the second direction.

[0305] The second ridge divider T11D2 is connected to the first straight portion T11L1 and the third straight portion T11L3. More specifically, the second ridge divider T11D2 is connected to the end of the first straight portion T11L1 closer to the second ridge R12, and is also connected to the end of the third straight portion T11L3 closer to the second ridge R12. In this way, the position where the first ridge divider T11D1 is connected to the first straight portion T11L1 differs from the position where the second ridge divider T11D2 is connected to the first straight portion T11L1.

[0306] Similarly to the first transverse groove T11, the transverse grooves T1 other than the first transverse groove T11 also have at least one straight portion and at least one ridge dividing portion.

[0307] In this modification, the same effects as those of the twelfth modification are achieved.

[0308] In this modification, the division grooves T2 are not formed, but the division grooves T2 may be formed along each division.

[0309] (Modifications, etc.) The semiconductor light emitting device and the method for manufacturing the semiconductor light emitting device according to the present disclosure have been described above based on the embodiments, but the present disclosure is not limited to the above-described embodiments.

[0310] For example, in each of the above-described embodiments, the semiconductor light-emitting element is a semiconductor laser element. However, the semiconductor light-emitting element is not limited to a semiconductor laser element. For example, the semiconductor light-emitting element may be a superluminescent diode. In this case, the reflectance of the front and rear end faces of the semiconductor stack included in the semiconductor light-emitting element with respect to light emitted from the semiconductor stack may be 0.1% or less. Such a reflectance can be achieved, for example, by forming an anti-reflection film made of a dielectric multilayer film on the front and rear end faces. Alternatively, if the ridge serving as the optical waveguide has an inclined stripe structure in which the ridge intersects with the front end facet 1F at an angle of 5° or more from the normal direction of the front end facet 1F, the proportion of the guided light reflected by the front end facet 1F that recouples with the optical waveguide and becomes guided light can be reduced to a small value of 0.1% or less.

[0311] Furthermore, although the semiconductor light emitting device in the above embodiment uses a nitride-based semiconductor material, the present disclosure is not limited to this example and can be applied to cases where a semiconductor material other than a nitride-based semiconductor material is used.

[0312] In the above embodiment, the multiple transverse grooves are spaced apart from one another, but two adjacent transverse grooves may be connected. For example, the first transverse groove T11 and the second transverse groove T12 shown in Fig. 13 may be connected in the first region. More specifically, the portions of the first transverse groove T11 and the second transverse groove T12 shown in Fig. 13 that extend in the second direction may be integrated.

[0313] In the semiconductor light emitting element 1 and the manufacturing method thereof according to the above embodiment, the dividing grooves T2 are formed in the semiconductor laminate 1S, but they may be formed on the lower surface of the wafer 10M (the main surface 10b of the substrate 10). In this case, the dividing grooves T2 are formed in a separate step from the crossing grooves T1.

[0314] In addition, in the method for manufacturing a semiconductor light emitting device, the step of forming the dividing grooves may be omitted.

[0315] In addition, this disclosure also includes forms obtained by applying various modifications to the above embodiments that a person skilled in the art would think of, and forms realized by arbitrarily combining the components and functions of each embodiment within the scope of the present disclosure.

[0316] The semiconductor light-emitting element according to the present disclosure is useful as a light source element for various products, including projectors, optical discs, vehicle headlamps, lighting devices, laser processing devices, and the like.

[0317] REFERENCE SIGNS LIST 1 Semiconductor light emitting element 1F Front end face 1R Rear end face 1S Semiconductor laminate 1Sa Side face of first laminate 1Sb Side face of second laminate 10 Substrate 10a, 10b Main surface 10M Wafer 10Mb Bar-shaped substrate 20 n-side semiconductor layer 21 Underlayer 22 Buffer layer 23 n-type cladding layer 24 n-side optical guide layer 30 Active layer 31 Barrier layer 32 Well layer 33 Barrier layer 40 p-side semiconductor layer 41 Electron barrier layer 42 First p-side optical guide layer 43 Second p-side optical guide layer 44 P-type cladding layer 45 Contact layer 50 Current blocking layer 50a Opening 62 P-side electrode 66 Pad electrode 70 N-side electrode AR1 First region AR2 Second region AR3 Third region AR4 Fourth region AR5 Fifth region AR6 Sixth region FD Broken line frame L1 Cleavage line L11 First cleavage line L12 Second cleavage line L13 Third cleavage line L14 Fourth cleavage line L2 Parting line L21 First parting line L22 Second parting line L23 Third parting line L24 Fourth parting line L25 Fifth dividing line L26 Sixth dividing line L27 Seventh dividing line L28 Eighth dividing line L29 Ninth dividing line P1 Projection R1, R1d Ridge R11 First ridge R12 Second ridge R13 Third ridge R14 Fourth ridge R15 Fifth ridge R16 Sixth ridge R17 Seventh ridge R18 Eighth ridge R19 Ninth ridge R20 10th ridge R2 Dummy ridges T1, T101, T102 Transverse groove T11 First transverse groove T11D1 First ridge dividing portion T11D2 Second ridge dividing portion T11L1 First straight portion T11L2 Second straight portion T11L3 Third straight portion T12 Second transverse groove T13 Third transverse groove T14 Fourth transverse groove T1a, T1b, T1c Linear groove T2 Dividing groove T3 Ridge groove T4 End surface groove Tc Intersection portion

Claims

1. A method for manufacturing a semiconductor light-emitting device, comprising: a growing step of growing a semiconductor laminate on a main surface of the wafer; a ridge groove forming step of forming a plurality of ridge grooves in the semiconductor laminate, the ridge grooves extending in a first direction parallel to a main surface of the wafer, to form a plurality of protrusions and a plurality of ridges extending in the first direction; a transverse groove forming step of forming a plurality of transverse grooves in the semiconductor laminate that are deeper than the plurality of ridge grooves; a cleaving step of forming a plurality of bar-shaped substrates by cleaving the wafer along a plurality of cleavage lines parallel to a second direction, the second direction being parallel to a main surface of the wafer and perpendicular to the first direction; a singulation step of dividing the plurality of bar-shaped substrates along a plurality of division lines parallel to the first direction, the semiconductor laminate includes an n-side semiconductor layer disposed above the wafer, an active layer disposed above the n-side semiconductor layer, and a p-side semiconductor layer disposed above the active layer; the plurality of ridge grooves are formed only in the p-side semiconductor layer of the semiconductor laminate, a height of the plurality of protrusions from the main surface of the wafer is equal to a height of the plurality of ridges from the main surface of the wafer, each of the plurality of ridges is adjacent to one of the plurality of protrusions via one of the plurality of ridge grooves; each of the plurality of transverse grooves is formed continuously from a position in the second direction of one of the plurality of dividing lines to a position in the second direction of one of the dividing lines adjacent to the one of the dividing lines, the plurality of cleavage lines include a first cleavage line, and a second cleavage line and a third cleavage line adjacent to the first cleavage line; The plurality of division lines are a first parting line and a second parting line extending from the first cleavage line to the second cleavage line and adjacent to each other in the second direction; a third parting line and a fourth parting line extending from the first cleavage line to the third cleavage line and being two parting lines adjacent to each other in the second direction; The semiconductor laminate is a first region surrounded by the first parting line, the second parting line, the first cleavage line, and the second cleavage line; a second region surrounded by the third parting line, the fourth parting line, the first cleavage line, and the third cleavage line, the first region is adjacent to the second region in the first direction, the plurality of ridges include a first ridge and a second ridge; the plurality of transverse grooves includes a first transverse groove that intersects with the first cleavage line; the first ridge intersects the first cleavage line and the second cleavage line, is continuously formed between the first cleavage line and the second cleavage line, and has at least a portion disposed in the second region; the second ridge intersects the first cleavage line and the third cleavage line and is at least partially disposed in the first region; The first transverse groove intersects the first cleavage line between the first ridge and the second ridge. A method for manufacturing a semiconductor light-emitting device.

2. A method for manufacturing a semiconductor light-emitting device, comprising: a growing step of growing a semiconductor laminate on a main surface of the wafer; a ridge groove forming step of forming a plurality of ridge grooves in the semiconductor laminate, the ridge grooves extending in a first direction parallel to a main surface of the wafer, to form a plurality of protrusions and a plurality of ridges extending in the first direction; a transverse groove forming step of forming a plurality of transverse grooves in the semiconductor laminate that are deeper than the plurality of ridge grooves; a cleaving step of forming a plurality of bar-shaped substrates by cleaving the wafer along a plurality of cleavage lines parallel to a second direction, the second direction being parallel to a main surface of the wafer and perpendicular to the first direction; a singulation step of dividing the plurality of bar-shaped substrates along a plurality of division lines parallel to the first direction, the semiconductor laminate includes an n-side semiconductor layer disposed above the wafer, an active layer disposed above the n-side semiconductor layer, and a p-side semiconductor layer disposed above the active layer; the plurality of ridge grooves are formed only in the p-side semiconductor layer of the semiconductor laminate, a height of the plurality of protrusions from the main surface of the wafer is equal to a height of the plurality of ridges from the main surface of the wafer, each of the plurality of ridges is adjacent to one of the plurality of protrusions via one of the plurality of ridge grooves; the plurality of cleavage lines include a first cleavage line, and a second cleavage line and a third cleavage line adjacent to the first cleavage line; The plurality of division lines are a first parting line and a second parting line extending from the first cleavage line to the second cleavage line and adjacent to each other in the second direction; a third parting line and a fourth parting line extending from the first cleavage line to the third cleavage line and being two parting lines adjacent to each other in the second direction; The semiconductor laminate is a first region surrounded by the first parting line, the second parting line, the first cleavage line, and the second cleavage line; a second region surrounded by the third parting line, the fourth parting line, the first cleavage line, and the third cleavage line, the first region is adjacent to the second region in the first direction, the plurality of ridges include a first ridge and a second ridge; the plurality of transverse grooves includes a first transverse groove that intersects with the first cleavage line; the first ridge intersects the first cleavage line and the second cleavage line, is continuously formed between the first cleavage line and the second cleavage line, and has at least a portion disposed in the second region; the second ridge intersects the first cleavage line and the third cleavage line and is at least partially disposed in the first region; the first transverse groove intersects the first cleavage line between the first ridge and the second ridge; the first transverse groove is disposed between the first ridge and the third cleavage line; the second ridge intersects the first cleavage line and the third cleavage line and is formed continuously between the first cleavage line and the third cleavage line; The first transverse groove is disposed between the second ridge and the second cleavage line. A method for manufacturing a semiconductor light-emitting device.

3. The first transverse groove is disposed between the second ridge and the second cleavage line. The method for manufacturing the semiconductor light emitting device according to claim 1 .

4. the plurality of ridges includes a third ridge at least partially disposed in the first region; In the first region, the third ridge intersects with the second cleavage line; the first transverse groove is disposed between the second ridge and the third ridge; At least one of the plurality of protrusions is disposed in at least one of a region between the first transverse groove and the second ridge and a region between the first transverse groove and the third ridge. The method for manufacturing a semiconductor light emitting device according to claim 3 .

5. the plurality of cleavage lines includes a fourth cleavage line adjacent to the second cleavage line, the plurality of parting lines extend from the second cleavage line to the fourth cleavage line and include a fifth parting line and a sixth parting line which are two parting lines adjacent to each other in the second direction; The semiconductor laminate is a third region surrounded by the fifth parting line, the sixth parting line, the second cleavage line, and the fourth cleavage line; the first region is adjacent to the third region in the first direction, the plurality of transverse grooves include a second transverse groove that intersects with the second cleavage line; the first ridge is at least partially disposed in the third region; the second transverse groove is disposed between the first ridge and the fourth cleavage line; the second transverse groove is disposed between the third ridge and the first cleavage line; The second transverse groove intersects the second cleavage line between the first ridge and the third ridge. The method for manufacturing a semiconductor light emitting device according to claim 4 .

6. The first transverse groove intersects with the second dividing line. The method for manufacturing a semiconductor light-emitting device according to any one of claims 1 and 3 to 5.

7. the plurality of transverse grooves include a second transverse groove that intersects with the second cleavage line; The second transverse groove intersects with the second dividing line. The method for manufacturing a semiconductor light-emitting device according to any one of claims 1 and 3 to 5.

8. The first transverse groove intersects with the third dividing line. The method for manufacturing a semiconductor light-emitting device according to any one of claims 1 and 3 to 5.

9. The first transverse groove is disposed between the first ridge and the third cleavage line. The method for manufacturing a semiconductor light-emitting device according to any one of claims 1 and 3 to 5.

10. The second ridge intersects the first cleavage line and the third cleavage line and is formed continuously between the first cleavage line and the third cleavage line. The method for manufacturing a semiconductor light-emitting device according to any one of claims 1 and 3 to 5.

11. a division groove forming step of forming a plurality of division grooves in the semiconductor laminate along the plurality of division lines, The plurality of dividing grooves are deeper than the plurality of ridge grooves. The method for manufacturing a semiconductor light-emitting device according to any one of claims 1 to 5.

12. Two adjacent transverse grooves among the plurality of transverse grooves and two adjacent dividing grooves among the plurality of dividing grooves form a closed region. The method for manufacturing a semiconductor light emitting device according to claim 11 .

13. The depth of the plurality of dividing grooves is greater than the thickness of the p-side semiconductor layer. The method for manufacturing a semiconductor light emitting device according to claim 11 .

14. The depth of the plurality of dividing grooves is greater than the thickness of the semiconductor laminate. The method for manufacturing a semiconductor light-emitting device according to claim 13 .

15. the plurality of dividing lines are periodically arranged, The plurality of cleavage lines are periodically arranged. The method for manufacturing a semiconductor light-emitting device according to any one of claims 1 to 5.

16. The sum of the area of ​​the upper surfaces of the plurality of ridges and the area of ​​the upper surfaces of the plurality of protrusions is 80% or more of the area of ​​the upper surface of the semiconductor laminate. The method for manufacturing a semiconductor light-emitting device according to any one of claims 1 to 5.

17. further comprising an end surface groove forming step of forming a plurality of end surface grooves along the plurality of cleavage lines; each of the plurality of end surface grooves is formed continuously between two adjacent ridges among the plurality of ridges, Each of the plurality of end surface grooves is formed in a region along the plurality of cleavage lines other than the region in which the plurality of ridges are formed. The method for manufacturing a semiconductor light-emitting device according to any one of claims 1 to 5.

18. The depth of the plurality of transverse grooves is greater than the thickness of the p-side semiconductor layer. The method for manufacturing a semiconductor light-emitting device according to any one of claims 1 to 5.

19. The depth of the plurality of transverse grooves is greater than the thickness of the semiconductor laminate. The method for manufacturing a semiconductor light-emitting device according to any one of claims 1 to 5.

20. The width of each of the plurality of transverse grooves is greater in a portion extending in the second direction than in a portion extending in the first direction. The method for manufacturing a semiconductor light-emitting device according to any one of claims 1 to 5.

21. When viewed from above, the wafer: Each of the plurality of transverse grooves is composed of a plurality of connected linear grooves, The angle between two connected linear grooves among the plurality of linear grooves is 90 degrees or more. The method for manufacturing a semiconductor light-emitting device according to any one of claims 1 to 5.

22. When viewed from above, each of the plurality of transverse grooves has no corners. The method for manufacturing a semiconductor light-emitting device according to any one of claims 1 to 5.

23. When viewed from above, the wafer has curved edges of the plurality of protrusions that face intersections between the plurality of transverse grooves and the plurality of dividing grooves. The method for manufacturing a semiconductor light emitting device according to claim 11 .

24. When viewed from above, the wafer has edges of the plurality of protrusions that face intersections where the plurality of transverse grooves and the plurality of dividing grooves intersect, and the edges of the edges of the plurality of protrusions form an inner angle of 90 degrees or more. The method for manufacturing a semiconductor light emitting device according to claim 11 .

25. The plurality of ridges are arranged at equal intervals in the second direction. The method for manufacturing a semiconductor light-emitting device according to any one of claims 1 to 5.

26. The spacing between the ridges alternates in the second direction. The method for manufacturing a semiconductor light-emitting device according to any one of claims 1 to 5.

27. A distance between two adjacent ridges among the plurality of ridges sandwiching one of the plurality of parting lines is twice the distance between two adjacent ridges among the plurality of ridges in the second direction between two adjacent parting lines among the plurality of ridges. The method for manufacturing a semiconductor light-emitting device according to claim 26.

28. The width of each of the plurality of protrusions in the second direction is 4 μm or more. The method for manufacturing a semiconductor light-emitting device according to any one of claims 1 to 5.

29. the wafer comprises GaN; The n-side semiconductor layer and the p-side semiconductor layer contain AlGaN. The method for manufacturing a semiconductor light-emitting device according to any one of claims 1 to 5.

30. The integrated stress of the semiconductor laminate on the wafer is −500 Pa·m or less The method for manufacturing a semiconductor light-emitting device according to any one of claims 1 to 5.

31. A method for manufacturing a semiconductor light-emitting device, comprising: a growing step of growing a semiconductor laminate on a main surface of the wafer; a ridge forming step of forming a plurality of ridges extending in a first direction parallel to a main surface of the wafer; a transverse groove forming step of forming a plurality of transverse grooves in the semiconductor laminate; a cleaving step of forming a plurality of bar-shaped substrates by cleaving the wafer along a plurality of cleavage lines parallel to a second direction, the second direction being parallel to a main surface of the wafer and perpendicular to the first direction; a singulation step of dividing the plurality of bar-shaped substrates along a plurality of division lines parallel to the first direction, the semiconductor laminate includes an n-side semiconductor layer disposed above the wafer, an active layer disposed above the n-side semiconductor layer, and a p-side semiconductor layer disposed above the active layer; the plurality of cleavage lines include a first cleavage line, and a second cleavage line and a third cleavage line adjacent to the first cleavage line; The plurality of division lines are a first parting line and a second parting line extending from the first cleavage line to the second cleavage line and adjacent to each other in the second direction; a third parting line and a fourth parting line extending from the first cleavage line to the third cleavage line and being two parting lines adjacent to each other in the second direction; The semiconductor laminate is a first region surrounded by the first parting line, the second parting line, the first cleavage line, and the second cleavage line; a second region surrounded by the third parting line, the fourth parting line, the first cleavage line, and the third cleavage line, the first region is adjacent to the second region in the first direction, the plurality of ridges include a first ridge and a second ridge; the plurality of transverse grooves includes a first transverse groove that intersects with the first cleavage line; The first transverse groove is a first ridge dividing portion disposed between the first cleavage line and the third cleavage line; a second ridge dividing portion disposed between the first cleavage line and the second cleavage line; at least one linear portion that overlaps the first cleavage line and extends in the second direction between the first parting line and the second parting line; the first ridge intersects the first cleavage line and the second cleavage line, is continuously formed between the first cleavage line and the second cleavage line, and has at least a portion disposed in the second region; the second ridge intersects the first cleavage line and the third cleavage line and is at least partially disposed in the first region; the first transverse groove intersects the first cleavage line between the first ridge and the second ridge; at least a portion of the first ridge dividing portion is disposed between the first ridge and the third cleavage line; at least a portion of the second ridge dividing portion is disposed between the second ridge and the second cleavage line; the second ridge intersects the first cleavage line and the third cleavage line and is formed continuously between the first cleavage line and the third cleavage line; the at least one straight portion does not intersect with the first ridge; The at least one straight line portion does not intersect with the second ridge. A method for manufacturing a semiconductor light-emitting device.

32. The at least one linear portion includes a first linear portion disposed between the first ridge and the second ridge. The method for manufacturing a semiconductor light-emitting device according to claim 31 .

33. the first ridge segment is connected to the first linear portion; The second ridge segment is connected to the first linear portion. The method for manufacturing a semiconductor light-emitting device according to claim 32.

34. The position where the first ridge dividing portion is connected to the first linear portion is The second ridge dividing portion is connected to the first linear portion at a position different from the position where the second ridge dividing portion is connected to the first linear portion. The method for manufacturing a semiconductor light-emitting device according to claim 33.

35. a distance between the first ridge and the first dividing line is narrower than a distance between the second ridge and the first dividing line; The at least one linear portion includes a second linear portion disposed between the first ridge and the first parting line. The method for manufacturing a semiconductor light-emitting element according to any one of claims 31 to 34.

36. The first ridge segment is connected to the second linear portion. The method for manufacturing a semiconductor light-emitting device according to claim 35.

37. a distance between the second ridge and the second dividing line is narrower than a distance between the first ridge and the second dividing line; The at least one linear portion includes a third linear portion disposed between the second ridge and the second parting line. The method for manufacturing a semiconductor light-emitting element according to any one of claims 31 to 34.

38. The second ridge segment is connected to the third linear portion. The method for manufacturing a semiconductor light-emitting device according to claim 37.

39. A method for manufacturing a semiconductor light-emitting device, comprising: a growing step of growing a semiconductor laminate on a main surface of the wafer; a ridge forming step of forming a plurality of ridges extending in a first direction parallel to a main surface of the wafer; a transverse groove forming step of forming a plurality of transverse grooves in the semiconductor laminate; a cleaving step of forming a plurality of bar-shaped substrates by cleaving the wafer along a plurality of cleavage lines parallel to a second direction, the second direction being parallel to a main surface of the wafer and perpendicular to the first direction; a singulation step of dividing the plurality of bar-shaped substrates along a plurality of division lines parallel to the first direction, the semiconductor laminate includes an n-side semiconductor layer disposed above the wafer, an active layer disposed above the n-side semiconductor layer, and a p-side semiconductor layer disposed above the active layer; each of the plurality of transverse grooves is formed continuously from a position in the second direction of one of the plurality of dividing lines to a position in the second direction of one of the dividing lines adjacent to the one of the dividing lines, the plurality of cleavage lines include a first cleavage line, and a second cleavage line and a third cleavage line adjacent to the first cleavage line; The plurality of division lines are a first parting line and a second parting line extending from the first cleavage line to the second cleavage line and adjacent to each other in the second direction; a third parting line and a fourth parting line extending from the first cleavage line to the third cleavage line and being two parting lines adjacent to each other in the second direction; The semiconductor laminate is a first region surrounded by the first parting line, the second parting line, the first cleavage line, and the second cleavage line; a second region surrounded by the third parting line, the fourth parting line, the first cleavage line, and the third cleavage line, the first region is adjacent to the second region in the first direction, the plurality of ridges include a first ridge and a second ridge; the plurality of transverse grooves includes a first transverse groove that intersects with the first cleavage line; the first transverse groove includes at least one straight line portion between the first parting line and the second parting line, the straight line portion overlapping the first cleavage line and extending in the second direction; the first ridge intersects the first cleavage line and the second cleavage line, is continuously formed between the first cleavage line and the second cleavage line, and has at least a portion disposed in the second region; the second ridge intersects the first cleavage line and the third cleavage line and is at least partially disposed in the first region; each of the at least one straight portion does not intersect with the first ridge; each of the at least one straight line portion does not intersect with the second ridge; The first transverse groove intersects the first cleavage line between the first ridge and the second ridge. A method for manufacturing a semiconductor light-emitting device.

40. an n-type substrate; a semiconductor laminate disposed on the main surface of the substrate, The semiconductor laminate is an n-side semiconductor layer disposed above the substrate; an active layer disposed above the n-side semiconductor layer; a p-side semiconductor layer disposed above the active layer; the semiconductor laminate has a front end surface and a rear end surface that are respectively disposed at one end and the other end in a first direction that is parallel to the main surface of the substrate, and a first laminate side surface and a second laminate side surface that are respectively disposed at one end and the other end in a second direction that is parallel to the main surface of the substrate and perpendicular to the first direction; The semiconductor laminate is a plurality of ridge grooves formed only in the p-side semiconductor layer of the semiconductor laminate and extending in the first direction; a ridge disposed between two adjacent ridge grooves among the plurality of ridge grooves and to which a current is supplied; a protrusion disposed adjacent to the ridge with one of the two ridge grooves interposed therebetween; a first dummy ridge disposed between two ridge grooves other than the two ridge grooves among the plurality of ridge grooves, and to which no current is supplied; a first transverse groove formed continuously between one of the front end surface and the rear end surface and the first stack side surface, the first transverse groove being deeper than the plurality of ridge grooves; The height of the protrusion from the substrate is equal to the height of the ridge from the substrate. Semiconductor light emitting element.

41. The ridge is formed continuously between the front end surface and the rear end surface. The semiconductor light emitting device according to claim 40.

42. The semiconductor stack has a dividing groove extending in the first direction along each of the first stack side surface and the second stack side surface.

42. The semiconductor light-emitting device according to claim 40 or 41.

43. The center of the ridge in the second direction is disposed at a position that divides the width of the semiconductor light emitting element in the second direction at a ratio of 3:

1.

42. The semiconductor light-emitting device according to claim 40 or 41.

44. The distance from the center of the ridge in the second direction to the center of the semiconductor light emitting element in the second direction is less than ¼ of the width of the semiconductor light emitting element in the second direction.

42. The semiconductor light-emitting device according to claim 40 or 41.

45. the ridge is disposed at the center of the semiconductor light emitting element in the second direction, The center of the first dummy ridge in the second direction is disposed at a position that divides the width of the semiconductor light emitting element in the second direction at a ratio of 1:

3.

42. The semiconductor light-emitting device according to claim 40 or 41.

46. The width of the protrusion in the second direction is 4 μm or more.

42. The semiconductor light-emitting device according to claim 40 or 41.

47. The first transverse groove is connected to one of the front end surface and the rear end surface between the ridge and the first dummy ridge.

42. The semiconductor light-emitting device according to claim 40 or 41.

48. The semiconductor laminate is a second dummy ridge disposed between two ridge grooves other than the two ridge grooves among the plurality of ridge grooves, and to which no current is supplied; a second transverse groove formed continuously between the other of the front end surface and the rear end surface and the side surface of the first stack, the second transverse groove being deeper than the plurality of ridge grooves; 42. The semiconductor light-emitting device according to claim 40 or 41.