Semiconductor device

Abstract

In the present invention, a plurality of semiconductor switches (51-5n) are connected between a plurality of power generation elements (11-1n) and a power supply node (PL2). A switch selection circuit (30) outputs a plurality of control signals (Sa1-San) for controlling ON / OFF of the plurality of semiconductor switches (51-5n) in order to select one from among the plurality of power generation elements (11-1n) and connect the same to the power supply node (PL2). A control voltage generation circuit (40) generates a plurality of control voltages (Sb1-Sbn) to be inputted to control electrodes of the plurality of semiconductor switches (51-5n) in accordance with the plurality of control signals (Sa1-San). The control voltage generation circuit (40) changes the respective control voltages (Sb1-Sbn) at a first speed when turning off the respective semiconductor switches (51-5n), and changes the respective control voltages (Sb1-Sbn) at a second speed slower than the first speed when turning on the respective semiconductor switches (51-5n).

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Semiconductor devices that use multiple power sources by switching between them are currently in use. In these semiconductor devices, the multiple power sources can be selectively used by controlling the on / off of multiple semiconductor switches provided corresponding to the multiple power sources. With this configuration, when multiple energy harvesting elements are used as power sources to utilize energy generated in nature, such as sunlight, magnetic fields, and vibrations, as stand-alone power sources, a continuous power supply can be achieved by selectively using the energy harvesting elements that are generating power.

[0003] In such a semiconductor device, when switching between power supplies, it is preferable to control the on / off of the semiconductor switch so that the outputs of the power supplies are not shorted together and unnecessary current does not flow between the power supplies.

[0004] For example, Japanese Patent No. 5924173 (Patent Document 1) describes a control for eliminating a period in which two or more semiconductor switches are turned on when switching the selected power source in a power source selection circuit having multiple semiconductor switches connected between multiple power sources and an electrical circuit to which power is to be supplied.

[0005] Specifically, the power supply selection circuit in Patent Document 1 describes a control in which, when switching the power supply to be selected, a signal indicating that an OFF command signal has been output to all semiconductor switches is fed back with a predetermined delay time, and then an ON command signal is output to a semiconductor switch connected between the selected power supply and the electric circuit. As a result, an ON command signal for one semiconductor switch is generated after a period in which all semiconductor switches are OFF, thereby preventing multiple semiconductor switches from being ON simultaneously.

[0006] Patent No. 5924173

[0007] However, in the power supply selection circuit of Patent Document 1, by proactively setting a period in which all semiconductor switches are turned off, no voltage is supplied to the electric circuit (the power supply target) from any power supply, and a period occurs in which the power supply impedance becomes very large. If the electric circuit consumes current during this period, the power supply voltage of the electric circuit will drop suddenly, which may affect the operation of the electric circuit.

[0008] Furthermore, if the power supply voltage suddenly changes when a selected semiconductor switch is turned on after a period in which all semiconductor switches are turned off, there is a concern that the operation of the electrical circuit (the object to which power is supplied) may be affected.

[0009] The present disclosure has been made to solve such problems, and an object of the present disclosure is to improve the operating characteristics of a semiconductor device that selectively uses multiple power sources by switching the connection of the semiconductor switch when the connection of the semiconductor switch is switched.

[0010] According to one aspect of the present invention, there is provided a semiconductor device. The semiconductor device includes a plurality of first semiconductor switches, a switch selection circuit, a control voltage generation circuit, and an internal circuit. The internal circuit operates using a voltage of a power supply node. The plurality of first semiconductor switches are respectively connected between a plurality of power supplies and the power supply node. The switch selection circuit selects one of the plurality of power supplies and outputs a plurality of control signals that respectively control the on / off of the plurality of first semiconductor switches so as to turn on a first semiconductor switch corresponding to the selected one of the plurality of first semiconductor switches. The control voltage generation circuit generates a plurality of control voltages that are input to control electrodes of the plurality of first semiconductor switches in response to the plurality of control signals. The control voltage generation circuit changes each of the plurality of control voltages at a first speed when changing each of the plurality of first semiconductor switches from on to off, and changes each of the plurality of control voltages at a second speed slower than the first speed when changing each of the plurality of first semiconductor switches from off to on, in response to the plurality of control signals.

[0011] According to the present disclosure, in a semiconductor device that selectively uses multiple power sources, when the connection of the first semiconductor switch is switched, the turn-off speed of each first semiconductor switch is made higher than the turn-on speed, thereby preventing a decrease in impedance between the power sources via the first semiconductor switch and suppressing the period of insufficient voltage supply from the multiple power sources, thereby improving the operating characteristics when the connection of the semiconductor switch is switched.

[0012] 14 is a block diagram illustrating a configuration of a semiconductor device according to a first embodiment. FIG. 15 is a circuit diagram illustrating a configuration example of a semiconductor switch in FIG. 1. FIG. 16 is a circuit diagram illustrating a configuration example of a slew rate adjustment circuit in FIG. 1. FIG. 17 is a circuit diagram illustrating a configuration example of a process start control circuit in FIG. 4. FIG. 4 is a waveform diagram illustrating an operation example of the process start control circuit in FIG. 4. FIG. 4 is a waveform diagram illustrating an operation example of the semiconductor device according to the first embodiment. FIG. 4 is a conceptual waveform diagram illustrating a change in impedance when a semiconductor switch of the semiconductor device according to the first embodiment is switched on and off. FIG. 17 is a block diagram illustrating a configuration of a semiconductor device according to a second embodiment. FIG. 4 is a waveform diagram illustrating an operation example of the semiconductor device according to the second embodiment. FIG. 4 is a first waveform diagram illustrating circuit operation of the semiconductor device according to the second embodiment. FIG. 4 is a second waveform diagram illustrating circuit operation of the semiconductor device according to the second embodiment. FIG. 17 is a block diagram illustrating a configuration of a semiconductor device according to a third embodiment. FIG. 4 is a waveform diagram illustrating an operation example of the semiconductor device according to the third embodiment. FIG. 4 is a block diagram illustrating a configuration of a semiconductor device according to a fourth embodiment. FIG. 18 is a circuit diagram illustrating a configuration example of a switch-on detection circuit in FIG. 14. FIG. 19 is a waveform diagram illustrating an operation example of the semiconductor device according to the fourth embodiment.

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings will be denoted by the same reference numerals, and their description will not be repeated in principle.

[0014] First Embodiment Fig. 1 is a block diagram illustrating the configuration of a semiconductor device 110A according to a first embodiment.

[0015] 1, the semiconductor device 110A selectively switches between and uses a plurality of power generating elements 11 to 1 n. The power generating elements 11 to 1 n correspond to one example of "a plurality of power sources." For example, each of the power generating elements 11 to 1 n is configured as an energy harvesting element that utilizes energy generated in nature, such as sunlight, magnetic fields, and vibrations, as a stand-alone power source.

[0016] The output sides of the power generating elements 11 to 1n are connected to input power supply lines PL11 to PL1n, respectively. Zener diodes and shunt regulators (not shown) are disposed on the input power supply lines PL11 to PL1n, and the input voltages Vin1 to Vinn of the input power supply lines PL11 to PL1n may be clipped so as not to exceed a certain voltage.

[0017] The semiconductor device 110A includes power supply detection circuits 21 to 2n, a switch selection circuit 30, a slew rate adjustment circuit 40, semiconductor switches 51 to 5n, a constant voltage circuit 60, a process start control circuit 70, and a circuit block 80 as an "internal circuit."

[0018] In general, the semiconductor device 110A inputs an input voltage from a selected one of the power generating elements 11 to 1 n to the power supply node PL2 by turning on one of the semiconductor switches 51 to 5 n. The circuit block 80 operates using, as a power supply voltage, an output voltage Vout generated by a constant voltage circuit 60 that receives the voltage Vsup of the power supply node PL2.

[0019] The circuit configuration will be described in detail below. The power supply detection circuits 21 to 2n are arranged to detect when the voltages of the input power supply lines PL11 to PL1n (input voltages Vin1 to Vinn) rise to a predetermined voltage. When the input voltages Vin1 to Vinn rise to a predetermined voltage, the power supply detection circuits 21 to 2n generate power supply detection signals Sd1 to Sdn, respectively. For example, when the input voltages Vin1 to Vinn rise, the power supply detection signals Sd1 to Sdn change from a logical low level (hereinafter simply referred to as an "L level") to a logical high level (hereinafter simply referred to as an "H level").

[0020] The input voltages Vin1 to Vinn from the power generating elements 11 to 1n, respectively, are supplied as power supplies and H-level voltages to the switch selection circuit 30 and the slew rate adjustment circuit 40. In the switch selection circuit 30 and the slew rate adjustment circuit 40, the ground voltage GND from the ground is set to an L-level voltage.

[0021] The power supply detection signals Sd1 to Sdn from the power supply detection circuits 21 to 2n are input to the switch selection circuit 30. The switch selection circuit 30 receives the power supply detection signals Sd1 to Sdn and the processing completion signal Scpl from the circuit block 80, and generates control signals Sa1 to San to turn on one of the semiconductor switches 51 to 5n while turning off the remaining (n-1) semiconductor switches.

[0022] The semiconductor switches 51 to 5n are connected between the input power supply lines PL11 to PL1n and the power supply node PL2, respectively. The semiconductor switches 51 to 5n correspond to the "plurality of first semiconductor switches."

[0023] 2 is a circuit diagram illustrating an example of the configuration of a semiconductor switch. In FIG. 2, input power supply line PL1 collectively refers to input power supply lines PL1 to PL1n, semiconductor switch 5 collectively refers to semiconductor switches 51 to 5n, and control voltage Sb collectively refers to control voltages Sb1 to Sbn.

[0024] The semiconductor switch 5 has P-type transistors MP0 and MP1 connected in series between the input power supply line PL1 and the power supply node PL2. The transistors MP0 and MP1 can be configured by field effect transistors such as MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors).

[0025] The transistor MP0 has a drain (first electrode) connected to the input power supply line PL1 and a gate (control electrode) that receives the control voltage Sb from the slew rate adjustment circuit 40. The transistor MP1 has a drain (first electrode) connected to the power supply node PL2 and a gate (control electrode) that receives the control voltage Sb from the slew rate adjustment circuit 40. The sources (second electrodes) of the transistors MP0 and MP1 are connected to each other.

[0026] Each of the P-type transistors MP0 and MP1 is turned off when a control voltage Sb corresponding to the gate voltage is at H level (input voltage Vin), and turned on when it is at L level (ground voltage GND).

[0027] 1 , slew rate adjustment circuit 40 generates control voltages Sb1 to Sbn to be input to the gates (control electrodes) of semiconductor switches 51 to 5n, respectively, based on control signals Sa1 to San from switch selection circuit 30. As will be described later, slew rate adjustment circuit 40 adjusts the speed (slew rate) at which corresponding control voltages Sb1 to Sbn transition between L level and H level when control signals Sa1 to San transition between L level and H level. That is, semiconductor switches 51 to 5n correspond to an embodiment of "plurality of first semiconductor switches," control signals Sa1 to San correspond to "plurality of control signals," and slew rate adjustment circuit 40 corresponds to an embodiment of "control voltage generation circuit."

[0028] 3 is a circuit diagram illustrating an example configuration of slew rate adjustment circuit 40. Referring to FIG. 3, slew rate adjustment circuit 40 includes adjustment units 40U provided corresponding to each of semiconductor switches 51 to 5n. Adjustment unit 40U includes P-type transistors 41 and 43, N-type transistors 42 and 44, resistor elements R1 and R2, and a capacitor 45.

[0029] The transistor 41 (P-type) is connected between a node Ns, to which one of the input voltages Vin1 to Vinn is transmitted as the input voltage Vin, and a node N1. The transistor 42 (N-type) is connected between the node N1 and a ground Ng (ground voltage GND). A control signal Sa from the switch selection circuit 30 is input to the gates of the transistors 41 and 42. The control signal Sa collectively refers to the control signals Sa1 to San.

[0030] Similarly, a transistor 43 (P-type) and a resistor R1 are connected in series between a node Ns where a control voltage Sb is generated and a node N2. A transistor 44 (N-type) and a resistor R2 are connected in series between the node N2 and a ground Ng. The gates of the transistors 43 and 44 are connected to the node N1.

[0031] The capacitor 45 includes at least the gate capacitances of the transistors MP0 and MP1, and may further include an element additionally connected between the node N2 and the ground Ng.

[0032] The transistor 41 (P-type) and the transistor 42 (N-type) operate as an inverter that outputs a signal that is the inverse of the logical level of the control signal Sa to the node N1. Similarly, the transistor 43 (P-type) and the transistor 44 (N-type) operate as an inverter that outputs a signal that is the inverse of the logical level of the voltage at the node N1 to the node N2. As a result, the control voltage Sb generated at the node N2 is set to the L level (ground voltage GND) or the H level (input voltage Vin) so as to have the same logical level as the control signal Sa.

[0033] In this embodiment, the semiconductor switch 5 is configured with P-type transistors MP0 and MP1, so when the semiconductor switch 5 is turned on, the corresponding control signal Sa and control voltage Sb are set to the L level (ground voltage GND). On the other hand, when the semiconductor switch 5 is turned off, the corresponding control signal Sa and control voltage Sb are set to the H level (input voltage Vin).

[0034] When the control voltage Sb, i.e., the gate voltage of the P-type transistors MP0 and MP1 that constitute the semiconductor switch 5, transitions between an L level and an H level, it changes in association with the charging and discharging of the capacitor 45. Therefore, when the semiconductor switch 5 changes from on to off (when turned off), the control voltage Sb (gate voltage) changes from an L level to an H level due to the charging of the capacitor 45 via the resistance element R1. Conversely, when the semiconductor switch 5 changes from off to on (when turned on), the control voltage Sb (gate voltage) changes from an H level to an L level due to the discharging of the capacitor 45 via the resistance element R2.

[0035] Therefore, the turn-off speed of the semiconductor switch 5, i.e., the speed at which the control voltage Sb changes from L level to H level, varies depending on the RC time constant of the resistor element R1 and the capacitor 45. Similarly, the turn-on speed of the semiconductor switch 5, i.e., the speed at which the control voltage Sb changes from H level to L level, varies depending on the RC time constant of the resistor element R2 and the capacitor 45. In this embodiment, the resistance value of the resistor element R1 is set smaller than that of the resistor element R2, thereby making the turn-on speed of the semiconductor switch slower than the turn-off speed.

[0036] In this way, when the semiconductor switches 51 to 5n are turned on or off in accordance with the control signals Sa1 to San, they are controlled so that they turn off quickly at a first speed, while turning on slowly at a second speed that is slower than the first speed.

[0037] 1 , the constant voltage circuit 60 receives the voltage Vsup at the power supply node PL2 as an input and generates a constant, controlled output voltage Vout. The output voltage Vout is supplied as a power supply voltage to the process start control circuit 70 and the circuit block 80. For example, the circuit block 80 executes a predetermined process in response to a start instruction signal Sstr from the process start control circuit 70 in accordance with switching of the power generation element (power supply) connected to the power supply node PL2 among the power generation elements 11 to 1n. When the process by the circuit block 80 is completed, the circuit block 80 outputs a process completion signal Scpl to the switch selection circuit 30. The circuit block 80 corresponds to an example of an "internal circuit."

[0038] The process start control circuit 70 generates a start instruction signal Sstr to the circuit block 80 based on the control signals Sa 1 to San from the switch selection circuit 30 .

[0039] 4 is a circuit diagram illustrating an example configuration of the process start control circuit 70. As shown in Fig. 4, the process start control circuit 70 includes a power-on reset (POR) circuit 71, logic gates LG11 to LG1n, LG21 to LG2n, and LG3, inverters INV1 to INVn, and delay elements DLY1 to DLYn that provide a delay time Td.

[0040] When the output voltage Vout of the constant voltage circuit 60 rises to a predetermined voltage level (for example, a voltage level at which the circuit block 80 can operate), the POR circuit 71 transitions the POR signal from L level to H level.

[0041] The logic gates LG11 to LG1n each output the result of a NAND (negative logical product) operation between the POR signal and inverted signals ( / Sa1 to / San) of the control signals Sa1 to San from the switch selection circuit 30. The inverters INV1 to INVn invert and output the output signals of the logic gates LG11 to LG1n, respectively. The delay elements DLY1 to DLYn delay the output signals of the logic gates LG11 to LG1n by Td and output them.

[0042] The logic gates LG21 to LG2n output the results of NAND (negative logical product) operations between the output signals of the inverters INV1 to INVn and the output signals of the delay elements DLY1 to DLYn, respectively. The logic gate LG3 outputs the result of the NAND (negative logical product) operation between the output signals of the logic gates LG21 to LG2n as the start instruction signal Sstr.

[0043] 5 shows an example of the operating waveforms of the process start control circuit 70 of FIG. 4. In the example of FIG. 5, at time tp, the POR signal transitions from L level to H level. Thereafter, the switch selection circuit 30 switches the connections of the semiconductor switches 51 to 5n so that all of the semiconductor switches 51 to 5n are off and the semiconductor switch 51 is turned on. At this time, the control signal Sa1 changes from H level to L level ( / Sa1 changes from L level to H level). Thereafter, the connections of the semiconductor switches 51 to 5n are switched so that the semiconductor switch 51 is turned off and the semiconductor switch 52 is turned on. At this time, the control signal Sa1 changes from L level to H level ( / Sa1 changes from H level to L level), and the control signal Sa2 changes from H level to L level ( / Sa2 changes from L level to H level).

[0044] Therefore, at time ta, in response to / Sa changing from L level to H level in accordance with the control signal Sa1 from switch selection circuit 30, the output signal of inverter INV1 changes from L level to H level. Furthermore, at time tb, which is when delay time Td has elapsed since time ta, the output of delay element DLY1 changes from H level to L level. As a result, the output signal of logic gate LG21 changes from H level to L level between times ta and tb. In response to this, start instruction signal Sstr output from logic gate LG3 is set to a pulsed H level between times ta and tb.

[0045] Similarly, at time tc, in accordance with the control signals Sa1 and Sa2 from the switch selection circuit 30, / Sa1 changes from H level to L level, and / Sa2 changes from L level to H level. In response to this, at time tc, the output signal of the inverter INV1 changes from H level to L level, and the output signal of the inverter INV2 changes from L level to H level. Furthermore, at time td, which is the time delay time Td after time tc, the output of the delay element DLY2 changes from H level to L level. As a result, the output signal of the logic gate LG22 changes from H level to L level between times tc and td. In response to this, the start instruction signal Sstr output from the logic gate LG3 is set to a pulsed H level between times tc and td.

[0046] In this way, when the semiconductor switches 51 to 5n are switched on and off, the processing start control circuit 70 can generate a pulse signal having a pulse width corresponding to the delay time Td as the start instruction signal Sstr in response to a change in any of the control signals Sa1 to San from H level to L level.

[0047] Next, an example of the operation of the semiconductor device 110A according to the first embodiment will be described with reference to waveform diagrams in FIGS.

[0048] 6, from an initial state in which all of the semiconductor switches 51 to 5n are off, the input voltage Vin1 from the power generating element 11 increases, and at time t1, it rises to the detection determination voltage Vact of the power supply detection circuits 21 to 2n. In response to this, at time t1, the power supply detection circuit 21 changes the power supply detection signal Sd1 from L level to H level. Meanwhile, the other power supply detection signals Sd2 to Sdn are maintained at L level.

[0049] In response to the power supply detection signal Sd1 changing from L level to H level, the switch selection circuit 30 changes the control signal Sa1 from H level to L level to instruct the semiconductor switch 51 to turn on. On the other hand, the control signals Sa2 to San are maintained at H level, so the semiconductor switches 52 to 5n are maintained off.

[0050] In response to the change of the control signal Sa1 from H level to L level, the slew rate adjustment circuit 40 changes the control voltage Sb1 (i.e., the gate voltage Vg1 of the transistors MP0 and MP1) from H level (input voltage Vin1) to L level (ground voltage GND) at a slew rate according to the RC time constant of the resistor element R2 and the capacitor 45. As a result, at time t2, the control voltage Sb1 changes completely to L level, and the semiconductor switch 51 is turned completely on.

[0051] Between times t1 and t2, as transistors MP0 and MP1 are gradually turned on, input voltage Vin1 is transmitted to power supply node PL2, and voltage Vsup and output voltage Vout of constant voltage circuit 60 increase. When a start instruction signal Sstr is generated in response to a change of the POR signal shown in FIGS. 4 and 5 from L level to H level around time t2, circuit block 80 starts process A. Process A is completed at time t4, and a process completion signal Scpl is output from circuit block 80 to switch selection circuit 30 at this timing.

[0052] Meanwhile, starting around time t1, the input voltage Vin2 from the power generating element 12 increases, and at time t3, before time t4, the input voltage Vin2 increases to the detection determination voltage Vact. In response to this, the power supply detection circuit 22 changes the power supply detection signal Sd2 from L level to H level at time t3. As a result, from time t3 onwards, both the power supply detection signals Sd1 and Sd2 are set to H level. However, because process A, which was started using the power generating element 11 (input voltage Vin1), has not yet ended, the switch selection circuit 30 maintains the control signal Sa2 at H level at this timing.

[0053] In this way, the switch selection circuit 30 sets only one of the control signals Sa1 to San to the L level by exclusive control so that two or more semiconductor switches are not turned on at the same time. As shown in Fig. 6, at time t4, in response to input of the processing completion signal Scpl for the processing A started by turning on the semiconductor switch 51, the switch selection circuit 30 changes the control signal Sa1 from the L level to the H level to turn off the semiconductor switch 51. At time t5 when the input voltage Vin1 drops to the detection release voltage Vinact (Vinact<Vact), the power supply detection signal Sd1 is returned from the H level to the L level.

[0054] At time t4, in response to the processing completion signal Scpl, the switch selection circuit 30 changes the control signal Sa2 corresponding to the power supply detection signal Sd2 (H level) from H level to L level, thereby turning on the semiconductor switch 52. As a result, at time t4, the semiconductor switches 51 to 5n are switched on and off so that the semiconductor switch 51 is turned off and the semiconductor switch 52 is turned on. Furthermore, at time t4, in response to the control signal Sa2 being set to L level, the processing start control circuit 70 generates the start instruction signal Sstr.

[0055] At the time of switching on / off of the semiconductor switches 51 to 5n, even if a plurality of power supply detection signals are set to H level in addition to the power supply detection signal Sd1 corresponding to the power generating element 11 currently in use, the switch selection circuit 30 selects and turns on only one semiconductor switch. For example, it is possible to select the semiconductor switch corresponding to the power supply detection signal that changed to H level first among the plurality of power supply detection signals.

[0056] At time t4, the logic levels of the control signals Sa1 and Sa2 are switched simultaneously without providing a period during which both the control signals Sa1 and Sa2 are at the H level, i.e., without providing a period during which both the semiconductor switches 51 and 52 are in a completely off state. In other words, the turn-off of the semiconductor switch 51 and the turn-on of the semiconductor switch 52 can be initiated at the same time without providing an intentional time lag.

[0057] After time t4, in response to the change of the control signal Sa1 from the L level to the H level, the slew rate adjustment circuit 40 changes the control voltage Sb1 from the L level (ground voltage GND) to the H level (input voltage Vin1) at a slew rate according to the RC time constant of the resistance element R1 and the capacitor 45. This turns off the semiconductor switch 51, but as described above, the slew rate of the control voltage Sb1 at the turn-off time (the rate of change of the gate voltage Vg1) is greater than the slew rate of the control voltage Sb1 at the turn-on time (the rate of change of the gate voltage Vg1).

[0058] Meanwhile, in response to the change of the control signal Sa2 from H level to L level, the slew rate adjustment circuit 40 changes the control voltage Sb2 from H level (input voltage Vin1) to L level (ground voltage GND) at a slew rate according to the RC time constant of the resistor element R2 and the capacitor 45. As a result, at time t6, the control voltage Sb2 drops to the ground voltage GND, and the semiconductor switch 52 is fully turned on.

[0059] In this way, from time t4, the power generating element 12 is connected to the power supply node PL2, i.e., the input of the constant voltage circuit 60, instead of the power generating element 11. As a result, even when the input voltage Vin1 from the power generating element 11 drops, the output voltage of the constant voltage circuit 60 is maintained constant.

[0060] At time t4, the POR signal (FIG. 5) is at H level, and therefore the start instruction signal Sstr is generated immediately in response to the change in the logic levels of the control signals Sa1 and Sa2. In response to this start instruction signal Sstr, the circuit block 80 executes process B, and when process B is completed, outputs a process completion signal Scpl to the switch selection circuit 30.

[0061] In response to this, at time t7, in response to the processing completion signal Scpl, the switch selection circuit 30 changes the control signal Sa2 from L level to H level to turn off the semiconductor switch 52. From time t7, the slew rate adjustment circuit 40 changes the control voltage Sb2 (gate voltage Vg2 of the semiconductor switch 52) from L level to H level in accordance with the turn-off slew rate, which is greater than the turn-on slew rate, thereby turning off the semiconductor switch 52.

[0062] Thereafter, at time t8, when the input voltage Vin2 drops to the detection cancellation voltage Vinact, the power supply detection circuit 22 returns the power supply detection signal Sd2 from the H level to the L level.

[0063] In this way, the switch selection circuit 30 generates the control signals Sa1 to San to switch the semiconductor switches 51 to 5 n on and off based on the power supply detection signals Sd1 to Sdn from the power supply detection circuits 21 to 2 n and further reflecting the processing completion signal Scpl. It can be understood that the slew rate adjustment circuit 40 controls the control voltages Sb1 to Sbn (i.e., the gate voltages of the P-type transistors MP0 and MP1 constituting each of the semiconductor switches 51 to 5 n) so that the turn-off speed of each of the semiconductor switches 51 to 5 n is higher than the turn-on speed.

[0064] FIG. 7 is a conceptual waveform diagram illustrating the change in impedance when the semiconductor switches 51 and 52 shown in FIG. 6 are switched on and off.

[0065] 7, similar to FIG. 6, shows the transitions of the impedance Z51 of semiconductor switch 51 and the impedance Z52 of semiconductor switch 52 when semiconductor switch 51 is turned on at time t1, then semiconductor switch 51 is turned off and semiconductor switch 52 is turned on at time t4, and then semiconductor switch 52 is turned off at time t7.

[0066] Due to the difference between the turn-on speed and the turn-off speed described above, when the impedances Z51 and Z52 change between the on-state impedances Z1on and Z2on (ideally zero) and the off-state impedances Z1off and Z2off (ideally infinity), they gradually decrease during turn-on but rapidly increase during turn-off.

[0067] In the semiconductor device 110A, the power supply impedance Zps with respect to the power supply node PL2 is the composite impedance of the impedances Z51 and Z52 connected in parallel to the power supply node PL2. Also, the power supply impedance Zpg between the power generating elements 11 and 12 is the composite impedance of the impedances Z51 and Z52 connected in series.

[0068] 7, for the power supply impedance Zps and the power supply impedance Zpg, the values ​​when both semiconductor switches 51 and 52 are fully on are designated Zpon and Zson, and the values ​​when both semiconductor switches 51 and 52 are fully off are designated Zpoff and Zsoff. Zpon corresponds to the combined impedance obtained by connecting Z1on and Z2on in parallel, as described above, and Zson corresponds to the combined impedance obtained by connecting Z1on and Z2on in series, as described above. Similarly, Zpoff corresponds to the combined impedance obtained by connecting Z1off and Z2off in parallel, as described above, and Zsoff corresponds to the combined impedance obtained by connecting Z1off and Z2off in series, as described above.

[0069] As described above, when the semiconductor switches 51, 52 are switched on and off, if the impedance Zpg between the power sources drops too much, there is a concern of a short circuit between the power sources (between the power generating elements 11 and 12), while if the power source impedance Zps becomes excessively large, there is a concern of a drop in the output voltage of the constant voltage circuit 60 (the power source voltage of the circuit block 80) due to current consumption by the circuit block 80, etc.

[0070] In this regard, in the semiconductor device 110A according to the first embodiment, by providing the above-mentioned difference between the turn-on speed and the turn-off speed of each semiconductor switch 5, it is understood that it is possible to prevent the power supply impedance Zps from becoming excessive when the semiconductor switches 51 and 52 are switched on and off between times t4 and t7, and to prevent a decrease in the power supply impedance Zpg, without providing a period in which both semiconductor switches 51 and 52 are completely turned off as in Patent Document 1.

[0071] Specifically, by not providing a period in which both of the semiconductor switch elements that are switched on and off are completely off, it is possible to prevent the power supply impedance Zps from becoming excessively large, thereby stabilizing the output voltage Vout and thereby stabilizing the operation of the circuit block 80, particularly stabilizing continuous operation.

[0072] In addition, by increasing the turn-off speed, the impedance Zpg between the power supplies can be secured, thereby improving the effectiveness of preventing short circuits between the power supplies. Furthermore, by decreasing the turn-on speed, a sudden change (rise) in voltage at the power supply node PL2 can be suppressed. This allows the output voltage Vout, which is the power supply voltage for the circuit block 80, etc., to be stabilized without increasing the operating speed (current consumption) of the constant voltage circuit 60, which is effective in reducing power consumption.

[0073] As a result, in the semiconductor device 110A, a decrease in the power supply impedance Zpg via the semiconductor switch 5 is prevented, and the period during which the power supply impedance Zps becomes excessive and the voltage supply from the multiple power generating elements 11 to 1 n becomes insufficient is suppressed, thereby improving the operating characteristics when the connection of the semiconductor switch 5 is switched.

[0074] While Figure 6 illustrates an example in which there is no intentional time difference between the turn-off instruction for one semiconductor switch and the turn-on instruction for the other semiconductor switch when switching the two semiconductor switches on and off (i.e., both instructions are generated at substantially the same timing), it is also acceptable to intentionally provide a time difference between the two instructions as long as the power supply impedance Zps and the power supply impedance Zpg described in Figure 7 exhibit acceptable characteristics. In other words, the effects of this embodiment can be achieved even if the timing of the two instructions is not the same. However, not needing to intentionally provide a difference between the turn-off instruction (a change in the logic level of the control signal Sa1) and the turn-on instruction (a change in the logic level of the control signal Sa2), as in Figure 6, leads to simplification of the control logic.

[0075] Second Embodiment Fig. 8 is a block diagram illustrating the configuration of a semiconductor device 110B according to a second embodiment.

[0076] 8, the semiconductor device 110B according to the second embodiment further includes semiconductor switches 101 to 10n, diodes 111 to 11n, and a control circuit 90 in addition to the configuration of the semiconductor device 110A according to the first embodiment (FIG. 1). Each of the semiconductor switches 101 to 10n can be configured using a semiconductor switch similar to the semiconductor switches 51 to 5n (for example, FIG. 2).

[0077] The semiconductor switches 101 to 10n and the diodes 111 to 11n each form a series circuit and are connected in parallel to the semiconductor switches 51 to 5n, respectively. For example, the semiconductor switch 101 and the diode 111 are connected in series between the input power supply line PL11 and the power supply node PL2 to form a "series circuit" connected in parallel to the semiconductor switch 51. In this way, a plurality of "series circuits" are connected between the input power supply lines PL11 to PL1n and the power supply node PL2, each of which has the semiconductor switches 101 to 10n and the diodes 111 to 11n connected in series in parallel with the semiconductor switches 51 to 5n. The diodes 111 to 11n are connected with the forward direction being from the input power supply lines PL11 to PL1n to the power supply node PL2.

[0078] The control circuit 90 generates control signals Sc1 to Scn for controlling the on / off of the semiconductor switches 101 to 10n, respectively, based on the control signals Sa1 to San from the switch selection circuit 30. When all of the control signals Sa1 to San are at H level (all of the semiconductor switches 51 to 5n are off), the control circuit 90 sets all of the control signals Sc1 to Scn to L level, thereby turning on each of the semiconductor switches 101 to 10n. Like the control signals Sa1 to San, the control signals Sc1 to Scn are generated with their H level corresponding to the input voltages Vin1 to Vinn and their L level corresponding to the ground voltage GND.

[0079] On the other hand, the control circuit 90 generates control signals Sc1 to Scn so that the semiconductor switch 10 connected in parallel to the semiconductor switch that transitions from on to off is turned on for a certain period of time from the timing when any of the control signals Sa1 to San transitions from L level (semiconductor switch is on) to H level (semiconductor switch is off). During periods other than the above, each of the semiconductor switches 101 to 10n is turned off. As a result, when one of the semiconductor switches 51 to 5n is turned on, (n-1) of the semiconductor switches 101 to 10n that are connected in parallel to the remaining (n-1) semiconductor switches 5 that are turned off are turned off.

[0080] However, the control signal Sc (collectively referring to Sc1 to Scn) of one of the semiconductor switches 101 to 10n that is connected in parallel with one of the semiconductor switches 51 to 5n that is turned on may be either H level or L level.

[0081] For example, when the control signal Sa1 is at an L level and the control signals Sa2 to San are at an H level, the control signals Sc2 to San are set to an H level, while the logical level of the control signal Sc1 is "undefined" and can be either an H level or an L level.

[0082] 8, semiconductor switches 51 to 5n correspond to "plurality of first semiconductor switches," semiconductor switches 101 to 10n correspond to "plurality of second semiconductor switches," and control signals Sa1 to San correspond to "plurality of control signals."

[0083] 9 is a waveform diagram illustrating an example of operation of the semiconductor device according to the second embodiment. In FIG. 9, the waveforms of the input voltages Vin1 and Vin2 from the power generating elements 11 and 12 are different from those in FIG. 6. Specifically, the amount of power generated by the power generating element 11 is greater than that in FIG. 6, and the timing at which the power generating element 12 starts generating power is also later than that in FIG. 6. Furthermore, due to the arrangement of the semiconductor switches 101 to 10n and the diodes 111 to 11n, the waveform of the voltage Vsup at the power supply node PL2 is different between FIG. 9 (second embodiment) and FIG. 6 (first embodiment).

[0084] 6 (Embodiment 1), in the initial state until semiconductor switch 51 is turned on in response to power supply detection signal Sd1 at time t1, all of semiconductor switches 51 to 5n are in the off state. Therefore, from time t1 when semiconductor switch 51 is turned on, voltage Vsup at power supply node PL2 rises relatively rapidly. For this reason, there is a concern that a sudden change in the input voltage to constant voltage circuit 60 may cause an overshoot or the like in output voltage Vout, which is the power supply voltage of circuit block 80.

[0085] In contrast to this, in FIG. 9, all of the semiconductor switches 101 to 10n are on before time t1, so at time t0, before time t1, when the input voltage Vin1 has risen above the forward voltage of the diode 111, the conduction of the diode 111 allows the voltage Vsup to start rising in accordance with the input voltage Vin1.

[0086] Before time t1, as in FIG. 6, all of the semiconductor switches 51 to 5n are turned off, so each of the control signals Sc1 to Scn is set to the L level, and all of the semiconductor switches 101 to 10n are turned on.

[0087] Then, at time t1, when the input voltage Vin1 rises to the detection determination voltage Vact, the control signal Sa1 is set to L level in response to the power supply detection signal Sd1, and the semiconductor switch 51 is turned on. The operation between times t1 and t4 is the same as in the first embodiment. Note that between times t1 and t4, the semiconductor switch 101 connected in parallel to the semiconductor switch 51 that is turned on may be either on or off, and therefore the logic level of the control signal Sc1 is indefinite. On the other hand, the semiconductor switch 102 connected in parallel to the semiconductor switch 52 that is turned off must be turned off, and therefore the control signal Sc2 is set to H level.

[0088] At time t4, when the semiconductor switches 51 and 52 are switched on and off, an L level period of the control signal Sc1 is provided (times t4 to t4x) so as to provide an ON period of the semiconductor switch 101 connected in parallel with the semiconductor switch 51 that is turned off. For example, the L level period of the control signal Sc1 can be set by detecting an edge at which the control signal Sa1 transitions from L level to H level in combination with a timer.

[0089] After time t4, the logic level of the control signal Sc2 of the semiconductor switch 102 is indefinite, corresponding to the ON period of the semiconductor switch 52 (the L level period of the control signal Sa2). Similarly, after time t4x, the control signal Sc1 of the semiconductor switch 101 is set to the H level to turn off the semiconductor switch 101 during the ON period of the semiconductor switch 52.

[0090] At time t8, when the power supply detection signal Sd2 changes from H level to L level and all of the power supply detection signals Sd1 to Sdn are set to L level, all of the semiconductor switches 51 to 5n are turned off (the same state as before time t1), and the input voltage Vin2 is also at a low voltage below the detection release voltage Vinact (the same state as before time t1), so all of the control signals Sc1 to Scn are set to L level.

[0091] Here, the reason why the input voltage Vin2 is also waiting to become equal to or lower than the detection release voltage Vinact is to prevent unnecessary current from being supplied from the input voltage Vin2 if the input voltage Vin2 is maintained at a high level. Therefore, if such unnecessary current is acceptable from a system perspective, it is possible to confirm that all of the control signals Sa1 to Sa1 of the semiconductor switches 51 to 5n are at the H level (semiconductor switch 5 is off), and then set all of the control signals Sc1 to Scn to the L level.

[0092] 9, the time t5 at which the input voltage Vin1 drops to the detection cancellation voltage Vinact is later than in FIG. 6, but this timing does not affect the on / off of the semiconductor switches 51 and 101.

[0093] Here, the circuit operation at time t1 (power rise) and time t4 (switch on / off switching) in Fig. 9 will be described using the waveform diagrams of Fig. 10 and 11. In Fig. 10 and 11, for the voltage Vsup of the power supply node PL2, a voltage Vsup(1) in the first embodiment and a voltage Vsup(2) in the second embodiment are compared for the waveform of the same input voltage Vin1.

[0094] 10 illustrates the circuit operation at power-on when one of the semiconductor switches 51 to 5n is turned on from a state in which all of the semiconductor switches 51 to 5n are off, that is, at time t1 in FIGS.

[0095] 10 , in the first embodiment, in response to the rise in the input voltage Vin, the voltage Vsup(1) does not rise until Vin1≧Vact at time t1, and then rises following the input voltage Vin1 as the semiconductor switch 51 turns on after time t1. Therefore, immediately after time t1, there is a concern that the voltage Vsup(1), i.e., the input voltage to the constant voltage circuit 60, may suddenly change, causing an overshoot or the like in the output voltage Vout, which is the power supply voltage of the circuit block 80. This may cause the operation of the circuit block 80 to become unstable.

[0096] In contrast to this, in the second embodiment, after time t0 when the input voltage Vin1 rises to the forward voltage Vf of the diode 111, the voltage Vsup(2) rises following (Vin1-Vf).

[0097] As a result, at time t1, the voltage fluctuation occurring in voltage Vsup(2) in response to the turning on of semiconductor switch 51 is only equivalent to the forward voltage Vf of diode 111. Therefore, as can be seen from a comparison of the waveforms of voltages Vsup(1) and Vsup(2), in the second embodiment, at power-on when one of semiconductor switches 51 to 5n is turned on from a state in which all of semiconductor switches 51 to 5n are off, the voltage fluctuation at power-on node PL2 is suppressed, thereby suppressing fluctuations in the power supply voltage of an internal circuit (e.g., circuit block 80) of semiconductor device 110B. As a result, the operation of semiconductor device 110B at power-on can be stabilized.

[0098] 11 illustrates the circuit operation at the time of on / off switching of the semiconductor switches 51 to 5n that are turned on, that is, at time t4 in FIG.

[0099] 11, in the first embodiment, as described with reference to FIG. 6, at time t4, semiconductor switch 51 is quickly turned off, while semiconductor switch 52 is slowly turned on.

[0100] 11 shows a case in which the input voltage Vin2 transmitted by the turned-on semiconductor switch 52 is lower than the input voltage Vin1 transmitted by the turned-off semiconductor switch 51. In the first embodiment, in such a case, there is a concern that the voltages Vsup and Vout will suddenly drop during the period in which the power supply impedance Zps (FIG. 7) increases due to the influence of the current consumption by the circuit block 80.

[0101] In contrast to this, in the second embodiment, during the period from time t4 to t4x in FIG. 9, semiconductor switch 101 is turned on, and diode 111 (forward voltage Vf) is connected between input power supply line PL1 and power supply node PL2.

[0102] Therefore, when the voltage Vsup of the power supply node PL2 drops below (Vin1-Vf), the diode 111 becomes conductive, and a current (charge) can be supplied from the input power supply line PL1 (input voltage Vin1) to the power supply node PL2. As a result, it can be understood that even if a current consumption similar to that for the voltage Vsup(1) occurs, the drop in the voltage Vsup(2) in the second embodiment is suppressed compared to the voltage Vsup(1) in the first embodiment.

[0103] As a result, in the second embodiment, even when semiconductor switch 5 is switched on and off, voltage fluctuations at power supply node PL2 can be suppressed.

[0104] Thus, according to the semiconductor device 110B of the second embodiment, by suppressing the voltage fluctuation of the power supply node PL2 to which voltage is transmitted by the on / off control of the semiconductor switch 5, it is possible to suppress the fluctuation of the power supply voltage of the internal circuit and stabilize operation.

[0105] Third Embodiment Fig. 12 is a block diagram illustrating the configuration of a semiconductor device 110C according to a third embodiment.

[0106] As shown in FIG. 12, the semiconductor device 110C according to the third embodiment further includes a delay circuit 120 in addition to the configuration of the semiconductor device 110B according to the second embodiment (FIG. 8).

[0107] The delay circuit 120 delays the start instruction signal Sstr from the process start control circuit 70 and inputs it to the circuit block 80 .

[0108] 13 shows a waveform diagram illustrating an example of the operation of the semiconductor device according to the third embodiment. The waveform diagram in Fig. 13 differs from the waveform diagram in Fig. 9 (second embodiment) in the timing of the processing sequence by the circuit block 80.

[0109] Specifically, in FIG. 9, processing A and processing B are started in response to the generation of start instruction signals Sstr at times t2 and t4, respectively, whereas in FIG. 13, processing A and processing B are started at times t2d and t4d, respectively, after the delay time Tr applied by delay circuit 120 has elapsed from times t2 and t4.

[0110] The delay time Tr by the delay circuit 120 can be set to correspond to the turn-on speed of the semiconductor switch 5 and can be set to be equal to or longer than the time required for the semiconductor switch 5 to be completely turned on from the time when the control signal Sa changes from H level to L level (the length of the period between times t4 and t6).

[0111] This prevents the circuit block 80 from operating during a period in which the power supply impedance Zps (FIG. 7) increases due to the on / off switching of the semiconductor switches 51 to 5n. This prevents the internal circuit of the semiconductor device 110B (for example, the circuit block 80) from operating under conditions in which the power supply voltage fluctuates (drops) due to voltage fluctuations at the power supply node PL2 during power-up or switching of the semiconductor switches 51 to 5n that are turned on, as described in the second embodiment.

[0112] Therefore, according to the semiconductor device 110C of the third embodiment, it is possible to prevent the internal circuit from operating in a state where the power supply voltage is reduced due to voltage fluctuations at the power supply node PL2, to which voltage is transmitted by the on / off control of the semiconductor switch 5, thereby stabilizing the operation of the semiconductor device.

[0113] In the third embodiment, a configuration example (FIG. 13) in which the delay circuit 120 is applied to the semiconductor device 110B (FIG. 8) of the second embodiment has been described. However, it is also possible to combine the first and third embodiments by applying the delay circuit 120 to the semiconductor device 110A (FIG. 1) of the first embodiment.

[0114] Fourth Embodiment Fig. 14 is a block diagram illustrating the configuration of a semiconductor device 110D according to a fourth embodiment.

[0115] 14, the semiconductor device 110D according to the fourth embodiment includes, in addition to the configuration of the semiconductor device 110B according to the second embodiment (FIG. 8), a switch-on detection circuit 130. The switch-on detection circuit 130 generates on-detection signals Son1 to Sonn for the semiconductor switches 51 to 5n, respectively, based on control voltages Sb1 to Sbn of the semiconductor switches 51 to 5n.

[0116] Furthermore, unlike the first to third embodiments, the processing start control circuit 70 generates a start instruction signal Sstr for the circuit block 80 based on the on detection signals Son1 to Sonn from the switch on detection circuit 130 instead of the control signals Sa1 to San from the switch selection circuit 30.

[0117] 15 is a circuit diagram illustrating an example configuration of the switch-on detection circuit 130. As shown in Fig. 15, the switch-on detection circuit 130 has a detection unit 130U provided corresponding to each of the semiconductor switches 51 to 5n. The detection unit 130U has a P-type transistor 131, resistance elements R3, R4a, R4b, R5a, and R5b, and a comparator 135.

[0118] The P-type transistor 131 is connected in series with the resistor element R4a between the node Ns, to which one of the input voltages Vin1 to Vinn is transmitted as the input voltage Vin, and the node N3. The resistor element R5a is connected between the node N3 and the ground Ng (ground voltage GND). The control voltage Sb from the slew rate adjustment circuit 40 is input to the gate of the P-type transistor 131. As described above, the control voltage Sb corresponds to the voltage (gate voltage) of the control electrodes of the P-type transistors MP0 and MP1 that constitute the semiconductor switch 5.

[0119] Resistor elements R3 and R4b are connected in series between nodes Ns and N4. Resistor element R5b is connected between node N4 and ground Ng (ground voltage GND). Resistor elements R4a and R4b have the same resistance value, and resistor elements R5a and R5b have the same resistance value. Comparator 135 outputs an on-detection signal Son according to the comparison result between the voltage of node N3 and the voltage of node N4. The on-detection signal Son collectively represents the on-detection signals Son1 to Sonn of the semiconductor switches 51 to 5n, respectively. When the voltage of node N3 is higher than the voltage of node N4, the on-detection signal Son is set to H level. On the other hand, when the voltage of node N4 is higher than the voltage of node N3, the on-detection signal Son is set to L level.

[0120] When the control voltage Sb is at H level (input voltage Vin) and the semiconductor switch 5 is off, the node N3 is pulled down to the ground voltage GND, while a divided voltage of the input voltage Vin is generated at the node N4 by the resistor elements R3, R4b and the resistor element R5b. Therefore, the voltage at the node N4 is higher than the voltage at the node N3, and the on-detection signal Son is set to L level.

[0121] In contrast, when the control voltage Sb decreases toward the ground voltage GND to turn on the semiconductor switch 5, the transistor 131 (P-type) changes from off to on. As a result, the on-resistance of the transistor 131 decreases, and the voltage of the node N3 increases from when the transistor 131 was off. Meanwhile, the voltage of the node N4 remains unchanged from when the transistor 131 was off. Therefore, as the control voltage Sb decreases, the voltage of the node N3 becomes higher than the voltage of the node N4, and the on-detection signal Son changes from low to high.

[0122] In this way, the switch-on detection circuit 130 can accurately detect whether the semiconductor switch 5 is in an on state or an off state based on the voltages of the control electrodes of the transistors (transistors MP0 and MP1 in FIG. 2) that constitute the semiconductor switch 5.

[0123] 16 is a waveform diagram illustrating an example of the operation of the semiconductor device according to the fourth embodiment. The waveform diagram in Fig. 16 is different from the waveform diagram in Fig. 9 (second embodiment) in the timing of the processing sequence by the circuit block 80, more specifically, the timing at which the start instruction signal Sstr is generated.

[0124] Specifically, in Figure 9, the start instruction signal Sstr is generated around time t2 based on the control signal Sa1 and the POR signal, whereas in Figure 13, at time t2, in response to the semiconductor switch 5 turning off, the on detection signal Son1 changes from L level to H level, and the start instruction signal Sstr is generated at that timing.

[0125] Furthermore, at time t4, when the control signal Sa1 changes from L level to H level and the control voltage Sb1 (gate voltage) starts to rise, the on-detection signal Son1 changes from H level to L level as the transistor 131 (FIG. 14) is turned off.

[0126] 9, the start instruction signal Sstr is generated at time t4 based on the control signals Sa1 and Sa2, whereas in Fig. 13, the start instruction signal Sstr is generated in response to the change of the on-detection signal Son2 from L level to H level at time t6. When the control voltage Sb2 (gate voltage) starts to rise in response to the change of the control signal Sa2 from L level to H level at time t7, the on-detection signal Son2 changes from H level to L level in response to the transistor 131 (Fig. 14) being turned off.

[0127] In this way, when semiconductor switches 51 to 5n are switched on and off, operation of circuit block 80 begins after semiconductor switch 5 that is turned on is fully on, so that circuit block 80 can operate while avoiding periods when power supply impedance Zps (FIG. 7) is rising, as in embodiment 3. Furthermore, while embodiment 3 requires precision in adjusting delay time Tr (delay circuit 120), embodiment 4 does not require such adjustment and allows circuit block 80 to operate while reliably avoiding periods when power supply impedance Zps is rising.

[0128] Therefore, according to the semiconductor device of the fourth embodiment, it is possible to more reliably prevent the internal circuit from operating in a state where the power supply voltage is reduced due to voltage fluctuations at the power supply node PL2, to which voltage is transmitted by on / off control of the semiconductor switches 51 to 5n, thereby further stabilizing the operation of the semiconductor device.

[0129] In the fourth embodiment, a configuration example (FIG. 14) in which the switch-on detection circuit 130 is applied to the semiconductor device 110B (FIG. 8) according to the second embodiment has been described. However, it is also possible to apply the switch-on detection circuit 130 to the semiconductor device 110A (FIG. 1) according to the first embodiment, thereby forming a configuration in which the first and fourth embodiments are combined.

[0130] In addition, in the first to fourth embodiments, an example has been described in which the semiconductor switches 51 to 5 n and 101 to 10 n are configured as semiconductor switches using P-type field effect transistors, but this configuration example is suitable as a semiconductor switch connected to a power supply line from the viewpoint of on / off controllability and prevention of backflow. However, the present invention is not limited to this configuration example, and the effects of the present invention can be obtained even if the semiconductor switches 51 to 5 n and 101 to 10 n are configured with other configurations or other elements, as long as the impedance varies in accordance with the control voltage.

[0131] Regarding the multiple embodiments described above, we would like to confirm that it was intended from the beginning of the application to appropriately combine the configurations described in each embodiment, including combinations not mentioned in the specification, within the scope that does not result in inconsistencies or contradictions.

[0132] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0133] 11 to 1n power generating elements, 21 to 2n power supply detection circuits, 5, 51 to 5n, 10, 101 to 10n semiconductor switches, 111 to 11n diodes, 30 switch selection circuit, 40 slew rate adjustment circuit, 40U adjustment unit, 41 to 44, 131 to 135, MP0, MP1 transistor, 45 capacitor, 60 constant voltage circuit, 70 processing start control circuit, 71 POR circuit, 80 circuit block, 90 control circuit, 110A to 110D semiconductor device, 120 delay circuit, 130 switch-on detection circuit, 130U detection unit, DLY1 to DLYn delay element, INV1 to INVn inverter, LG11 to LG1n, LG21 to LG2n, LG3 logic gate, Ng ground, PL1, PL11 to PL1n input power line, PL2 Power supply node, Sa, Sa1 to San control signals (first control signals), Sc, Sc1 to Scn control signals (second control signals), Sb, Sb1 to Sbn control voltages, Scpl processing completion signal, Sd1 to Sdn power supply detection signals, Son to Sonn on detection signals, Sstr start instruction signal, Vact detection determination voltage, Vf forward voltage (diode), Vg1, Vg2 gate voltages, Vin1 to Vinn input voltages, Vinact detection release voltage, Vout output voltage (constant voltage circuit), Vsup voltage (power supply node PL2), Z51, Z52 impedances, Zpg impedance between power supplies, Zps power supply impedance.

Claims

1. an internal circuit that operates using the voltage of the power supply node; a plurality of first semiconductor switches respectively connected between a plurality of power supplies and the power supply node; a switch selection circuit that selects one of the plurality of power supplies and outputs a plurality of control signals that respectively control on / off of the plurality of first semiconductor switches so as to turn on a first semiconductor switch corresponding to the selected one of the plurality of first semiconductor switches; a control voltage generating circuit that generates a plurality of control voltages to be input to control electrodes of the plurality of first semiconductor switches in response to the plurality of control signals; the control voltage generation circuit changes each of the plurality of control voltages at a first speed when changing each of the plurality of first semiconductor switches from on to off in response to the plurality of control signals, and changes each of the plurality of control voltages at a second speed slower than the first speed when changing each of the plurality of first semiconductor switches from off to on.

2. a plurality of series circuits connected in parallel with the plurality of first semiconductor switches between the plurality of power supplies and the power supply node; Each of the series circuits comprises: a diode connected with a forward direction from each of the plurality of power supplies to the power supply node; a second semiconductor switch connected in series with the diode; The semiconductor device includes: a control circuit for controlling the on / off of the second semiconductor switch of each of the plurality of series circuits; 2. The semiconductor device according to claim 1, wherein said control circuit turns on said second semiconductor switch in each of said plurality of series circuits when all of said plurality of first semiconductor switches are turned off.

3. 3. The semiconductor device according to claim 2, wherein when one of the plurality of first semiconductor switches changes from on to off, the control circuit provides an on period for the second semiconductor switch in a series circuit connected in parallel to the one of the plurality of series circuits after the one first semiconductor switch has turned off.

4. the internal circuit is configured to start a predetermined process in response to switching of a power supply, among the plurality of power supplies, that is connected to the power supply node via the plurality of first semiconductor switches; The semiconductor device includes:

4. The semiconductor device according to claim 1, further comprising a signal generating circuit for generating a start command signal for the internal circuit to start the predetermined process in response to any one of the plurality of first semiconductor switches changing from off to on.

5. each of the plurality of control signals is set to a different logic level when turning on and off each of the plurality of first semiconductor switches; 5. The semiconductor device according to claim 4, wherein said signal generating circuit generates said start command signal in response to changes in said logic levels of said plurality of control signals.

6. a delay circuit that adds a predetermined delay time to the start command signal from the signal generating circuit and transmits the signal to the internal circuit; 6. The semiconductor device according to claim 5, wherein the delay time is set so that the elapsed time from the timing at which the logic level of each of the plurality of control signals changes to change each of the plurality of first semiconductor switches from off to on until the start command signal is input to the internal circuit is equal to or longer than the time required for each of the plurality of control voltages to complete a change according to the second speed.

7. The semiconductor device includes: a switch-on detection circuit for detecting an on state of each of the first semiconductor switches based on the plurality of control voltages; 5. The semiconductor device according to claim 4, wherein the signal generating circuit outputs the start command signal to the internal circuit in response to detection by the switch-on detection circuit that any one of the plurality of first semiconductor switches has changed from an off state to the on state.

8. a constant voltage circuit to which the voltage of the power supply node is input, 4. The semiconductor device according to claim 1, wherein said internal circuit operates using the output voltage of said constant voltage circuit as a power supply voltage.

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