Semiconductor module and vehicle

Abstract

This semiconductor module comprises: a semiconductor device with a signal terminal protruding from a sealing part toward one side in the thickness direction of the sealing part; and a wiring board. The wiring board includes a base material, a first wire, a second wire, a third wire, and a fourth wire. The base material has a first surface facing the one side in the thickness direction, a second surface facing the other side in the thickness direction, a through hole penetrating in the thickness direction, and a first recess part recessed from the inner surface of the through hole and the second surface. The first wire is disposed on the first surface. The second wire is disposed on the second surface. The third wire is disposed on the inner surface of the through hole. The fourth wire is disposed in the first recess part, and is connected to both the second wire and the third wire. The signal terminal includes a base part and a bulging part that bulges in a direction orthogonal to the thickness direction. The bulging part is in contact with the third wire.

Description

Semiconductor modules and vehicles

[0001] The present disclosure relates to a semiconductor module and a vehicle equipped with the semiconductor module.

[0002] Various configurations have been proposed for semiconductor devices including semiconductor elements. Patent Document 1 discloses an example of a conventional semiconductor device. The semiconductor device disclosed in this document includes a semiconductor chip, a resin encapsulation portion, and multiple press-fit terminals. The resin encapsulation portion covers the semiconductor chip. The multiple press-fit terminals protrude upward from an upper surface of the resin encapsulation portion. The semiconductor device including the multiple press-fit terminals is used in combination with a circuit board. When assembling the semiconductor device and the circuit board, the multiple press-fit terminals are press-fit into through holes formed in the circuit board and inserted into the through holes. Here, high positioning accuracy is required between the press-fit terminals and the through holes of the circuit board, and insufficient positioning accuracy could cause problems when assembling the semiconductor device and the circuit board.

[0003] Japanese Patent Application Laid-Open No. 2020-17702

[0004] An object of the present disclosure is to provide an improved semiconductor device compared to conventional semiconductor devices. In particular, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor module having a structure suitable for facilitating assembly in a module in which terminals of a semiconductor device are inserted into through holes in a wiring substrate.

[0005] A semiconductor module provided by a first aspect of the present disclosure includes a semiconductor device including a semiconductor element, an encapsulation portion covering the semiconductor element, and a signal terminal protruding from the encapsulation portion to one side in a thickness direction of the encapsulation portion and conducting to the semiconductor element; and a wiring substrate arranged on one side of the encapsulation portion in the thickness direction. The wiring substrate includes a base material, a first wiring, a second wiring, a third wiring, and a fourth wiring. The base material has a first surface facing one side in the thickness direction, a second surface facing the other side in the thickness direction, at least one through hole penetrating the thickness direction, and an inner surface of the through hole and a first recess recessed from the second surface. The first wiring is arranged on the first surface. The second wiring is arranged on the second surface. The third wiring is arranged on the inner surface of the through hole. The fourth wiring is arranged in the first recess and is connected to both the second wiring and the third wiring. The signal terminal has a base portion extending in the thickness direction and a bulging portion bulging from the base portion in a direction perpendicular to the thickness direction, and the bulging portion is in contact with the third wiring.

[0006] A second aspect of the present disclosure provides a vehicle including a drive source and the semiconductor module according to the first aspect of the present disclosure, wherein the semiconductor device is electrically connected to the drive source.

[0007] According to the above configuration, it is possible to provide a semiconductor module having a structure that is favorable for easy assembly.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a perspective view showing a semiconductor module according to a first embodiment. FIG. 2 is a view in which the wiring board is omitted from the perspective view of FIG. 1. FIG. 3 is a plan view showing the semiconductor module according to the first embodiment. FIG. 4 is a view in which the wiring board is omitted from the plan view of FIG. 1. FIG. 5 is a front view showing the semiconductor module according to the first embodiment. FIG. 6 is a bottom view showing the semiconductor module according to the first embodiment. FIG. 7 is a left side view showing the semiconductor module according to the first embodiment. FIG. 8 is a right side view showing the semiconductor module according to the first embodiment. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 4. FIG. 10 is a cross-sectional view taken along line X-X in FIG. 4. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 4. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 4. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 4. FIG. 14 is a partially enlarged cross-sectional view of the semiconductor module according to the first embodiment. FIG. 15 is a perspective view showing a semiconductor device in a semiconductor module according to the first embodiment. FIG. 16 is a plan view showing a semiconductor device in a semiconductor module according to the first embodiment. FIG. 17 is a view showing the sealing portion in the plan view of FIG. 16 with imaginary lines. FIG. 18 is a view showing the sealing portion and second conductive member in the plan view of FIG. 17 without the sealing portion and second conductive member. FIG. 19 is a front view showing a semiconductor device in a semiconductor module according to the first embodiment. FIG. 20 is a bottom view showing a semiconductor device in a semiconductor module according to the first embodiment. FIG. 21 is a cross-sectional view taken along line XXI-XXI of FIG. 17. FIG. 22 is a partially enlarged cross-sectional view of FIG. 21. FIG. 23 is a partially enlarged cross-sectional view of FIG. 21. FIG. 24 is a cross-sectional view taken along line XXIV-XXIV of FIG. 17. FIG. 25 is a cross-sectional view taken along line XXV-XXV of FIG. 17. FIG. 26 is a cross-sectional view taken along line XXVI-XXVI of FIG. 17. FIG. 27 is a partially enlarged cross-sectional view of FIG. 9. Fig. 28 is a schematic diagram of a vehicle equipped with a semiconductor module according to the first embodiment. Fig. 29 is a partially enlarged cross-sectional view showing a semiconductor module according to a first modified example of the first embodiment, showing a cross section similar to that of Fig. 14. Fig. 30 is a partially enlarged cross-sectional view showing a semiconductor module according to a second modified example of the first embodiment, showing a cross section similar to that of Fig. 14.

[0010] A preferred embodiment of the semiconductor module of the present disclosure will be described below with reference to the drawings. Hereinafter, identical or similar components will be designated by the same reference numerals, and redundant description will be omitted. Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not intended to necessarily assign any order to their objects.

[0011] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an) object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an) object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. "a certain object A is located on (an) object B" include "a certain object A is in contact with a certain object B and is located on (an) object B" and "a certain object A is located on (an) object B with another object interposed between the certain object A and the certain object B." Unless otherwise specified, the phrase "object A overlaps object B when viewed in a certain direction" includes "object A overlaps the entire object B" and "object A overlaps a part of object B." The phrase "object A (its material) contains material C" includes "object A (its material) is made of material C" and "object A (its material) is mainly composed of material C." In the present disclosure, the phrase "a surface A faces direction B (on one side or the other side of direction B)" is not limited to the case where surface A is at an angle of 90° to direction B, but also includes the case where surface A is tilted with respect to direction B.

[0012] 1 to 14 show a semiconductor module A10 according to a first embodiment. The semiconductor module A10 includes a plurality of semiconductor devices B1, a heat sink C1, a mounting member D1, and a wiring substrate E1.

[0013] In the following description, the thickness direction z, the first direction x, and the second direction y, which are perpendicular to each other, will be referred to. The thickness direction z corresponds to the thickness direction of the semiconductor module A10. Furthermore, "plan view" refers to the view in the thickness direction z. The first direction x is perpendicular to the thickness direction z. The second direction y is perpendicular to the thickness direction z and the first direction x. One side of the first direction x will be referred to as the x1 side of the first direction x, and the other side of the first direction x will be referred to as the x2 side of the first direction x. One side of the second direction y will be referred to as the y1 side of the second direction y, and the other side of the second direction y will be referred to as the y2 side of the second direction y. One side of the thickness direction z will be referred to as the z1 side of the thickness direction z, and the other side of the thickness direction z will be referred to as the z2 side of the thickness direction z. The z1 side of the thickness direction z will sometimes be referred to as the upper side, and the z2 side of the thickness direction z will sometimes be referred to as the lower side. Note that terms such as "top," "bottom," "upper," "lower," "top surface," and "bottom surface" indicate the relative positional relationship of each part in the thickness direction z, and are not necessarily terms that define the relationship with the direction of gravity.

[0014] As shown in FIGS. 2 , 4 , 7 , and 8 , the multiple semiconductor devices B1 are arranged along the second direction y. Each of the multiple semiconductor devices B1 includes multiple semiconductor elements 21. As will be understood from the configuration described in detail later, the multiple semiconductor elements 21 are switching elements such as MOSFETs and IGBTs, and each of the multiple semiconductor devices B1 constitutes, for example, a half-bridge switching circuit. As shown in FIGS. 1 to 9 , each of the multiple semiconductor devices B1 includes multiple power terminals 13, multiple signal terminals 17, and a sealing portion 50. In each of the multiple semiconductor devices B1, the multiple semiconductor elements 21 are covered by the sealing portion 50. The multiple power terminals 13 protrude in the first direction x from a side surface (a second side surface 532 described below) of the sealing portion 50. The multiple signal terminals 17 protrude in the thickness direction z from an upper surface (a top surface 51 described below) of the sealing portion 50.

[0015] In the illustrated example, the semiconductor module A10 includes three semiconductor devices B1, but may include two or four or more semiconductor devices B1. In the following description, when distinguishing between the three semiconductor devices B1, they are referred to as a first device B11, a second device B12, and a third device B13. The first device B11 is located closest to the y1 side of the multiple semiconductor devices B1 in the second direction y. The third device B13 is located closest to the y2 side of the multiple semiconductor devices B1 in the second direction y. The second device B12 is located between the first device B11 and the third device B13 in the second direction y.

[0016] The heat sink C1 supports the multiple semiconductor devices B1. Most of the heat sink C1 is located below the multiple semiconductor devices B1 in the thickness direction z (on the z2 side). The heat sink C1 faces the lower surfaces (bottom surfaces 52 described below) of the sealing portions 50 of the multiple semiconductor devices B1. The material of the heat sink C1 includes, for example, aluminum. The material is not limited to aluminum, and may be other metal materials or resin materials (preferably those with good thermal conductivity). The heat sink C1 includes a main body portion 71, multiple pedestal portions 72, and multiple positioning portions 73.

[0017] The main body 71 is a plate material. The plurality of semiconductor devices B1 are mounted on the main body 71. Therefore, as shown in FIGS. 2, 4, 7, and 8, the plurality of semiconductor devices B1 are arranged on the main body 71 along the second direction y. The main body 71 faces the lower surface (bottom surface 52 described below) of each sealing portion 50 of the plurality of semiconductor devices B1. The main body 71 contacts each semiconductor device B1. The main body 71 is, for example, rectangular in plan view.

[0018] 2, 5, and 7 to 13, the plurality of pedestals 72 each protrude upward in the thickness direction z from the main body 71. In the illustrated example, the plurality of pedestals 72 are formed integrally with the main body 71, but they may be attached to the main body 71 as separate bodies.

[0019] As shown in FIGS. 9 to 13 , each of the multiple pedestal portions 72 includes a first portion 721 and a second portion 722. The first portion 721 is interposed between the wiring substrate E1 and the main body portion 71 in the thickness direction z. The dimension of the first portion 721 in the thickness direction z is greater than the dimension of the sealing portion 50 of each semiconductor device B1 in the thickness direction z. The second portion 722 is disposed on the first portion 721. The wiring substrate E1 is sandwiched between the first portion 721 and the second portion 722. With this configuration, the wiring substrate E1 is disposed at a fixed distance from the upper surface of the main body portion 71.

[0020] In the illustrated example, the first part 721 has a recessed part with an internal thread, and the second part 722 has a protruding part with an external thread. The second part 722 is fastened to the first part 721 by inserting the externally threaded part (protruding part) of the second part 722 into the internally threaded part (recessed part) of the first part 721. Each pedestal part 72 may have a structure in which the first part 721 and the second part 722 are fitted together. For example, the structure may be such that the second part 722 is press-fitted into the first part 721. The first part 721 may have a protruding part, and the second part 722 may have a recessed part.

[0021] As shown in FIGS. 2 and 13 , each of the positioning portions 73 protrudes upward from the main body portion 71 in the thickness direction z. In the illustrated example (e.g., FIG. 13 ), each of the positioning portions 73 is attached to the main body portion 71 as a separate body. Alternatively, each positioning portion 73 may be formed integrally with the main body portion 71. In the example shown in FIG. 13 , each positioning portion 73 is press-fitted into a through-hole formed in the main body portion 71. Each positioning portion 73 is cylindrical and tapered toward the z1 side in the thickness direction z. In the illustrated example, the diameter of each positioning portion 73 in a plan view is smaller than the diameter of each base portion 72 in a plan view. As shown in FIGS. 3 and 4 , some of the positioning portions 73 are arranged on the y1 side of the first device B11 in the second direction y, and others are arranged on the y2 side of the third device B13 in the second direction y.

[0022] The mounting member D1 holds the plurality of semiconductor devices B1 to the heat sink C1. The mounting member D1 is, for example, a leaf spring. The elastic force of the mounting member D1 presses the plurality of semiconductor devices B1 against the heat sink C1. The material of the mounting member D1 is not limited in any way, but may be, for example, copper, iron, titanium, or an alloy containing any of these (including, for example, stainless steel). As shown in FIGS. 4 and 7 to 13, the mounting member D1 includes a plurality of pressing portions 81 and a plurality of fixing portions 82.

[0023] The pressing portions 81 are provided individually for the semiconductor devices B1, respectively. Each pressing portion 81 contacts the sealing portion 50 (top surface 51) of the corresponding semiconductor device B1. Each pressing portion 81 presses the semiconductor device B1 it contacts against the main body 71 of the heat sink C1.

[0024] Each of the multiple fixing portions 82 is fixed to the heat sink C1, and in this embodiment, is fixed to the main body portion 71. Each of the multiple fixing portions 82 is, for example, in the shape of a flat plate parallel to the xy plane. A through hole is formed in each of the multiple fixing portions 82. A fastener 89 (a hexagonal bolt in the illustrated example) is inserted into the through hole. The fastener 89 fixes the fixing portion 82 to the main body portion 71.

[0025] The multiple fixing portions 82 include multiple end-arrangement portions 821 and multiple intermediate arrangement portions 822. In the semiconductor module A10, the multiple fixing portions 82 include a pair of end-arrangement portions 821 and two intermediate arrangement portions 822. As shown in FIGS. 4 and 10 , one of the pair of end-arrangement portions 821 is located on the y1 side of the first device B11 in the second direction y, and the other of the pair of end-arrangement portions 821 is located on the y2 side of the third device B13 in the second direction y. One of the two intermediate arrangement portions 822 is located between the first device B11 and the second device B12, and the other of the two intermediate arrangement portions 822 is located between the second device B12 and the third device B13.

[0026] In the example shown in FIG. 4 , the width (dimension in the first direction x) of each of the two-end arrangement portions 821 is smaller than the width (dimension in the first direction x) of each of the pressing portions 81 and the width (dimension in the first direction x) of each of the intermediate arrangement portions 822. This prevents interference between the mounting member D1 (each of the two-end arrangement portions 821) and each of the positioning portions 73. Unlike this example, the width of the pressing portion 81 and the width of each of the intermediate arrangement portions 822 may be the same as the width of each of the two-end arrangement portions 821. In this case, the mounting member D1 can be formed in a rectangular (strip-like) shape in a plan view. Alternatively, the width of each of the intermediate arrangement portions 822 may be the same as the width of each of the two-end arrangement portions 821.

[0027] As shown in FIGS. 1, 3, 7, and 8, the wiring substrate E1 is provided in common for multiple semiconductor devices B1. Alternatively, multiple wiring substrates E1 may be provided individually for multiple semiconductor devices B1. As can be seen from FIGS. 9 and 11, the signal terminals 17 of the multiple semiconductor devices B1 are inserted into the wiring substrate E1. The wiring substrate E1 is electrically connected to each signal terminal 17. The wiring substrate E1 is, for example, a drive circuit that controls the operation of each semiconductor element 21 of the multiple semiconductor devices B1. In an example where each semiconductor element 21 is a MOSFET or IGBT, the wiring substrate E1 is a gate driver. The wiring substrate E1 is disposed above (on the z1 side) each sealing portion 50 of the multiple semiconductor devices B1 in the thickness direction z. The wiring substrate E1 faces the upper surface (top surface 51) of each sealing portion 50 of the multiple semiconductor devices B1. The wiring substrate E1 is located on the opposite side of the multiple semiconductor devices B1 from the main body portion 71 of the heat sink C1. In a plan view, the wiring substrate E1 overlaps each of the sealing portions 50 of the semiconductor devices B1. The wiring substrate E1 is held by a plurality of pedestals 72 at a certain distance in the thickness direction z from the upper surfaces (top surfaces 51) of the sealing portions 50 of the semiconductor devices B1 (see FIG. 27 ).

[0028] As shown in FIG. 14, the wiring substrate E1 has a base material 90, a first wiring 91, a second wiring 92, a third wiring 93, and a fourth wiring 94.

[0029] The substrate 90 has a first surface 901 and a second surface 902. The first surface 901 is located at the upper side (z1 side) of the substrate 90 in the thickness direction z and faces the z1 side in the thickness direction z. The second surface 902 is located at the lower side (z2 side) of the substrate 90 in the thickness direction z and faces the z2 side in the thickness direction z. The substrate 90 has a plurality of through holes 903 penetrating in the thickness direction z. In this embodiment, the substrate 90 has a first recess 904. The first recess 904 is recessed from the inner surface of the through hole 903 and the second surface 902, and is formed individually for each through hole 903. The first recess 904 includes a portion (first portion) that is positioned radially inward of the through hole 903 as it extends toward the z1 side in the thickness direction z. In this embodiment, the first recess 904 has a conical shape that is inclined so that the entire first recess 904 is positioned radially inward of the through hole 903 as it extends toward the z1 side in the thickness direction z. The first recess 904 has a first edge 904a and a second edge 904b. The first edge 904a contacts the inner surface of the through hole 903. The second edge 904b contacts the second surface 902. The method for forming the first recess 904 is not particularly limited, and for example, the first recess 904 is formed by cutting concentrically with the through hole 903 from the z2 side in the thickness direction z of the substrate 90 using a drill with a conical tip.

[0030] The first wiring 91 is disposed on a first surface 901 of the substrate 90. The second wiring 92 is disposed on a second surface 902. The third wiring 93 is disposed on the inner surface of the through hole 903 and is connected to the first wiring. The fourth wiring 94 is disposed in the first recess 904. The fourth wiring 94 is connected to both the second wiring 92 and the third wiring 93. The first wiring 91 forms a path for mutual conduction between the second wiring 92, the fourth wiring 94, and the third wiring 93 and a circuit provided on the wiring substrate E1. The first wiring 91, the second wiring 92, the third wiring 93, and the fourth wiring 94 are formed, for example, by metal plating formed on the surface of the substrate 90. The composition of the metal plating includes copper (Cu).

[0031] Examples of dimensions of the substrate 90 include a first dimension L1, which is the length in the thickness direction z of the substrate 90, of approximately 1.6 mm to 3.2 mm. The inner diameter (diameter of the inner surface) of the through hole 903 is, for example, approximately 0.9 mm to 1.2 mm. The ratio of the second dimension L2, which is the radial length of the through hole 903 from the first edge 904a to the second edge 904b, to the thickness (first dimension L1) of the substrate 90 is, for example, 5% to 40%, preferably 9% to 15%. The ratio of the third dimension L3, which is the length in the thickness direction z from the first edge 904a to the second edge 904b, to the thickness (first dimension L1) of the substrate 90 is, for example, 5% to 40%, preferably 9% to 15%. The second dimension L2 is, for example, approximately 0.2 mm to 1.0 mm. The third dimension L3 is, for example, approximately 0.2 mm to 1.0 mm. The thickness of the first wiring 91, second wiring 92, third wiring 93 and fourth wiring 94 (metal plating) formed on the base material 90 is, for example, about 10 to 18 μm.

[0032] Each of the signal terminals 17 of the semiconductor devices B1 is inserted into a corresponding one of the through holes 903 of the wiring substrate E1. Fig. 14 shows the signal terminals 17 that are inserted into the through holes 903 of the base material 90. All of the signal terminals 17 of the semiconductor devices B1 are inserted into the through holes 903 of the base material 90, as shown in Fig. 14.

[0033] As shown in FIG. 14 , each signal terminal 17 has a base 170A and a bulge 170B. The z2 side of the base 170A in the thickness direction z is press-fitted into one of the multiple sleeves 64 (described below) of the multiple semiconductor devices B1. The outer diameter (diameter) of the base 170A is, for example, approximately 0.6 mm to 1.2 mm. The bulge 170B is provided on the z1 side of the base 170A in the thickness direction z. The bulge 170B bulges out from the base 170A in a direction perpendicular to the thickness direction z. The bulge 170B has a bulge tip 170c. The bulge tip 170c is the portion that bulges out most from the base 170A in a direction perpendicular to the thickness direction z. The bulge tip 170c is located at the center of the bulge 170B in the thickness direction z.

[0034] 14 , each signal terminal 17 is press-fitted into one of the plurality of through holes 903 of the wiring substrate E1. As a result, the bulging portion 170B (bulging tip 170c) of each signal terminal 17 contacts the third wiring 93 arranged in one of the plurality of through holes 903. The third wiring 93 arranged in one of the plurality of through holes 903 is pressed into contact with the bulging portion 170B (bulging tip 170c) of the signal terminal 17 inserted into that through hole 903. Therefore, each signal terminal 17 is press-fitted into the through hole 903 in the thickness direction z, thereby providing electrical continuity with the wiring substrate E1. As each signal terminal 17 is press-fitted into a corresponding one of the plurality of through holes 903, the wiring substrate E1 is supported by each signal terminal 17.

[0035] As shown in FIGS. 3, 9, and 11 to 13, a plurality of mounting holes 951 and a plurality of positioning holes 952 are formed in the wiring board E1.

[0036] As shown in FIGS. 3, 9, and 11 to 13, a plurality of pedestal portions 72 (e.g., second portions 722) are individually inserted into the plurality of mounting holes 951. Each mounting hole 951 is formed, for example, as a perfect circle in plan view. The diameter of each mounting hole 951 in plan view is smaller than the diameter of each pedestal portion 72 (particularly the first portions 721) in plan view. Therefore, the wiring substrate E1 is held above (on the z1 side of) the first portions 721 in the thickness direction z.

[0037] As shown in FIGS. 3 and 13 , a plurality of positioning portions 73 are individually inserted into the plurality of positioning holes 952. In the illustrated example, two positioning holes 952 are formed in the wiring substrate E1. One of the two positioning holes 952 (the positioning hole 952 located on the y1 side in the second direction y) is formed as a perfect circle, and the other of the two positioning holes 952 (the positioning hole 952 located on the y2 side in the second direction y) is formed as an elongated hole. This facilitates positioning of the wiring substrate E1 relative to the heat sink C1. In this case, by forming one of the two positioning holes 952 as an elongated hole, misalignment of the heat sink C1 and the wiring substrate E1 due to manufacturing errors can be suppressed.

[0038] Next, configuration examples of the multiple semiconductor devices B1 will be described with reference to Figures 15 to 26. Figures 15 to 26 are enlarged views of one of the multiple semiconductor devices B1. The multiple semiconductor devices B1 all have the same structure. Unless otherwise specified, the semiconductor device B1 described below is common to the first device B11, second device B12, and third device B13.

[0039] 15 to 26 , each semiconductor device B1 (each of the first device B11, second device B12, and third device B13) includes the above-described plurality of power terminals 13, plurality of signal terminals 17, plurality of semiconductor elements 21, and sealing portion 50, as well as a support substrate 11, a pair of thermistors 22, a first conductive member 31, a second conductive member 32, a plurality of wires, and a pair of control wirings 60. The plurality of power terminals 13 include a first power terminal 14, two second power terminals 15, and two third power terminals 16, and the plurality of signal terminals 17 include a first signal terminal 171, a second signal terminal 172, a third signal terminal 173, a fourth signal terminal 174, a pair of fifth signal terminals 181, and a pair of sixth signal terminals 182. The plurality of wires include a plurality of first wires 41, a plurality of second wires 42, a plurality of third wires 43, and a fourth wire 44.

[0040] Each semiconductor device B1 converts a DC power supply voltage applied to a first power terminal 14 and two second power terminals 15 into AC power using a plurality of semiconductor elements 21. The converted AC power is input from two third power terminals 16 to a power supply target such as a motor.

[0041] As shown in Figures 18 and 21, the support substrate 11 supports a plurality of semiconductor elements 21 in the thickness direction z. The support substrate 11 is made of, for example, a DBC (Direct Bonded Copper) substrate. As shown in Figures 21 to 26, the support substrate 11 includes an insulating layer 111, a first wiring layer 112, and a second wiring layer 113. The support substrate 11 is covered with a sealing portion 50 except for a portion of the second wiring layer 113.

[0042] 21 to 26, the insulating layer 111 includes a portion interposed between the first wiring layer 112 and the second wiring layer 113 in the thickness direction z. The insulating layer 111 is made of a material with relatively high thermal conductivity. The insulating layer 111 is made of ceramics containing aluminum nitride (AlN), for example. The insulating layer 111 may be made of ceramics or an insulating resin sheet.

[0043] As shown in FIGS. 18 and 21 to 26, the first wiring layer 112 is located above (on the z1 side of) the insulating layer 111 in the thickness direction z. The first wiring layer 112 contains copper (Cu). As shown in FIG. 18, the first wiring layer 112 is surrounded by the periphery of the insulating layer 111 in a planar view. As shown in FIGS. 18 and 21 to 26, the first wiring layer 112 includes a first mounting portion 1121 and a second mounting portion 1122. The first mounting portion 1121 and the second mounting portion 1122 are each rectangular in a planar view. The first mounting portion 1121 and the second mounting portion 1122 are spaced apart from each other in the first direction x. The first mounting portion 1121 is located on the x1 side of the second mounting portion 1122 in the first direction x. Each of the multiple semiconductor elements 21 is bonded to either the first mounting portion 1121 or the second mounting portion 1122.

[0044] As shown in FIGS. 21 to 26 , the second wiring layer 113 is located below (on the z2 side of) the insulating layer 111 in the thickness direction z. As shown in FIG. 20 , the second wiring layer 113 is exposed from the sealing portion 50. The lower surface of the second wiring layer 113 (the surface facing the z2 side in the thickness direction z) corresponds to the bottom surface of the support substrate 11. The lower surface of the second wiring layer 113 (the bottom surface of the support substrate 11) is in contact with the upper surface of the main body 71 of the heat sink C1 (the surface facing the z1 side in the thickness direction z). The composition of the second wiring layer 113 includes copper. The second wiring layer 113 is rectangular in plan view. The second wiring layer 113 is surrounded by the periphery of the insulating layer 111 in plan view.

[0045] As shown in FIGS. 18 and 21 , each of the multiple semiconductor elements 21 is mounted on either the first mounting portion 1121 or the second mounting portion 1122. Each semiconductor element 21 is, for example, a MOSFET. Alternatively, each semiconductor element 21 may be a switching element such as an IGBT or a diode. In the description of the semiconductor device B1, the semiconductor element 21 is an n-channel MOSFET with a vertical structure. The semiconductor element 21 includes a compound semiconductor substrate. The compound semiconductor substrate has a composition including silicon carbide (SiC) or silicon (Si).

[0046] As shown in FIGS. 18 and 21 , in each semiconductor device B1, the multiple semiconductor elements 21 include multiple first elements 21A and multiple second elements 21B. The structure of each of the multiple second elements 21B is the same as the structure of each of the multiple first elements 21A. As shown in FIGS. 18 , 21 , and 22 , the multiple first elements 21A are mounted on a first mounting portion 1121. The multiple first elements 21A are arranged along the second direction y. As shown in FIGS. 18 , 21 , and 23 , the multiple second elements 21B are mounted on a second mounting portion 1122. The multiple second elements 21B are arranged along the second direction y.

[0047] As shown in FIGS. 18, 22 and 23, the plurality of semiconductor elements 21 have a first electrode 211, a second electrode 212, a third electrode 213 and two fourth electrodes 214.

[0048] 22 and 23 , the first electrode 211 faces either the first mounting portion 1121 or the second mounting portion 1122. A current corresponding to the power before being converted by the semiconductor element 21 flows through the first electrode 211. In other words, the first electrode 211 corresponds to the drain electrode of the semiconductor element 21.

[0049] 22 and 23 , the second electrode 212 is located on the opposite side of the first electrode 211 in the thickness direction z. A current corresponding to the power converted by the semiconductor element 21 flows through the second electrode 212. In other words, the second electrode 212 corresponds to the source electrode of the semiconductor element 21.

[0050] 18 , the third electrode 213 is located on the same side as the second electrode 212 in the thickness direction z. A drive signal (gate voltage) for driving the semiconductor element 21 is input to the third electrode 213. That is, the third electrode 213 corresponds to the gate electrode of the semiconductor element 21. As shown in FIG. 18 , the area of ​​the third electrode 213 is smaller than the area of ​​the second electrode 212 in a plan view.

[0051] 18 , 22 , and 23 , the two fourth electrodes 214 are located on the same side as the second electrode 212 in the thickness direction z and adjacent to the third electrode 213 in the first direction x. In the illustrated example, the two fourth electrodes 214 are arranged on both sides of the third electrode 213 in the first direction x, with the third electrode 213 sandwiched therebetween. The potential of each fourth electrode 214 is equal to the potential of the second electrode 212. Unlike the illustrated example, each semiconductor element 21 may include only one of the two fourth electrodes 214, or may include neither of the two fourth electrodes 214.

[0052] As shown in FIGS. 22 and 23 , the conductive bonding layer 23 is interposed between either the first mounting portion 1121 or the second mounting portion 1122 and the first electrode 211 of one of the multiple semiconductor elements 21. The conductive bonding layer 23 is, for example, solder. Alternatively, the conductive bonding layer 23 may include a sintered body of metal particles. The first electrodes 211 of the multiple first elements 21A are conductively bonded to the first mounting portion 1121 via the conductive bonding layer 23. As a result, each of the first electrodes 211 of the multiple first elements 21A is electrically connected to the first mounting portion 1121. The first electrodes 211 of the multiple second elements 21B are conductively bonded to the second mounting portion 1122 via the conductive bonding layer 23. As a result, each of the first electrodes 211 of the multiple second elements 21B is electrically connected to the second mounting portion 1122.

[0053] The plurality of power terminals 13 are electrically connected to the plurality of semiconductor elements 21, respectively. A current corresponding to the power before being converted by the plurality of semiconductor elements 21 or a current corresponding to the power after being converted by the plurality of semiconductor elements 21 flows through the plurality of power terminals 13. The plurality of power terminals 13 include a first power terminal 14, two second power terminals 15, and two third power terminals 16.

[0054] As shown in FIGS. 18 and 24 , the first power terminal 14 is joined to the first mounting portion 1121. This joining method is not limited to any particular method and may be performed using a conductive joining material (e.g., solder), laser welding, or crimping. The first power terminal 14 is electrically connected to the first electrodes 211 of the multiple first elements 21A via the first mounting portion 1121. The first power terminal 14 is a P terminal (positive electrode) to which a DC power supply voltage to be converted into power is applied. As shown in FIG. 18 , the first power terminal 14 is located on the opposite side of the second mounting portion 1122 in the first direction x, with the first mounting portion 1121 sandwiched therebetween. The first power terminal 14 extends from the first mounting portion 1121 to one side (x1 side) in the first direction x and protrudes from the sealing portion 50 to one side (x1 side) in the first direction x. 17 and 24 , the first power terminal 14 includes a portion covered by the sealing portion 50 and a portion exposed from the sealing portion 50. In the first power terminal 14, the portion covered by the sealing portion 50 is joined to the first mounting portion 1121. In the first power terminal 14, the portion exposed from the sealing portion 50 is used as the aforementioned P terminal of each semiconductor device B1.

[0055] A second conductive member 32 is joined to the two second power terminals 15. The two second power terminals 15 are electrically connected to the second electrodes 212 of the multiple second elements 21B via the second conductive member 32. The two second power terminals 15 are N terminals (negative electrodes) to which the DC power supply voltage to be converted is applied. The two second power terminals 15 are spaced apart from each other in the second direction y. The first power terminal 14 is located between the two second power terminals 15. As shown in FIG. 18 , the two second power terminals 15 are located on the same side as the first power terminal 14 with respect to the first mounting portion 1121 and the second mounting portion 1122 in the first direction x. The two second power terminals 15 are spaced apart from the first mounting portion 1121 and the second mounting portion 1122. Each of the two second power terminals 15 extends in the first direction x and protrudes from the sealing portion 50 to one side in the first direction x (x1 side). As shown in Figures 17 and 21 , each of the two second power terminals 15 includes a portion covered by the sealing portion 50 and a portion exposed from the sealing portion 50. In each second power terminal 15, a second conductive member 32 is joined to the portion covered by the sealing portion 50. In each second power terminal 15, the portion exposed from the sealing portion 50 is used as the aforementioned N terminal of each semiconductor device B1.

[0056] As shown in FIGS. 18 and 21 , the two third power terminals 16 are each joined to the second mounting portion 1122. This joining is not limited to any particular method and may be performed using a conductive joining material (e.g., solder), laser welding, or crimping. The two third power terminals 16 are electrically connected to the first electrodes 211 of the plurality of second elements 21B via the second mounting portion 1122. The two third power terminals 16 are electrically connected to the second electrodes 212 of the plurality of first elements 21A via the second mounting portion 1122 and the first conductive member 31. AC power converted by the plurality of semiconductor elements 21 (the plurality of first elements 21A and the plurality of second elements 21B) is output from the two third power terminals 16. In other words, the two third power terminals 16 are output terminals for the AC power. The two third power terminals 16 are spaced apart from each other in the second direction y. As shown in FIG. 18 , the two third power terminals 16 are located on the opposite side of the first mounting portion 1121 in the first direction x, with the second mounting portion 1122 sandwiched therebetween. Each of the two third power terminals 16 extends from the second mounting portion 1122 toward the other side (x2 side) in the first direction x and protrudes from the sealing portion 50 toward the other side (x2 side) in the first direction x. As shown in FIGS. 17 and 21 , each of the two third power terminals 16 includes a portion covered by the sealing portion 50 and a portion exposed from the sealing portion 50. In each third power terminal 16, the portion covered by the sealing portion 50 is joined to the second mounting portion 1122. In each third power terminal 16, the portion exposed from the sealing portion 50 is used as the aforementioned output terminal of each semiconductor device B1.

[0057] The pair of control wirings 60 constitute part of the conductive paths between the plurality of signal terminals 17 and the plurality of semiconductor elements 21. As shown in FIGS. 17 , 18 , and 24 , the pair of control wirings 60 includes a first wiring 601 and a second wiring 602. The first wiring 601 is located between the plurality of first elements 21A and the first power terminal 14 and two second power terminals 15 in the first direction x. The first wiring 601 is bonded to the first mounting portion 1121 as shown in FIGS. 18 and 24 . The second wiring 602 is located between the plurality of second elements 21B and two third power terminals 16 in the first direction x. The second wiring 602 is bonded to the second mounting portion 1122 as shown in FIGS. 18 and 24 . The pair of control wirings 60 includes an insulating layer 61, a plurality of wiring layers 62, a metal layer 63, and a plurality of sleeves 64. The pair of control wirings 60 are covered by the sealing portion 50 except for a portion of each of the plurality of sleeves 64. Unless otherwise specified, the insulating layer 61, the plurality of wiring layers 62, the metal layer 63, and the plurality of sleeves 64 described below are common to the pair of control wirings 60 (first wiring 601 and second wiring 602).

[0058] 24 , the insulating layer 61 includes a portion interposed between the plurality of wiring layers 62 and the metal layer 63 in the thickness direction z. The insulating layer 61 is made of, for example, ceramics. The insulating layer 61 may be made of an insulating resin sheet instead of ceramics.

[0059] 24 , the multiple wiring layers 62 are located above (on the z1 side of) the insulating layer 61 in the thickness direction z. The multiple wiring layers 62 contain copper. As shown in FIG. 18 , the multiple wiring layers 62 include a first wiring layer 621, a second wiring layer 622, a third wiring layer 623, a fourth wiring layer 624, and a fifth wiring layer 625.

[0060] 24 , the metal layer 63 is located on the opposite side of the multiple wiring layers 62 in the thickness direction z, with the insulating layer 61 sandwiched therebetween. The metal layer 63 contains copper. The metal layer 63 of the first wiring 601 is bonded to the first mounting portion 1121 by an adhesive layer (not shown). The metal layer 63 of the second wiring 602 is bonded to the second mounting portion 1122 by an adhesive layer (not shown). These adhesive layers are made of materials that may or may not be conductive. For example, these adhesive layers are solder.

[0061] As shown in FIG. 24 , the multiple sleeves 64 are bonded to the multiple wiring layers 62, respectively. This bonding is performed using a conductive bonding layer (e.g., solder) not shown. The multiple sleeves 64 are made of a conductive material such as metal. Each of the multiple sleeves 64 has a cylindrical shape extending along the thickness direction z. One end of each of the multiple sleeves 64 (the edge on the z2 side in the thickness direction z) is conductively bonded to one of the multiple wiring layers 62. As shown in FIG. 24 , the other end of each of the multiple sleeves 64 (the edge on the z1 side in the thickness direction z) is exposed from the sealing portion 50.

[0062] As shown in FIG. 18 , one of the pair of thermistors 22 straddles and is conductively joined to a pair of third wiring layers 623 of the first wiring 601. As shown in FIG. 18 , the other of the pair of thermistors 22 straddles and is conductively joined to a pair of third wiring layers 623 of the second wiring 602. Each of the pair of thermistors 22 is, for example, an NTC (Negative Temperature Coefficient) thermistor. NTC thermistors have the characteristic of gradually decreasing resistance as temperature increases. Each of the pair of thermistors 22 is used as a temperature detection sensor for the semiconductor device B1.

[0063] As shown in FIGS. 15 and 24 , each of the signal terminals 17 is a metal pin extending in the thickness direction z. The signal terminals 17 protrude from a top surface 51 (described later) of the sealing portion 50. The signal terminals 17 are individually press-fitted into the sleeves 64 of the pair of control wires 60. As a result, each of the signal terminals 17 is supported by one of the sleeves 64 and is electrically connected to one of the wiring layers 62. The signal terminals 17 include a first signal terminal 171, a second signal terminal 172, a third signal terminal 173, a fourth signal terminal 174, a pair of fifth signal terminals 181, a pair of sixth signal terminals 182, and a seventh signal terminal 19. These first signal terminal 171, second signal terminal 172, third signal terminal 173, fourth signal terminal 174, a pair of fifth signal terminals 181, a pair of sixth signal terminals 182 and seventh signal terminal 19 are inserted into wiring board E1 and input or output each signal to wiring board E1.

[0064] The first signal terminal 171 is press-fitted into one of the multiple sleeves 64 that is joined to the first wiring layer 621 of the first wiring 601. As a result, the first signal terminal 171 is supported by the sleeve 64 and is electrically connected to the first wiring layer 621 of the first wiring 601. Furthermore, the first signal terminal 171 is electrically connected to the third electrodes 213 of the multiple first elements 21A. A gate voltage for driving the multiple first elements 21A is applied to the first signal terminal 171.

[0065] The second signal terminal 172 is press-fitted into one of the multiple sleeves 64 that is joined to the first wiring layer 621 of the second wiring 602. As a result, the second signal terminal 172 is supported by the sleeve 64 and is electrically connected to the first wiring layer 621 of the second wiring 602. Furthermore, the second signal terminal 172 is electrically connected to the third electrodes 213 of the multiple second elements 21B. A gate voltage for driving the multiple second elements 21B is applied to the second signal terminal 172.

[0066] 18 , the third signal terminal 173 is located adjacent to the first signal terminal 171 in the second direction y. The third signal terminal 173 is press-fitted into one of the multiple sleeves 64 that is joined to the second wiring layer 622 of the first wiring 601. As a result, the third signal terminal 173 is supported by the sleeve 64 and is electrically connected to the second wiring layer 622 of the first wiring 601. Furthermore, the third signal terminal 173 is electrically connected to the fourth electrodes 214 of the multiple first elements 21A. A voltage corresponding to the maximum current among the currents flowing through the fourth electrodes 214 of the multiple first elements 21A is applied to the third signal terminal 173.

[0067] 18 , the fourth signal terminal 174 is located adjacent to the second signal terminal 172 in the second direction y. The fourth signal terminal 174 is press-fitted into one of the multiple sleeves 64 that is joined to the second wiring layer 622 of the second wiring 602. As a result, the fourth signal terminal 174 is supported by the sleeve 64 and is electrically connected to the second wiring layer 622 of the second wiring 602. Furthermore, the fourth signal terminal 174 is electrically connected to the fourth electrodes 214 of the multiple second elements 21B. A voltage corresponding to the maximum current among the currents flowing through the fourth electrodes 214 of the multiple second elements 21B is applied to the fourth signal terminal 174.

[0068] 18 , the pair of fifth signal terminals 181 are located on the opposite side of the first signal terminal 171 from the third signal terminal 173 in the second direction y. The pair of fifth signal terminals 181 are adjacent to each other in the second direction y. The pair of fifth signal terminals 181 are individually press-fitted into a pair of sleeves 64 that are respectively joined to a pair of third wiring layers 623 of the first wiring 601. As a result, the pair of fifth signal terminals 181 are individually supported by the pair of sleeves 64 and are individually electrically connected to the pair of third wiring layers 623 of the first wiring 601. Furthermore, the pair of fifth signal terminals 181 are electrically connected to the thermistor 22 on the first wiring 601.

[0069] 18 , the pair of sixth signal terminals 182 are located on the opposite side of the second signal terminal 172 from the fourth signal terminal 174 in the second direction y. The pair of sixth signal terminals 182 are adjacent to each other in the second direction y. The pair of sixth signal terminals 182 are individually press-fitted into a pair of sleeves 64 that are respectively joined to a pair of third wiring layers 623 of the second wiring 602. As a result, the pair of sixth signal terminals 182 are individually supported by the pair of sleeves 64 and are individually electrically connected to the pair of third wiring layers 623 of the second wiring 602. Furthermore, the pair of sixth signal terminals 182 are electrically connected to the thermistor 22 on the second wiring 602.

[0070] 18 , the seventh signal terminal 19 is located on the opposite side of the first signal terminal 171 in the second direction y, with the third signal terminal 173 sandwiched therebetween. The seventh signal terminal 19 is press-fitted into a sleeve 64 joined to the fifth wiring layer 625 of the first wiring 601. As a result, the seventh signal terminal 19 is supported by the sleeve 64 and is electrically connected to the fifth wiring layer 625 of the first wiring 601. Furthermore, the seventh signal terminal 19 is electrically connected to the first mounting portion 1121. A voltage equivalent to the DC power input to the first power terminal 14 is applied to the seventh signal terminal 19.

[0071] The plurality of first wires 41, the plurality of second wires 42, the plurality of third wires 43, and the fourth wire 44 electrically connect portions spaced apart from one another. The plurality of first wires 41, the plurality of second wires 42, the plurality of third wires 43, and the fourth wire 44 are each bonding wires. Note that the plurality of first wires 41, the plurality of second wires 42, the plurality of third wires 43, and the fourth wire 44 are omitted in Figure 17 and Figures 21 to 24.

[0072] As shown in FIG. 18 , the plurality of first wires 41 include first wires 41 conductively joined to the third electrodes 213 of the plurality of first elements 21A and the fourth wiring layer 624 of the first wiring 601. As shown in FIG. 18 , the plurality of third wires 43 include third wires 43 conductively joined to the fourth wiring layer 624 of the first wiring 601 and the first wiring layer 621 of the first wiring 601. As a result, the first signal terminal 171 is electrically connected to the third electrodes 213 of the plurality of first elements 21A. The composition of the plurality of first wires 41 and the plurality of third wires 43 includes gold (Au). Alternatively, the composition of the plurality of first wires 41 and the plurality of third wires 43 may include copper or aluminum.

[0073] 18, the plurality of first wires 41 includes first wires 41 conductively bonded to the third electrodes 213 of the plurality of second elements 21B and the fourth wiring layer 624 of the second wiring 602. Further, the plurality of third wires 43 includes third wires 43 conductively bonded to the fourth wiring layer 624 of the second wiring 602 and the first wiring layer 621 of the second wiring 602. As a result, the second signal terminal 172 is electrically connected to the third electrodes 213 of the plurality of second elements 21B.

[0074] As shown in FIG. 18 , the plurality of second wires 42 includes a second wire 42 conductively bonded to one of the two fourth electrodes 214 of the plurality of first elements 21A and to the second wiring layer 622 of the first wiring 601. As a result, the third signal terminal 173 is electrically connected to one of the two fourth electrodes 214 of the plurality of first elements 21A. Furthermore, as shown in FIG. 18 , the plurality of second wires 42 includes a second wire 42 conductively bonded to one of the two fourth electrodes 214 of the plurality of second elements 21B and to the second wiring layer 622 of the second wiring 602. As a result, the fourth signal terminal 174 is electrically connected to one of the two fourth electrodes 214 of the plurality of second elements 21B. The composition of the plurality of second wires 42 includes gold. Alternatively, the composition of the plurality of second wires 42 may include copper or aluminum. When each semiconductor element 21 (each of the plurality of first elements 21A and the plurality of second elements 21B) does not include either of the two fourth electrodes 214, the plurality of second wires 42 are bonded one by one to the second electrodes 212 of the plurality of semiconductor elements 21.

[0075] 18 , the fourth wire 44 is conductively bonded to the fifth wiring layer 625 of the first wiring 601 and the first mounting portion 1121. As a result, the seventh signal terminal 19 is electrically connected to the first electrodes 211 of the multiple first elements 21A via the first mounting portion 1121. The composition of the fourth wire 44 includes gold. Alternatively, the composition of the fourth wire 44 may include copper or aluminum.

[0076] As shown in Figures 18 and 21 , the first conductive member 31 is conductively bonded to the second electrodes 212 of the multiple first elements 21A and the second mounting portion 1122. This allows the second electrodes 212 of the multiple first elements 21A to be electrically connected to the second mounting portion 1122. The first conductive member 31 contains copper. The first conductive member 31 is a metal clip. As shown in Figures 18 and 21 , the first conductive member 31 has a main body 311, multiple first joint portions 312, and multiple second joint portions 313.

[0077] The main body portion 311 forms a major portion of the first conductive member 31. As shown in FIG. 18 , the main body portion 311 extends in the first direction x. As shown in FIGS. 18 and 21 , the main body portion 311 straddles the first mounting portion 1121 and the second mounting portion 1122. In the example shown in FIG. 18 , a plurality of through holes are formed in the main body portion 311. Each of the plurality of through holes penetrates the main body portion 311 in the thickness direction z. In a plan view, the plurality of through holes overlap between the first mounting portion 1121 and the second mounting portion 1122. This allows the sealing portion 50 to flow smoothly downward in the thickness direction z of the main body portion 311 (toward the z2 side in the thickness direction z) during the formation of the sealing portion 50.

[0078] As shown in FIGS. 18 , 21 , and 22 , the multiple first joints 312 are individually joined to the second electrodes 212 of the multiple first elements 21A. Each of the multiple first joints 312 faces one of the second electrodes 212 of the multiple first elements 21A. In a plan view, each first joint 312 extends from the main body 311 toward the x1 side in the first direction x. In the illustrated example, the multiple first joints 312 are bifurcated from the main body 311, but they do not have to be bifurcated. The base end of each first joint 312 (the end connected to the main body 311) is bent downward in the thickness direction z (toward the z2 side in the thickness direction z). Therefore, the tip of each first joint 312 (the end opposite to the end connected to the main body 311) is located downward in the thickness direction z (toward the z2 side in the thickness direction z) from the main body 311 in the thickness direction z.

[0079] 18 and 21 , the multiple second joint portions 313 are joined to the second mounting portion 1122. Each of the multiple second joint portions 313 faces the second mounting portion 1122. In a plan view, each second joint portion 313 extends from the main body portion 311 toward the x2 side in the first direction x. The base end of each second joint portion 313 (the end connected to the main body portion 311) is bent downward in the thickness direction z (toward the z2 side in the thickness direction z). Therefore, the tip end of each second joint portion 313 (the end opposite to the end connected to the main body portion 311) is located downward in the thickness direction z (toward the z2 side in the thickness direction z) from the main body portion 311 in the thickness direction z.

[0080] The semiconductor device B1 further includes a plurality of first conductive bonding layers 33. The plurality of first conductive bonding layers 33 are respectively interposed between the second electrodes 212 of the plurality of first elements 21A and the plurality of first bonding portions 312. The first conductive bonding layers 33 conductively bond the second electrodes 212 of the plurality of first elements 21A to the plurality of first bonding portions 312. The first conductive bonding layers 33 are, for example, solder. Alternatively, the first conductive bonding layers 33 may include a sintered body of metal particles.

[0081] The semiconductor device B1 further includes a plurality of second conductive bonding layers 34. The plurality of second conductive bonding layers 34 are respectively interposed between the second mounting portion 1122 and the plurality of second bonding portions 313. The second conductive bonding layers 34 conductively bond the second mounting portion 1122 and the plurality of second bonding portions 313. The second conductive bonding layers 34 are, for example, solder. Alternatively, the second conductive bonding layers 34 may include a sintered body of metal particles.

[0082] As shown in Fig. 17 , the second conductive member 32 is conductively joined to the second electrodes 212 of the plurality of second elements 21B and the two second power terminals 15. As a result, the second electrodes 212 of the plurality of second elements 21B are electrically connected to the two second power terminals 15. The second conductive member 32 contains copper. The second conductive member 32 is a metal clip. As shown in Figs. 17 and 21 to 26 , the second conductive member 32 includes a main body portion 321, a plurality of third joint portions 322, and a pair of fourth joint portions 323.

[0083] The main body portion 321 forms a main portion of the second conductive member 32. As shown in Figures 21 and 25, the main body portion 321 is disposed parallel to the upper surface of the first mounting portion 1121 and the upper surface of the second mounting portion 1122. The main body portion 321 is spaced apart from the main body portion 311 of the first conductive member 31, as well as from the first mounting portion 1121 and the second mounting portion 1122.

[0084] As shown in FIGS. 17 , 21 , and 23 , the third joints 322 are individually joined to the second electrodes 212 of the second elements 21B. Each of the third joints 322 faces one of the second electrodes 212 of the second elements 21B. In a plan view, the third joints 322 extend in the first direction x from the main body 321. The base end of each third joint 322 (the end connected to the main body 321) is bent downward in the thickness direction z (toward the z2 side in the thickness direction z). Therefore, the tip of each third joint 322 (the end opposite to the end connected to the main body 321) is located downward in the thickness direction z (toward the z2 side in the thickness direction z) from the main body 321 in the thickness direction z.

[0085] 17 and 21 , the pair of fourth joint portions 323 are individually joined to the two second power terminals 15. Each of the pair of fourth joint portions 323 faces a corresponding one of the two second power terminals 15.

[0086] The semiconductor device B1 further includes a plurality of third conductive bonding layers 35. The plurality of third conductive bonding layers 35 are respectively interposed between the second electrodes 212 of the plurality of second elements 21B and the plurality of third bonding portions 322. The plurality of third conductive bonding layers 35 conductively bond the second electrodes 212 of the plurality of second elements 21B to the plurality of third bonding portions 322. The third conductive bonding layer 35 is, for example, solder. Alternatively, the third conductive bonding layer 35 may include a sintered body of metal particles.

[0087] The semiconductor device B1 further includes two fourth conductive bonding layers 36. The two fourth conductive bonding layers 36 are respectively interposed between the two second power terminals 15 and the pair of fourth bonding portions 323. The two fourth conductive bonding layers 36 conductively bond the two second power terminals 15 and the pair of fourth bonding portions 323. The fourth conductive bonding layers 36 are, for example, solder. Alternatively, the fourth conductive bonding layers 36 may include a sintered body of metal particles.

[0088] As shown in FIGS. 15 to 26 , the sealing portion 50 covers the semiconductor elements 21, the first conductive members 31, the second conductive members 32, the first wires 41, the second wires 42, the third wires 43, and the fourth wires 44. Furthermore, the sealing portion 50 covers the support substrate 11, a portion of each of the power terminals 13, and a portion of each of the signal terminals 17. The sealing portion 50 has electrical insulation properties. The sealing portion 50 contains, for example, a black epoxy resin. The sealing portion 50 is formed, for example, by molding. As shown in FIGS. 15 to 17 and 19 to 26 , the sealing portion 50 has a top surface 51, a bottom surface 52, a plurality of resin side surfaces 53, and a pair of recesses 55.

[0089] 21 and 24 to 26, the top surface 51 faces the same direction in the thickness direction z as the upper surfaces of the first mounting portion 1121 and the second mounting portion 1122 (the z1 side in the thickness direction z). The top surface 51 of each semiconductor device B1 contacts the mounting member D1. As shown in FIG. 27, the wiring substrate E1 is disposed at a fixed distance from the top surface 51 of the sealing portion 50 of each semiconductor device B1. The fourth dimension L4, which is the length in the thickness direction z from the top surface 51 of the sealing portion 50 to the bulging tip portion 170c of the signal terminal 17, is, for example, approximately 5 mm to 15 mm.

[0090] 19, 21, and 24 to 26, bottom surface 52 faces the opposite side to top surface 51 in thickness direction z (the z2 side in thickness direction z). As shown in FIGS. 20, 21, and 24 to 26, second wiring layer 113 of support substrate 11 is exposed from bottom surface 52. Bottom surface 52 of each semiconductor device B1 contacts main body 71 of heat sink C1.

[0091] The plurality of resin side surfaces 53 are each connected to the top surface 51. The plurality of resin side surfaces 53 include a pair of first side surfaces 531 and a pair of second side surfaces 532.

[0092] As shown in Figures 16, 17, 19 to 21, and 24, the pair of first side surfaces 531 are spaced apart from each other in the first direction x. The pair of first side surfaces 531 face opposite each other in the first direction x and extend in the second direction y. The pair of first side surfaces 531 are connected to the top surface 51. A first power terminal 14 and two second power terminals 15 protrude from the first side surface 531 on the x1 side in the first direction x. Two third power terminals 16 protrude from the first side surface 531 on the x2 side in the first direction x.

[0093] 16 , 17 , 20 , 25 , and 26 , the pair of second side surfaces 532 are spaced apart from each other in the second direction y. The pair of second side surfaces 532 face opposite each other in the second direction y and extend in the first direction x. The pair of second side surfaces 532 are connected to the top surface 51 and the bottom surface 52.

[0094] 16 , 17 , and 20 , the pair of recesses 55 are recessed in the first direction x from the first side surface 531 on the x1 side in the first direction x of the pair of first side surfaces 531. The pair of recesses 55 extend from the top surface 51 to the bottom surface 52 in the thickness direction z. The pair of recesses 55 are located on both sides of the first power terminal 14 in the second direction y.

[0095] The specific configuration of the semiconductor device B1 described above is merely an example and is not limited to the above example. The number of signal terminals 17, the signals input / output to / from each signal terminal 17, the number of semiconductor elements 21, the configuration of the first wiring 601 and the second wiring 602, and the like may be changed as appropriate. The support substrate 11 may have a conductive plate-like member bonded to the first wiring layer 112 (each of the first mounting portion 1121 and the second mounting portion 1122). In this case, the plurality of semiconductor elements 21 (each of the plurality of first elements 21A and the plurality of second elements 21B) and a pair of control wirings 60 are mounted on the conductive plate-like member.

[0096] 28 is a schematic diagram of a vehicle F1 equipped with a semiconductor module A10. The vehicle F1 is, for example, an electric vehicle (EV).

[0097] As shown in Figure 28, the vehicle F1 includes an on-board charger 96, a storage battery 97, and a drive system 98. The on-board charger 96 is supplied with power wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power may be supplied from the power supply facility to the on-board charger 96 via a wired connection. The on-board charger 96 is configured with a step-up DC-DC converter. The voltage of the power supplied to the on-board charger 96 is stepped up by the converter and then supplied to the storage battery 97. The stepped-up voltage is, for example, 600V.

[0098] The drive system 98 drives the vehicle F1. The drive system 98 includes an inverter 981 and a drive source 982. The semiconductor module A10 (semiconductor device B1) constitutes part of the inverter 981. Power stored in the storage battery 97 is supplied to the inverter 981. The power supplied from the storage battery 97 to the inverter 981 is DC power. In addition, unlike the power system shown in FIG. 28 , a step-up DC-DC converter may be further provided between the storage battery 97 and the inverter 981. The inverter 981 converts DC power into AC power. The inverter 981 including the semiconductor device B1 is electrically connected to a drive source 982. The drive source 982 includes an AC motor and a transmission. When AC power converted by the inverter 981 is supplied to the drive source 982, the AC motor rotates, and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotational speed transmitted from the AC motor and then rotates the drive shaft of the vehicle F1, thereby driving the vehicle F1. To drive the vehicle F1, it is necessary to freely control the rotational speed of the AC motor based on information such as the amount of fluctuation in the accelerator pedal. The semiconductor device B1 in the inverter 981 is necessary to output AC power whose frequency is appropriately changed to correspond to the required rotational speed of the AC motor.

[0099] The functions and effects of the semiconductor module A10 are as follows.

[0100] In the semiconductor module A10, the base material 90 of the wiring substrate E1 has a first recess 904. The first recess 904 is recessed from the inner surface of the through-hole 903 and from a second surface 902 of the base material 90 facing downward in the thickness direction z (the z2 side). The bulging portion 170B of the signal terminal 17 contacts the third wiring 93 arranged on the inner surface of the through-hole 903. With this configuration, when the signal terminal 17 is press-fitted into the through-hole 903 from its tip side (the z1 side in the thickness direction z) during assembly of the semiconductor module A10, even if the signal terminal 17 is slightly misaligned with respect to the through-hole 903, the tip of the signal terminal 17 is guided by the first recess 904 (the fourth wiring 94 on the first recess 904). This facilitates assembly of the semiconductor module A10 (the semiconductor device B1 and the wiring substrate E1).

[0101] The first recess 904 includes a portion (first portion) that is positioned radially inward of the through-hole 903 as it moves toward the z1 side in the thickness direction z. The first recess 904 has a conical shape that is inclined so that the entire first recess 904 is positioned radially inward of the through-hole 903 as it moves toward the z1 side in the thickness direction z. With this configuration, when the signal terminal 17 is press-fitted into the through-hole 903, it is appropriately guided by the first recess 904 (the fourth wiring 94 on the first recess 904). This is preferable in terms of facilitating assembly of the semiconductor module A10 (the semiconductor device B1 and the wiring substrate E1).

[0102] When the semiconductor module A10 is mounted on a vehicle F1, for example, vibrations occurring while the vehicle F1 is traveling can displace the signal terminal 17 (base 170A) between the wiring substrate E1 and the top surface 51 of the sealing portion 50 in a direction perpendicular to the thickness direction z. If the thickness (first dimension L1) of the substrate 90 increases, the signal terminal 17 may come into contact with the opening end of the substrate 90 on the lower side (z2 side) in the thickness direction z, potentially causing stress. In this embodiment, the first recess 904 is connected to the through-hole 903 on the lower side (z2 side) in the thickness direction z, and the opening end of the substrate 90 on the lower side (z2 side) in the thickness direction z is larger than the diameter of the through-hole 903. The ratio of the second dimension L2, which is the radial length of the through-hole 903 from the first edge 904a to the second edge 904b of the first recess 904, to the thickness (first dimension L1) of the substrate 90 is 5% to 40%. The ratio of the third dimension L3, which is the length in the thickness direction z from the first edge 904a to the second edge 904b, to the thickness (first dimension L1) of the base material 90 is, for example, 5% to 40%. With this configuration, even if the signal terminal 17 (base 170A) is displaced in a direction perpendicular to the thickness direction z due to the vibration, the signal terminal 17 is prevented from contacting the opening end on the lower side (z2 side) in the thickness direction z of the base material 90. Therefore, unnecessary stress is prevented from being generated in the signal terminal 17 and the wiring substrate E1, and the durability of the semiconductor module A10 can be improved.

[0103] 29 and 30 show modified examples of the semiconductor module of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are given the same reference numerals as in the above embodiment, and redundant explanations will be omitted. Furthermore, the configurations of the various parts in each modified example and each embodiment can be combined with each other as appropriate to the extent that no technical contradictions arise.

[0104] First Modification: Fig. 29 shows a first modification of the semiconductor module A10. Fig. 29 is a partially enlarged cross-sectional view showing a semiconductor module A11 according to the first modification, and shows the same cross-section as Fig. 14. The semiconductor module A11 of this modification differs from the semiconductor module A10 in the configuration of the first recess 904 in the base material 90.

[0105] 29 , the first recess 904 includes a first portion 9041 and a second portion 9042. The first portion 9041 has a conical shape that slopes toward the z1 side in the thickness direction z so as to be positioned radially inward of the through-hole 903. The first portion 9041 has a first edge 904a that contacts the inner surface of the through-hole 903. The second portion 9042 has a cylindrical shape that extends along the thickness direction z and is connected to the z2 side in the thickness direction z relative to the first portion 9041. The second portion 9042 has a second edge 904b that contacts the second surface 902.

[0106] In the semiconductor module A11, the base material 90 of the wiring substrate E1 also has a first recess 904. The first recess 904 is recessed from the inner surface of the through-hole 903 and from the second surface 902 of the base material 90, which faces downward in the thickness direction z (the z2 side). The bulging portion 170B of the signal terminal 17 contacts the third wiring 93 disposed on the inner surface of the through-hole 903. Therefore, when assembling the semiconductor module A11, when the signal terminal 17 is press-fitted into the through-hole 903 from its tip side (the z1 side in the thickness direction z) first, even if the signal terminal 17 is slightly misaligned with respect to the through-hole 903, the tip of the signal terminal 17 is guided by the first recess 904 (the fourth wiring 94 on the first recess 904). This facilitates assembly of the semiconductor module A11 (the semiconductor device B1 and the wiring substrate E1). Additionally, the semiconductor module A11 exhibits the same effects as the semiconductor module A10 of the above embodiment.

[0107] Second Modification: Fig. 30 shows a second modification of the semiconductor module A10. Fig. 30 is a partially enlarged cross-sectional view showing a semiconductor module A12 according to the second modification, and shows the same cross section as Fig. 14. The semiconductor module A12 of this modification differs from the semiconductor module A10 in the configuration of the first recess 904 in the base material 90.

[0108] 30 , the first recess 904 includes a portion (first portion) that is positioned radially inward of the through hole 903 as it moves toward the z1 side in the thickness direction z. In this modification, the entire first recess 904 is spherical and is positioned radially inward of the through hole 903 as it moves toward the z1 side in the thickness direction z.

[0109] In the semiconductor module A12, the base material 90 of the wiring substrate E1 also has a first recess 904. The first recess 904 is recessed from the inner surface of the through-hole 903 and from the second surface 902 of the base material 90, which faces downward in the thickness direction z (the z2 side). The bulging portion 170B of the signal terminal 17 contacts the third wiring 93 disposed on the inner surface of the through-hole 903. Therefore, when assembling the semiconductor module A12, when the signal terminal 17 is press-fitted into the through-hole 903 from its tip side (the z1 side in the thickness direction z) first, even if the signal terminal 17 is slightly misaligned with respect to the through-hole 903, the tip of the signal terminal 17 is guided by the first recess 904 (the fourth wiring 94 on the first recess 904). This facilitates assembly of the semiconductor module A12 (the semiconductor device B1 and the wiring substrate E1). The semiconductor module A12 also provides the same advantages as the semiconductor module A10 of the above embodiment.

[0110] The semiconductor module according to the present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the semiconductor module according to the present disclosure can be freely modified in various ways.

[0111] The present disclosure includes embodiments described in the following appendices: Appendix 1. a semiconductor device including a semiconductor element, a sealing portion covering the semiconductor element, and a signal terminal protruding from the sealing portion to one side in a thickness direction of the sealing portion and conducting to the semiconductor element; and a wiring board arranged on one side in the thickness direction of the sealing portion, wherein the wiring board includes a base material, a first wiring, a second wiring, a third wiring, and a fourth wiring, and the base material has a first surface facing one side in the thickness direction and a second surface facing the other side in the thickness direction, at least one through hole penetrating in the thickness direction, and an inner surface of the through hole and a first recess recessed from the second surface, wherein the first wiring is arranged on the first surface, the second wiring is arranged on the second surface, the third wiring is arranged on the inner surface of the through hole, and the fourth wiring is arranged in the first recess and is connected to both the second wiring and the third wiring, and the signal terminal has a base portion extending in the thickness direction and a bulging portion bulging from the base portion in a direction perpendicular to the thickness direction, The semiconductor module, wherein the bulge contacts the third wiring. Appendix 2. The semiconductor module according to Appendix 1, wherein the first recess includes a first portion located radially inward of the through hole as it moves toward one side in the thickness direction. Appendix 3. The semiconductor module according to Appendix 2, wherein the first portion is conical. Appendix 4. The semiconductor module according to Appendix 3, wherein the entire first recess is formed by the first portion. Appendix 5. The semiconductor module according to any one of Appendixes 1 to 4, wherein the first recess has a first edge contacting the inner surface of the through hole and a second edge contacting the second surface, and wherein a ratio of a second dimension, which is the radial length of the through hole from the first edge to the second edge, to a first dimension, which is the length in the thickness direction of the base, is 5% to 40%. Appendix 6. The semiconductor module according to Appendix 5, wherein a ratio of a third dimension, which is the length in the thickness direction from the first edge to the second edge, to the first dimension is 5% to 40%. Appendix 7. The semiconductor module according to Appendix 5 or 6, wherein the first dimension is 1.6 mm to 3.2 mm.Appendix 8. The semiconductor module according to any one of Appendixes 1 to 7, wherein the sealing portion has a top surface facing one side in the thickness direction, the bulging portion has a bulging tip portion that bulges most in a direction perpendicular to the thickness direction from the base portion, and a fourth dimension that is a length in the thickness direction from the top surface to the bulging tip portion is 5 mm to 15 mm. Appendix 9. The semiconductor module according to any one of Appendixes 1 to 8, wherein the semiconductor device further comprises a support substrate on which the semiconductor element is mounted and a sleeve mounted on the support substrate, and the base portion is inserted into the sleeve. Appendix 10. The semiconductor module according to Appendix 9, wherein the semiconductor device further comprises a power terminal protruding from the sealing portion in a first direction perpendicular to the thickness direction. Appendix 11. The semiconductor module according to Appendix 10, wherein the semiconductor element includes a first element and a second element, and the power terminal includes a first power terminal electrically connected to the first element and a second power terminal electrically connected to the second element. Appendix 12. The semiconductor module according to Supplementary Note 11, wherein the support substrate includes a first mounting portion on which the first element is mounted and a second mounting portion on which the second element is mounted, the first mounting portion being located on one side in the first direction with respect to the second mounting portion, and the first power terminal and the second power terminal protruding from the sealing portion to one side in the first direction.Supplementary Note 13. The semiconductor module according to Supplementary Note 12, wherein the power terminal includes a third power terminal electrically connected to the first element and the second element, and the third power terminal protruding from the sealing portion to the other side in the first direction.Supplementary Note 14. The semiconductor module according to any of Supplements 10 to 13, comprising a plurality of the semiconductor devices, the plurality of semiconductor devices being arranged in a second direction perpendicular to the thickness direction and the first direction.Supplementary Note 15. The semiconductor module according to claim 14, further comprising a heat sink, wherein the support substrate of each of the plurality of semiconductor devices has a bottom surface facing the other side in the thickness direction, the bottom surface of each of the plurality of semiconductor devices is exposed from the sealing portion, and the heat sink is in contact with the bottom surface of each of the plurality of semiconductor devices.

[0112] A10, A11, A12: Semiconductor module B1: Semiconductor device B11: First device B12: Second device B13: Third device C1: Heat sink D1: Mounting member E1: Wiring board F1: Vehicle L1: First dimension L2: Second dimension L3: Third dimension L4: Fourth dimension 11: Support substrate 111: Insulating layer 112: First wiring layer 1121: First mounting portion 1122: Second mounting portion 113: Second wiring layer 13: Power terminal 14: First power terminal 15: Second power terminal 16: Third power terminal 17: Signal terminal 170A: Base 170B: Bulging portion 170c: Bulging tip 171: First signal terminal 172: Second signal terminal 173: Third signal terminal 174: Fourth signal terminal 181: Fifth signal terminal 182: Sixth signal terminal 19: Seventh signal terminal 21: Semiconductor element 21A: First element 21B: Second element 211: First electrode 212: Second electrode 213: Third electrode 214: Fourth electrode 22: Thermistor 23: Conductive bonding layer 31: First conductive member 311: Main body 312: First bonding portion 313: Second bonding portion 32: Second conductive member 321: Main body 322: Third bonding portion 323: Fourth bonding portion 33: First conductive bonding layer 34: Second conductive bonding layer 35: Third conductive bonding layer 36: Fourth conductive bonding layer 41: First wire 42: Second wire 43: Third wire 44: Fourth wire 50: Sealing portion 51: Top surface 52: Bottom surface 53: Resin side surface 531: First side surface 532: Second side surface 55: Recess 60: Control wiring 601: First wiring 602: Second wiring 61: Insulation layer 62: Wiring layer 621: First wiring layer 622: Second wiring layer 623: Third wiring layer 624: Fourth wiring layer 625: Fifth wiring layer 63: Metal layer 64: Sleeve 71: Main body portion 72: Base portion 721: First portion 722: Second portion 73: Positioning portion 81: Pressing portion 82, 82A,82B: fixing portion 821: both end arrangement portion 822: middle arrangement portion 89: fastener 90: base material 901: first surface 902: second surface 903: through hole 904: first recess 904a: first edge 904b: second edge 9041: first portion 9042: second portion 91: first wiring 92: second wiring 93: third wiring 94: fourth wiring 951: mounting hole 952: positioning hole 96: on-board charger 97: storage battery 98: drive system 981: inverter 982: drive source

Claims

1. a semiconductor device including a semiconductor element, a sealing portion covering the semiconductor element, and a signal terminal protruding from the sealing portion to one side in a thickness direction of the sealing portion and conducting to the semiconductor element; a wiring substrate disposed on one side of the sealing portion in the thickness direction, the wiring board includes a base material, a first wiring, a second wiring, a third wiring, and a fourth wiring; the substrate has a first surface facing one side in the thickness direction, a second surface facing the other side in the thickness direction, at least one through hole penetrating in the thickness direction, and a first recess recessed from an inner surface of the through hole and the second surface; the first wiring is disposed on the first surface, the second wiring is disposed on the second surface, the third wiring is disposed on the inner surface of the through hole, the fourth wiring is disposed in the first recess and is connected to both the second wiring and the third wiring; The signal terminal has a base portion extending in the thickness direction and a bulging portion bulging from the base portion in a direction perpendicular to the thickness direction, The bulging portion contacts the third wiring.

2. The semiconductor module according to claim 1 , wherein the first recess includes a first portion positioned radially inward of the through hole as it moves toward one side in the thickness direction.

3. The semiconductor module according to claim 2 , wherein the first portion is conical.

4. The semiconductor module according to claim 3 , wherein the first recess is entirely formed by the first portion.

5. the first recess has a first edge in contact with the inner surface of the through hole and a second edge in contact with the second surface; A semiconductor module as described in any one of claims 1 to 4, wherein the ratio of a second dimension, which is the radial length of the through hole from the first edge to the second edge, to a first dimension, which is the length in the thickness direction of the substrate, is 5% to 40%.

6. 6. The semiconductor module according to claim 5, wherein a ratio of a third dimension, which is a length in the thickness direction from the first edge to the second edge, to the first dimension is 5% to 40%.

7. 6. The semiconductor module according to claim 5, wherein the first dimension is between 1.6 mm and 3.2 mm.

8. the sealing portion has a top surface facing one side in the thickness direction, the bulging portion has a bulging tip portion that bulges most from the base portion in a direction perpendicular to the thickness direction, 5. The semiconductor module according to claim 1, wherein a fourth dimension, which is a length in the thickness direction from the top surface to the bulging tip, is 5 mm to 15 mm.

9. The semiconductor device further includes a support substrate on which the semiconductor element is mounted, and a sleeve mounted on the support substrate.

5. The semiconductor module according to claim 1, wherein the base is inserted into the sleeve.

10. The semiconductor module according to claim 9 , wherein the semiconductor device further comprises a power terminal protruding from the sealing portion in a first direction perpendicular to the thickness direction.

11. the semiconductor element includes a first element and a second element; The semiconductor module according to claim 10 , wherein the power terminals include a first power terminal electrically connected to the first element and a second power terminal electrically connected to the second element.

12. the support substrate includes a first mounting portion on which the first element is mounted and a second mounting portion on which the second element is mounted; the first mounting portion is located on one side of the second mounting portion in the first direction, The semiconductor module according to claim 11 , wherein the first power terminal and the second power terminal protrude from the sealing portion to one side in the first direction.

13. the power terminal includes a third power terminal electrically connected to the first element and the second element; The semiconductor module according to claim 12 , wherein the third power terminal protrudes from the sealing portion to the other side in the first direction.

14. The semiconductor module according to claim 10 , comprising a plurality of the semiconductor devices, the plurality of semiconductor devices being arranged in a second direction perpendicular to the thickness direction and the first direction.

15. Further comprising a heat sink; the support substrate of each of the plurality of semiconductor devices has a bottom surface facing the other side in the thickness direction, In each of the plurality of semiconductor devices, the bottom surface is exposed from the sealing portion, The semiconductor module according to claim 14 , wherein the heat sink contacts the bottom surface of each of the plurality of semiconductor devices.

16. A driving source; The semiconductor module according to claim 13, The semiconductor device is electrically connected to the drive source.