Semiconductor light-emitting element

Abstract

A semiconductor light-emitting element (1) comprises: a substrate (10); an n-side cladding layer (20); a hole barrier layer (40); an active layer (50); and a first p-side cladding layer (71). The hole barrier layer (40) includes: a first hole barrier layer (41a) comprising (Alx1Ga1-x1)y1In1-y1P (0 ≤ x1 ≤ 1, 0 ≤ y1 ≤ 1); a first intermediate layer (42a) disposed over the first hole barrier layer (41a) and comprising Alx2Ga1-x2Py2As1-y2 (0 ≤ x2 ≤ 1, 0 ≤ y2 < 1); and a second hole barrier layer (41b) disposed over the first intermediate layer (42a) and comprising (Alx3Ga1-x3)y3In1-y3P (0 ≤ x3 ≤ 1, 0 ≤ y3 ≤ 1). The average band gap energy of each of the first hole barrier layer (41a) and the second hole barrier layer (41b) is greater than the average band gap energy of the first intermediate layer (42a).

Description

Semiconductor light emitting device

[0001] The present disclosure relates to semiconductor light emitting devices.

[0002] Conventionally, semiconductor light-emitting devices have been known to have a problem of carrier leakage from an active layer, and a hole-blocking layer and an electron-blocking layer are used to suppress carrier leakage from the active layer (see, for example, Patent Document 1).

[0003] Japanese Patent Application Publication No. 8-330666

[0004] In the semiconductor laser device disclosed in Patent Document 1, a hole barrier layer, which is composed of alternating AlGaInP layers and GaInP layers, is disposed between the active layer and the n-side cladding layer. In this case, an energy barrier is formed in the valence band of the hole barrier layer, thereby suppressing leakage of holes from the active layer to the n-side cladding layer. Meanwhile, an energy barrier is also formed in the conduction band of the hole barrier layer, so the hole barrier layer also serves as a barrier against electrons moving from the n-side cladding layer to the active layer. As a result, the threshold current for laser oscillation may increase in the semiconductor laser device described in Patent Document 1.

[0005] The present disclosure is intended to solve such problems, and has an object to provide a semiconductor light-emitting device including a hole barrier layer that can reduce the magnitude of the energy barrier in the conduction band.

[0006] In order to solve the above problems, one aspect of the semiconductor light emitting device according to the present disclosure includes a substrate, an n-side cladding layer disposed above the substrate, a hole barrier layer disposed above the n-side cladding layer, an active layer disposed above the hole barrier layer, and a p-side cladding layer disposed above the active layer, wherein the hole barrier layer is made of (Al ｘ１ Ga １－ｘ１ ) ｙ１ In １－ｙ１ a first hole blocking layer made of P (0≦x1≦1, 0≦y1≦1); and an Al ｘ２ Ga １－ｘ２ P ｙ２ As １－ｙ２ a first intermediate layer consisting of (0≦x2≦1, 0≦y2<1), and a second intermediate layer (Al ｘ３ Ga１－ｘ３ ) ｙ３ In １－ｙ３ and a second hole blocking layer consisting of P (0≦x3≦1, 0≦y3≦1), wherein the average band gap energy of each of the first hole blocking layer and the second hole blocking layer is greater than the average band gap energy of the first intermediate layer.

[0007] According to the present disclosure, it is possible to provide a semiconductor light-emitting element including a hole barrier layer that can reduce the magnitude of the energy barrier in the conduction band.

[0008] 1 is a schematic cross-sectional view showing the overall configuration of a semiconductor light-emitting device according to a first embodiment. FIG. 2 is a schematic cross-sectional view showing the configuration of a hole barrier layer of the semiconductor light-emitting device according to the first embodiment. FIG. 3 is a schematic cross-sectional view showing the configuration of an active layer of the semiconductor light-emitting device according to the first embodiment. FIG. 4 is a first diagram showing the composition, impurity concentration, and film thickness of each layer included in the semiconductor light-emitting device according to the first embodiment. FIG. 5 is a second diagram showing the composition, impurity concentration, and film thickness of each layer included in the semiconductor light-emitting device according to the first embodiment. FIG. 6 is a graph showing the energy distribution of the lower end of the conduction band from the n-side cladding layer to the p-side guide layer of Comparative Example 1 and Comparative Example 2. FIG. 7 is a graph showing the energy distribution of the upper end of the valence band from the n-side cladding layer to the p-side guide layer of Comparative Example 1 and Comparative Example 2. FIG. 8 is a schematic diagram for explaining a band offset ratio. FIG. 9 is a graph showing the relationship between the supply current density and the optical output of the semiconductor light-emitting device according to Comparative Example 1 and Comparative Example 2. FIG. 10 is a graph showing the energy distribution of the lower end of the conduction band from the n-side cladding layer to the p-side guide layer of the semiconductor light-emitting device according to the first embodiment. 1 is a graph showing the relationship between the stacking direction position near the active layer and the current density. FIG. 2 is a graph showing the relationship between the supply current density and the optical output of the semiconductor light-emitting element according to the first embodiment. FIG. 3 is a schematic cross-sectional view showing the configuration of a hole barrier layer according to the second embodiment. FIG. 4 is a diagram showing the composition, impurity concentration, and film thickness of the hole barrier layer according to the second embodiment. FIG. 5 is a graph showing the distribution of the refractive index and light intensity from the n-side cladding layer to the first p-side cladding layer of the semiconductor light-emitting element according to the second embodiment. FIG. 6 is a graph showing the distribution of the refractive index from the n-side guide layer to the active layer of the semiconductor light-emitting element according to the second embodiment. FIG. 7 is a schematic cross-sectional view showing the configuration of a hole barrier layer according to the third embodiment. FIG. 8 is a diagram showing the composition, impurity concentration, and film thickness of the hole barrier layer according to the third embodiment. FIG. 9 is a schematic graph showing the energy distributions of the conduction band and valence band of the n-side guide layer and the hole barrier layer according to the third embodiment. FIG. 10 is a schematic graph showing the refractive index distributions of the n-side guide layer and the hole barrier layer according to the third embodiment.10 is a graph showing the relationship between the ratio of the film thickness of the first intermediate layer to the film thickness of the first hole barrier layer and the normalized resistance variation rate according to embodiment 3. FIG. 11 is a graph showing the relationship between the ratio of the film thickness of the first intermediate layer to the film thickness of the first hole barrier layer and the normalized hole leakage rate according to embodiment 3. FIG. 12 is a schematic cross-sectional view showing the configuration of a hole barrier layer according to embodiment 4. FIG. 13 is a diagram showing the composition, impurity concentration, and film thickness of a hole barrier layer according to embodiment 4. FIG. 14 is a graph showing the distribution of refractive index and light intensity from the n-side cladding layer to the first p-side cladding layer of a semiconductor light-emitting element according to embodiment 4. FIG. 15 is a graph showing the distribution of refractive index from the n-side guide layer to the active layer of a semiconductor light-emitting element according to embodiment 4. FIG. 16 is a schematic cross-sectional view showing the overall configuration of a semiconductor light-emitting element according to embodiment 5. FIG. 17 is a schematic cross-sectional view showing the configuration of a hole barrier layer of a semiconductor light-emitting element according to embodiment 5. FIG. 18 is a schematic cross-sectional view showing the configuration of an active layer of a semiconductor light-emitting element according to embodiment 5. FIG. 19 is a first diagram showing the composition, impurity concentration, and film thickness of each layer included in a semiconductor light-emitting element according to embodiment 5. FIG. 19 is a second diagram showing the composition, impurity concentration, and film thickness of each layer included in a semiconductor light-emitting element according to embodiment 5. 10 is a schematic cross-sectional view showing the overall configuration of a semiconductor light-emitting device according to a sixth embodiment. FIG. 11 is a schematic cross-sectional view showing the configuration of a hole barrier layer of the semiconductor light-emitting device according to the sixth embodiment. FIG. 12 is a schematic cross-sectional view showing the configuration of an active layer of the semiconductor light-emitting device according to the sixth embodiment. FIG. 13 is a first diagram showing the composition, impurity concentration, and film thickness of each layer included in the semiconductor light-emitting device according to the sixth embodiment. FIG. 14 is a second diagram showing the composition, impurity concentration, and film thickness of each layer included in the semiconductor light-emitting device according to the sixth embodiment. FIG. 15 is a schematic cross-sectional view showing the configuration of a hole barrier layer according to a seventh embodiment. FIG. 16 is a diagram showing the composition, impurity concentration, and film thickness of the hole barrier layer according to the seventh embodiment. FIG. 17 is a graph showing the energy distribution of the lower end of the conduction band from the first n-side guide layer to the second p-side guide layer according to the seventh embodiment. FIG. 18 is a graph showing the energy distribution of the upper end of the valence band from the first n-side guide layer to the second p-side guide layer according to the seventh embodiment.

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that each of the embodiments described below represents a specific example of the present disclosure. Therefore, the numerical values, shapes, materials, components, and the arrangement and connection of the components shown in the following embodiments are merely examples and are not intended to limit the present disclosure.

[0010] Furthermore, each figure is a schematic diagram and is not necessarily an exact representation. Therefore, the scales and the like do not necessarily match in each figure. In each figure, the same reference numerals are used to denote substantially the same components, and redundant explanations will be omitted or simplified.

[0011] Furthermore, in this specification, terms indicating the relationship between elements, such as "equal," terms indicating the shape of elements, such as "flat," "parallel," "vertical," "plate-shaped," and "curved," as well as numerical ranges, are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0012] In this specification, the terms "above" and "below" do not refer to vertically above and below in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. The terms "above" and "below" are used not only when two components are arranged with a gap between them and another component is present between them, but also when two components are arranged in contact with each other.

[0013] First Embodiment A semiconductor light emitting device according to a first embodiment will be described.

[0014] [1-1. Overall Configuration of Semiconductor Light-Emitting Device] The overall configuration of a semiconductor light-emitting device according to this embodiment will be described with reference to FIGS. 1 to 5. FIG. 1 is a schematic cross-sectional view showing the overall configuration of a semiconductor light-emitting device 1 according to this embodiment. FIGS. 2 and 3 are schematic cross-sectional views showing the configurations of a hole barrier layer 40 and an active layer 50 of the semiconductor light-emitting device 1 according to this embodiment, respectively. FIGS. 1 to 3 show cross sections parallel to the stacking direction of the semiconductor light-emitting device 1 (i.e., the thickness direction of each layer included in the semiconductor light-emitting device 1) and perpendicular to the propagation direction of light (laser light). Note that each drawing shows mutually orthogonal X-, Y-, and Z-axes. The X-, Y-, and Z-axes are in a right-handed Cartesian coordinate system. The stacking direction of the semiconductor light-emitting device 1 is parallel to the Z-axis direction, and the main propagation direction of light is parallel to the Y-axis direction. FIGS. 4 and 5 are first and second diagrams, respectively, showing the composition, impurity concentration, and film thickness of each layer included in the semiconductor light-emitting device 1 according to this embodiment. 4 shows the composition of each layer from the active layer 50 to the p-type contact layer 92 of the semiconductor light emitting element 1 in the order of lamination, etc. Fig. 5 shows the composition of each layer from the substrate 10 to the hole barrier layer 40 of the semiconductor light emitting element 1 in the order of lamination, etc.

[0015] The semiconductor light-emitting element 1 is a semiconductor element that emits light. In this embodiment, the semiconductor light-emitting element 1 is an edge-emitting semiconductor light-emitting element that has a waveguide between its front and rear end faces and emits light from the front end face. In this embodiment, the semiconductor light-emitting element 1 is a semiconductor laser element that emits laser light with a wavelength of 600 nm or more and 750 nm or less.

[0016] 1 , the semiconductor light-emitting element 1 includes a substrate 10, an n-side cladding layer 20, a hole barrier layer 40, an active layer 50, a first p-side cladding layer 71, and a second p-side cladding layer 72. In this embodiment, the semiconductor light-emitting element 1 further includes an n-type buffer layer 12, a boundary layer 14, an n-side guide layer 30, a p-side guide layer 60, an etching stop layer 80, a boundary layer 90, a p-type contact layer 92, a current blocking layer 94, an ohmic electrode 96, a p-side electrode 98, and an n-side electrode 99.

[0017] 1 , the semiconductor light emitting device 1 according to this embodiment has a ridge R0 extending in the Y-axis direction. The lower end Ru0 of the ridge R0 is located in the etching stop layer 80. In other words, the semiconductor light emitting device 1 has two trenches T0 extending in the Y-axis direction. Accordingly, the ridge R0 is formed between the two trenches T0, and a protrusion P0 is formed on the outer side of each trench T0 in the X-axis direction. Each of the two trenches T0 is formed in the p-type contact layer 92, the boundary layer 90, the second p-side cladding layer 72, and the etching stop layer 80. Each of the two trenches T0 penetrates the p-type contact layer 92, the boundary layer 90, and the second p-side cladding layer 72. The bottom of each of the two trenches T0 is located in the etching stop layer 80.

[0018] The substrate 10 is a plate-like member that serves as a base for the semiconductor light-emitting device 1. In this embodiment, as shown in Fig. 5, the substrate 10 is an n-type GaAs substrate. An n-side electrode (not shown) is disposed on the lower surface of the substrate 10 (the lower main surface in Fig. 1).

[0019] The n-type buffer layer 12 is an n-type semiconductor layer disposed above the substrate 10. In this embodiment, the n-type buffer layer 12 is disposed between the substrate 10 and the boundary layer 14. As shown in FIG. 5 , the n-type buffer layer 12 has a concentration of 5.0×10 １７ cm －３ The n-type GaAs layer is doped with n-type impurities (Si) and has a thickness of 0.40 μm.

[0020] The boundary layer 14 is an n-type semiconductor layer disposed between the n-type buffer layer 12 and the n-side cladding layer 20. In this embodiment, the boundary layer 14 has a concentration of 7.5×10 １７ cm －３ n-type Al doped with n-type impurities (Si) having a thickness of 0.10 μm Ｘ Ga １－Ｘ The boundary layer 14 is an As layer (0.05≦X≦0.60). The Al composition ratio X of the boundary layer 14 increases toward the n-side cladding layer 20. The Al composition ratio X of the boundary layer 14 is 0.05 at the interface with the n-type buffer layer 12 and 0.60 at the interface with the n-side cladding layer 20.

[0021] The n-side cladding layer 20 is an n-type semiconductor layer disposed above the substrate 10. The average refractive index of the n-side cladding layer 20 is smaller than the average refractive index of the active layer 50. In this embodiment, the n-side cladding layer 20 is disposed on the boundary layer 14 and is made of (Al ｖ１ Ga １－ｖ１ ) ｗ１ In １－ｗ１ P (0≦v1≦1, 0≦w1≦1). More specifically, as shown in FIG. 5, the n-side cladding layer 20 is made of an n-type (Al ０．８０ Ga ０．２０ ) ０．５１ In ０．４９ The impurity concentration of the n-side cladding layer 20 is 7.5×10 in a region where the distance from the boundary surface with the boundary layer 14 (i.e., the film thickness) is 1.80 μm or less. １７ cm －３ In the region where the distance from the boundary surface with the boundary layer 14 is greater than 1.80 μm and less than 2.30 μm, １７ cm －３ In the region where the distance from the boundary surface with the boundary layer 14 is greater than 2.30 μm and less than or equal to 3.30 μm, １７ cm －３ is.

[0022] In the present disclosure, the average refractive index of each layer refers to the refractive index value obtained by integrating the magnitude of the refractive index at a certain position in the stacking direction of the layer from the position of the interface closer to the substrate 10 in the stacking direction of the layer to the position of the interface farther from the substrate 10, and dividing the result by the film thickness of the layer (the distance between the interface closer to the substrate 10 and the interface farther from the substrate 10).

[0023] The n-side guide layer 30 is a semiconductor layer disposed between the n-side cladding layer 20 and the active layer 50. The average refractive index of the n-side guide layer 30 is greater than the average refractive index of the n-side cladding layer 20. In this embodiment, the n-side guide layer 30 has a concentration of 3.0×10 １７ cm －３ The n-type impurity (Si) doped n-type (Al) ０．７０ Ga ０．３０ ) ０．５１ In ０．４９ This is the P layer.

[0024] The hole barrier layer 40 is a semiconductor layer disposed above the n-side cladding layer 20. The hole barrier layer 40 has a function of suppressing leakage of holes from the active layer 50 to the n-side cladding layer 20. In the present embodiment, as shown in FIG. 2 , the hole barrier layer 40 is disposed above the n-side guide layer 30, and includes a first hole barrier layer 41 a, a first intermediate layer 42 a, a second hole barrier layer 41 b, a second intermediate layer 42 b, a third hole barrier layer 41 c, a third intermediate layer 42 c, a fourth hole barrier layer 41 d, a fifth hole barrier layer 41 e, a fifth intermediate layer 42 e, and a sixth hole barrier layer 41 f.

[0025] The first hole barrier layer 41a is disposed above the n-side cladding layer 20 and is made of (Al ｘ１ Ga １－ｘ１ ) ｙ１ In １－ｙ１ P (0≦x1≦1, 0≦y1≦1) In this embodiment, the first hole barrier layer 41 a is disposed above the n-side guide layer 30 .

[0026] The first intermediate layer 42a is disposed above the first hole blocking layer 41a and is made of (Al ｘ２ Ga １－ｘ２ P ｙ２ As １－ｙ２ (0≦x2≦1, 0≦y2<1).

[0027] The second hole blocking layer 41b is disposed above the first intermediate layer 42a and is made of (Al ｘ３ Ga １－ｘ３ ) ｙ３ In １－ｙ３ P (0≦x3≦1, 0≦y3≦1).

[0028] The second intermediate layer 42b is disposed above the second hole blocking layer 41b and is made of (Al ｘ４ Ga １－ｘ４ P ｙ４ As １－ｙ４ (0≦x4≦1, 0≦y4<1).

[0029] The third hole blocking layer 41c is disposed above the second intermediate layer 42b and is made of (Al ｘ５ Ga １－ｘ５ ) ｙ５ In １－ｙ５P (0≦x5≦1, 0≦y5≦1).

[0030] The third intermediate layer 42c is disposed above the third hole blocking layer 41c, and ｘ６ Ga １－ｘ６ P ｙ６ As １－ｙ６ (0≦x6≦1, 0≦y6<1).

[0031] The fourth hole blocking layer 41d is disposed above the third intermediate layer 42c and is made of (Al ｘ７ Ga １－ｘ７ ) ｙ７ In １－ｙ７ The semiconductor layer is made of P (0≦x7≦1, 0≦y7≦1).

[0032] The fourth intermediate layer 42d is disposed above the fourth hole blocking layer 41d and comprises (Al ｘ８ Ga １－ｘ８ P ｙ８ As １－ｙ８ (0≦x8≦1, 0≦y8<1).

[0033] The fifth hole blocking layer 41e is disposed above the fourth intermediate layer 42d and is made of (Al ｘ９ Ga １－ｘ９ ) ｙ９ In １－ｙ９ The semiconductor layer is made of P (0≦x9≦1, 0≦y9≦1).

[0034] The fifth intermediate layer 42e is disposed above the fifth hole blocking layer 41e, and ｘ１０ Ga １－ｘ１０ P ｙ１０ As １－ｙ１０ (0≦x10≦1, 0≦y10<1).

[0035] The sixth hole blocking layer 41f is disposed above the fifth intermediate layer 42e and has a thickness of (Al ｘ１１ Ga １－ｘ１１ ) ｙ１１ In １－ｙ１１ It is a semiconductor layer made of P (0≦x11≦1, 0≦y11≦1).

[0036] The average band gap energy of each of the first hole blocking layer 41a, the second hole blocking layer 41b, the third hole blocking layer 41c, the fourth hole blocking layer 41d, the fifth hole blocking layer 41e, and the sixth hole blocking layer 41f is greater than the average band gap energy of each of the first intermediate layer 42a, the second intermediate layer 42b, the third intermediate layer 42c, the fourth intermediate layer 42d, and the fifth intermediate layer 42e.

[0037] In the present disclosure, the average band gap energy of each layer refers to the value of the band gap energy obtained by integrating the magnitude of the band gap energy at a certain position in the stacking direction of the layer in the stacking direction from the position of the interface closer to the substrate 10 in the stacking direction of the layer to the position of the interface farther from the substrate 10, and dividing the integrated value by the film thickness of the layer (the distance between the interface closer to the substrate 10 and the interface farther from the substrate 10).

[0038] In this embodiment, as shown in FIG. 5, each of the first hole barrier layer 41a, the second hole barrier layer 41b, the third hole barrier layer 41c, the fourth hole barrier layer 41d, the fifth hole barrier layer 41e, and the sixth hole barrier layer 41f has a concentration of 3.0×10 １７ cm －３ n-type impurity (Si) doped n-type (Al ０．８０ Ga ０．２０ ) ０．５１ In ０．４９ The first intermediate layer 42a, the second intermediate layer 42b, the third intermediate layer 42c, the fourth intermediate layer 42d, and the fifth intermediate layer 42e each have a concentration of 3.0×10 １７ cm －３ n-type Al doped with n-type impurities (Si) having a thickness of 0.002 μm ０．４５ Ga ０．５５ This is an As layer.

[0039] The active layer 50 is a light-emitting layer disposed above the hole barrier layer 40. In this embodiment, the active layer 50 emits light with a wavelength of 600 nm or more and 750 nm or less. In this embodiment, the active layer 50 has a quantum well structure consisting of multiple barrier layers and one or more well layers. As shown in FIG. 3 , the active layer 50 has barrier layers 51 a, 51 b, 51 c, and 51 d and well layers 52 a, 52 b, and 52 c.

[0040] The barrier layer 51a is a semiconductor layer disposed above the hole barrier layer 40 and functions as a barrier of the quantum well structure. In this embodiment, the barrier layer 51a is an undoped (Al ０．５０ Ga ０．５０ ) ０．５１ In ０．４９ This is the P layer.

[0041] The well layer 52a is a semiconductor layer disposed above the barrier layer 51a and functions as a well of the quantum well structure. In this embodiment, the well layer 52a is an undoped Ga ０．５５ In ０．４５ This is the P layer.

[0042] The barrier layer 51b is a semiconductor layer disposed above the well layer 52a and functions as a barrier of the quantum well structure. In this embodiment, the barrier layer 51b is an undoped (Al ０．５０ Ga ０．５０ ) ０．５１ In ０．４９ This is the P layer.

[0043] The well layer 52b is a semiconductor layer disposed above the barrier layer 51b and functions as a well of the quantum well structure. In this embodiment, the well layer 52b is an undoped Ga ０．５５ In ０．４５ This is the P layer.

[0044] The barrier layer 51c is a semiconductor layer disposed above the well layer 52b and functions as a barrier of the quantum well structure. In this embodiment, the barrier layer 51c is an undoped (Al ０．５０ Ga ０．５０ ) ０．５１ In ０．４９ This is the P layer.

[0045] The well layer 52c is a semiconductor layer disposed above the barrier layer 51c and functions as a well of the quantum well structure. In this embodiment, the well layer 52c is an undoped Ga ０．５５ In ０．４５ This is the P layer.

[0046] The barrier layer 51d is a semiconductor layer disposed above the well layer 52c and functions as a barrier for the quantum well structure. In this embodiment, the barrier layer 51d is an undoped (Al ０．５０ Ga ０．５０ ) ０．５１ In ０．４９ This is the P layer.

[0047] The p-side guide layer 60 is a semiconductor layer disposed between the active layer 50 and the p-side cladding layer. In this embodiment, the p-side guide layer 60 is disposed between the active layer 50 and the first p-side cladding layer 71. The average refractive index of the p-side guide layer 60 is larger than the average refractive index of the first p-side cladding layer 71. In this embodiment, the p-side guide layer 60 is an undoped (Al ０．７０ Ga ０．３０ ) ０．５１ In ０．４９ This is the P layer.

[0048] The first p-side cladding layer 71 is an example of a p-side cladding layer disposed above the active layer 50. The average refractive index of the first p-side cladding layer 71 is smaller than the average refractive index of the active layer 50. In this embodiment, the first p-side cladding layer 71 is disposed above the p-side guide layer 60 and is made of (Al ｖ２ Ga １－ｖ２ ) ｗ２ In １－ｗ２ P (0≦v2≦1, 0≦w2≦1). The first p-side cladding layer 71 has a concentration of 3.2×10 １７ cm －３ p-type Al doped with p-type impurities (Zn or Mg) having a thickness of 0.240 μm ０．５ In ０．５ This is the P layer.

[0049] The etching stop layer 80 is a semiconductor layer disposed above the active layer 50. The etching stop layer 80 is less susceptible to etching than the second p-side cladding layer 72 (i.e., has a lower etching rate). Therefore, when forming the ridge R0 by etching, it becomes easier to control the position of the bottom end Ru0 of the ridge R0. In this embodiment, as shown in FIG. 4, the etching stop layer 80 is made of five layers of p-type Ga ０．５６ In ０．４４ P layer and four layers of p-type Al０．５５ In ０．４５ P layer. Five p-type Ga ０．５６ In ０．４４ Each of the P layers and four layers of p-type Al ０．５５ In ０．４５ The five p-type GaAs layers are stacked alternately. ０．５６ In ０．４４ Each of the P layers is 8.0 × 10 １７ cm －３ The semiconductor layer is doped with p-type impurities (Zn or Mg) and has a thickness of 0.002 μm. ０．５５ In ０．４５ Each of the P layers is 4.6 × 10 １７ cm －３ The semiconductor layer is doped with a p-type impurity (Zn or Mg) and has a thickness of 0.004 μm. By using such an etching stop layer 80, when the ridge R0 is formed by etching, it becomes easier to stop the etching at the etching stop layer 80. In other words, as shown in FIG. 1 , it becomes easier to control the position of the bottom end Ru0 of the ridge R0 at the etching stop layer 80.

[0050] The second p-side cladding layer 72 is an example of a p-side cladding layer disposed above the active layer 50. The average refractive index of the second p-side cladding layer 72 is smaller than the average refractive index of the active layer 50. In this embodiment, the second p-side cladding layer 72 is disposed above the etching stop layer 80, and ｖ２ Ga １－ｖ２ ) ｗ２ In １－ｗ２ P (0≦v2≦1, 0≦w2≦1). The second p-side cladding layer 72 has a concentration of 1.0×10 １８ cm －３ p-type Al doped with p-type impurities (Zn or Mg) having a thickness of 0.10 μm ０．５ In ０．５ P layer and a layer with a concentration of 1.2 × 10 １８ cm －３ p-type Al doped with p-type impurities (Zn or Mg) having a thickness of 1.35 μm ０．５ In ０．５ and a P layer.

[0051] The boundary layer 90 is a semiconductor layer disposed between the second p-side cladding layer 72 and the p-type contact layer 92. In this embodiment, the boundary layer 90 has a concentration of 1.2×10 １８ cm －３ p-type impurity (Zn or Mg) doped p-type (Al ０．６０ Ga ０．４０ ) ０．５１ In ０．４９ P layer and a layer with a concentration of 1.2 × 10 １８ cm －３ p-type impurity (Zn or Mg) doped p-type (Al ０．２５ Ga ０．７５ ) ０．５１ In ０．４９ P layer and a layer with a concentration of 2×10 １８ cm －３ p-type Ga doped with p-type impurities (Zn or Mg) of 0.038 μm thickness ０．５１ In ０．４９ and a P layer.

[0052] The p-type contact layer 92 is a semiconductor layer disposed above the p-side cladding layer. An ohmic electrode 96 and a p-side electrode 98 are disposed on the p-type contact layer 92 as shown in FIG. 1 . The p-type contact layer 92 is a p-type semiconductor layer that is in ohmic contact with the ohmic electrode 96. In this embodiment, the p-type contact layer 92 has a concentration of 3×10 １９ cm －３ The layer is a p-type GaAs layer doped with p-type impurities (C) and having a thickness of 0.23 μm.

[0053] The current blocking layer 94 is an electrical insulating layer disposed between the p-side electrode 98 and each semiconductor layer. In this embodiment, the current blocking layer 94 is disposed in a region of the upper surface of the p-type contact layer 92 where the ohmic electrode 96 is not disposed, and in the trench T0. The current blocking layer 94 is disposed in a region of the upper surface of the semiconductor stack including the etching stop layer 80, the second p-side cladding layer 72, the boundary layer 90, and the p-type contact layer 92, other than the upper surface of the ridge R0. In this embodiment, the current blocking layer 94 is also disposed at the edge portion of the upper surface of the ridge R0. This makes it possible to prevent current from flowing from the p-side electrode 98 to regions other than the ridge R0. The material of the current blocking layer 94 is not particularly limited as long as it is electrically insulating. The current blocking layer 94 may be, for example, a 100-nm-thick SiN film, SiO ２ An insulating film such as a film can be used.

[0054] The ohmic electrode 96 is an electrode disposed above the p-type contact layer 92 and in ohmic contact with the p-type contact layer 92. In this embodiment, the ohmic electrode 96 is disposed only above the ridge R0. More specifically, the ohmic electrode 96 is disposed on the upper surface of the ridge R0, except for the edge portion. The ohmic electrode 96 may be a single-layer film made of any conductive material that makes ohmic contact with the p-type contact layer 92, or a multilayer film in which another conductive material layer is laminated on the single-layer film. The ohmic electrode 96 may be, for example, a multilayer film including a 150-nm-thick Ag film that makes ohmic contact with the upper surface of the p-type contact layer 92, a 50-nm-thick Ti film that is disposed on the Ag film, and a 150-nm-thick Pt film that is disposed on the Ti film. The refractive index of the Ag film (0.135 for light with a wavelength of 630 nm) is significantly smaller than the refractive index of a Ti film (2.153 for light with a wavelength of 630 nm) that is commonly used as the ohmic electrode 96, thereby preventing light from propagating upward beyond the ohmic electrode 96. This reduces the light intensity in the p-type contact layer 92, the ohmic electrode 96, and the p-side electrode 98, which have high optical absorption, thereby reducing optical absorption loss. Furthermore, as described above, reducing the optical absorption loss in the ohmic electrode 96 and the p-side electrode 98 allows the thickness of each p-side cladding layer to be reduced. This reduces the electrical resistance in each p-side cladding layer, thereby reducing the operating voltage of the semiconductor light-emitting element 1.

[0055] The ohmic electrode 96 may further include a Ni film having a thickness of more than 0 nm and not more than 1 nm, which is disposed between the p-type contact layer 92 and the Ag film. This can improve the adhesion between the ohmic electrode 96 and the p-type contact layer 92. This can improve the reliability of the semiconductor light emitting element 1.

[0056] Alternatively, the ohmic electrode 96 may be a laminated film including, for example, a 50 nm thick Ti film that is in ohmic contact with the upper surface of the p-type contact layer 92 and a 150 nm thick Pt film that is disposed on the Ti film.

[0057] The p-side electrode 98 is an electrode that is disposed above the ohmic electrode 96 and electrically connected to the ohmic electrode 96. In the present embodiment, the p-side electrode 98 is disposed above the ohmic electrode 96 and the current blocking layer 94 and is in contact with the ohmic electrode 96 and the current blocking layer 94. The configuration of the p-side electrode 98 is not particularly limited as long as it is conductive. For example, an Au film or the like can be used as the p-side electrode 98.

[0058] The n-side electrode 99 is an electrode disposed on the lower surface of the substrate 10 (i.e., one of the two main surfaces of the substrate 10, the main surface behind the main surface on which the semiconductor layers are stacked). The configuration of the n-side electrode 99 is not particularly limited as long as it is conductive. The n-side electrode 99 can be a laminated film including, stacked in this order from the substrate 10 side, a 90-nm-thick AuGe film, a 20-nm-thick Ni film, a 50-nm-thick Au film, a 100-nm-thick Ti film, a 50-nm-thick Pt film, a 50-nm-thick Ti film, a 100-nm-thick Pt film, and a 500-nm-thick Au film.

[0059] [1-2. Effects] The effects of the semiconductor light emitting device 1 according to this embodiment will be described in comparison with a comparative example.

[0060] First, the comparative examples will be described with reference to FIGS. 6 to 9 . FIG. 6 is a graph showing the energy distribution of the lower end of the conduction band (i.e., the bottom of the conduction band) from the n-side cladding layer to the p-side guide layer in Comparative Examples 1 and 2. FIG. 7 is a graph showing the energy distribution of the upper end of the valence band (i.e., the top of the valence band) from the n-side cladding layer to the p-side guide layer in Comparative Examples 1 and 2. The solid lines in FIGS. 6 and 7 show the energy distribution of the semiconductor light-emitting device in Comparative Example 1, and the dotted lines show the energy distribution of the semiconductor light-emitting device in Comparative Example 2. FIG. 8 is a schematic diagram for explaining the band offset ratio. FIG. 8 shows an overview of the energy distribution of the lower end of the conduction band and the upper end of the valence band of the first hole barrier layer and the first intermediate layer. FIG. 9 is a graph showing the relationship between the supply current density and the light output of the semiconductor light-emitting device in Comparative Examples 1 and 2.

[0061] The semiconductor light-emitting device of Comparative Example 1 has the same configuration as hole barrier layer 40 of semiconductor light-emitting device 1 according to the present embodiment, except for the hole barrier layer. The first hole barrier layer, second hole barrier layer, third hole barrier layer, fourth hole barrier layer, fifth hole barrier layer, and sixth hole barrier layer of the semiconductor light-emitting device of Comparative Example 1 are made of AlGaInP, and the first intermediate layer, second intermediate layer, third intermediate layer, fourth intermediate layer, and fifth intermediate layer are made of GaInP.

[0062] The semiconductor light emitting device of Comparative Example 2 has the same configuration as the hole barrier layer 40 of the semiconductor light emitting device 1 according to the present embodiment, except for the hole barrier layer. The semiconductor light emitting device of Comparative Example 2 includes, between the n-side cladding layer and the active layer, an AlGaInP layer that has the same film thickness as the hole barrier layer 40 according to the present embodiment and the same composition as the barrier layer 51a of the active layer 50. In other words, the semiconductor light emitting device of Comparative Example 2 does not have a hole barrier structure (i.e., a structure that suppresses leakage of holes from the active layer).

[0063] Hereinafter, the band offset ratio is used as one of the indices for evaluating the configuration of the bottom of the conduction band and the top of the valence band of the hole barrier layer. The band offset ratio will be explained using FIG. 8 . As shown in FIG. 8 , the average band gap energies of the first hole barrier layer and the first intermediate layer are represented by Eg1 and Eg2, respectively. The energy barriers in the conduction band and valence band between the first hole barrier layer and the first intermediate layer are represented by ΔEc and ΔEv, respectively. The ratio of these energy barriers ΔEc and ΔEv (Ec:ΔEv) is referred to as the band offset ratio. The relationship ΔEg = ΔEc + ΔEv holds between the average band gap energy difference ΔEg (= Eg1 - Eg2) between the first hole barrier layer and the first intermediate layer and the energy barriers ΔEc and ΔEv.

[0064] In the semiconductor light-emitting device of Comparative Example 1, as shown in FIGS. 6 and 7 , the energy barrier ΔEc is 0.23 eV, the energy barrier ΔEv is 0.19 eV, and the band offset ratio is ΔEc:ΔEv = 65:35. Thus, the hole barrier layer forms an energy barrier ΔEv in the valence band, thereby suppressing hole leakage from the active layer to the n-side guide layer (and n-side cladding layer). However, the hole barrier layer forms an energy barrier ΔEc in the conduction band. Furthermore, as indicated by the band offset ratio of ΔEc:ΔEv = 65:35, the energy barrier ΔEc is larger than the energy barrier ΔEv. This energy barrier ΔEc acts as a barrier to electrons flowing from the n-side cladding layer through the n-side guide layer to the active layer, inhibiting electron injection into the active layer. Therefore, as shown in FIG. 9 , the threshold current density for laser oscillation of the semiconductor light-emitting device of Comparative Example 1 is higher than the threshold current density for laser oscillation of the semiconductor light-emitting device of Comparative Example 2, which does not have a hole barrier structure. As described above, the semiconductor light emitting device of Comparative Example 1 has worse light output characteristics than the semiconductor light emitting device of Comparative Example 2, which does not have a hole barrier structure.

[0065] Next, the effects of the semiconductor light-emitting device 1 according to this embodiment will be described with reference to FIGS. 10 to 13 . FIGS. 10 and 11 are graphs showing the energy distributions of the lower end of the conduction band and the upper end of the valence band from the n-side cladding layer 20 to the p-side guide layer 60 of the semiconductor light-emitting device 1 according to this embodiment, respectively. In FIGS. 10 and 11 , the energy distribution of the semiconductor light-emitting device 1 according to this embodiment is shown by a solid line, and the energy distribution of Comparative Example 1 is also shown by a dotted line. FIG. 12 is a graph showing the relationship between the stacking direction position near the active layer 50 and the current density. FIG. 12 shows the current density due to the flow of holes and the current density due to the flow of electrons. In FIG. 12 , the current density of the semiconductor light-emitting device 1 according to this embodiment is shown by a solid line, and the current density of the semiconductor light-emitting device of Comparative Example 1 is also shown by a dotted line. FIG. 13 is a graph showing the relationship between the supply current density and the optical output of the semiconductor light-emitting device 1 according to this embodiment. In FIG. 13 , the relationship of the semiconductor light-emitting device 1 according to this embodiment is shown by a solid line, and the relationship of the semiconductor light-emitting device of Comparative Example 1 is also shown by a dotted line.

[0066] The hole barrier layer 40 of the semiconductor light emitting element 1 according to this embodiment is made of (Al ｘ１ Ga １－ｘ１ ) ｙ１ In １－ｙ１ a first hole blocking layer 41a made of P (0≦x1≦1, 0≦y1≦1); ｘ２ Ga １－ｘ２ P ｙ２ As １－ｙ２ a first intermediate layer 42a made of (0≦x2≦1, 0≦y2<1), and ｘ３ Ga １－ｘ３ ) ｙ３ In １－ｙ３ P (0≦x3≦1, 0≦y3≦1), and a second hole blocking layer made of P (0≦x3≦1, 0≦y3≦1), wherein the average band gap energy of each of the first hole blocking layer 41a and the second hole blocking layer 41b is greater than the average band gap energy of the first intermediate layer 42a.

[0067] As described above, the semiconductor light emitting device 1 according to the present embodiment includes the first hole barrier layer 41 a, the second hole barrier layer 41 b, and the first intermediate layer 42 a disposed therebetween and having an average band gap energy smaller than those of the first and second hole barrier layers 41 a, 41 b. This allows for the formation of two or more barrier layers against holes. Therefore, for example, leakage of holes from the active layer 50 to the n-side cladding layer 20 can be more effectively suppressed than when the semiconductor light emitting device includes a single barrier layer against holes.

[0068] 11 , the hole barrier layer 40 according to this embodiment has an energy barrier ΔEv in the valence band of 0.31, which is larger than that of the hole barrier layer of the semiconductor light-emitting device of Comparative Example 1. Therefore, leakage of holes from the active layer 50 to the n-side guide layer 30 can be further suppressed than in the semiconductor light-emitting device of Comparative Example 1. Therefore, as shown in FIG. 12 , the semiconductor light-emitting device 1 according to this embodiment can further suppress leakage of holes to the n-side layer such as the n-side guide layer 30 than in the semiconductor light-emitting device of Comparative Example 1.

[0069] 10 , the hole barrier layer 40 of the semiconductor light emitting device 1 according to this embodiment has an energy barrier ΔEc in the conduction band of 0.0066 eV, which is smaller than the hole barrier layer of the semiconductor light emitting device of Comparative Example 1. The hole barrier layer 40 according to this embodiment has a band offset ratio of ΔEc:ΔEv=2.1:97.9, which is larger than the energy barrier ΔEc in the conduction band and is significantly smaller than the energy barrier ΔEv in the valence band. Therefore, in the semiconductor light emitting device 1, the hole barrier layer 40 can suppress inhibition of electron injection from the n-side guide layer 30 to the active layer 50.

[0070] Due to the above effects, in the semiconductor light emitting device 1 according to this embodiment, as shown in Fig. 13, the threshold current density of laser oscillation can be significantly reduced compared to the semiconductor light emitting device of Comparative Example 1. Note that, in the semiconductor light emitting device 1 according to this embodiment, the threshold current density of laser oscillation can be reduced compared to the semiconductor light emitting device of Comparative Example 2 which does not have a hole barrier structure, as shown in Figs.

[0071] Furthermore, in the hole barrier layer 40 according to the present embodiment, by adjusting the P composition ratios of the first to fifth intermediate layers 42a to 42e, at least a portion of the lattice mismatch of the first to sixth hole barrier layers 41a to 41f with respect to the substrate 10 can be offset by the lattice mismatch of the first to fifth intermediate layers 42a to 42e with respect to the substrate 10. This reduces stacking strain in the hole barrier layer 40. This reduces crystal defects in the semiconductor light-emitting device, thereby improving the reliability of the semiconductor light-emitting device.

[0072] In this embodiment, the n-side cladding layer 20 is made of (Al ｖ１ Ga １－ｖ１ ) ｗ１ In １－ｗ１ P (0≦v1≦1, 0≦w1≦1), and the first p-side cladding layer 71 is made of (Al ｖ２ Ga １－ｖ２ ) ｗ２ In １－ｗ２ P (0≦v2≦1, 0≦w2≦1).

[0073] This makes it possible to realize the n-side cladding layer 20, the first p-side cladding layer 71, and the second p-side cladding layer 72 suitable for the semiconductor light-emitting element 1 that emits light with a wavelength of 600 nm to 750 nm and uses the active layer 50 that is made of barrier layers 51 a, 51 b, 51 c, and 51 d made of AlGaInP and well layers 52 a, 52 b, and 52 c made of GaInP.

[0074] Furthermore, in the semiconductor light-emitting device 1 according to this embodiment, the ohmic electrode 96 includes an Ag film that is in ohmic contact with the p-type contact layer 92. Using an Ag film, which has a smaller refractive index than other conductive films, as the ohmic electrode 96 can prevent light from propagating upward beyond the ohmic electrode 96. This reduces the light intensity in the p-type contact layer 92, the ohmic electrode 96, and the p-side electrode 98, which have high optical absorption, thereby reducing light absorption loss. Furthermore, reducing light absorption loss in the ohmic electrode 96 and the p-side electrode 98 allows the film thickness of each p-side cladding layer to be reduced. This reduces the electrical resistance in each p-side cladding layer, thereby reducing the operating voltage of the semiconductor light-emitting device 1.

[0075] Furthermore, in the semiconductor light emitting device 1 according to this embodiment, the ohmic electrode 96 may further include a Ni film disposed between the p-type contact layer 92 and the Ag film. This can improve the adhesion between the ohmic electrode 96 and the p-type contact layer 92. Therefore, the reliability of the semiconductor light emitting device 1 can be improved.

[0076] Second Embodiment A semiconductor light-emitting device according to the second embodiment will be described. The semiconductor light-emitting device according to the second embodiment differs from the semiconductor light-emitting device 1 according to the first embodiment in the configuration of the hole barrier layer. The semiconductor light-emitting device according to the second embodiment will be described below with reference to FIGS. 14 to 17 , focusing on the differences from the semiconductor light-emitting device 1 according to the first embodiment. FIG. 14 is a schematic cross-sectional view showing the configuration of the hole barrier layer 140 according to the second embodiment. FIG. 14 shows a cross section parallel to the stacking direction of the hole barrier layer 140 and perpendicular to the light propagation direction. FIG. 15 is a diagram showing the composition, impurity concentration, and film thickness of the hole barrier layer 140 according to the second embodiment. FIG. 16 is a graph showing the distribution of refractive index and optical intensity from the n-side cladding layer 20 to the first p-side cladding layer 71 of the semiconductor light-emitting device according to the second embodiment. FIG. 17 is a graph showing the distribution of refractive index from the n-side guide layer 30 to the active layer 50 of the semiconductor light-emitting device according to the second embodiment. In FIGS. 16 and 17 , the refractive index and optical intensity of the semiconductor light-emitting device according to the second embodiment are shown by solid lines, and the refractive index and optical intensity of the semiconductor light-emitting device according to the first embodiment are also shown by dotted lines.

[0077] As shown in FIG. 14 , the hole barrier layer 140 of the semiconductor light-emitting element of this embodiment has a first hole barrier layer 141 a, a first intermediate layer 142 a, a second hole barrier layer 141 b, a second intermediate layer 142 b, a third hole barrier layer 141 c, a third intermediate layer 142 c, a fourth hole barrier layer 141 d, a fourth intermediate layer 142 d, a fifth hole barrier layer 141 e, a fifth intermediate layer 142 e, and a sixth hole barrier layer 141 f.

[0078] In this embodiment, as shown in FIG. 15, the first hole blocking layer 141a has a concentration of 3.0×10 １７ cm －３ n-type impurity (Si) doped n-type (Al ０．８０ Ga ０．２０ ) ０．５１ In ０．４９ The second hole blocking layer 141b is a P layer. １７ cm －３ n-type impurity (Si) doped n-type (Al ０．７６ Ga ０．２４ )０．５１ In ０．４９ The third hole blocking layer 141c is a P layer. １７ cm －３ n-type impurity (Si) doped n-type (Al ０．７２ Ga ０．２８ ) ０．５１ In ０．４９ The fourth hole blocking layer 141d is a P layer. １７ cm －３ n-type impurity (Si) doped n-type (Al ０．６８ Ga ０．３２ ) ０．５１ In ０．４９ The fifth hole blocking layer 141e has a concentration of 3.0×10 １７ cm －３ n-type impurity (Si) doped n-type (Al ０．６４ Ga ０．３６ ) ０．５１ In ０．４９ The sixth hole blocking layer 141f is a P layer. １７ cm －３ n-type impurity (Si) doped n-type (Al ０．６０ Ga ０．４０ ) ０．５１ In ０．４９ The first intermediate layer 142a, the second intermediate layer 142b, the third intermediate layer 142c, the fourth intermediate layer 142d, and the fifth intermediate layer 142e each have a concentration of 3.0×10 １７ cm －３ n-type Al doped with n-type impurities (Si) having a thickness of 0.002 μm ０．４５ Ga ０．５５ This is an As layer.

[0079] 16 and 17 , in the present embodiment, the average refractive index of the second hole barrier layer 141b is greater than that of the first hole barrier layer 141a, the average refractive index of the third hole barrier layer 141c is greater than that of the second hole barrier layer 141b, the average refractive index of the fourth hole barrier layer 141d is greater than that of the third hole barrier layer 141c, the average refractive index of the fifth hole barrier layer 141e is greater than that of the fourth hole barrier layer 141d, and the average refractive index of the sixth hole barrier layer 141f is greater than that of the fifth hole barrier layer 141e.

[0080] In this way, in the semiconductor light emitting device according to this embodiment, by increasing the average refractive index of the layers close to the active layer 50, the light confinement ratio in the active layer 50 can be made higher than that of the semiconductor light emitting device 1 according to embodiment 1, as shown in the light intensity distribution in Fig. 16. Therefore, the light emitting efficiency of the semiconductor light emitting device can be improved.

[0081] Third Embodiment A semiconductor light-emitting device according to the third embodiment will be described. The semiconductor light-emitting device according to the present embodiment differs from the semiconductor light-emitting device according to the second embodiment in the film thickness of each intermediate layer of the hole barrier layer. The semiconductor light-emitting device according to the present embodiment will be described below with reference to FIGS. 18 to 21 , focusing on the differences from the semiconductor light-emitting device according to the second embodiment. FIG. 18 is a schematic cross-sectional view showing the configuration of a hole barrier layer 240 according to the present embodiment. FIG. 18 shows a cross section parallel to the stacking direction of the hole barrier layer 240 and perpendicular to the light propagation direction. FIG. 19 is a diagram showing the composition, impurity concentration, and film thickness of the hole barrier layer 240 according to the present embodiment. FIG. 20 is a schematic graph showing the energy distributions of the conduction band and valence band of the n-side guide layer 30 and the hole barrier layer 240 according to the present embodiment. FIG. 21 is a schematic graph showing the refractive index distributions of the n-side guide layer 30 and the hole barrier layer 240 according to the present embodiment. The horizontal axes in FIGS. 20 and 21 indicate the position in the stacking direction.

[0082] As shown in FIG. 18 , the hole barrier layer 240 of the semiconductor light-emitting element of this embodiment has a first hole barrier layer 241 a, a first intermediate layer 242 a, a second hole barrier layer 241 b, a second intermediate layer 242 b, a third hole barrier layer 241 c, a third intermediate layer 242 c, a fourth hole barrier layer 241 d, a fourth intermediate layer 242 d, a fifth hole barrier layer 241 e, a fifth intermediate layer 242 e, and a sixth hole barrier layer 241 f.

[0083] As shown in FIG. 19, the hole blocking layer 240 of this embodiment differs from the hole blocking layer 140 of embodiment 2 in that the film thicknesses of the first intermediate layer 242a to the fifth intermediate layer 242e are 0.004 μm, but is the same in other respects.

[0084] Thus, in this embodiment, t1 represents the thickness of the first hole barrier layer 241a, t2 represents the thickness of the first intermediate layer 242a, and t3 represents the thickness of the second hole barrier layer 241b, and the following relationship holds: t1=t3≦t2.

[0085] 20 and 21 , the thickness t2 of the first intermediate layer 242a, which has a small average band gap energy and a large average refractive index, is greater than the thickness t1 of the first hole barrier layer 241a and the thickness t3 of the second hole barrier layer 241b. In addition, in this embodiment, the thicknesses of the first to sixth hole barrier layers 241a to 241f are smaller than the thicknesses of the first to fifth intermediate layers 242a to 242e.

[0086] The effects of the semiconductor light-emitting device according to this embodiment will be described below with reference to FIGS. 22 to 24 . FIG. 22 is a graph showing the relationship between the ratio of the thickness t2 of the first intermediate layer 242a to the thickness t1 of the first hole barrier layer 241a according to this embodiment and the normalized optical confinement ratio. The normalized optical confinement ratio, which is the vertical axis of FIG. 22 , is the optical confinement ratio in the active layer 50 normalized by the optical confinement ratio in the active layer 50 when the ratio of the thickness t2 to the thickness t1 is 1. FIG. 23 is a graph showing the relationship between the ratio of the thickness t2 of the first intermediate layer 242a to the thickness t1 of the first hole barrier layer 241a according to this embodiment and the normalized resistance variation ratio. The normalized resistance variation ratio, which is the vertical axis of FIG. 23 , is the resistance value of the entire semiconductor light-emitting device normalized by the resistance value of the entire semiconductor light-emitting device when the ratio of the thickness t2 to the thickness t1 is 1. 24 is a graph showing the relationship between the ratio of the thickness t2 of the first intermediate layer 242a to the thickness t1 of the first hole barrier layer 241a according to the present embodiment and the normalized hole leakage rate. The normalized hole leakage rate, which is the vertical axis of Fig. 24, is a value obtained by normalizing the amount of holes leaking from the active layer 50 to the n-side guide layer 30 by the amount of holes leaking from the active layer 50 to the n-side guide layer 30 when the ratio of the thickness t2 to the thickness t1 is 1.

[0087] In this embodiment, as described above, by increasing the film thickness of the first intermediate layer 242a having a large average refractive index in the hole barrier layer 240 located closer to the active layer 50 than the n-side cladding layer 20, the optical confinement rate in the active layer 50 can be increased as shown in Fig. 22. Therefore, the luminous efficiency of the semiconductor light emitting element can be increased.

[0088] Furthermore, in this embodiment, the first hole barrier layer 241a to the sixth hole barrier layer 241f are made of AlGaInP, and the first intermediate layer 242a to the fifth intermediate layer 242e are made of AlGaPAs. Here, AlGaPAs has a higher mobility than AlGaInP. Therefore, as in the semiconductor light emitting device of this embodiment, the film thicknesses of the first hole barrier layer 241a to the sixth hole barrier layer 241f made of AlGaInP, which has a lower mobility, are made smaller than the film thicknesses of the first intermediate layer 242a to the fifth intermediate layer 242e made of AlGaPAs, which has a higher mobility, thereby reducing the resistance of the hole barrier layer 240. Therefore, as shown in FIG. 23 , the resistance of the semiconductor light emitting device can be reduced by increasing the film thickness ratio t2 / t1.

[0089] 24, the hole leakage rate can be reduced by increasing the film thickness ratio t2 / t1, thereby increasing the light emitting efficiency of the semiconductor light emitting element.

[0090] Fourth Embodiment A semiconductor light-emitting device according to the fourth embodiment will be described. The semiconductor light-emitting device according to the present embodiment differs from the semiconductor light-emitting device 1 according to the first embodiment in the composition of each intermediate layer of the hole barrier layer. The semiconductor light-emitting device according to the present embodiment will be described below with reference to FIGS. 25 to 28 , focusing on the differences from the semiconductor light-emitting device according to the first embodiment. FIG. 25 is a schematic cross-sectional view showing the configuration of a hole barrier layer 340 according to the present embodiment. FIG. 25 shows a cross section parallel to the stacking direction of the hole barrier layer 340 and perpendicular to the light propagation direction. FIG. 26 is a diagram showing the composition, impurity concentration, and film thickness of the hole barrier layer 340 according to the present embodiment. FIG. 27 is a graph showing the distribution of refractive index and light intensity from the n-side cladding layer 20 to the first p-side cladding layer 71 of the semiconductor light-emitting device according to the present embodiment. FIG. 28 is a graph showing the distribution of refractive index from the n-side guide layer 30 to the active layer 50 of the semiconductor light-emitting device according to the present embodiment. In Figures 27 and 28, the refractive index and light intensity of the semiconductor light-emitting element according to this embodiment are shown by solid lines, and the refractive index and light intensity of the semiconductor light-emitting element according to embodiment 1 are also shown by dotted lines.

[0091] As shown in FIG. 25 , the hole barrier layer 340 of the semiconductor light-emitting element of this embodiment has a first hole barrier layer 341 a, a first intermediate layer 342 a, a second hole barrier layer 341 b, a second intermediate layer 342 b, a third hole barrier layer 341 c, a third intermediate layer 342 c, a fourth hole barrier layer 341 d, a fourth intermediate layer 342 d, a fifth hole barrier layer 341 e, a fifth intermediate layer 342 e, and a sixth hole barrier layer 341 f.

[0092] 26, the first hole barrier layer 341a to the sixth hole barrier layer 341f according to the present embodiment have the same configuration as the first hole barrier layer 41a to the sixth hole barrier layer 41f according to Embodiment 1. The first intermediate layer 342a has a concentration of 3.0×10 １７ cm －３ n-type Al doped with n-type impurities (Si) having a thickness of 0.002 μm ０．４５ Ga ０．５５ The second intermediate layer 342b is an As layer. １７ cm －３ n-type Al doped with n-type impurities (Si) having a thickness of 0.002 μm ０．４３ Ga ０．５７ The third intermediate layer 342c is an As layer. １７ cm －３ n-type Al doped with n-type impurities (Si) having a thickness of 0.002 μm ０．４２ Ga ０．５８ The fourth intermediate layer 342d is an As layer. １７ cm －３ n-type Al doped with n-type impurities (Si) having a thickness of 0.002 μm ０．４１ Ga ０．５９ The fifth intermediate layer 342e is an As layer. １７ cm －３ n-type Al doped with n-type impurities (Si) having a thickness of 0.002 μm ０．４０ Ga ０．６０ This is an As layer.

[0093] 27 and 28 , in the present embodiment, the average refractive index of the first intermediate layer 342a to the fifth intermediate layer 342e is smaller than the average refractive index of one or more well layers 52a to 52c of the active layer 50, and is larger than the average refractive index of the n-side cladding layer 20. As a result, in the semiconductor light emitting device according to the present embodiment, as shown in the light intensity distribution in Fig. 27 , the optical confinement ratio in the active layer 50 can be made higher than that of the semiconductor light emitting device 1 according to embodiment 1. Therefore, the luminous efficiency of the semiconductor light emitting device can be improved.

[0094] In the present embodiment, the average refractive index of the second intermediate layer 342b is greater than that of the first intermediate layer 342a, the average refractive index of the third intermediate layer 342c is greater than that of the second intermediate layer 342b, the average refractive index of the fourth intermediate layer 342d is greater than that of the third intermediate layer 342c, and the average refractive index of the fifth intermediate layer 342e is greater than that of the fourth intermediate layer 342d.

[0095] In this way, in the semiconductor light emitting device according to this embodiment, by increasing the average refractive index of the layers close to the active layer 50, the light confinement ratio in the active layer 50 can be made higher than that of the semiconductor light emitting device 1 according to embodiment 1, as shown in the light intensity distribution in Fig. 27. Therefore, the light emitting efficiency of the semiconductor light emitting device can be improved.

[0096] Fifth Embodiment A semiconductor light-emitting device according to the fifth embodiment will be described. The semiconductor light-emitting device according to the present embodiment differs from the semiconductor light-emitting device 1 according to the first embodiment mainly in the wavelength band of the emitted light. The semiconductor light-emitting device according to the present embodiment will be described below with reference to FIGS. 29 to 33, focusing on the differences from the semiconductor light-emitting device according to the first embodiment. FIG. 29 is a schematic cross-sectional view showing the overall configuration of a semiconductor light-emitting device 401 according to the present embodiment. FIGS. 30 and 31 are schematic cross-sectional views showing the configurations of the hole barrier layer 440 and the active layer 450 of the semiconductor light-emitting device 401 according to the present embodiment, respectively. FIGS. 29 to 31 show cross sections parallel to the stacking direction of the semiconductor light-emitting device 401 and perpendicular to the light propagation direction. FIGS. 32 and 33 are first and second diagrams, respectively, showing the composition, impurity concentration, and film thickness of each layer included in the semiconductor light-emitting device 401 according to the present embodiment. FIG. 32 shows the composition and other details of each layer, from the active layer 450 to the p-type contact layer 92, of the semiconductor light-emitting device 401 in stacking order. FIG. 33 shows the composition of each layer from the substrate 10 to the hole barrier layer 440 of the semiconductor light emitting element 401 in the stacking order.

[0097] In this embodiment, the semiconductor light emitting element 401 is a semiconductor laser element that emits light (laser light) with a wavelength of 750 nm or more and 860 nm or less.

[0098] 29 , the semiconductor light emitting device 401 includes a substrate 10, an n-side cladding layer 420, a hole barrier layer 440, an active layer 450, a first p-side cladding layer 471, and a second p-side cladding layer 472. In this embodiment, the semiconductor light emitting device 401 further includes an n-type buffer layer 12, a boundary layer 414, an n-side guide layer 430, a p-side guide layer 460, an etching stop layer 80, a boundary layer 490, a p-type contact layer 92, a current blocking layer 94, an ohmic electrode 96, a p-side electrode 98, and an n-side electrode 99.

[0099] As shown in FIG. 33, the boundary layer 414 according to this embodiment has a concentration of 7.5×10 １７ cm －３ n-type Al doped with n-type impurities (Si) having a thickness of 0.075 μm Ｘ Ga １－ＸThe boundary layer 414 is an As layer (0.05≦X≦0.31). The Al composition ratio X of the boundary layer 414 increases toward the n-side cladding layer 420. The Al composition ratio X of the boundary layer 414 is 0.05 at the interface with the n-type buffer layer 12 and 0.31 at the interface with the n-side cladding layer 420.

[0100] The n-side cladding layer 420 according to this embodiment is made of (Al ｖ１ Ga １－ｖ１ ) ｗ１ In １－ｗ１ P (0≦v1≦1, 0≦w1≦1). More specifically, as shown in FIG. 33, the n-side cladding layer 420 is made of an n-type (Al ０．６３ Ga ０．３７ ) ０．５１ In ０．４９ The impurity concentration of the n-side cladding layer 420 is 7.5×10 in a region where the distance from the boundary surface with the boundary layer 414 (i.e., the film thickness) is 1.78 μm or less. １７ cm －３ In the region where the distance from the boundary surface with the boundary layer 414 is greater than 1.78 μm and less than or equal to 2.28 μm, １７ cm －３ In the region where the distance from the boundary surface with the boundary layer 414 is greater than 2.28 μm and less than or equal to 3.28 μm, １７ cm －３ is.

[0101] The n-side guide layer 430 according to this embodiment is made of Al ｖ４ Ga １－ｖ４ P ｗ４ As １－ｗ４ (0≦v4≦1, 0≦w4<1). More specifically, as shown in FIG. 33, the n-side guide layer 430 has a concentration of 3.0×10 １７ cm －３ n-type Al doped with n-type impurities (Si) having a thickness of 0.009 μm ０．５９ Ga ０．４１ This is an As layer.

[0102] As shown in FIG. 30 , the hole blocking layer 440 of this embodiment has a first hole blocking layer 441 a, a first intermediate layer 442 a, a second hole blocking layer 441 b, a second intermediate layer 442 b, a third hole blocking layer 441 c, a third intermediate layer 442 c, and a fourth hole blocking layer 441 d.

[0103] In this embodiment, as shown in FIG. 33, each of the first hole barrier layer 441a, the second hole barrier layer 441b, the third hole barrier layer 441c, and the fourth hole barrier layer 441d has a concentration of 3.0×10 １７ cm －３ n-type impurity (Si) doped n-type (Al ０．６３ Ga ０．３７ ) ０．５１ In ０．４９ The first intermediate layer 442a, the second intermediate layer 442b, and the third intermediate layer 442c each have a concentration of 3.0×10 １７ cm －３ n-type Al doped with n-type impurities (Si) having a thickness of 0.004 μm ０．４５ Ga ０．５５ This is an As layer.

[0104] The active layer 450 according to this embodiment has barrier layers 451a, 451b, and 451c and well layers 452a and 452b as shown in Fig. 31. As shown in Fig. 32, the barrier layers 451a, 451b, and 451c according to this embodiment are made of undoped AlN 0.004 µm thick. ０．５９ Ga ０．４１ The well layers 452a and 452b according to this embodiment are undoped GaAs layers with a thickness of 0.0037 μm.

[0105] The p-side guide layer 460 according to this embodiment is an example of a p-side guide layer, and is made of Al ｖ３ Ga １－ｖ３ P ｗ３ As １－ｗ３ (0≦v3≦1, 0≦w3<1). More specifically, as shown in FIG. 32, the p-side guide layer 460 is an undoped Al ０．５９ Ga ０．４１ This is an As layer.

[0106] The first p-side cladding layer 471 according to this embodiment is an example of a p-side cladding layer, and is made of (Al ｖ２ Ga １－ｖ２ ) ｗ２ In １－ｗ２ P (0≦v2≦1, 0≦w2≦1). More specifically, as shown in FIG. 32, the first p-side cladding layer 471 has a concentration of 3.2×10 １７ cm －３ p-type impurity (Zn or Mg) doped p-type (Al ０．７０ Ga ０．３０ ) ０．５１ In ０．４９ This is the P layer.

[0107] The second p-side cladding layer 472 according to the present embodiment is an example of a p-side cladding layer, and is made of (Al ｖ２ Ga １－ｖ２ ) ｗ２ In １－ｗ２ P (0≦v2≦1, 0≦w2≦1). More specifically, as shown in FIG. 32, the second p-side cladding layer 472 has a concentration of 1.2×10 １８ cm －３ p-type impurity (Zn or Mg) doped p-type (Al ０．７０ Ga ０．３０ ) ０．５１ In ０．４９ This is the P layer.

[0108] As shown in FIG. 32, the boundary layer 490 according to this embodiment has a concentration of 1.2×10 １８ cm －３ p-type impurity (Zn or Mg) doped p-type (Al ０．４５ Ga ０．５５ ) ０．５１ In ０．４９ P layer and a layer with a concentration of 1.2 × 10 １８ cm －３ p-type impurity (Zn or Mg) doped p-type (Al ０．２５ Ga ０．７５ ) ０．５１ In ０．４９ P layer and a layer with a concentration of 2×10 １８ cm －３p-type Ga doped with p-type impurities (Zn or Mg) of 0.038 μm thickness ０．５１ In ０．４９ and a P layer.

[0109] In the semiconductor light-emitting element 401 having the above-described configuration, similar to the semiconductor light-emitting element 1 according to the first embodiment, it is possible to realize a semiconductor light-emitting element 401 having a hole barrier layer 440 that can suppress the magnitude of the energy barrier in the conduction band.

[0110] In this embodiment, the n-side cladding layer 420 is made of (Al ｖ１ Ga １－ｖ１ ) ｗ１ In １－ｗ１ P (0≦v1≦1, 0≦w1≦1), and the first p-side cladding layer 471 and the second p-side cladding layer 472 are made of (Al ｖ２ Ga １－ｖ２ ) ｗ２ In １－ｗ２ P (0≦v2≦1, 0≦w2≦1), and the p-side guide layer 460 is Al ｖ３ Ga １－ｖ３ P ｗ３ As １－ｗ３ (0≦v3≦1, 0≦w3<1).

[0111] This makes it possible to realize the n-side cladding layer 420, the first p-side cladding layer 471, the second p-side cladding layer 472, and the p-side guide layer 460 suitable for the semiconductor light-emitting element 401 that emits light with a wavelength of 750 nm or more and 860 nm or less, using the active layer 450 that includes the barrier layers 451 a, 451 b, and 451 c made of AlGaAs and the well layers 452 a and 452 b made of GaAs.

[0112] Sixth Embodiment A semiconductor light-emitting device according to the sixth embodiment will be described. The semiconductor light-emitting device according to the sixth embodiment differs from the semiconductor light-emitting device 1 according to the first embodiment mainly in the wavelength band of the emitted light. The semiconductor light-emitting device according to the sixth embodiment will be described below with reference to FIGS. 34 to 38, focusing on the differences from the semiconductor light-emitting device according to the first embodiment. FIG. 34 is a schematic cross-sectional view showing the overall configuration of a semiconductor light-emitting device 501 according to the sixth embodiment. FIGS. 35 and 36 are schematic cross-sectional views showing the configurations of a hole barrier layer 540 and an active layer 550 of the semiconductor light-emitting device 501 according to the sixth embodiment, respectively. FIGS. 34 to 36 show cross sections parallel to the stacking direction of the semiconductor light-emitting device 501 and perpendicular to the light propagation direction. FIGS. 37 and 38 are first and second diagrams, respectively, showing the composition, impurity concentration, and film thickness of each layer included in the semiconductor light-emitting device 501 according to the sixth embodiment. FIG. 37 shows the composition and other details of each layer, from the active layer 550 to the p-type contact layer 592, of the semiconductor light-emitting device 501 in stacking order. FIG. 38 shows the composition and other details of each layer from the substrate 10 to the third n-side guide layer 533 of the semiconductor light emitting device 501 in the order of lamination.

[0113] In this embodiment, the semiconductor light emitting element 501 is a semiconductor laser element that emits light (laser light) with a wavelength of 830 nm or more and 1000 nm or less.

[0114] 34 , a semiconductor light emitting device 501 includes a substrate 10, an n-side cladding layer 520, a hole barrier layer 540, an active layer 550, a first p-side cladding layer 571, a second p-side cladding layer 572, and a third p-side cladding layer 573. In this embodiment, the semiconductor light emitting device 501 further includes an n-type buffer layer 12, boundary layers 514, 516, and 570, a first n-side guiding layer 531, a second n-side guiding layer 532, a third n-side guiding layer 533, a first p-side guiding layer 561, a second p-side guiding layer 562, a first etching stop layer 581, a second etching stop layer 582, a p-type contact layer 592, a current blocking layer 94, an ohmic electrode 96, a p-side electrode 98, and an n-side electrode 99.

[0115] As shown in FIG. 38, the boundary layer 514 according to this embodiment has a density of 2.0×10１８ cm －３ n-type Al doped with n-type impurities (Si) having a thickness of 0.05 μm Ｘ Ga １－Ｘ The boundary layer 514 is an As layer (0.15≦X≦0.29). The Al composition ratio X of the boundary layer 514 increases toward the n-side cladding layer 520. The Al composition ratio X of the boundary layer 514 is 0.15 at the interface with the n-type buffer layer 12 and 0.29 at the interface with the n-side cladding layer 520.

[0116] The n-side cladding layer 520 according to this embodiment is made of Al ｖ５ Ga １－ｖ５ P ｗ５ As １－ｗ５ (0≦v5≦1, 0≦w5<1). More specifically, as shown in FIG. 38, the n-side cladding layer 520 is made of an n-type Al ０．２９ Ga ０．７１ The impurity concentration of the n-side cladding layer 520 is 2.0×10 in a region where the distance from the boundary surface with the boundary layer 514 (i.e., the film thickness) is 2.50 μm or less. １８ cm －３ In the region where the distance from the boundary surface with the boundary layer 514 is greater than 2.50 μm and equal to or less than 2.70 μm, １７ cm －３ In the region where the distance from the boundary surface with the boundary layer 514 is greater than 2.70 μm and less than or equal to 3.00 μm, １７ cm －３ is.

[0117] The boundary layer 516 according to this embodiment is a semiconductor layer disposed between the n-side cladding layer 520 and the first n-side guide layer 531. As shown in FIG. 38 , the boundary layer 516 has a concentration of 2.0×10 １７ cm －３ to 1.0 x 10 １７ cm －３ n-type Al doped with n-type impurities (Si) having a thickness of 0.20 μm Ｘ Ga １－Ｘ As layer (0.29≧X≧0.26) and a layer having a concentration of 3.5×10 １７ cm －３n-type Al doped with n-type impurities (Si) having a thickness of 0.56 μm Ｘ Ga １－Ｘ The boundary layer 516 has an n-type Al layer having a thickness of 0.20 μm. Ｘ Ga １－Ｘ In the As layer (0.29≧X≧0.26), the Al composition ratio X and the n-type impurity concentration decrease toward the first n-side guide layer 531. Ｘ Ga １－Ｘ In the As layer (0.26≧X≧0.23), the Al composition ratio X decreases toward the first n-side guide layer 531 .

[0118] The first n-side guide layer 531 according to this embodiment is made of Al ｖ４ Ga １－ｖ４ P ｗ４ As １－ｗ４ (0≦v4≦1, 0≦w4<1). More specifically, as shown in FIG. 38, the first n-side guide layer 531 has a concentration of 3.5×10 １７ cm －３ n-type Al doped with n-type impurities (Si) having a thickness of 0.32 μm ０．２１ Ga ０．７９ This is an As layer.

[0119] The second n-side guide layer 532 according to this embodiment is made of Al ｖ４ Ga １－ｖ４ P ｗ４ As １－ｗ４ (0≦v4≦1, 0≦w4<1). More specifically, as shown in FIG. 38, the second n-side guide layer 532 has a concentration of 1.0×10 １７ cm －３ n-type Al doped with n-type impurities (Si) having a thickness of 0.020 μm ０．１５ Ga ０．８５ This is an As layer.

[0120] As shown in FIG. 35 , the hole blocking layer 540 of this embodiment has a first hole blocking layer 541 a, a first intermediate layer 542 a, a second hole blocking layer 541 b, a second intermediate layer 542 b, a third hole blocking layer 541 c, a third intermediate layer 542 c, a fourth hole blocking layer 541 d, a fourth intermediate layer 542 d, and a fifth hole blocking layer 541 e.

[0121] In this embodiment, as shown in FIG. 38 , each of the first hole barrier layer 541 a, the second hole barrier layer 541 b, the third hole barrier layer 541 c, the fourth hole barrier layer 541 d, and the fifth hole barrier layer 541 e has a concentration of 1.0×10 １７ cm －３ n-type impurity (Si) doped n-type (Al ０．１２ Ga ０．８８ ) ０．５１ In ０．４９ The first intermediate layer 542a, the second intermediate layer 542b, the third intermediate layer 542c, and the fourth intermediate layer 542d each have a concentration of 1.0×10 １７ cm －３ n-type Al doped with n-type impurities (Si) having a thickness of 0.004 μm ０．１５ Ga ０．８５ This is an As layer.

[0122] The third n-side guide layer 533 according to this embodiment is disposed between the hole barrier layer 540 and the active layer 550, and is made of Al ｖ４ Ga １－ｖ４ P ｗ４ As １－ｗ４ (0≦v4≦1, 0≦w4<1). More specifically, as shown in FIG. 38, the third n-side guide layer 533 has a concentration of 1.0×10 １７ cm －３ n-type Al doped with n-type impurities (Si) having a thickness of 0.020 μm ０．１５ Ga ０．８５ This is an As layer.

[0123] The active layer 550 according to this embodiment has barrier layers 551a and 551b and a well layer 552a as shown in Fig. 36. As shown in Fig. 37, the barrier layer 551a according to this embodiment is an undoped Al layer having a thickness of 0.025 µm. Ｘ Ga １－ＸThe Al composition ratio of the barrier layer 551a decreases toward the well layer 552a. The well layer 552a according to this embodiment is an undoped In layer with a thickness of 0.0090 μm. ０．１３５ Ga ０．８６５ The barrier layer 551b according to this embodiment is an undoped Al layer having a thickness of 0.025 μm. Ｘ Ga １－Ｘ The Al composition ratio of the barrier layer 551b decreases toward the well layer 552a.

[0124] The first p-side guide layer 561 according to the present embodiment is an example of a p-side guide layer, and is made of Al ｖ３ Ga １－ｖ３ P ｗ３ As １－ｗ３ 37, the first p-side guide layer 561 is an undoped Al ０．１５ Ga ０．８５ This is an As layer.

[0125] The second p-side guide layer 562 according to the present embodiment is an example of a p-side guide layer, and is made of Al ｖ３ Ga １－ｖ３ P ｗ３ As １－ｗ３ (0≦v3≦1, 0≦w3<1). More specifically, as shown in FIG. 37, the second p-side guide layer 562 has a concentration of 3.0×10 １６ cm －３ p-type Al doped with p-type impurities (C) having a thickness of 0.02 μm ０．２５ Ga ０．７５ As layer and a layer having a concentration of 4.0×10 １６ cm －３ 1.5 x 10 １７ cm －３ The following p-type impurity (C) doped p-type Al with a thickness of 0.16 μm: Ｘ Ga １－Ｘ The second p-side guide layer 562 has a p-type Al layer (0.25≦X≦0.26). Ｘ Ga １－ＸThe p-type impurity concentration and Al composition ratio of the As layer (0.25≦X≦0.26) increase with increasing distance from the first p-side guide layer 561 .

[0126] The boundary layer 570 according to this embodiment is a semiconductor layer disposed between the second p-side guide layer 562 and the first p-side cladding layer 571. As shown in FIG. 37 , the boundary layer 570 has a concentration of 3.0×10 １６ cm －３ 6.5 x 10 １７ cm －３ The following p-type impurity (C) doped p-type Al with a thickness of 0.10 μm: Ｘ Ga １－Ｘ The boundary layer 570 is an As layer (0.26≦X≦0.75). The p-type impurity concentration and the Al composition ratio X of the boundary layer 570 increase with increasing distance from the second p-side guide layer 562 .

[0127] The first p-side cladding layer 571 according to the present embodiment is an example of a p-side cladding layer, and is made of Al ｖ６ Ga １－ｖ６ P ｗ６ As １－ｗ６ (0≦v6≦1, 0≦w6<1). More specifically, as shown in FIG. 37, the first p-side cladding layer 571 has a concentration of 1.0×10 １８ cm －３ p-type Al doped with p-type impurities (C) having a thickness of 0.05 μm ０．７５ Ga ０．２５ This is an As layer.

[0128] The second p-side cladding layer 572 according to the present embodiment is an example of a p-side cladding layer, and is made of Al ｖ６ Ga １－ｖ６ P ｗ６ As １－ｗ６ (0≦v6≦1, 0≦w6<1). More specifically, as shown in FIG. 37, the second p-side cladding layer 572 has a concentration of 3.7×10 １８ cm －３ p-type Al doped with p-type impurities (C) having a thickness of 0.20 μm ０．８５ Ga ０．１５ This is an As layer.

[0129] The first etching stop layer 581 according to the present embodiment is an example of an etching stop layer disposed above the active layer 550. As shown in FIG. 37 , the first etching stop layer 581 has a concentration of 5.0×10 １８ cm －３ p-type Al doped with p-type impurities (C) having a thickness of 0.05 μm ０．７０ Ga ０．３０ The first etching stop layer 581 is an As layer. The first etching stop layer 581 is less susceptible to etching than the third p-side cladding layer 573 (i.e., has a lower etching rate). Therefore, when the ridge R0 is formed by etching, it is easy to stop the etching at the first etching stop layer 581. That is, as shown in FIG. 34 , it is easy to control the position of the bottom end Ru0 of the ridge R0 at the first etching stop layer 581.

[0130] The third p-side cladding layer 573 according to the present embodiment is an example of a p-side cladding layer, and is made of Al ｖ６ Ga １－ｖ６ P ｗ６ As １－ｗ６ (0≦v6≦1, 0≦w6<1). More specifically, as shown in FIG. 37, the third p-side cladding layer 573 has a concentration of 3.7×10 １８ cm －３ p-type Al doped with p-type impurities (C) having a thickness of 0.20 μm ０．８５ Ga ０．１５ This is an As layer.

[0131] The second etching stop layer 582 according to the present embodiment is an example of an etching stop layer disposed above the active layer 550. As shown in FIG. 37 , the second etching stop layer 582 has a concentration of 5.0×10 １８ cm －３ p-type Al doped with p-type impurities (C) having a thickness of 0.05 μm ０．７０ Ga ０．３０ As layer and a layer having a concentration of 5.0×10 １８ cm －３ p-type Al doped with p-type impurities (C) having a thickness of 0.01 μm Ｘ Ga １－Ｘ As layer (0.70≧X≧0.60) and a layer having a concentration of 5.0×10１８ cm －３ p-type Al doped with p-type impurities (C) having a thickness of 0.03 μm ０．６０ Ga ０．４０ As layer and a layer having a concentration of 5.0×10 １８ cm －３ p-type Al doped with p-type impurities (C) having a thickness of 0.01 μm Ｘ Ga １－Ｘ As layer (0.60≧X≧0.15). Ｘ Ga １－Ｘ The Al composition ratio of the As layer decreases with increasing distance from the third p-side cladding layer 573. The second etching stop layer 582 is less susceptible to etching than the p-type contact layer 592 (i.e., has a lower etching rate), and therefore, of the p-type contact layer 592 and the second etching stop layer 582, it is easy to etch only the p-type contact layer 592.

[0132] The p-type contact layer 592 according to this embodiment has a concentration of 1.0×10 １８ cm －３ Above 3.0 x 10 １９ cm －３ The p-type contact layer 592 is a 0.01 μm thick p-type GaAs layer doped with the following p-type impurity (C): The p-type impurity concentration of the p-type contact layer 592 increases with increasing distance from the second etching stop layer 582 .

[0133] In the semiconductor light-emitting element 501 having the above-described configuration, similar to the semiconductor light-emitting element 1 according to the first embodiment, it is possible to realize a semiconductor light-emitting element 501 having a hole barrier layer 540 that can suppress the magnitude of the energy barrier in the conduction band.

[0134] In this embodiment, each n-side cladding layer is made of Al ｖ５ Ga １－ｖ５ P ｗ５ As １－ｗ５ (0≦v5≦1, 0≦w5<1), and each p-side cladding layer is Al ｖ６ Ga １－ｖ６ P ｗ６ As １－ｗ６ (0≦v6≦1, 0≦w6<1).

[0135] This makes it possible to realize n-side cladding layers and p-side cladding layers suitable for a semiconductor light-emitting element 501 that emits light with a wavelength of 830 nm or more and 1000 nm or less, using an active layer 550 that includes barrier layers 551 a, 551 b made of AlGaAs and a well layer 552 a made of InGaAs.

[0136] Seventh Embodiment A semiconductor light-emitting device according to the seventh embodiment will be described. The semiconductor light-emitting device according to the present embodiment differs from the semiconductor light-emitting device 501 according to the sixth embodiment in the configuration of the hole barrier layer. Hereinafter, the semiconductor light-emitting device according to the present embodiment will be described with reference to FIGS. 39 to 43, focusing on the differences from the semiconductor light-emitting device 501 according to the sixth embodiment. FIG. 39 is a schematic cross-sectional view showing the configuration of a hole barrier layer 640 according to the present embodiment. FIG. 39 shows a cross section parallel to the stacking direction of the hole barrier layer 640 and perpendicular to the propagation direction of light. FIG. 40 is a diagram showing the composition, impurity concentration, and film thickness of the hole barrier layer 640 according to the present embodiment. FIG. 41 is a graph showing the energy distribution of the lower end of the conduction band from the first n-side guide layer 531 to the second p-side guide layer 562 according to the present embodiment. FIG. 42 is a graph showing the energy distribution of the upper end of the valence band from the first n-side guide layer 531 to the second p-side guide layer 562 according to the present embodiment. 41 and 42, the energy distribution of the semiconductor light emitting device according to this embodiment is shown by a solid line, and the energy distribution of the semiconductor light emitting device 501 according to embodiment 6 is also shown by a dotted line. Fig. 43 is a graph showing the relationship between the voltage applied to the semiconductor light emitting device according to this embodiment and the current density. In Fig. 43, the relationship of the semiconductor light emitting device according to this embodiment is shown by a solid line, and the relationship of the semiconductor light emitting device 501 according to embodiment 6 is also shown by a dotted line.

[0137] The hole barrier layer 640 of the semiconductor light-emitting element of this embodiment has a first hole barrier layer 641a, a first intermediate layer 642a, a second hole barrier layer 641b, a second intermediate layer 642b, a third hole barrier layer 641c, a third intermediate layer 642c, a fourth hole barrier layer 641d, a fourth intermediate layer 642d, and a fifth hole barrier layer 641e, as shown in Figure 39.

[0138] In this embodiment, as shown in FIG. 40, the first hole barrier layer 641a has a concentration of 1.0×10 １７ cm －３ n-type impurity (Si) doped n-type (Al ０．１２ Ga ０．８８ ) ０．５１ In ０．４９ Each of the second hole barrier layer 641b, the third hole barrier layer 641c, the fourth hole barrier layer 641d, and the fifth hole barrier layer 641e has a concentration of 1.0×10 １７ cm －３ n-type impurity (Si) doped n-type (Al ０．０４ Ga ０．９６ ) ０．４５ In ０．５５ The first intermediate layer 642a, the second intermediate layer 642b, the third intermediate layer 642c, and the fourth intermediate layer 642d each have a concentration of 1.0×10 １７ cm －３ n-type Al doped with n-type impurities (Si) having a thickness of 0.004 μm ０．１５ Ga ０．８５ This is an As layer.

[0139] In the present embodiment, by making the In composition ratio of the second hole barrier layer 641b larger than that of the first hole barrier layer 641a, the average band gap energy of the second hole barrier layer 641b can be made smaller than the average band gap energy of the first hole barrier layer 641a, as shown in Figures 41 and 42. Accordingly, the energy of the lower end of the conduction band of the second hole barrier layer 641b can be made smaller than the energy of the lower end of the conduction band of the first hole barrier layer 641a, as shown in Figure 41.

[0140] Thus, the average conduction band energy of the second hole barrier layer 641b is smaller than that of the first hole barrier layer 641a and is equal to or smaller than that of the layer adjacent to the hole barrier layer 640 above (in this embodiment, the third n-side guide layer 533).

[0141] This reduces the energy required for electrons to overcome the hole barrier layer 640, and as shown in Figure 43, the operating voltage of the semiconductor light-emitting device can be reduced below that of the semiconductor light-emitting device 501 according to embodiment 6.

[0142] (Embodiment 8) A semiconductor light-emitting device according to embodiment 8 will be described. The semiconductor light-emitting device according to this embodiment differs from the semiconductor light-emitting device according to embodiment 7 mainly in that it has an electron barrier layer. The semiconductor light-emitting device according to this embodiment will be described below with reference to FIG. 44, focusing on the differences from the semiconductor light-emitting device according to embodiment 7. FIG. 44 is a schematic cross-sectional view showing the overall configuration of a semiconductor light-emitting device 701 according to this embodiment. FIG. 44 shows a cross-section parallel to the stacking direction of the semiconductor light-emitting device 701 and perpendicular to the light propagation direction.

[0143] 44 , a semiconductor light emitting device 701 includes a substrate 10, an n-side cladding layer 520, a hole barrier layer 640, an active layer 550, an electron barrier layer 761, a first p-side cladding layer 571, a second p-side cladding layer 572, and a third p-side cladding layer 573. In this embodiment, the semiconductor light emitting device 701 further includes an n-type buffer layer 12, boundary layers 514, 516, and 570, a first n-side guiding layer 531, a second n-side guiding layer 532, a third n-side guiding layer 533, a p-side guiding layer 762, a first etching stop layer 581, a second etching stop layer 582, a p-type contact layer 592, a current blocking layer 94, an ohmic electrode 96, a p-side electrode 98, and an n-side electrode 99.

[0144] The hole blocking layer 640 according to this embodiment has the same structure as the hole blocking layer according to the seventh embodiment.

[0145] The electron barrier layer 761 according to this embodiment is a semiconductor layer that is disposed between the active layer 550 and the first p-side cladding layer 571 and serves as a barrier against electrons. In this embodiment, the electron barrier layer 761 has a concentration of 5.0×10 １７ cm －３ p-type Al doped with p-type impurities (C) having a thickness of 0.020 μm ０．１５ Ga ０．８５ This is an As layer.

[0146] The p-side guide layer 762 according to this embodiment is Al ｖ３ Ga １－ｖ３ P ｗ３ As １－ｗ３ (0≦v3≦1, 0≦w3<1). More specifically, the p-side guide layer 762 has a concentration of 3.0×10 １６ cm －３ p-type Al doped with p-type impurities (C) having a thickness of 0.010 μm ０．２５ Ga ０．７５ As layer and a layer having a concentration of 4.0×10 １６ cm －３ 1.5 x 10 １７ cm －３ The following p-type impurity (C) doped p-type Al with a thickness of 0.16 μm: Ｘ Ga １－Ｘ The p-side guide layer 762 has a p-type Al layer. Ｘ Ga １－Ｘ The p-type impurity concentration and Al composition ratio of the As layer (0.25≦X≦0.26) increase with increasing distance from the first p-side guide layer 561 .

[0147] The semiconductor light emitting device 701 according to this embodiment includes an electron barrier layer 761. Increasing the p-type impurity concentration or Al composition ratio in the electron barrier layer 761 increases the energy of the conduction band minimum. In this embodiment, the p-type impurity concentration of the electron barrier layer 761 is made higher than that of each adjacent layer, thereby increasing the energy of the conduction band minimum. Specifically, the p-type impurity concentration of the electron barrier layer 761 is higher than that of the adjacent p-side guide layer 762. The p-type impurity concentration of the electron barrier layer 761 is lower than that of the p-side cladding layer (the first p-side cladding layer 571 in this embodiment). In this case, the electron barrier layer 761 may have a band gap energy equal to or lower than that of the first p-side cladding layer 571. This suppresses electron leakage without impairing light confinement in the active layer 550. Alternatively, the electron barrier layer 761 may have a band gap energy equal to or lower than that of the p-side guide layer 762. That is, the electron barrier layer 761 may have a refractive index equal to or higher than that of the p-side guide layer 762. By making the refractive index of the electron barrier layer 761 equal to or higher than that of the p-side guide layer 762, light confinement in the active layer 550 is improved, light emission efficiency is increased, and electron leakage can be suppressed. Alternatively, the electron barrier layer 761 made of AlGaAs may have a bandgap energy smaller than that of the hole barrier layer 640 made of AlGaInP. That is, the electron barrier layer 761 may have a refractive index higher than that of the hole barrier layer 640. By making the refractive index of the electron barrier layer 761 higher than that of the hole barrier layer 640, light confinement in the active layer 550 is improved and light emission efficiency is increased. Alternatively, the p-type impurity concentration of the electron barrier layer 761 may be higher than the n-type impurity concentration of the hole barrier layer 640. In this embodiment, the semiconductor light emitting device 701 includes the electron barrier layer 761, which can suppress leakage of electrons from the active layer 550 to the p-side guide layer 762 and the first p-side cladding layer 571. Therefore, the light emitting efficiency of the semiconductor light emitting device 701 can be improved.

[0148] Ninth Embodiment A semiconductor light-emitting device according to a ninth embodiment will be described. The semiconductor light-emitting device according to this embodiment differs from the semiconductor light-emitting device 701 according to the eighth embodiment in the configuration of the electron barrier layer. The semiconductor light-emitting device according to this embodiment will be described below with reference to FIG. 45 , focusing on the differences from the semiconductor light-emitting device 701 according to the eighth embodiment. FIG. 45 is a schematic cross-sectional view showing the overall configuration of a semiconductor light-emitting device 801 according to this embodiment. FIG. 45 shows a cross-section parallel to the stacking direction of the semiconductor light-emitting device 801 and perpendicular to the light propagation direction.

[0149] 45 , a semiconductor light emitting device 801 includes a substrate 10, an n-side cladding layer 520, a hole barrier layer 640, an active layer 550, an electron barrier layer 861, a first p-side cladding layer 571, a second p-side cladding layer 572, and a third p-side cladding layer 573. In this embodiment, the semiconductor light emitting device 801 further includes an n-type buffer layer 12, boundary layers 514, 516, and 570, a first n-side guiding layer 531, a second n-side guiding layer 532, a third n-side guiding layer 533, a p-side guiding layer 762, a first etching stop layer 581, a second etching stop layer 582, a p-type contact layer 592, a current blocking layer 94, an ohmic electrode 96, a p-side electrode 98, and an n-side electrode 99.

[0150] The electron barrier layer 861 according to this embodiment has a concentration of 3.7×10 １８ cm －３ p-type Al doped with p-type impurities (C) having a thickness of 0.020 μm ０．８７ Ga ０．１３ This is an As layer.

[0151] In the semiconductor light emitting device 801 according to this embodiment, the energy of the lower end of the conduction band can be increased by increasing the Al composition ratio in the electron barrier layer 861. The electron barrier layer 861 has a band gap energy higher than that of the first p-side cladding layer 571. More specifically, the electron barrier layer 861 is made of AlGaAs having a band gap energy higher than that of the first p-side cladding layer 571. In this embodiment, the semiconductor light emitting device 801 includes the electron barrier layer 861, which can suppress leakage of electrons from the active layer 550 to the p-side guide layer 762 and the first p-side cladding layer 571. Therefore, the light emitting efficiency of the semiconductor light emitting device 801 can be improved.

[0152] (Other Modifications, etc.) Although the semiconductor light emitting device according to the present disclosure has been described above based on the respective embodiments, the present disclosure is not limited to the above-described respective embodiments.

[0153] For example, although the semiconductor light emitting element is a semiconductor laser element in each of the above embodiments, the semiconductor light emitting element is not limited to a semiconductor laser element. For example, the semiconductor light emitting element may be a superluminescent diode.

[0154] In the first embodiment and the like, the active layer has a multiple quantum well structure having a plurality of well layers, but the configuration of the active layer is not limited to this. For example, the active layer may have a single quantum well structure having a single well layer. In this case, the active layer may be, for example, an undoped (Al ０．６５ Ga ０．３５ ) ０．５１ In ０．４９ Two barrier layers, each being a P layer, and an undoped Ga layer having a thickness of 0.0125 μm, disposed between the two barrier layers. ０．５５ In ０．４５ It may have a single well layer that is a P layer.

[0155] This disclosure also includes forms obtained by applying various modifications to the above embodiments and modifications that a person skilled in the art would conceive, and forms realized by arbitrarily combining the components and functions of the above embodiments and modifications within the scope that does not deviate from the intent of this disclosure.

[0156] The semiconductor light emitting device according to the present disclosure can be used, for example, as a high-output, highly efficient light source.

[0157] 1, 401, 501, 701, 801 Semiconductor light emitting element 10 Substrate 12 n-type buffer layer 14, 90, 414, 490, 514, 516, 570 Boundary layer 20, 420, 520 N-side cladding layer 30, 430 N-side guide layer 40, 140, 240, 340, 440, 540, 640 Hole barrier layer 41a, 141a, 241a, 341a, 441a, 541a, 641a First hole barrier layer 41b, 141b, 241b, 341b, 441b, 541b, 641b Second hole barrier layer 41c, 141c, 241c, 341c, 441c, 541c, 641c Third hole barrier layer 41d, 141d, 241d, 341d, 441d, 541d, 641d Fourth hole blocking layer 41e, 141e, 241e, 341e, 541e, 641e Fifth hole blocking layer 41f, 141f, 241f, 341f Sixth hole blocking layer 42a, 142a, 242a, 342a, 442a, 542a, 642a First intermediate layer 42b, 142b, 242b, 342b, 442b, 542b, 642b Second intermediate layer 42c, 142c, 242c, 342c, 442c, 542c, 642c Third intermediate layer 42d, 142d, 242d, 342d, 542d, 642d Fourth intermediate layer 42e, 142e, 242e, 342e Fifth intermediate layer 50, 450, 550 Active layer 51a, 51b, 51c, 51d, 451a, 451b, 451c, 551a, 551b Barrier layer 52a, 52b, 52c, 452a, 452b, 552a Well layer 60, 460, 762 P-side guide layer 71, 471, 571 First p-side cladding layer 72, 472, 572 Second p-side cladding layer 80 Etching stop layer 92, 592 P-type contact layer 94 Current blocking layer 96 Ohmic electrode 98 P-side electrode 99 N-side electrode 531 First n-side guide layer 532 Second n-side guide layer 533 Third n-side guide layer 561 First p-side guide layer 562 Second p-side guide layer 573 Third p-side cladding layer 581 First etching stop layer 582 Second etching stop layer 761, 861 Electron barrier layer P0 Protrusion R0 Ridge Ru0 Bottom end T0 Groove

Claims

1. A substrate; an n-side cladding layer disposed above the substrate; a hole barrier layer disposed above the n-side cladding layer; an active layer disposed above the hole blocking layer; a p-side cladding layer disposed above the active layer; The hole blocking layer is (Al ｘ１ Ga １－ｘ１ ) ｙ１ In １－ｙ１ a first hole blocking layer consisting of P(0≦x1≦1, 0≦y1≦1); an Al layer disposed above the first hole blocking layer; ｘ２ Ga １－ｘ２ P ｙ２ As １－ｙ２ a first intermediate layer consisting of (0≦x2≦1, 0≦y2<1); (Al ｘ３ Ga １－ｘ３ ) ｙ３ In １－ｙ３ a second hole blocking layer consisting of P(0≦x3≦1, 0≦y3≦1), The average band gap energy of each of the first hole blocking layer and the second hole blocking layer is greater than the average band gap energy of the first intermediate layer. Semiconductor light emitting element.

2. The average refractive index of the second hole blocking layer is greater than the average refractive index of the first hole blocking layer. The semiconductor light emitting device according to claim 1 .

3. Regarding t1 representing the thickness of the first hole blocking layer, t2 representing the thickness of the first intermediate layer, and t3 representing the thickness of the second hole blocking layer, t1=t3≦t2 holds true The semiconductor light-emitting device according to claim 1 or 2.

4. the active layer has a quantum well structure consisting of a plurality of barrier layers and one or more well layers; The refractive index of the first intermediate layer is smaller than the average refractive index of the one or more well layers and larger than the average refractive index of the n-side cladding layer. The semiconductor light-emitting device according to claim 1 or 2.

5. The hole blocking layer is an Al layer disposed above the second hole blocking layer; ｘ４ Ga １－ｘ４ P ｙ４ As １－ｙ４ (0≦x4≦1, 0≦y4<1), and a second intermediate layer (Al ｘ５ Ga １－ｘ５ ) ｙ５ In １－ｙ５ a third hole blocking layer consisting of P(0≦x5≦1, 0≦y5≦1), The average refractive index of the second intermediate layer is greater than the average refractive index of the first intermediate layer. The semiconductor light-emitting device according to claim 1 or 2.

6. The n-side cladding layer is made of (Al ｖ１ Ga １－ｖ１ ) ｗ１ In １－ｗ１ P (0≦v1≦1, 0≦w1≦1), The p-side cladding layer is (Al ｖ２ Ga １－ｖ２ ) ｗ２ In １－ｗ２ P (0≦v2≦1, 0≦w2≦1) The semiconductor light-emitting device according to claim 1 or 2.

7. a p-side guide layer disposed between the active layer and the p-side cladding layer; The n-side cladding layer is made of (Al ｖ１ Ga １－ｖ１ ) ｗ１ In １－ｗ１ P (0≦v1≦1, 0≦w1≦1), The p-side cladding layer is (Al ｖ２ Ga １－ｖ２ ) ｗ２ In １－ｗ２ P (0≦v2≦1, 0≦w2≦1), The p-side guide layer is Al ｖ３ Ga １－ｖ３ P ｗ３ As １－ｗ３ (0≦v3≦1, 0≦w3<1) The semiconductor light-emitting device according to claim 1 or 2.

8. The n-side cladding layer is Al ｖ５ Ga １－ｖ５ P ｗ５ As １－ｗ５ (0≦v5≦1, 0≦w5<1) The p-side cladding layer is Al ｖ６ Ga １－ｖ６ P ｗ６ As １－ｗ６ (0≦v6≦1, 0≦w6<1) The semiconductor light-emitting device according to claim 1 or 2.

9. The average conduction band energy of the second hole blocking layer is smaller than the average conduction band energy of the first hole blocking layer and is equal to or smaller than the average conduction band energy of the layer adjacent to the hole blocking layer above. The semiconductor light emitting device according to claim 7 .

10. an electron barrier layer disposed between the active layer and the p-side cladding layer; The semiconductor light-emitting device according to claim 1 or 2.