Drive circuit for power semiconductor device, and power module

Abstract

During turn-on, a turn-on control period, which is set from a start timing (t0) at which a turn-on command is generated to an end timing (t5) provided within the Miller period of a control electrode voltage (Vg) of a power semiconductor device, is divided into four or more multiple periods (T1 to T4). For a control electrode of the power semiconductor device, a drive capacity (Ig) is switched in each of the multiple periods (T1 to T4), and after the end of the multiple periods (T1 to T4), the control electrode is driven at a power supply voltage (VCC) by a predetermined drive capacity that is greater than or equal to the maximum value of the drive capacities during the respective multiple periods.

Description

Power semiconductor device drive circuit and power module

[0001] The present disclosure relates to a drive circuit for a power semiconductor device and a power module.

[0002] Power semiconductor devices that control large amounts of power are used in power supply circuits that generate AC of a different frequency from DC or AC, or in power conversion devices (inverters) that have such circuits. When power semiconductor devices are used in inverters, etc., it is important to reduce power consumption in order to reduce greenhouse gas emissions.

[0003] A method for reducing energy consumption (loss) in a power semiconductor element by controlling the drive of the power semiconductor element is known. For example, Japanese Patent Application Laid-Open No. 2018-38174 (Patent Document 1) describes a gate drive device that can switch the voltage slope of the rising and falling waveforms of the gate voltage of a switching element in multiple stages.

[0004] Patent Document 1 proposes a gate drive device that includes a plurality of turn-on current sources that switch the voltage slope of the rising waveform of the gate voltage of the switching element in a plurality of stages when the switching element is turned on, a plurality of turn-on switches that drive and control the turn-on current sources, and a plurality of turn-off current sources that switch the voltage slope of the falling waveform of the gate voltage in a plurality of stages when the switching element is turned off, and a plurality of turn-off switches that drive and control the turn-off current sources, so that a first voltage slope in the period corresponding to the mirror region in the rising waveform and the falling waveform is smaller than a second voltage slope in the period not corresponding to the mirror region.

[0005] The gate drive device described in Patent Document 1 makes it possible to make adjustments to suppress increases in surge voltage that occurs when a switching element is turned off and surge current that occurs when the switching element is turned on, or to reduce switching loss, thereby improving device quality.

[0006] JP 2018-38174 A

[0007] The gate drive device of Patent Document 1 performs gate drive that allows the voltage slope of the rising and falling waveforms of the gate voltage of the switching element to be switched in multiple stages, thereby making it possible to suppress increases in surge voltage that occurs when the switching element is turned off and surge current that occurs when the switching element is turned on, or to make adjustments to reduce switching loss.

[0008] However, in Patent Document 1, when adjustment is applied to reduce switching losses while suppressing surge currents generated at turn-on or surge voltages generated at turn-off, it is difficult to simultaneously shorten the dead time and the mirror period of the gate voltage while controlling the current change rate or voltage change rate of the switching element so as to suppress surges and noise at turn-on or turn-off. For this reason, there is concern that adjustment using the gate driver described in Patent Document 1 may make it difficult to reduce both the surges and noise of the switching element and losses.

[0009] The present disclosure has been made to solve such problems, and the purpose of the present disclosure is to reduce both surges, noise, and losses when power semiconductor elements are turned on and off by a drive circuit.

[0010] In one aspect of the present disclosure, there is provided a semiconductor element drive circuit. The drive circuit turns on or off a power semiconductor element in response to a turn-on command or a turn-off command. The drive circuit includes a control unit and a drive unit. The drive unit outputs a control voltage to a control electrode of the power semiconductor element at the time of turn-on and turn-off. The control unit variably controls the drive capacity of the drive unit. The control unit is configured to execute at least one of turn-on control and turn-off control. At the time of turn-on, the turn-on control divides a turn-on control period from a start timing at which the turn-on command is generated to an end timing set within a mirror period of the control electrode voltage of the power semiconductor element into four or more periods, and switches the drive capacity for each of the multiple periods. The turn-off control divides a turn-off control period, which begins with a start timing at which a turn-off command is generated and ends with a predetermined end timing at which the inter-electrode voltage of the power semiconductor element starts to decrease within a period in which the inter-electrode current of the power semiconductor element is decreasing after the end of a mirror period, into four or more periods, and switches the drive capacity for each of the plurality of periods. The drive unit is configured to switch the drive capacity for each of the plurality of periods in accordance with a command from the control unit during each of the turn-on control and the turn-off control, and to drive the power semiconductor element at a predetermined drive capacity that is equal to or greater than the maximum value of the drive capacity for each of the plurality of periods after the end of the plurality of periods.

[0011] According to the present disclosure, by dividing at least one of the turn-off control period and the turn-off control period into four or more periods and applying control to switch the drive capacity, it is possible to reduce both surges, noise, and losses when the power semiconductor element is turned on and off by the drive circuit.

[0012] 12 is a block diagram illustrating a schematic configuration of a drive circuit for a power semiconductor element according to a first embodiment. It is a schematic diagram illustrating an example of a semiconductor element that is turned on and off by the drive circuit shown in FIG. 1. It is a block diagram illustrating an example configuration of the digital control unit and drive unit shown in FIG. 1. It is a diagram illustrating an example configuration of the turn-on period setting circuit shown in FIG. 3. It is a circuit diagram illustrating the configuration of the selection circuit in FIG. 4. It is a waveform diagram illustrating an example operation of the turn-on period setting circuit shown in FIG. 4. It is a circuit diagram illustrating an example configuration of the turn-on drive capacity setting circuit and the turn-on logic operation circuit shown in FIG. 3. It is a waveform diagram illustrating a first control pattern example of turn-on control by the drive circuit for a semiconductor element according to the first embodiment. It is a waveform diagram illustrating a second control pattern example of turn-on control by the drive circuit for a semiconductor element according to the first embodiment. It is a waveform diagram illustrating a first control pattern example of turn-off control by the drive circuit for a semiconductor element according to the first embodiment. It is a waveform diagram illustrating a second control pattern example of turn-off control by the drive circuit for a semiconductor element according to the first embodiment. It is a block diagram illustrating an example configuration of the digital control unit and drive unit of the drive circuit for a power semiconductor element according to a second embodiment. It is a circuit diagram illustrating an example configuration of each selection circuit arranged in the drive circuit shown in FIG. 17 is a block diagram illustrating an example configuration of a digital control unit and a drive unit of a drive circuit for a power semiconductor element according to a third embodiment. FIG. 18 is a block diagram illustrating a schematic configuration of a drive circuit for a power semiconductor element according to a modified example of the third embodiment. FIG. 19 is a block diagram illustrating a schematic configuration of a drive circuit for a power semiconductor element according to a fourth embodiment. FIG. 19 is a waveform diagram illustrating an example of an output signal of a modulation circuit at the time of turn-on. FIG. 19 is a waveform diagram illustrating an example of an output signal of a modulation circuit at the time of turn-off. FIG. 19 is a circuit diagram illustrating an example configuration of the drive unit shown in FIG. 16. FIG. 19 is a block diagram illustrating a first example configuration of a power module according to a fifth embodiment. FIG. 19 is a block diagram illustrating a second example configuration of a power module according to the fifth embodiment. FIG. 19 is a schematic diagram illustrating a first example configuration of a power conversion device according to the fifth embodiment. FIG. 19 is a schematic diagram illustrating a second example configuration of a power conversion device according to the fifth embodiment.

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, identical or corresponding parts in the drawings will be denoted by the same reference numerals, and their description will not be repeated in principle.

[0014] First Embodiment (Configuration of Drive Circuit) Fig. 1 is a block diagram illustrating the schematic configuration of a drive circuit 1000A for a power semiconductor device according to a first embodiment.

[0015] 1 , the drive circuit 1000A generates a gate voltage Vg for controlling the switching (turn-on and turn-off) of the power semiconductor device 3 in accordance with a control signal VIN input to a control input terminal 4. More specifically, the drive circuit 1000A includes a digital control unit 1 and a drive unit 2 that generates the gate voltage Vg based on the digital control signal generated by the digital control unit 1.

[0016] The control signal VIN is a digital signal for indicating the on-period and off-period of the power semiconductor element 3, and is set to, for example, a logical high level (hereinafter referred to as "H level") during the on-period of the power semiconductor element 3, while being set to a logical low level (hereinafter referred to as "L level") during the off-period of the power semiconductor element 3. Therefore, a turn-on command for the power semiconductor element 3 is generated in response to the control signal VIN changing from the L level to the H level, while a turn-off command for the power semiconductor element 3 is generated in response to the control signal VIN changing from the H level to the L level.

[0017] As will be described in detail later, the drive unit 2 divides a turn-on control period (described later) and / or a turn-off control period (described later) of the power semiconductor device 3 into four or more periods based on the digital control signal generated by the digital control unit 1, and further switches the drive capacity of the drive unit 2 for each of the multiple periods to generate the gate voltage Vg. Furthermore, after the end of the turn-on control period and / or the turn-off control period divided into four or more periods, the drive unit 2 generates the gate voltage Vg with a drive capacity that is equal to or greater than the maximum value of the drive capacity in each of the four or more periods.

[0018] 2 shows an example of a power semiconductor element 3 that is turned on or off by the drive circuit 1000A. The power semiconductor element 3 has a switching element 31 and a freewheel diode 32. In the example of FIG. 2, the switching element 31 is configured by an IGBT (Insulated Gate Bipolar Transistor) having a gate (G) that is a control electrode, a collector (C) that is a first electrode, and an emitter (E) that is a second electrode.

[0019] A node Ng corresponding to the output terminal of the driver 2 is electrically connected to the gate of the switching element 31, and the driver 2 drives the gate to generate a gate voltage Vg. By changing the driving capacity of the driver 2, the slope (voltage change rate) at which the gate voltage Vg changes can be adjusted.

[0020] Hereinafter, the gate-emitter voltage (Vge), which is the voltage difference between the gate (G) and the emitter (E), will be simply referred to as the gate voltage Vg. The voltage difference between the collector (E) and the emitter (C) will be referred to as the collector-emitter voltage Vce, and the current flowing from the collector (C) to the emitter (E) will be referred to as the collector current Ic. The current that charges and discharges the gate (G) will be referred to as the gate current Ig. The gate current Ig is a charging current with a positive value (Ig>0) and a discharging current with a negative value (Ig<0).

[0021] The gate voltage Vg corresponds to an example of a "control voltage," the gate current corresponds to an example of a "drive current," the collector current Ic corresponds to an example of an "interelectrode current," and the collector-emitter voltage Vce corresponds to an example of an "interelectrode voltage."

[0022] In addition to IGBTs, other switching elements such as MOS-FETs (Metal Oxide Semiconductor Field Effect Transistors) and bipolar transistors can also be used as the switching elements 31 in the power semiconductor elements 3. When a MOS-FET is used, the drain (D) and source (S) serve as the first and second electrodes instead of the collector (C) and emitter (E). When a bipolar transistor is used, the base (B) serves as the control electrode.

[0023] Next, a description will be given of an example of the configuration of the digital control unit 1 and the drive unit 2. Fig. 3 is a block diagram illustrating an example of the configuration of the digital control unit 1 and the drive unit 2 shown in Fig. 1.

[0024] The digital control unit 1 includes a clock (CLK) circuit 14, an inversion circuit 15, a turn-on period setting circuit 11a, a turn-off period setting circuit 11b, a turn-on drive capacity setting circuit 12a, a turn-off drive capacity setting circuit 12b, a turn-on logic operation circuit 13a, and a turn-off logic operation circuit 13b.

[0025] The turn-on period setting circuit 11a uses the control signal VIN and the clock signal CLK from the clock circuit 14 to generate a digital control signal for defining the first to nth periods obtained by dividing the turn-on control period into a predetermined number of n periods (n: an integer of 4 or greater).

[0026] The turn-on drive capacity setting circuit 12a outputs a digital control signal corresponding to a drive capacity command value for each of the first to n-th periods into which the turn-on control period defined by the turn-on period setting circuit 11a is divided.

[0027] Similarly, the turn-off period setting circuit 11b receives an inverted signal of the control signal VIN from the inverting circuit 15 and a clock signal CLK from the clock circuit 14, and outputs a digital control signal for defining the first to nth periods obtained by dividing the turn-off control period into n predetermined periods (n: an integer of 4 or more).

[0028] The turn-off drive capacity setting circuit 12b outputs a digital control signal corresponding to a drive capacity command value for each of the first to n-th periods into which the turn-off control period defined by the turn-off period setting circuit 11b is divided.

[0029] The turn-on period setting circuit 11a includes a counter circuit 110a and first to n-th period setting circuits 111a to 11na. For example, when n=4, four period setting circuits, namely, first to fourth period setting circuits 111a to 114a, are provided. The turn-on period setting circuit 11a operates in response to a turn-on command in which the control signal VIN changes from L level to H level. In response to the turn-on command, the first to n-th period setting circuits 111a to 11na use clock pulses output from the counter circuit 110a to output pulse signals P1a to Pna that are set to H level during first to n-th periods, respectively, which are obtained by dividing the turn-on control period into a predetermined number of n periods.

[0030] The turn-off period setting circuit 11b receives the control signal VIN inverted by the inverter circuit 15, and therefore operates in response to a turn-off command in which the control signal VIN changes from H level to L level. Therefore, the turn-off period setting circuit 11b can have the same configuration as the turn-on period setting circuit 11a. The turn-off period setting circuit 11b outputs pulse signals P1b to Pnb that are set to H level in each of the first to nth periods obtained by dividing the turn-off control period into n predetermined periods.

[0031] The turn-on drive capacity setting circuit 12a includes a first period drive capacity setting circuit 121a to an nth period drive capacity setting circuit 12na. The first period drive capacity setting circuit 121a to the nth period drive capacity setting circuit 12na receive digital control signals (pulse signals P1a to Pna) from the first period setting circuit 111a to the nth period setting circuit 11na, respectively, and generate digital control signals for setting drive capacity for each of the first to nth periods obtained by dividing the turn-on control defined by the turn-on period setting circuit 11a.

[0032] The turn-off drive capacity setting circuit 12b has the same configuration as the turn-on drive capacity setting circuit 12a, and generates digital control signals for setting the drive capacity for each of the first to nth periods obtained by dividing the turn-off control period defined by the turn-off period setting circuit 11b.

[0033] The turn-on logic operation circuit 13a receives the digital control signals output from the first period drive capacity setting circuit 121a to the nth period drive capacity setting circuit 12na of the turn-on drive capacity setting circuit 12a and the control signal VIN, and generates a digital control signal for the turn-on drive unit 21a of the drive unit 2.

[0034] The turn-off logic operation circuit 13b has the same configuration as the turn-on logic operation circuit 13a, and receives the n digital control signals output from the turn-off drive capacity setting circuit 12b and an inverted signal of the control signal VIN by the inversion circuit 15, to generate a digital control signal for the turn-off drive unit 21b of the drive unit 2.

[0035] The driver 2 includes a turn-on driver 21a and a turn-off driver 21b. The turn-on driver 21a has k (k is an integer equal to or greater than n) P-type transistors 211a to 21ka connected in parallel between a power supply node that supplies a power supply voltage VCC for turning on the switching element 31 and a node Ng. The on / off of each of the P-type transistors 211a to 21ka is controlled by a digital control signal from the turn-on logic operation circuit 13a. Each of the P-type transistors 211a to 21ka can be configured using P-type transistors (e.g., P-MOS transistors) with equivalent current supply capabilities.

[0036] The turn-on driver 21a drives the node Ng, i.e., the gate (control electrode) of the power semiconductor element 3 (switching element 31), with the power supply voltage VCC by the turned-on transistor among the P-type transistors 211a to 21ka. As a result, when turned on, the node Ng is charged by a gate current Ig that depends on the number Na of the turned-on P-type transistors 211a to 21ka, and the gate voltage Vg rises, turning on the power semiconductor element 3 (switching element 31). In other words, the drive capacity when turned on can be controlled by controlling the number Na of the turned-on P-type transistors 211a to 21ka.

[0037] The turn-on logic operation circuit 13a generates digital control signals for controlling the on / off of the P-type transistors 211a to 21ka in accordance with the drive capabilities for each of the first to n-th periods obtained by dividing the turn-on control period into n periods, which are set by the turn-on drive capability setting circuit 12a. By setting k≧n, it is possible to set different drive capabilities for each of the first to n-th periods.

[0038] The turn-off driver 21b has k (k is an integer equal to or greater than n) N-type transistors 211b to 21kb connected in parallel between a power supply node that supplies a ground voltage GND for turning off the switching element 31 and a node Ng. The on / off of each of the N-type transistors 211b to 21kb is controlled by a digital control signal from the turn-off logic operation circuit 13b. Each of the N-type transistors 211b to 21kb can be configured using an N-type transistor (e.g., an N-MOS transistor) with the same current supply capability. Note that a negative voltage can be used instead of the ground voltage GND as the voltage for turning off the switching element 31.

[0039] The turn-off driver 21b drives the node Ng, i.e., the gate (control electrode) of the power semiconductor element 3 (switching element 31), with the ground voltage GND by the transistors that are turned on among the N-type transistors 211b to 21kb. As a result, when turning off, the node Ng is discharged by a gate current Ig that depends on the number Nb of the N-type transistors 211b to 21kb that are turned on, and when the gate voltage Vg drops, the power semiconductor element 3 (switching element 31) is turned off. In other words, the driving capability at the time of turning off can be controlled by controlling the number Nb of the N-type transistors 211b to 21kb that are turned on.

[0040] The turn-off logic operation circuit 13b generates digital control signals that control the on / off of the N-type transistors 211b to 21kb in accordance with the drive capabilities set by the turn-off drive capability setting circuit 12b for each of the first to nth periods into which the turn-off control period is divided into n parts.

[0041] FIG. 4 is a circuit diagram illustrating an example configuration of the turn-on period setting circuit 11a. As shown in FIG. 4, the counter circuit 110a includes a plurality of cascaded D flip-flop circuits 1101 to 110m (m: an integer equal to or greater than n), a plurality of inverter circuits 1111 to 111m, and a NOR circuit 1120. Note that m is determined so as to ensure the time length required for the turn-on control period, which is predetermined according to the characteristics of the switching element 31. The resolution of the time lengths of the first to nth periods is determined by the period of the clock signal CLK input from the clock circuit 14 to the counter circuit 110a. Furthermore, the number (m) of the D flip-flop circuits 1101 to 110m is determined to be equal to or greater than the value (number of clock cycles) obtained by dividing the sum of the time lengths of the first to nth periods, which corresponds to the time length of the turn-on control period, by the period of the clock signal CLK.

[0042] In the counter circuit 110a, output signals Q1 to Qm of the D flip-flop circuits 1101 to 110m are input to an OR circuit 1120 via inversion circuits 1111 to 111m. The output signal of the OR circuit 1120 is input to the D terminal of the first-stage D flip-flop circuit 1101. In each of the D flip-flop circuits 1101 to 110m, an inverted signal of the control signal VIN is input to the respective reset terminal (RST), and a clock signal CLK from the clock circuit 14 (FIG. 3) is input to the respective clock terminal (CLK).

[0043] 6 shows an example of the operating waveforms of the turn-on period setting circuit 11a shown in FIG. 6. As shown in FIG. 6, the counter circuit 110a operates in response to the input of the control signal VIN and the clock signal CLK having a constant period, starting from the clock cycle following time t0 when the turn-on command is generated by the control signal VIN. When the counter circuit 110a operates, the output signals Q1 to Qm of the D flip-flop circuits 1101 to 110m become pulse signals having sequentially high-level periods each corresponding to one cycle of the clock signal CLK. On the other hand, during the period when the control signal VIN is low, each of the D flip-flop circuits 1101 to 110m is reset, and each of the output signals Q1 to Qm is fixed at low.

[0044] 4 again, the first period setting circuit 111a has a plurality of selection circuits 11101 to 1110m, a plurality of AND circuits 11111 to 1111m, and an OR circuit 11120. Since the first period setting circuit 111a to the n-th period setting circuit 11na each have the same configuration, an example configuration of the first period setting circuit 111a is shown in FIG.

[0045] 5 shows the configuration of each of the multiple selection circuits 11101 to 1110m. As shown in FIG. 5, the selection circuit SLC (which collectively refers to the selection circuits 11101 to 1110m) has a switch SW that selects and outputs either the power supply voltage VCC or the ground voltage GND in a fixed manner. The switch SW can be configured, for example, by a transistor whose on / off state is fixed by a wire connection to its gate.

[0046] Each selection circuit 1110 holds either "selected" or "unselected." When "selected" is held, the switch SW outputs the power supply voltage VCC (H level). On the other hand, when "unselected" is held, the switch SW outputs the ground voltage GND (L level).

[0047] 4, AND circuits 11111 to 1111m receive output signals Q1 to Qm from counter circuit 110a (D flip-flop circuits 1101 to 110m) and signals from selection circuits 11101 to 1110m. Selection circuits 11101 to 1110m are programmed to hold "selected" data for output signals Q1 to Qm corresponding to m clock cycles shown in FIG. 6 during a period included in first period T1, and to hold "non-selected" data during other periods.

[0048] The OR circuit 11120 receives the output signals of the AND circuits 11111 to 1111m, and outputs a pulse signal P1a that is set to H level during the first period T1 as a digital control signal.

[0049] The second period setting circuit 112a to the n-th period setting circuit 11na are configured similarly to the first period setting circuit 111a and output pulse signals P2a to Pna, respectively. The pulse signal P2a is set to H level during the second period T2, and the pulse signal Pna is set to H level during the n-th period Tn.

[0050] Referring again to FIG. 6, in the operation example of FIG. 6, from the next clock cycle (time tc1 to tc2) in which turn-on is instructed by the control signal VIN, a first period T1 (time tc1 to tc3) and a second period T2 (time tc3 to tc5) are provided consecutively, each consisting of two clock cycles.

[0051] In this case, in the first period setting circuit 111a, selection circuits 11101 and 11102 for selecting output signals Q1 and Q2 are programmed to hold "selection" as their retention data, while the other selection circuits 11103 to 1110m are programmed to hold "non-selection" as their retention data. Also, in the second period setting circuit 112a, selection circuits 11103 and 11104 for selecting output signals Q3 and Q4 are programmed to hold "selection" as their retention data, while the other selection circuits 11101, 11102, etc. are programmed to hold "non-selection" as their retention data.

[0052] As a result, the pulse signal P1a output from the first period setting circuit 111a is generated as an OR signal of the output signals Q1 and Q2, and the pulse signal P2a output from the second period setting circuit 112a is generated as an OR signal of the output signals Q3 and Q4.

[0053] As a result, it can be understood that by adjusting the data held by the selection circuits 11101 to 1110m in each of the first period setting circuit 111a to the nth period setting circuit 11na as to whether they are "selected" or "non-selected," it is possible to set each of the first period T1 to the nth period Tn as n consecutive periods starting from the turn-on command, each having an arbitrary period length that is an integer multiple of the cycle of the clock signal CLK. In other words, the turn-on control period can be set to an arbitrary period length and divided into n periods at any timing depending on the data held by the selection circuits 11101 to 1110m in each of the first period setting circuit 111a to the nth period setting circuit 11na.

[0054] The turn-off period setting circuit 11b can also have the same configuration as the turn-on period setting circuit 11a shown in Fig. 4. As a result, the turn-off period setting circuit 11b operates in response to a turn-off command in which the control signal VIN changes from H level to L level, and the turn-off control period can also be set to an arbitrary period length and divided into n portions at arbitrary timing according to the data held in each selection circuit (Fig. 5) in the turn-off period setting circuit 11b.

[0055] Next, a specific example of the circuit configuration of the turn-on drive capacity setting circuit 12a and the turn-on logic operation circuit 13a shown in FIG. 3 will be described with reference to FIG.

[0056] 7, the turn-on drive capability setting circuit 12a includes a first-period drive capability setting circuit 121a to an n-th period drive capability setting circuit 12na. The first-period drive capability setting circuits 121a to 12na have the same configuration, so Fig. 7 shows a specific example of the configuration of the first-period drive capability setting circuit 121a.

[0057] The first-period drive capacity setting circuit 121a has a plurality of selection circuits 1201 to 120k and a plurality of AND circuits 1211 to 121k. As described above, k is the number of parallel-connected P-type transistors included in the turn-on driver 21a of the driver 2, and k determines the resolution for adjusting the drive capacity. For example, if k=8, the drive capacity can be switched in eight stages.

[0058] Each of the selection circuits 1201 to 120k is configured in the same manner as the selection circuits 11101 to 1110m in Fig. 4. That is, the configuration example in Fig. 5 can be applied.

[0059] The AND circuits 1211 to 121k receive the pulse signal P1a and the output signals of the selection circuits 1201 to 120k. Therefore, while the pulse signal P1a is at L level, the output signals of the AND circuits 1211 to 121k are set to L level. On the other hand, while the pulse signal P1a is at H level, the output signals of the AND circuits 1211 to 121k are set to H level or L level depending on the data held in the selection circuits 1201 to 120k.

[0060] The second-period drive capability setting circuit 122a to the n-th period drive capability setting circuit 12na are configured similarly to the first-period drive capability setting circuit 121a, and receive the pulse signals P2a to Pna, respectively, which cause the first-period drive capability setting circuit 121a to the n-th period drive capability setting circuit 12na to output output signals from the AND circuits 1211 to 121k, respectively.

[0061] The turn-on logic operation circuit 13 a has a plurality of NOR circuits 1301 to 130 k and a flip-flop circuit 1310 .

[0062] A control signal VIN and a pulse signal Pna that defines an n-th period Tn are input to the flip-flop circuit 1310. The output signal of the flip-flop circuit 1310 is set to an H level only during the period after the n-th period Tn during which the control signal VIN is at an H level. On the other hand, the output signal of the flip-flop circuit 1310 is set to an L level during each of the first period T1 to the n-th period Tn during which the control signal VIN is at an H level and during the L-level period of the control signal VIN.

[0063] The NOR circuit 1301 receives (k+1) input signals, which are the output signals of the AND circuits 1211 of the first-period drive capacity setting circuit 121a to the n-th-period drive capacity setting circuit 12na and the output signal of the flip-flop circuit 1310. The output signal of the NOR circuit 1301 is set to L level when any of the (k+1) signals is set to H level. At this time, the P-type transistor 211a, which receives the output signal of the NOR circuit 1301 at its gate, is turned on. On the other hand, when all of the (k+1) input signals are set to L level, the output signal of the NOR circuit 1301 is set to H level, and the P-type transistor 211a is turned off. Similarly, the on / off of the P-type transistors 212a to 21ka is controlled by the output signals of the NOR circuits 1302 to 130k.

[0064] As a result, during the L level period of the control signal VIN, the output signals of the AND circuits 1211 to 121k from the first period drive capacity setting circuit 121a to the nth period drive capacity setting circuit 12na are at L level, and the output signal of the flip-flop circuit 1310 is at L level, so that the output signals of the NOR circuits 1301 to 130k are all set to H level, thereby turning off all of the P-type transistors 211a to 21ka, and preventing the node Ng from being driven by the power supply voltage VCC.

[0065] In contrast, during the first period T1 of the H level period of the control signal VIN, NOR circuits 1301-130k output an L level signal when an output signal from a selection circuit that holds "selection" is input, in accordance with the data ("selected" / "non-selected") held by selection circuits 1201-120k of first period drive capacity setting circuit 121a. Therefore, at least some of P-type transistors 211a-21ka are turned on in accordance with the number of selection circuits 1201-120k that hold "selection." As a result, node Ng is driven to power supply voltage VCC with a drive capacity corresponding to the number Na of P-type transistors 211a-21ka that are turned on.

[0066] In each of the second period T2 to the nth period Tn, the number Na of P-type transistors 211a to 21ka that are turned on can be adjusted as desired depending on the number of selection circuits that hold "selection" in the second-period drive capacity setting circuit 122a to the nth-period drive capacity setting circuit 121n. Therefore, it can be understood that the drive capacity in each of the first period T1 to the nth period Tn, into which the turn-on control period is divided into n periods, can be set as desired depending on the data held in the selection circuits 1201 to 120k in the first-period drive capacity setting circuit 121a to the nth-period drive capacity setting circuit 121n.

[0067] Furthermore, after the end of the n-th period Tn during which the control signal VIN is at H level, the output signal of the flip-flop circuit 1310 goes to H level, and all output signals of the NOR circuits 1301 to 130k go to L level. As a result, after the end of the n-th period Tn, the node Ng is driven to the power supply voltage VCC with the driving capability of all of the P-type transistors 211a to 21ka being turned on.

[0068] Note that, after the end of the nth period Tn during which the control signal VIN is at H level, the number Na of P-type transistors 211a to 21ka that are turned on is determined by the number of NOR circuits 1301 to 130k to which the output signal of flip-flop circuit 1310 is input. That is, in the example of Figure 6, the output signal of flip-flop circuit 1310 is input to all of NOR circuits 1301 to 130k, but it is also possible to configure so that the output signal of flip-flop circuit 1310 is input to only some of NOR circuits 1301 to 130k. However, as will be described later, after the end of the nth period Tn, the drive capacity is set to be equal to or greater than the maximum value of the drive capacity in each of the first period T1 to the nth period Tn. Therefore, the wiring between the output side of the flip-flop circuit 1310 and the input side of the NOR circuits 1301 to 130k is designed so that after the end of the nth period Tn, the number of P-type transistors that are turned on is equal to or greater than the maximum number Na of P-type transistors that are turned on in each of the first period T1 to the nth period Tn.

[0069] The turn-off drive capacity setting circuit 12b and the turn-off logic operation circuit 13b can also have circuit configurations similar to those of the turn-on drive capacity setting circuit 12a and the turn-on logic operation circuit 13a in Figure 6. However, because the turn-off drive unit 21b of the drive unit 2 is composed of k N-type transistors 211b to 21kb connected in parallel, the logic level of the output signal of the turn-off logic operation circuit 13b must be inverted from that of the turn-on logic operation circuit 13a. For example, the turn-off logic operation circuit 13b can be configured by replacing the NOR circuits 1301 to 130k in the turn-on logic operation circuit 13a (Figure 7) with k OR circuits.

[0070] As a result, the drive capability for each of the first period T1 to the nth period Tn, which are obtained by dividing the turn-off control period into n periods, can be set arbitrarily using the data held in the k selection circuits, as in Figure 7. Furthermore, after the end of the nth period Tn during which the control signal VIN is at low level, the drive capability of all of the N-type transistors 211b to 21kb of the turn-off driver 21b can drive the node Ng to the ground voltage GND. Thus, even after the end of the n-divided turn-off control period and the nth period Tn during which the control signal VIN is at low level, the drive capability to the ground voltage GND can be adjusted in the same way as after the end of the turn-on control period and the nth period Tn described in Figure 6.

[0071] (Driving Capacity Control at Turn-On) Next, an example of controlling the driving capacity at the time of switching by the driving circuit for the power semiconductor device according to the first embodiment (an example of a control pattern) will be described.

[0072] 8 and 9 show examples of first and second control patterns, respectively, for turn-on control. The horizontal axis in each of FIGS. 8 and 9 represents time, and the vertical axis represents the control signal VIN, as well as the gate voltage Vg, gate current Ig, collector current Ic, and collector-emitter voltage Vce of switching element 31 (FIG. 2). In FIGS. 8 and 9, the gate current Ig is a positive value or 0 (Ig≧0).

[0073] 8 and 9, the solid lines indicate the switching waveforms for each of the first to fourth periods T1 to T4 and the control pattern in which the gate drive capacity is switched after the end of the fourth period T4, where n=4. As a comparative example, the dotted lines indicate the switching waveforms when turning on with a constant drive capacity.

[0074] Referring to FIG. 8, a typical turn-on operation according to a comparative example (dotted line) will be described first. At time t0, when the control signal VIN changes from low to high to generate a turn-on command, charging of the gate begins at a constant drive capacity. The period from time t0 to t1 corresponds to the delay time of the drive circuit 1000A, so the gate voltage Vg does not rise above the ground voltage GND (0). After time t1, the gate is further charged by the gate current Ig, which depends on the drive capacity, and the gate voltage Vg rises. With a constant drive capacity, the gate current gradually decreases according to the difference between the power supply voltage VCC and the gate voltage.

[0075] At time t2, when the gate voltage Vg rises to the threshold voltage Vth of the switching element 31, a collector current Ic is generated. After time t2, the collector current Ic rises in response to the rise in the gate voltage Vg, while the collector-emitter voltage Vce gradually falls.

[0076] Thereafter, as the gate continues to be charged, the collector current Ic reaches a steady-state on-current Ion, and the collector-emitter voltage Vce decreases under a constant gate voltage Vg, creating a Miller period. During the Miller period, the collector current Ic generates a surge current and then settles to the steady-state on-current Ion.

[0077] When the mirror period ends (time t7), the gate voltage Vg rises to the power supply voltage VCC. When gate charging ends, the gate current Ig becomes zero and the collector-emitter voltage Vce becomes the collector-emitter saturation voltage.

[0078] In the first control pattern example of Figure 8, when a turn-on command is generated by the control signal VIN at time t0, a first period T1 to a fourth period T4 are set according to the elapsed time from time t0 (the number of cycles of the clock signal CLK) in accordance with the data held in the selection circuits (Figure 5) in the first period setting circuit 111a to the fourth period setting circuit 114a.

[0079] The first period T1 is set to the period from time t0 when the turn-on command is generated to time t2 when the gate voltage Vg rises to the threshold voltage Vth. During the first period T1, a first driving force (ON number Na = N1a) is set and the gate is charged. After time t1 when the delay time of the drive circuit 1000A has elapsed, the gate is charged by a gate current Ig1 that depends on the ON number N1a, and the gate voltage Vg rises from 0 to Vth at a slope according to the gate current Ig1 that corresponds to the ON number N1a. Time t0 corresponds to the "first time point," and time t2 corresponds to the "second time point."

[0080] The second period T2 is set to the period from time t2 to time t3 after the gate voltage Vg enters the mirror period. In other words, time t3 is set to the timing after the start of the mirror period. In the second period T2, the second driving force (ON number Na=N2a) is set, and the gate is charged by the gate current Ig2. The gate voltage Vg rises at a slope that follows the gate current Ig2 until the mirror period begins. Time t3 corresponds to the "third point in time."

[0081] The third period T3 is set to the period from time t3 to time t4 within the mirror period during which a surge current of the collector current Ic is generated. During the third period T3, a third driving force (ON number Na=N3a) is set, and gate current Ig3 is supplied to the gate. During the mirror period, the gate voltage Vg does not increase but remains constant. Time t4 corresponds to the "fourth point in time."

[0082] The fourth period T4 is set from time t4 to time t5, which is set after time t4 within the mirror period. This time t5 is set, for example, within the mirror period and within a section where a voltage change occurs in the collector-emitter voltage Vce (i.e., within a section where Vce>0). Time t5 corresponds to the "end timing" of the turn-on control period. During the fourth period T4, a fourth driving force (ON number Na=N4a) is set, and gate current Ig4 is supplied to the gate. Because the fourth period T4 is within the mirror period, the gate voltage Vg is maintained constant.

[0083] After the fourth period T4 ends, that is, from time t5 onwards, the maximum driving force (the number of ONs Na=Namax) is set and the gate current Igmax is supplied to the gate. From time t6 onwards, when the mirror period ends, the gate current Ig gradually decreases even at the maximum driving force, eventually reaching Ig=0. The maximum driving force is set to be equal to or greater than the maximum value of the first to fourth driving forces. That is, the number of ONs Namax is set to be equal to or greater than the maximum value of N1a to N4a (Namax≧max(N1a, N2a, N3a, N4a)). For example, as in the example of FIG. 7, Namax=k.

[0084] The switching timings (times t2 to t5) between the first period T1 to the fourth period T4 can be determined in advance from actual measurements or simulation results of the operating waveforms when the power semiconductor element 3 (switching element 31) is turned on. Then, by converting the elapsed time from time t0 to times t2 to t5 into the number of clocks of the clock signal CLK, the data held in the selection circuits (FIG. 5) in the first period setting circuit 111a to the fourth period setting circuit 114a can be determined.

[0085] Furthermore, as described above, the drive capabilities (numbers of ONs N1a to N4a, Namax) during the first period T1 to the fourth period T4 and after the end of the fourth period can be determined arbitrarily by the data held in the selection circuits (FIG. 5) in the first period drive capability setting circuit 121a to the nth period drive capability setting circuit 12na (n=4) and the connection mode between the input sides of the NOR circuits 1301 to 130k and the output side of the flip-flop circuit 1310 in the turn-on logic operation circuit 13a.

[0086] As described above, the turn-on control by the drive circuit for a power semiconductor device according to the first embodiment is characterized in that the period from the turn-on start timing (time t0) at which a turn-on command is generated to the end timing (time t5) within the mirror period is defined as a "turn-on control period," which is a period subject to drive capacity control, and the drive capacity is switched between the first period T1 to the nth period Tn (n≧4) obtained by dividing the turn-on control period into four or more periods. Note that although an example where n=4 is described in FIGS. 8 and 9, it is also possible to divide at least one of the first period T1 to the fourth period T4 into five or more periods and switch the drive capacity.

[0087] In the first control pattern example of the turn-on control, the driving capabilities during the first period T1 to the fourth period T4 and after the end of the fourth period are set as follows.

[0088] The driving capability in the first period T1 is set to be equal to that in the comparative example. If the driving capability in the first period T1 is increased to increase the gate current Ig1, the dead time can be shortened.

[0089] The drive capacity during the second period T2 is set so that the gate current Ig2 is greater than the gate current Ig (dotted line) of the comparative example during the same period (corresponding to times t2 to t3). This increases the current change rate (dIc / dt) of the collector current Ic compared to the comparative example, thereby reducing losses during the second period T2. Note that in the example of FIG. 8 , Ig1 > Ig2 between the first period T1 and the second period T2. However, even if the ON numbers N1a and N2a are the same, as in the comparative example, the gate current Ig decreases after time t2 (Vg = Vth) for the same drive capacity, which may result in Ig1 > Ig2.

[0090] The driving capability during the third period T3 is set so that the gate current Ig3 is smaller than the gate current Ig (dotted line) of the comparative example during the same period (corresponding to times t3 to t4), thereby reducing the surge current generated in the collector current Ic.

[0091] The drive capacity in the fourth period is set so that the gate current Ig4 is larger than the gate current Ig (dotted line) in the comparative example during the same period (corresponding to times t4 to t5). This increases the voltage change rate (dVce / dt) of the collector-emitter voltage Vce, thereby reducing the loss that occurs in the fourth period T4.

[0092] After the fourth period T4 ends, increasing the gate current Igmax increases the voltage change rate (dVc / dt) of the collector-emitter voltage Vce, shortening the mirror period and thereby reducing losses that occur after the fourth period T4. Therefore, the gate current Igmax is generated at or above the maximum value of the gate currents Ig1 to Ig4, and preferably at the maximum driving capability of the driver 2 (for example, the number of ON gates Namax = k).

[0093] Thus, in the first control pattern example during turn-on by the drive circuit for a power semiconductor device according to embodiment 1, the "turn-on control period" defined above is divided into four periods, and the drive capabilities are switched so that the relationship Igmax > Ig1 > Ig2 > Ig4 > Ig3 holds among the gate currents Ig1 to Ig4 and Igmax. This shortens the dead time (time t0 to t1) from when the turn-on command is generated until the gate voltage Vg rises and the collector current begins to flow, compared to the comparative example in which turn-on is performed at a constant drive capability. This reduces losses during turn-on and reduces surge currents occurring in the collector current Ic. Note that in the comparative example of FIG. 8 , for ease of explanation, the gate current Ig1 is set to the same as in the conventional example. However, the dead time can be shortened by increasing Ig1 compared to the conventional example. The period from time t0 to t1 is a delay time generated by the drive circuit 1000A and is unrelated to the effect of embodiment 1.

[0094] 8, the gate current Ig4 in the fourth period T4 can be set lower than the gate current Ig (dotted line) in the comparative example for the same period, provided that Igmax > Ig1 > Ig2 > Ig4 > Ig3 is satisfied. In this way, while the loss in the fourth period T4 increases, the noise generated by the voltage change rate (dVc / dt) of the collector-emitter voltage Vce can be reduced more than in the comparative example.

[0095] An example of the second control pattern at turn-on is shown in Fig. 9. In Fig. 9, a comparative example similar to Fig. 8 is indicated by the same dotted lines as Fig. 8, and the operating waveforms in the first control pattern (Fig. 8) are further indicated by dotted lines spaced closer together than in the comparative example. The operating waveforms in the second control pattern are indicated by solid lines in Fig. 9.

[0096] In the second control pattern shown in Fig. 9, the first period T1 to the fourth period T4 are provided in the same manner as in Fig. 8. In the second control pattern, the settings of the gate currents Ig1 to Ig4 and Igmax are different from those in the first control pattern (Fig. 8).

[0097] Specifically, in the second control pattern, the drive capabilities are switched so that the relationship Igmax > Ig1 > Ig4 > Ig2 > Ig3 is established among the gate currents Ig1 to Ig4 and Igmax. As can be seen from a comparison between Fig. 9 and Fig. 8, in the second control pattern, compared to the first control pattern, the gate current Ig2 in the second period T2 is set small, while the gate current Ig4 in the fourth period T4 is set large.

[0098] Like the first control pattern, the second control pattern at turn-on also shortens the dead time compared to the comparative example in which turn-on is performed at a constant driving capacity, reduces the surge current generated in the collector current Ic, and increases the voltage change rate (dVc / dt) of the collector-emitter voltage Vce, thereby reducing losses at turn-on.

[0099] Furthermore, compared to the first control pattern, noise generated by the current change rate (dIc / dt) of the collector current Ic can be reduced in the second period T2. Furthermore, by increasing the voltage change rate (dVc / dt) of the collector-emitter voltage Vce in the fourth period T4, the loss reduction effect can be enhanced.

[0100] (Driving Capacity Control at Turn-Off) Figures 10 and 11 show first and second control pattern examples at turn-off, respectively. The horizontal axis in Figures 10 and 11 is the time axis, as in Figures 8 and 9, and the vertical axis represents the control signal VIN, gate voltage Vg, gate current Ig, collector current Ic, and collector-emitter voltage Vce, as in Figures 8 and 9. Note that in Figures 10 and 11, the gate current Ig is negative or 0 (Ig≦0). Therefore, in the figures, the lower Ig is located, the greater the driving capacity, i.e., the greater the gate current (absolute value).

[0101] 10 and 11, the solid lines show the switching waveforms in the control pattern in which the gate drive capacity is switched during each of the first to fourth periods T1 to T4 and after the end of the fourth period T4, with n=4. As a comparative example, the dotted lines show the switching waveforms when the gate is turned off with a constant drive capacity.

[0102] Referring to FIG. 10 , a typical turn-off operation for a comparative example (dotted line) will be described first. At time t10, when the control signal VIN changes from H level to L level and a turn-off command is generated, gate discharge begins at a constant drive capacity. Between times t10 and t11, the gate voltage Vg does not decrease from the power supply voltage VCC due to delays in the drive circuit 1000A. After time t11, the gate current Ig (absolute value) increases to a current value dependent on the drive capacity, and the gate is discharged, causing the gate voltage Vg to decrease. When the gate voltage Vg decreases and the mirror period begins, the collector-emitter voltage Vce gradually increases, and the collector current Ic gradually decreases from the on-current Ion.

[0103] Then, as the gate discharge progresses, from time t16 within the mirror period, the collector-emitter voltage Vce rises sharply, and the rate at which the collector current Ic falls also increases.

[0104] When the mirror period ends (time t18), the gate voltage Vg starts to decrease toward the ground voltage GND (0), and the gate current Ig starts to increase toward I0, which was the level before time t11. Accordingly, the collector current Ic decreases toward zero, and the collector-emitter voltage Vce increases, accompanied by the generation of a surge voltage. When the gate voltage Vg reaches 0, the collector-emitter voltage Vce settles to its steady-state value during off-state.

[0105] In the first control pattern example of FIG. 10, when the control signal VIN changes from H level to L level at time t10 to generate a turn-off command, a first period T1 to a fourth period T4 are set in accordance with the elapsed time from time t10 (the number of cycles of the clock signal CLK) based on the data held in the selection circuit (FIG. 5) in the turn-off period setting circuit 11b, which corresponds to the selection circuits in the first period setting circuit 111a to the fourth period setting circuit 114a.

[0106] The first period T1 is set to the period from time t10 when a turn-off command is generated by the control signal VIN to time t12 after the gate voltage Vg enters the mirror period. Time t10 corresponds to the "first point in time," and time t12 corresponds to the "second point in time."

[0107] During the first period T1, a first driving force (ON number Nb=N1b) is set and the gate is discharged. After time t11 when the delay time of the drive circuit 1000A has elapsed, the gate is discharged by a gate current Ig1 that depends on the ON number N1b, and the gate voltage Vg decreases from the power supply voltage VCC at a slope according to the gate current Ig1 that corresponds to the ON number N1b.

[0108] The second period T2 is the period from time t12 to time t13, which is set before the end of the mirror period of the gate voltage Vg. During the second period T2, the second driving force (the number N2b of ON N-type transistors 211b to 21kb) is set, and the gate is discharged by the gate current Ig2. The gate voltage Vg is maintained constant during the mirror period. Time t13 corresponds to the "third point in time."

[0109] The third period T3 is set from time t13 to time t14 when the mirror period ends, i.e., the period until time t14 just before a surge voltage (i.e., a voltage higher than the steady-state voltage when the transistor is off) occurs in the collector-emitter voltage Vce. During the third period T3, a third driving force (ON number Nb=N3b) is set, and the gate is discharged by gate current Ig3. However, since this is during the mirror period, the gate voltage Vg does not change. Time t14 corresponds to the "fourth point in time."

[0110] The fourth period T4 is set from time t14 to time t15, which is the end of the mirror period, during which the collector current Ic is decreasing, and when the surge voltage of the collector-emitter voltage Vce begins to decrease. Time t15 corresponds to the "end timing" of the turn-off control period. During the fourth period T4, a fourth driving force (ON number Nb = N4b) is set, and the gate is discharged by the gate current Ig4. Since the fourth period T4 occurs after the end of the mirror period, the gate voltage Vg decreases.

[0111] After the end of the fourth period T4, that is, from time t15 onwards, the maximum driving force (the number of ONs Nb = Nbmax) is set, and the gate current Igmax is supplied to the gate. From time t16 onwards, as the discharge of the gate progresses, the absolute value of the gate current Ig decreases from |Igmax| to |I0| before time t11, and from time t17 onwards, Ig = I0. The maximum driving force is set to be equal to or greater than the maximum value of the first driving force to the fourth driving force. That is, the number of ONs Nbmax is set to be equal to or greater than the maximum value of N1b to N4b (Nbmax ≥ max(N1b, N2b, N3b, N4b). For example, Nbmax = k).

[0112] The timing of switching between the first period T1 to the fourth period T4 at turn-off (times t12 to t15) can also be determined in advance from actual measurements or simulation results of the operating waveform at turn-off of the power semiconductor element 3 (switching element 31). By converting the elapsed time from time t10 to times t12 to t15 into the number of clocks of the clock signal CLK, the data held in the selection circuit (FIG. 5) in the turn-off period setting circuit 11b can be determined.

[0113] In addition, the driving capacities (the numbers N1b to N4b, Nbmax of the N-type transistors 211b to 21kb that are turned on) during the first period T1 to the fourth period T4 and after the end of the fourth period can be arbitrarily determined by the turn-off driving capacity setting circuit 12b and the turn-off logic operation circuit 13b, just like the driving capacities at the time of turn-on.

[0114] As described above, the control pattern at the time of turn-off by the drive circuit for the power semiconductor device according to the first embodiment is characterized in that the period from the turn-off start timing (time t10) when the turn-off command is generated to the predetermined end timing (time t15) corresponding to the timing when the collector-emitter voltage Vce, which had risen once after the end of the mirror period, begins to decrease is defined as a "turn-off control period," which is a period subject to drive capacity control, and the drive capacity is switched among a first period T1 to an n-th period Tn (n≧4) obtained by dividing the turn-off control period into four or more periods. Note that although an example where n=4 is also described in Figures 10 and 11, it is also possible to divide at least one of the first period T1 to the fourth period T4 into five or more periods and switch the drive capacity.

[0115] In the first control pattern example at turn-off, the driving capabilities during the first period T1 to the fourth period T4 and after the end of the fourth period are set as follows:

[0116] The driving capacity during the first period T1 can be shortened by setting the absolute value of the gate current Ig1 to be greater than the absolute value of the gate current Ig (dotted line) from time t1 to t2 in the comparative example.

[0117] The drive capability during the second period T2 is set so that the absolute value of the gate current Ig2 is greater than the absolute value of the gate current Ig (dotted line) of the comparative example during the same period (corresponding to times t12 to t13). This increases the voltage change rate (dVce / dt) of the collector-emitter voltage Vce compared to the comparative example, thereby reducing losses during the second period T2. Even if the ON numbers N1b and N2b are the same between the first period T1 and the second period T2, the absolute value of the gate current Ig decreases after time t12 for the same drive capability, as in the comparative example, and this may result in the gate current Ig2 (absolute value) being smaller than the gate current Ig1 (absolute value).

[0118] The drive capacity during the third period T3 is set so that the absolute value of the gate current Ig3 is greater than the absolute value of the gate current Ig (dotted line) of the comparative example during the same period (corresponding to times t13 to t14). This increases the voltage change rate (dVce / dt) of the collector-emitter voltage Vce, thereby reducing the loss that occurs during the third period T3.

[0119] The drive capacity in the fourth period is set so that the absolute value of the gate current Ig4 is smaller than the absolute value of the gate current Ig (dotted line) in the comparative example during the same period (corresponding to times t14 to t15). This makes it possible to reduce the surge voltage generated in the collector-emitter voltage Vce compared to the comparative example.

[0120] After the end of the fourth period T4, the absolute value of the gate current Igmax is increased to increase the current change rate (dIc / dt) of the collector current Ic, thereby reducing losses that occur after the fourth period T4. Therefore, the gate current Igmax (absolute value) is equal to or greater than the maximum value of the absolute values ​​of the gate currents Ig1 to Ig4, and is preferably generated by the maximum driving capability of the driving unit 2 (for example, the number of ON states Nbmax=k).

[0121] Thus, in the first control pattern example at the time of turn-off by the drive circuit for a power semiconductor device according to the first embodiment, the "turn-off control period" defined above is divided into four, and the drive capabilities are switched so that the relationship Igmax > Ig1 > Ig2 > Ig3 > Ig4 holds among the gate currents Ig1 to Ig4 and Igmax (absolute values). This shortens the dead time compared to the comparative example in which turn-on is performed at a constant drive capability, and by controlling to increase the rate of change of the collector current Ic, it is possible to reduce losses and also reduce the surge voltage of the collector-emitter voltage Vce.

[0122] 10, the absolute value of the gate current Ig3 in the third period T3 can be set lower than the absolute value of the gate current Ig (dotted line) in the comparative example during the same period, provided that the relationship of absolute values ​​Igmax > Ig1 > Ig2 > Ig3 > Ig4 holds. In this way, while loss in the third period T3 increases, noise caused by the voltage change rate (dVce / dt) of the collector-emitter voltage Vce can be reduced more than in the comparative example.

[0123] An example of the second control pattern at turn-off is shown in Fig. 11. In Fig. 11, a comparative example similar to Fig. 10 is indicated by the same dotted lines as in Fig. 10, and the operating waveforms in the first control pattern (Fig. 10) are further indicated by dotted lines spaced closer together than in the comparative example. The operating waveforms in the second control pattern are shown by solid lines in Fig. 11.

[0124] In the second control pattern shown in Fig. 11, the first period T1 to the fourth period T4 are provided in the same manner as in Fig. 10. In the second control pattern, the settings of the gate currents Ig1 to Ig4 and Igmax are different from those in the first control pattern (Fig. 10).

[0125] Specifically, in the second control pattern, the drive capacity is switched so that the relationship Igmax > Ig1 > Ig2 > Ig4 > Ig3 is established among the gate currents Ig1 to Ig4 and Igmax (absolute value). As can be seen from a comparison between Figure 11 and Figure 10, in the second control pattern, compared to the first control pattern, the gate current Ig3 (absolute value) in the third period T3 is set small, while the gate current Ig4 (absolute value) in the fourth period T4 is set large.

[0126] The gate currents Ig1 and Ig2 in the first period T1 and the second period T2 are equivalent to those in the first control pattern, so as with the first control pattern, it is possible to shorten the dead time and reduce losses that occur in the second period T2.

[0127] In the third period T3, the absolute value of the gate current Ig3 is made smaller than that in the first control pattern, thereby reducing the voltage change rate (dVce / dt) of the collector-emitter voltage Vce. As a result, although the loss occurring in the third period T3 increases, it is possible to reduce the noise caused by the voltage change rate (dVce / dt).

[0128] In the fourth period T4, the absolute value of the gate current Ig4 is set to be larger than that in the first control pattern and equal to the absolute value of the gate current Ig (dotted line) in the comparative example, thereby making it possible to reduce losses occurring in the fourth period T4 while keeping the surge voltage occurring in the collector-emitter voltage Vce equal to that in the comparative example.

[0129] As with the first control pattern, the second control pattern at turn-off also shortens the dead time compared to the comparative example, which turns on the transistor with a constant driving capacity. Furthermore, it is possible to reduce noise caused by the voltage change rate (dVce / dt) more than in the comparative example, while keeping the surge voltage generated in the collector-emitter voltage Vce equivalent to that in the comparative example, and suppress an increase in loss that occurs at turn-off.

[0130] As described above, the drive circuit for a power semiconductor device according to the first embodiment divides at least one of the above-described "turn-on control period" and "turn-off control period" into four or more periods (n≧4), and can switch the drive capacity in stages within the plurality of periods. Furthermore, after the end of the turn-on control period or the turn-off control period, the drive capacity is set to be equal to or greater than the maximum value of the drive capacity within each of the plurality of periods into which the turn-on control period or the turn-off control period is divided.

[0131] In particular, at turn-on, a third period T3, a fourth period T4, and a division after the end of the fourth period T4 are provided, which can effectively reduce both noise or surges and losses.

[0132] Specifically, during the third period T3, which begins after the mirror period begins (time t3) and ends when a surge current in the collector current Ic occurs (time t4), the gate current Ig3 can be set to suppress the surge current in the collector current Ic. Furthermore, during the fourth period T4, which begins at time t4 and ends at time t5 within the mirror period, the gate current Ig4 can be set to control the voltage change rate (dVce / dt) of the collector-emitter voltage Vce. After the end of the fourth period T4, the mirror period can be shortened, and the gate current can be increased compared to the fourth period T4 to reduce losses. As described above, time t5 can be set as the timing when a voltage change in the collector-emitter voltage Vce occurs.

[0133] In this way, the driving capacity can be adjusted during the third period T3, the fourth period T4, and after the end of the fourth period T4, thereby reducing both the noise or surges and losses generated in the power semiconductor element 3 (switching element 31).

[0134] In contrast, in Patent Document 1, the period from the turn-on command to the completion of the gate voltage change is divided into three parts, and the drive capacity (gate current) is switched accordingly. Therefore, the drive capacity is set constant during the period corresponding to the third period T3 and thereafter in this embodiment. As a result, it is understood that the gate drive device of Patent Document 1 has difficulty reducing both noise or surges and losses, as in the drive circuit of this embodiment. For example, if the drive capacity (gate current) is set to suppress the voltage change rate or current change rate in order to reduce noise or surges during the above period, the loss during that period will increase, making it impossible to suppress the overall loss during turn-on.

[0135] In the drive circuit for the power semiconductor element according to the first embodiment, even when the element is turned off, it is possible to switch the drive capability during the third period T3, the fourth period T4, and after the end of the fourth period T4, thereby effectively reducing both noise or surges and losses.

[0136] Specifically, during the third period T3 from the timing before the end of the mirror period (time t13) to the timing just before a surge voltage occurs in the collector-emitter voltage Vce (time t14), the gate current Ig3 (absolute value) can be set so as to control the voltage change rate (dVce / dt) of the collector-emitter voltage Vce.

[0137] Furthermore, during the fourth period T4 from time t14 to time t15, the gate current Ig4 (absolute value) can be set so as to suppress surge voltages in the collector-emitter voltage Vce. After the fourth period T4 ends, the mirror period can be shortened and the absolute value of the gate current can be made larger than that during the fourth period T4 to reduce losses.

[0138] In this way, even when turning off, the driving capacity can be adjusted during the third period T3, the fourth period T4, and after the end of the fourth period T4, so that it is possible to reduce both the noise or surge generated in the power semiconductor element 3 (switching element 31) and losses.

[0139] Second Embodiment Fig. 12 is a block diagram illustrating an example of the configuration of a digital control unit 1 and a drive unit 2 of a drive circuit 1000B for a power semiconductor device according to a second embodiment.

[0140] Comparing FIG. 12 with FIG. 3, the power semiconductor element driving circuit 1000B according to the second embodiment differs from the driving circuit 1000A according to the first embodiment shown in FIG. 3 in that it further comprises a turn-on setting terminal 2002 and a turn-off setting terminal 2003 to which an electrical signal can be input.

[0141] Furthermore, the configuration of each selection circuit in drive circuit 1000B is changed compared to drive circuit 1000A according to embodiment 1. Specifically, the selection circuits for setting the first period T1 to the n-th period Tn, which are arranged in turn-on period setting circuit 11a and turn-off period setting circuit 11b, and the selection circuits for setting the drive capacity for each of the first period T1 to the n-th period Tn, which are arranged in turn-on drive capacity setting circuit 12a and turn-off drive capacity setting circuit 12b, are replaced from the selection circuit SLC shown in FIG.

[0142] FIG. 13 is a circuit diagram illustrating an example of the configuration of each selection circuit arranged in the drive circuit 1000B shown in FIG.

[0143] 13 with FIG. 5, the selection circuit SLCX according to the second embodiment has a memory element STR and a switch SW. The memory element STR stores data specifying either "selected" or "unselected" that is input to a turn-on setting terminal 2002 or a turn-off setting terminal 2003. For example, the memory element STR can be configured using a nonvolatile memory element such as an EEPROM (Electrically Erasable Programmable Read-Only Memory).

[0144] The switch SW selectively outputs one of the power supply voltage VCC (H level) and the ground voltage GND (L level) according to the data stored in the storage element STR. For example, the switch SW can be configured by a CMOS (Complementary Metal Oxide Semiconductor) inverter.

[0145] As a result, in the drive circuit 1000B according to the second embodiment, the data held in each selection circuit can be easily written from outside the drive circuit 1000B using an input signal to the turn-on setting terminal 2002 or the turn-off setting terminal 2003. In other words, the turn-on setting terminal 2002 and the turn-off setting terminal 2003 correspond to an example of an "input terminal."

[0146] The rest of the configuration of the drive circuit 1000B according to the second embodiment is the same as that of the drive circuit 1000A according to the first embodiment. Therefore, as described in the first embodiment, each of the "turn-on control period" and the "turn-off control period" is divided into a first period T1 to an n-th period Tn (n≧4), and the drive capability can be switched between each of the first period T1 to the n-th period Tn and after the end of the n-th period. This makes it possible to reduce both noise or surges and losses when the power semiconductor element 3 (switching element 31) is turned on and turned off, as in the first embodiment.

[0147] Furthermore, in the drive circuit for a power semiconductor element according to the second embodiment, the data held in each selection circuit SLCX for setting the switching timing of the first period T1 to the nth period Tn and the data held in each selection circuit SLCX for setting the drive capacity for each of the first period T1 to the nth period Tn can be easily changed by inputting an electrical signal from outside the drive circuit 1000B.

[0148] This makes it possible to easily adjust the switching timing and drive capacity of the first period T1 to the nth period Tn to realize a desired control pattern. Therefore, even if the power semiconductor element 3 that is the target of on / off control by the drive circuit is changed, or if the characteristics of the power semiconductor element 3 change due to manufacturing variations, adjustments to realize the desired control pattern can be easily made using the input signal to the turn-on setting terminal 2002 or the turn-off setting terminal 2003. This makes it possible to provide a low-cost drive circuit with reduced design and manufacturing costs.

[0149] Third Embodiment Fig. 14 is a block diagram illustrating an example of the configuration of a digital control unit 1 and a drive unit 2 of a drive circuit 1000C for a power semiconductor device according to a third embodiment.

[0150] Comparing Fig. 14 with Fig. 3, a drive circuit 1000C for power semiconductor elements according to the third embodiment differs from drive circuit 1000A according to the first embodiment shown in Fig. 3 in that digital control unit 1 further includes a turn-on feedback (FB) calculation circuit 16a and a turn-off feedback (FB) calculation circuit 16b. Furthermore, as in the second embodiment, each of the selection circuits arranged inside turn-on period setting circuit 11a, turn-off period setting circuit 11b, turn-on drive capacity setting circuit 12a, and turn-off drive capacity setting circuit 12b is configured by the selection circuit SLCX shown in Fig. 15.

[0151] In the third embodiment, the detected values ​​(actual measured values) of the voltage, current, temperature, etc. of the power semiconductor element 3 are input as a feedback signal SNSfb to the turn-on feedback calculation circuit 16a and the turn-off feedback calculation circuit 16b.

[0152] The turn-on feedback calculation circuit 16a generates control signals Cton and Cdon, which correspond to the input signal to the turn-on setting terminal 2002 in the second embodiment, in accordance with a predetermined control calculation.

[0153] The control signal Cton is input to a selection circuit SLCX arranged in the turn-on period setting circuit 11a and stored in a memory element STR, thereby making it possible to adjust the timing of switching between the first period T1 to the n-th period Tn at turn-on by feedback of the detected values ​​of the voltage, current, temperature, or the like of the power semiconductor element 3.

[0154] The control signal Cdon is input to a selection circuit SLCX arranged in the turn-on drive capacity setting circuit 12a and stored in a storage element STR, thereby making it possible to adjust the drive capacity for each of the first period T1 to the n-th period Tn during turn-on by feedback of the detected values ​​of the voltage, current, temperature, or the like of the power semiconductor element 3.

[0155] Similarly, the turn-off feedback calculation circuit 16b generates control signals Ctoff and Cdoff, which correspond to the input signal to the turn-off setting terminal 2003 in the second embodiment, in accordance with a predetermined control calculation.

[0156] The control signal Ctoff is input to a selection circuit SLCX arranged in the turn-off period setting circuit 11b and stored in a memory element STR, thereby making it possible to adjust the timing of switching between the first period T1 to the n-th period Tn at the time of turn-off by feedback of the detected values ​​of the voltage, current, temperature, or the like of the power semiconductor element 3.

[0157] The control signal Cdoff is input to a selection circuit SLCX arranged in the turn-off drive capacity setting circuit 12b and stored in a storage element STR, thereby making it possible to adjust the drive capacity for each of the first period T1 to the n-th period Tn during turn-off by feedback of a detected value such as the voltage, current, or temperature of the power semiconductor element 3.

[0158] For example, feedback control calculations can be performed in the turn-on feedback calculation circuit 16a and the turn-off feedback calculation circuit 16b so as to adjust the switching timings of the first period T1 to the n-th period Tn at the time of turn-on and turn-off, respectively, based on actual waveform data of the gate voltage Vg, the collector-emitter voltage Vce, and the collector current Ic of the power semiconductor element 3. For example, the content of the feedback control calculations can be set so as to adjust the switching timings of the first period T1 to the n-th period Tn based on detected values ​​such as the start and end timings of the mirror periods in the actual waveform data and the timings at which the surge voltage or surge current starts to rise or fall.

[0159] Alternatively, the contents of the control calculations in the turn-on feedback calculation circuit 16a and the turn-off feedback calculation circuit 16b can be determined so as to change the setting pattern of the drive capacity for each of the first period T1 to the nth period Tn at turn-on and turn-off, based on the actual measurement values ​​of the temperature, surge voltage (collector-emitter voltage Vce), or surge current (collector current Ic) of the power semiconductor element 3. For example, a pattern of gate currents Ig1 to Ig4, Igmax that increases the voltage change rate or current change rate to reduce loss when the temperature rises can be selected. Alternatively, the contents of the feedback control calculations can be set so as to select a pattern of gate currents Ig1 to Ig4, Igmax that decreases the voltage change rate or current change rate when the detected value of the surge voltage or surge current is large.

[0160] As a result, the semiconductor element drive circuit according to the third embodiment can adjust the control pattern described in the first embodiment based on the detected values ​​of the voltage, current, temperature, etc. of the power semiconductor element 3. As a result, even if the operating state of the power semiconductor element 3 changes while online, the effect of reducing both noise or surge and loss according to the first embodiment can be obtained.

[0161] FIG. 15 shows a schematic configuration of a semiconductor device drive circuit 1000D according to a modification of the third embodiment.

[0162] As shown in FIG. 15, in a semiconductor element driving circuit 1000D according to a modification of the third embodiment, the control calculations in the turn-on feedback calculation circuit 16a and the turn-off feedback calculation circuit 16b shown in FIG. 14 are executed outside the driving circuit 1000D.

[0163] Specifically, the feedback signal SNSfb from the power semiconductor device 3 is input to a feedback (FB) calculation circuit 3004 arranged outside the drive circuit 1000D. The feedback calculation circuit 3004 executes control calculations similar to those of the turn-on feedback calculation circuit 16a and the turn-off feedback calculation circuit 16b in Fig. 14 to generate control signals Cton, Cdon, Ctoff, and Cdoff similar to those in Fig. 14. The control signals Cton, Cdon, Ctoff, and Cdoff are input to the digital control unit 1 of the drive circuit 1000D.

[0164] The digital control unit 1 in Fig. 15 can be configured by excluding the turn-on feedback calculation circuit 16a and the turn-off feedback calculation circuit 16b from the configuration of the digital control unit 1 shown in Fig. 14. Furthermore, the turn-on period setting circuit 11a and the turn-on drive capacity setting circuit 12a can receive control signals Cton and Cdon from the feedback calculation circuit 3004, respectively. Similarly, the turn-off period setting circuit 11b and the turn-off drive capacity setting circuit 12b can receive control signals Ctoff and Cdoff from the feedback calculation circuit 3004, respectively. The modified configuration shown in Fig. 15 can also achieve the same effects as the semiconductor element drive circuit of embodiment 3.

[0165] It should be noted that the third embodiment and its modification can be combined with the second embodiment. That is, the data held in each selection circuit SLCX can be configured to be writable by either the feedback control signals Cton, Cdon, Ctoff, and Cdoff or the input signals to the turn-on setting terminal 2002 and the turn-off setting terminal 2003.

[0166] Fourth Embodiment Fig. 16 is a block diagram illustrating the schematic configuration of a power semiconductor device drive circuit 1000E according to a fourth embodiment.

[0167] 16, the drive circuit 1000E includes a digital control unit 1X and a drive unit 2X that generates a gate voltage Vg based on a digital control signal generated by the digital control unit 1. The digital control unit 1X includes a modulation circuit 4011 that outputs a digital control signal obtained by modulating the control signal VIN.

[0168] 17 and 18 show examples of the digital control signal output from the modulation circuit 4011. In FIG.

[0169] FIG. 17 is a waveform diagram illustrating an example of an output signal from modulation circuit 4011 when turned on.

[0170] 17, when the modulation circuit 4011 is turned on, it outputs to the drive unit 2 a digital control signal DSon in which the H level periods are individually set in each of the first period T1 to the n-th period Tn, as in the first embodiment. Also in FIG. 17, an example is shown in which the division number n of the "turn-on control period" defined in the same manner as in the first embodiment is 4.

[0171] The modulation circuit 4011 is configured to include, for example, the turn-on period setting circuit 11a of the first embodiment so as to be able to generate the pulse signals P1a to Pna described in the first embodiment. Furthermore, the modulation circuit 4011 is configured to include a group of selection circuits for setting the drive capabilities of the turn-on drive capability setting circuit 12a of the first embodiment. This makes it possible to set the switching timing for the first period T1 to the n-th period Tn into which the turn-on control period is divided, and the drive capabilities for each of the first period T1 to the n-th period Tn, in accordance with the data held in each selection circuit, as in the first embodiment.

[0172] In the digital control signal DSon output from the modulation circuit 4011, the ratio of the time length of the H level period to the time length of the L level period (for example, duty, which is the ratio of the H level period to the total of the H level period and the L level period) in each of the first period (time t0 to t2), the second period (time t2 to t3), the third period (time t3 to t4), and the fourth period (time t4 to t5) is set in accordance with the drive capability determined by the data held in the selection circuit.

[0173] Furthermore, after the fourth period T4 (n-th period Tn) ends, the digital control signal DSon is generated so that the duty, i.e., the H-level period ratio, becomes 100(%). As a result, similar to the first embodiment, at turn-on, the driving capability after the end of the fourth period T4 (n-th period Tn) can be set to be equal to or greater than the maximum value of the driving capabilities in each of the first period T1 to fourth period T4 (n-th period Tn).

[0174] FIG. 18 is a waveform diagram illustrating an example of an output signal from the modulation circuit 4011 at the time of turn-off.

[0175] 18, at the time of turn-off, modulation circuit 4011 outputs to drive unit 2 a digital control signal DSoff in which the H level period ratio (duty) is individually set for each of the first period T1 to the n-th period Tn, as in embodiment 1. Also in FIG. 18, an example is shown in which the division number n of the "turn-off control period" defined in the same manner as in embodiment 1 is 4.

[0176] The modulation circuit 4011 is configured to include, for example, the turn-off period setting circuit 11b of the first embodiment so as to be able to generate the pulse signals P1b to Pnb described in the first embodiment. Furthermore, the modulation circuit 4011 is configured to include a group of selection circuits for setting the drive capabilities of the turn-off drive capability setting circuit 12b of the first embodiment. As a result, similar to the first embodiment, the timing for switching between the first period T1 to the n-th period Tn into which the turn-off control period is divided, and the drive capabilities for each of the first period T1 to the n-th period Tn can be set by the data held in each selection circuit.

[0177] In the digital control signal DSoff output by the modulation circuit 4011, the duty (H level period ratio) in each of the first period (time t10 to t12), second period (time t12 to t13), third period (time t13 to t14), and fourth period (time t14 to t15) is set in accordance with the driving capability determined by the data held in the selection circuit.

[0178] Furthermore, after the fourth period T4 (nth period Tn) ends, the digital control signal DSoff is generated so that the duty (ratio of the H level period) becomes 100(%). As a result, similar to the first embodiment, at the time of turn-off, the driving capability after the end of the fourth period T4 (nth period Tn) can be set to be equal to or greater than the maximum value of the driving capabilities in each of the first period T1 to fourth period T4 (nth period Tn).

[0179] The modulation circuit 4011 can generate the digital control signals DSon and DSoff by digitally modulating the control signal VIN using a digital modulation method such as on-off modulation or amplitude shift keying, or a pulse modulation method such as pulse width modulation or pulse density modulation.

[0180] Fig. 19 is a circuit diagram illustrating an example configuration of the driver 2X shown in Fig. 16. As shown in Fig. 19, the driver 2X has a P-type transistor 25a and an N-type transistor 25b. The P-type transistor 25a is connected between a power supply node that supplies the power supply voltage VCC and a node Ng, and constitutes the turn-on driver 21a. An inverted signal of the digital control signal DSon is input to the gate of the P-type transistor 25a.

[0181] The N-type transistor 25b is connected between the node Ng and a power supply node that supplies the ground voltage GND, and constitutes the turn-off driver 21b. A digital control signal DSoff is input to the gate of the N-type transistor 25b.

[0182] At turn-on, the P-type transistor 25a is turned on during the H-level period of the digital control signal DSon, thereby generating a charging current for the gate of the power semiconductor device 3. Meanwhile, the P-type transistor 25a is turned off during the L-level period of the digital control signal DSon. Therefore, the average value of the gate current during each of the first to fourth periods T1 to T4 (n-th period Tn) is controlled by the duty (H-level period ratio) of the digital control signal DSon during each period. As a result, the gate current Ig (average value) during turn-on during the first to fourth periods T1 to T4 (n-th period Tn) and after the end of the fourth period T4 (n-th period Tn) can be controlled to be equivalent to Ig1 to Ig4 and Igmax in the first embodiment.

[0183] Similarly, during turn-off, the N-type transistor 25b is turned on during the H-level period of the digital control signal DSoff, thereby generating a discharge current at the gate of the power semiconductor device 3. Meanwhile, the N-type transistor 25b is turned off during the L-level period of the digital control signal DSoff. Therefore, the average value of the gate current during each of the first to fourth periods T1 to T4 (n-th period Tn) is controlled by the duty (H-level period ratio) of the digital control signal DSoff during each period. This allows the average value of the gate current Ig (absolute value) after the end of the first to fourth periods T1 to T4 (n-th period Tn) and the fourth period T4 (n-th period Tn) to be controlled to be equivalent to the absolute values ​​of Ig1 to Ig4 and Igmax in the first embodiment.

[0184] In this way, the drive circuit of embodiment 4 uses a digital modulation signal, which simplifies the hardware configuration for switching the drive capability, and yet provides the same effect as the drive circuit of embodiment 1, namely, the effect of reducing both noise or surge and loss when the power semiconductor element 3 (switching element 31) is turned on and turned off.

[0185] It is also possible to combine the second and / or third embodiments with the fourth embodiment. In this case, the selection circuit SLCX shown in Fig. 15 is applied to a group of selection circuits for setting the switching timing and drive capacity of the first to n-th periods obtained by dividing the turn-on control period or the turn-off control period. The data held in each selection circuit SLCX (selection / non-selection) can be input using the turn-on setting terminal 2002 and the turn-off setting terminal 2003 (Fig. 12) and at least one of the turn-on feedback calculation circuit 16a and the turn-off feedback calculation circuit 16b (Fig. 14) and the feedback calculation circuit 3004 (Fig. 15).

[0186] Fifth Embodiment In a fifth embodiment, a power module to which the drive circuits for the power semiconductor devices described in the first to fourth embodiments are applied will be described.

[0187] FIG. 20 is a block diagram illustrating a first configuration example of a power module according to the fifth embodiment.

[0188] 20, the drive circuit 1000 for the power semiconductor element according to this embodiment may be arranged separately from the power module 1010 including the power semiconductor element 3. The drive circuit 1000 collectively refers to the drive circuits 1000A to 1000E according to the first to fourth embodiments, and may be configured by any of the drive circuits 1000A to 1000E.

[0189] In the configuration of FIG. 20 , a wiring 1015 is arranged between the drive circuit 1000 and the power module 1010 to electrically connect the node Ng of the drive circuit 1000 and the gate of the power semiconductor element 3 (switching element 31).

[0190] FIG. 21 is a block diagram illustrating a second configuration example of the power module according to the fifth embodiment.

[0191] 21 , a power module 1010A according to the second configuration example is configured to incorporate a drive circuit 1000 and a power semiconductor element 3. In the configuration of FIG. 21 , a node Ng of the drive circuit 1000 and a gate of the power semiconductor element 3 (switching element 31) are electrically connected inside the power module 1010A. A control signal VIN is input to an input terminal 1012 of the power module 1010A and is provided to the digital control unit 1.

[0192] Although the power module using a single power semiconductor element 3 is shown as an example in FIGS. 20 and 21, a power module having a plurality of built-in power semiconductor elements 3 can also be configured.

[0193] FIG. 22 is a schematic diagram illustrating a third configuration example of the power module according to the fifth embodiment.

[0194] 22, a power module 1010C according to the third configuration example is configured to incorporate six power semiconductor elements 3up, 3un, 3vp, 3vn, 3wp, and 3wn. The power semiconductor elements 3up, 3un, 3vp, 3vn, 3wp, and 3wn are wired inside the power module 1010C to form a three-phase inverter.

[0195] The three-phase inverter performs DC / AC power conversion between the DC voltage across the high-voltage side and low-voltage side DC terminals 1011P and 1011N and the three-phase AC power at the three-phase AC terminals 1016U, 1016V, and 1016W by controlling the on / off of power semiconductor elements 3up, 3un, 3vp, 3vn, 3wp, and 3wn in accordance with control signals VINup, VINun, VINvp, VINvn, VINwp, and VINwn.

[0196] The drive circuits 1000wp, 1000vp, 1000up control the on / off of the power semiconductor elements 3wp, 3vp, 3up in accordance with the control signals VINwp, VINvp, VINup input to the control input terminals 4wp, 4vp, 4up, respectively. Similarly, the drive circuits 1000wn, 1000vn, 1000un control the on / off of the power semiconductor elements 3wn, 3vn, 3un in accordance with the control signals VINwn, VINvn, VINun input to the control input terminals 4wn, 4vn, 4un, respectively.

[0197] Each of the drive circuits 1000wp, 1000vp, 1000up, 1000wn, 1000vn, and 1000un may be configured by any of the drive circuits 1000A to 1000E according to the first to fourth embodiments, similar to the drive circuit 1000 of FIGS.

[0198] In the configuration of Figure 22, driving circuits 1000wp, 1000vp, 1000up, 1000wn, 1000vn, 1000un are electrically connected to the gates of power semiconductor elements 3wp, 3vp, 3up, 3wn, 3vn, 3un by wiring 1015wp, 1015vp, 1015up, 1015wn, 1015vn, 1015un.

[0199] FIG. 23 is a schematic diagram illustrating a fourth configuration example of the power module according to the fifth embodiment.

[0200] As shown in FIG. 23, a power module 1010D according to the fourth configuration example is configured to incorporate drive circuits 1000wp, 1000vp, 1000up, 1000wn, 1000vn, and 1000un and power semiconductor elements 3wp, 3vp, 3up, 3wn, 3vn, and 3un shown in FIG. 22.

[0201] In the configuration of FIG. 23, inside power module 1010D, nodes Ng of drive circuits 1000wp, 1000vp, 1000up, 1000wn, 1000vn, and 1000un are electrically connected to the gates of power semiconductor elements 3wp, 3vp, 3up, 3wn, 3vn, and 3un.

[0202] Control signals VINwp, VINvp, VINup, VINwn, VINvn, and VINun are input to input terminals 1012wp, 1012vp, 1012up, 1012wn, 1012vn, and 1012un of the power module 1010D.

[0203] In this way, the drive circuit for power semiconductor devices according to this embodiment can be incorporated into a power module in any desired manner. That is, it can be disposed outside a power module incorporating any number of power semiconductor devices (1-in-1, 2-in-1, 6-in-1, etc.) and used to control the on / off of the power semiconductor devices, or it can be disposed so as to be incorporated into the same power module as the power semiconductors.

[0204] Furthermore, in this embodiment, an example has been described in which both turn-on control having a turn-on control period divided into four or more parts and turn-off control having a turn-off control period divided into four or more parts are executed, but it is also possible to modify the embodiment so that the turn-on control or turn-off control according to this embodiment is executed only at the time of turn-on or only at the time of turn-off control.

[0205] Regarding the multiple embodiments described above, we would like to confirm that it was intended from the beginning of the application to appropriately combine the configurations described in each embodiment, including combinations not mentioned in the specification, within the scope that does not result in inconsistencies or contradictions.

[0206] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0207] 1, 1X digital control unit, 2, 2X drive unit, 3, 3un, 3up, 3vn, 3vp, 3wn, 3wp power semiconductor elements, 4, 4un, 4up, 4vn, 4vp, 4wn, 4wp control input terminals, 11a turn-on period setting circuit, 11b turn-off period setting circuit, 111a first period setting circuit (turn-on), 112a second period setting circuit (turn-on), 11na nth period setting circuit (turn-on), 12a turn-on drive capacity setting circuit, 12b turn-off drive capacity setting circuit, 13a turn-on logic operation circuit, 13b turn-off logic operation circuit, 14 clock circuit, 15, 1111 to 111m inversion circuits, 16a turn-on feedback operation circuit, 16b turn-off feedback operation circuit, 211a to 21ka, 25a P-type transistor, 211b to 21kb, 25b N-type transistor, 21a turn-on driver, 21b turn-off driver, 31 switching element, 32 freewheel diode, 110a counter circuit, 111a, 111b first period setting circuit, 112a second period setting circuit, 114a fourth period setting circuit, 121a first period driving capacity setting circuit (turn-on), 122a second period driving capacity setting circuit (turn-on), 12na nth period driving capacity setting circuit (turn-on), 1000, 1000A, 1000B, 1000C, 1000D, 1000E, 1000un, 1000up, 1000vn, 1000vp, 1000wn, 1000wp driver circuit, 1010, 1010A, 1010C, 1010D Power module, 1011N, 1011P DC terminal, 1012, 1012un, 1012up, 1012vn, 1012vp, 1012wn, 1012wp input terminal, 1015, 1015un, 1015up, 1015vn, 1015vp, 1015wn, 1015wp wiring, 1016U, 1016V, 1016W AC terminal, 1101 to 110m D flip-flop circuit, 1120, 1301 to 130k NOR circuit, 1201 to 120k, 11101 to 1110m, SLC, SLCX selection circuit, 1211 to 121k,11111 to 1111m AND circuit, 1310 flip-flop circuit, 2002 turn-on setting terminal, 2003 turn-off setting terminal, 3004 feedback calculation circuit, 4011 modulation circuit, 11120 OR circuit, CLK clock signal, Cdoff, Cdon, Ctoff, Cton, VIN, VINun, VINup, VINvn, VINvp, VINwn, VINwp control signal, DSoff, DSon digital control signal, GND ground voltage, Ig, Ig1, Ig2, Ig3, Ig4, Igmax gate current, N1 driving capability, Ng node, P1a to Pna, P1b to Pnb pulse signal, Q1 to Qm output signal (D flip-flop circuit), SNSfb feedback signal, STR Memory element (selection circuit), SW switch (selection circuit), T1 first period, T2 second period, T3 third period, T4 fourth period, Vg gate voltage, Vth threshold voltage.

Claims

1. A drive circuit that turns on or off a power semiconductor device in response to a turn-on command or a turn-off command, a driver that outputs a control voltage to a control electrode of the power semiconductor device when the power semiconductor device is turned on and when the power semiconductor device is turned off; a control unit for variably controlling the driving capacity of the power semiconductor device by the driving unit, The control unit a turn-on control that divides a turn-on control period from a start timing at which the turn-on command is generated to an end timing that is set within a mirror period of a control electrode voltage of the power semiconductor element into four or more periods at the time of turning on the power semiconductor element, and switches the driving capability in each of the plurality of periods; and at the time of turn-off, a turn-off control period from a start timing at which the turn-off command is generated to an end timing that is predetermined to be a timing at which an inter-electrode voltage starts to decrease within a period in which an inter-electrode current of the power semiconductor element is decreasing after the end of the mirror period is divided into four or more periods, and turn-off control is performed to switch the driving capability in each of the plurality of periods, The drive unit is a drive circuit for a power semiconductor element configured to switch the drive capability in accordance with an instruction from the control unit during each of the plurality of periods during the turn-on control and the turn-off control, and to drive the power semiconductor element at a predetermined drive capability that is equal to or greater than the maximum value of the drive capability during each of the plurality of periods after the end of the plurality of periods.

2. 2. The drive circuit for a power semiconductor device according to claim 1, wherein the end timing of the turn-on control period is predetermined within a period during which a surge current of the interelectrode current subsides while the interelectrode voltage is changing within the mirror period.

3. The plurality of periods into which the turn-on control period is divided are: a period during which the driving capability is set to suppress a surge current occurring in the interelectrode current during the mirror period; 2. The power semiconductor device drive circuit according to claim 1, further comprising a period during which said drive capability is set to control a rate of change of said inter-electrode voltage within said mirror period.

4. The plurality of periods into which the turn-on control period is divided are:

4. The power semiconductor device drive circuit according to claim 3, further comprising a period for setting said drive capability to control the rate of change of said interelectrode current before said mirror period.

5. The plurality of periods into which the turn-off control period is divided are a period during which the driving capability is set to control a voltage change rate of the interelectrode voltage within the mirror period; 2. The drive circuit for a power semiconductor device according to claim 1, further comprising a period for setting said drive capability in order to control a surge voltage occurring in said interelectrode voltage after said mirror period has ended.

6. The plurality of periods into which the turn-on control period is divided are: a first time period from a first time point when the turn-on command is generated to a second time point when the control electrode voltage reaches a threshold voltage of the power semiconductor device; a second time period from the second time point to a third time point after the start of the mirror period; a third period from the third time point to a fourth time point during which a surge current is generated in the inter-electrode current; 2. The drive circuit for a power semiconductor device according to claim 1, further comprising a fourth period from said fourth time point to said end timing of said turn-on control period.

7. a drive current with which the drive section drives the control electrode in the second period is greater than the drive current in the fourth period; the drive current in the fourth period is greater than the drive current in the third period; 7. The power semiconductor device drive circuit according to claim 6, wherein the drive current after the end of the plurality of periods is equal to or greater than a maximum value of the drive current with which the drive section drives the control electrode during the plurality of periods.

8. a drive current with which the drive unit drives the control electrode in the second period is smaller than the drive current in the fourth period; the drive current in the second period is greater than the drive current in the third period; 7. The power semiconductor device drive circuit according to claim 6, wherein the drive current after the end of each of the plurality of periods is equal to or greater than a maximum value of the drive current during each of the plurality of periods.

9. 7. The power semiconductor device drive circuit according to claim 6, wherein the plurality of periods obtained by dividing the turn-on control period are provided by further subdividing at least one of the first period to the fourth period.

10. The plurality of periods into which the turn-off control period is divided are a first time period from a first time point when the turn-off command is generated to a second time point when the mirror period begins; a second time period from the second time point to a third time point before the end of the mirror period; a third period from the third time point to a fourth time point at which the mirror period ends; 2. The drive circuit for a power semiconductor device according to claim 1, further comprising a fourth period from said fourth time point to said end timing of said turn-off control period.

11. a drive current with which the drive section drives the control electrode in the second period is greater than the drive current in the third period; the drive current in the third period is greater than the drive current in the fourth period; 11. The drive circuit for a power semiconductor device according to claim 10, wherein the drive current with which said drive section drives said control electrode after said plurality of periods has ended is equal to or greater than the maximum value of said drive current in said plurality of periods.

12. a drive current with which the drive section drives the control electrode in the second period is greater than the drive current in the fourth period; the drive current in the fourth period is greater than the drive current in the third period; 11. The power semiconductor device drive circuit according to claim 10, wherein the drive current after the end of the plurality of periods is equal to or greater than a maximum value of the drive current during the plurality of periods.

13. 11. The power semiconductor device drive circuit according to claim 10, wherein the plurality of periods obtained by dividing the turn-off control period are provided by further subdividing at least one of the first period to the fourth period.

14. The control unit a switching timing of the plurality of periods obtained by dividing the turn-on control period or the turn-off control period and the driving capability for each of the plurality of periods are set based on the data held in a plurality of memory elements whose held data is electrically rewritable; The drive circuit 2. The power semiconductor device drive circuit according to claim 1, further comprising an input terminal to which an electrical signal for writing data to said plurality of memory elements is input.

15. The control unit a switching timing of the plurality of periods obtained by dividing the turn-on control period or the turn-off control period and the driving capability for each of the plurality of periods are set based on the data held in a plurality of memory elements whose held data is electrically rewritable; 2. The power semiconductor element drive circuit according to claim 1, wherein the data held in the plurality of memory elements is rewritable based on a detection signal including at least one of the temperature of the power semiconductor element, the inter-electrode voltage, and the inter-electrode current.

16. The drive circuit 16. The power semiconductor device drive circuit according to claim 15, further comprising an input terminal to which an electrical signal for writing data to said plurality of memory elements is input.

17. The control unit a modulation unit that outputs a digital control signal obtained by modulating a digital signal that controls on / off of the power semiconductor device, the modulation unit modulates the digital signal so that a ratio of a time length between a high level period and a low level period of the digital control signal is individually set in accordance with the commanded driving capability in each of the plurality of periods obtained by dividing the turn-on control period or the turn-off control period; 2. The drive circuit for a power semiconductor device according to claim 1, wherein the drive section is configured to supply a drive current to the control electrode during one of the high level period and the low level period of the digital control signal, and to stop supplying the drive current during the other of the high level period and the low level period.

18. 18. The power semiconductor device drive circuit according to claim 17, wherein the modulation section digitally modulates the digital signal to generate the digital control signal.

19. 18. The power semiconductor device drive circuit according to claim 17, wherein the modulation section pulse-modulates the digital signal to generate the digital control signal.

20. A power module configured to incorporate one or more power semiconductor elements and the drive circuit according to any one of claims 1 to 19, arranged corresponding to each of the power semiconductor elements.