Electric power conversion apparatus

JPWO2024257327A5Active Publication Date: 2025-08-05MITSUBISHI ELECTRIC CORP
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Patent Information

Application Number
JP2025527179
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Filing Date
2025-05-27
Publication Date
2025-08-05
Estimated Expiration
2043-06-16

AI Technical Summary

Technical Problem

Conventional multilevel power conversion devices face challenges in reducing size and weight while maintaining high power output, as they require numerous semiconductor switching elements and capacitors, leading to increased volume and cost.

Method used

A power conversion device design featuring an inductor on the AC side, a main converter connected to the DC positive, negative, and neutral points, a capacitor circuit with semiconductor switching elements, and a sub-converter between the neutral points, controlled by a control section to output multi-level voltages using low-voltage semiconductor switching elements, thereby reducing the size and weight.

Benefits of technology

Enables the output of multi-level voltages without increasing the device's size and weight, utilizing low-voltage semiconductor switching elements and optimizing capacitor voltage control for efficient power conversion.

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Abstract

The present invention comprises: a main converter (3) that has one end side connected to an inductor (2), and a DC positive electrode (P), a negative electrode (N), and a neutral point (O) set on the other end side; a capacitor circuit (5) that has a positive electrode terminal (P), a negative electrode terminal (N), and a neutral point (O) connected to the DC side; a sub-converter (4) that is composed of a capacitor (Csx) and a plurality of elements (Sx7–Sx10), is connected between the neutral point (O) of the capacitor circuit (5) and the neutral point (O) of the main converter (3), and in which a capacitor voltage (Vsx) changes according to a combination of opening / closing settings for the elements (Sx7–Sx10); and a control unit (6) that controls the operation of the main converter (3) and the sub-converter (4).
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Description

Power Conversion Device

[0001] The present disclosure relates to a power conversion device.

[0002] Power conversion devices such as inverters and converters that convert power between direct current and three-phase alternating current are used in a variety of applications, and are therefore required to be compact and lightweight. To address this, multilevel power conversion devices (see, for example, Patent Document 1 and Non-Patent Document 1) are used to reduce the volume of passive components such as capacitors, inductors, and resistors that occupy the power conversion device.

[0003] In a multilevel power conversion device, a voltage lower than the DC voltage is borne by semiconductor switching elements and smoothing capacitors, making it possible to use low-voltage semiconductor switching elements and low-voltage capacitors, thereby achieving high power output and high power density.Furthermore, because it is possible to output multilevel voltages, by increasing the number of voltage levels, it is possible to reduce the energy stored in the inductor, thereby achieving a smaller inductor and lower loss.

[0004] JP 2021-100363 A (paragraphs 0020 to 0025, Figure 1)

[0005] B. Singh, BN Singh, A. Chandra, K. Al-Haddad, A. Pandey and DP Kothari, "A review of three-phase improved power quality AC-DC converters," in IEEE Transactions on Industrial Electronics (USA), vol. 51, no. 3, pp. 641-660, June 2004, doi: 10.1109 / TIE.2004.825341.

[0006] On the other hand, typical multilevel power conversion systems, such as diode clamp, flying capacitor, and cascade connection systems, require the addition of numerous semiconductor switching elements, bidirectional semiconductor switching elements, and capacitors. For example, diode clamp systems require numerous diodes, and capacitor balance control becomes complex for systems with four or more levels, resulting in increased volume due to the need for external voltage balancing circuits. While the flying capacitor system simplifies capacitor voltage balance control, it requires numerous capacitors, increasing the system size. Furthermore, the cascade connection system requires separate DC power supplies because the DC section cannot be shared, increasing the system size and weight. In other words, regardless of the system, conventional multilevel power conversion systems have faced the challenges of increased volume and cost.

[0007] The present disclosure discloses a technique for solving the above-described problems, and aims to obtain a power conversion device that can output multilevel voltages by applying low-voltage semiconductor switching elements without increasing the size and weight of the device.

[0008] The power conversion device disclosed herein is characterized by comprising: an inductor provided for each phase on the AC side; a main converter having one end connected to the inductor and the other end having a DC positive pole, a DC negative pole, and a DC neutral point; a capacitor circuit having a positive pole end, a negative pole end, and a DC neutral point connected to the DC side; a sub-converter composed of a capacitor and a plurality of semiconductor switching elements, connected between the neutral point of the capacitor circuit and the neutral point of the main converter, and in which the capacitor voltage changes depending on the combination of opening and closing settings of the plurality of semiconductor switching elements; and a control unit that controls the operation of the main converter and the sub-converter.

[0009] According to the power conversion device of the present disclosure, a low-voltage semiconductor switching element can be applied to the sub-converter, and a power conversion device capable of outputting multilevel voltages can be obtained without increasing the size and weight of the device.

[0010] 1A and 1B are circuit diagrams for explaining the configuration of a power conversion apparatus according to a first embodiment and the configuration of a submodule constituting the power conversion circuit, respectively. This is a circuit diagram for explaining a power conversion circuit for one phase of the power conversion apparatus according to the first embodiment. This is a tabular diagram showing output terminal voltages and switch settings for each switching state in the power conversion apparatus according to the first embodiment. FIGS. 4A to 4F are each a diagram showing a conduction path for each switching state in the power conversion circuit for one phase of the power conversion apparatus according to the first embodiment. This is a tabular diagram showing an output voltage with respect to the output terminal voltage and current direction for each switching state in the power conversion apparatus according to the first embodiment, a capacitor charge / discharge state of a subconverter, and charge / discharge states of a positive-side capacitor and a negative-side capacitor. This is a circuit diagram for explaining the configuration of a control unit constituting the power conversion apparatus according to the first embodiment. FIGS. 7A and 7B are schematic diagrams showing transitions of modes and switching states in the power conversion apparatus according to the first embodiment when the current direction is positive and when the current direction is negative, respectively. This is a schematic diagram showing transitions of modes and switching states in the power conversion circuit for one phase when the current direction is positive in the power conversion apparatus according to the first embodiment, together with conduction paths in the power conversion circuit for one phase. 10A to 10D are schematic diagrams showing transitions of modes and switching states when the current direction is negative, together with conduction paths in a power conversion circuit for one phase, in a power conversion device according to a first embodiment. 10A to 10D are diagrams showing time-series changes in modes set when the current is positive and negative, respectively, when a zero voltage generation unit is not provided in the power conversion device, and when it is provided. 10B is a block diagram showing an example of the hardware configuration of a control unit constituting a power conversion device according to the present disclosure.

[0011] 1A to 10D are diagrams for explaining the configuration and operation of a power conversion device according to a first embodiment, in which Fig. 1A is a circuit diagram for explaining the configuration of the power conversion device, Fig. 1B is a circuit diagram of a sub-module that constitutes a sub-converter of a power conversion circuit, and Fig. 2 is a circuit diagram for explaining a power conversion circuit for one phase when a sub-converter is constituted using one sub-module shown in Fig. 1B for each phase.

[0012] FIG. 3 is a table showing the output terminal voltage and switch open / close (on / off) settings for each switching state in the power conversion circuit for one phase shown in FIG. 2. FIGS. 4A to 4F are diagrams showing the conduction paths for each switching state shown in FIG. 3 in the power conversion circuit for one phase shown in FIG. 2. FIG. 5 is a table showing the output voltage for each output terminal voltage and current direction for each switching state shown in FIG. 3, the charge / discharge state of the capacitor of the sub-converter, and the charge / discharge state of the positive-side capacitor and the negative-side capacitor. Note that in FIGS. 4A to 4F, the power conversion circuit itself is drawn with thin lines to highlight the current paths. This is also true for FIGS. 8 and 9, which will be described later.

[0013] 6 is a circuit diagram for explaining the configuration of the control unit that controls the switching states described above, Fig. 7A is a schematic diagram showing the transition of the mode and switching state together with the set values ​​when the current direction is positive, and Fig. 7B is a schematic diagram showing the transition of the mode and switching state together with the set values ​​when the current direction is negative. In Figs. 7A and 7B, the mode, output terminal voltage, and open / closed states of each of the four switches are described in that order from left to right.

[0014] 8 is a schematic diagram corresponding to FIG. 7A showing the transition of the mode and switching state when the current direction is positive, together with the conduction path in the power conversion circuit for one phase, and FIG. 9 is a schematic diagram corresponding to FIG. 7B showing the transition of the mode and switching state when the current direction is negative, together with the conduction path in the power conversion circuit for one phase.

[0015] Figures 10A and 10B are diagrams showing the time series changes in the mode set to the switching elements in the submodule when the current is positive and when a zero voltage generation unit is not provided and when a zero voltage generation unit is provided, respectively. Figures 10C and 10D are diagrams showing the time series changes in the mode set to the switching elements in the submodule when the current is negative and when a zero voltage generation unit is not provided and when a zero voltage generation unit is provided, respectively.

[0016] As shown in FIG. 1A , the power conversion device 10 of the present disclosure includes a power conversion circuit 1 having DC side terminals P, O, and N connected to a DC power source or a DC device, and AC side terminals R, S, and T connected to an AC power source or an AC device, and a control unit 6 that controls the operation of the power conversion circuit.

[0017] The power conversion circuit 1 is arranged in the order of an inductor 2, a main converter 3, and a capacitor circuit 5 from the AC terminals (R, S, T) toward the DC terminals (P, O, N). The power conversion circuit 1 is characterized by having multiple sub-modules 7 shown in FIG. 1B connected in series, and a sub-converter 4 arranged between the neutral points O of the main converter 3 and the capacitor circuit 5.

[0018] By outputting multi-level voltages from the AC output terminals (R, S, T) of the main converter 3, a voltage equal to the difference between the multi-level voltages and the AC terminal voltage is applied to the inductor 2 connected between the main converter 3 and the AC terminals (R, S, T). The sub-converter 4 is connected between the neutral point O of the DC terminal and the DC terminal of the main converter 3. The positive terminal P and negative terminal N of the DC terminal are connected to the terminals of the main converter 3, respectively. The main converter 3 can output multi-level voltages by outputting voltages corresponding to the positive voltage, negative voltage, and output terminal voltage of the sub-converter 4.

[0019] In FIG. 1A, the main converter 3 is shown as a power conversion circuit 1 capable of bidirectional power conversion using an active neutral point clamping method. However, a configuration capable of unidirectional power conversion is also possible. In this case, the semiconductor switching elements of the main converter 3 can be replaced with diodes to reduce the number of semiconductor switching elements. In FIG. 1B, the sub-converter 4 is configured such that each sub-module 7 is a two-level full-bridge converter incorporating at least one capacitor, and at least one sub-module 7 is connected between the main converter 3 and the neutral point O of each of the capacitor circuits 5. If the neutral point voltage is the reference potential (GND, 0 V), the output terminal voltage of the sub-converter 4 is the positive voltage, negative voltage, or 0 V of the capacitor voltage Vsx of the sub-converter 4.

[0020] The control unit 6 controls the opening and closing (off and on) of the switches of the main converter 3 and the sub-converter 4 based on information such as the AC output terminal voltages vr, vs, vt, the positive side capacitor voltage Vmp, the negative side capacitor voltage Vmn, the capacitor voltages Vsr, Vss, Vst (denoted as "Vsx" in FIG. 1B) of the sub-converter 4, and the inductor currents ir, is, it.

[0021] The control unit 6 controls the capacitor voltages of the sub-converter 4. The control unit 6 also controls the positive and negative voltages. The control unit 6 also controls the inductor currents. Note that the state quantities to be controlled may vary depending on the systems (voltage sources, current sources, passive components) connected to the input and output.

[0022] The main converter 3 and the sub-converter 4 are not limited to the illustrated configurations, and may be of a two-level type, a diode clamp type, a flying capacitor type, a T-type type, a neutral point clamp type, or the like, and may have any number of output levels other than two or three levels. However, the main converter 3 must be configured to be connectable to the neutral point, and the sub-converter 4 is connected between the neutral point connection point of the main converter 3 and the neutral point of the capacitor circuit 5. The capacitor Csx of the sub-converter 4 may be an external power source such as a battery. When limiting power conversion to unidirectional AC to DC only, some of the semiconductor switching elements of the main converter 3 and the sub-converter 4 may be replaced with diodes.

[0023] The semiconductor switching element may be a silicon (Si)-based or silicon carbide (SiC)-based metal-oxide-semiconductor field-effect transistor (MOSFET) or insulated gate bipolar transistor (IGBT), or may be a gallium nitride (GaN)-based power transistor or a gallium oxide (GaO)-based power transistor. Although the symbol shows one semiconductor switching element, multiple elements may be connected in parallel or in series to increase the current capacity or withstand voltage. When multiple elements are connected in parallel or in series, the semiconductor switching elements may be a mixture of the above-mentioned silicon-based IGBTs and silicon carbide-based MOSFETs.

[0024] As long as the inductor 2 connected between the AC terminal and the main converter 3 has at least one inductor L, other passive components may be connected in series or parallel to the inductor 2. An LC filter, an LCL filter, or the like may be connected to remove harmonic switching noise. Also, a damping circuit may be provided to suppress filter resonance.

[0025] The control unit 6 may have one or more controllers (control devices). For example, separate controllers may be applied to the main converter 3 and the sub-converter 4, or separate controllers may be used for the main converter 3 and the sub-converter 4 corresponding to each phase. Communication between the controllers may be either wired or wireless. Furthermore, the current detection value, voltage detection value, temperature detection value, gate signal, etc. of the power conversion circuit 1 may be connected to the control unit 6 by wire or wirelessly.

[0026] The control unit 6 is configured with a CPU (Central Processing Unit), DSP (Digital Signal Processor), FPGA (Field-Programmable Gate Array), analog circuitry, etc. Control may be applied so that the positive and negative voltages are the same voltage. The control unit 6 controls the capacitor voltage Vsx of the sub-converter 4 to a predetermined voltage by controlling the difference voltage between the positive and negative voltages to zero. The control unit 6 controls each voltage using proportional-integral (PI) control, etc., so that the target voltage and the voltage detected by the voltage detection means approach each other.

[0027] The voltage detection means may directly detect the voltages across the positive and negative capacitors Cmp and Cmn as the positive and negative voltages. The negative and positive voltages may be estimated by subtracting the positive and negative capacitor voltages Vmp and Vmn from the voltages at the positive and negative terminals. The capacitor voltage Vsx of the sub-converter 4 may be estimated from the capacitor current value. To reduce the number of voltage sensors, the capacitor voltage Vsx of the sub-converter 4 may be estimated from the switching patterns of the main converter 3 and the sub-converter 4, the inductor currents ir, is, it, the positive and negative voltages, etc.

[0028] Furthermore, in order to control the input / output power, the control unit 6 may detect the inductor currents ir, is, and it, perform dq (direct / quadrature) conversion, and control the dq converted current using PI control or the like. It may also detect the inductor currents of all three phases. It may also detect the inductor currents of two phases and calculate the current of the third phase based on Kirchhoff's first law. It may also detect the AC voltages of all three phases and synchronize the phases using a PLL (phase locked loop). It may also detect the AC voltage of only one phase and calculate the AC voltage that is not detected by utilizing the 120-degree phase shift between the phases.

[0029] To reduce the number of current sensors, the inductor currents ir, is, and it may be estimated from the inductor voltage, the AC terminal voltage, the main converter output voltage command value in the control unit 6, etc. A device composed of passive components, electronic components, semiconductor switching elements, etc. may be connected to the AC terminal end, and the output terminal of this device may be connected to the DC terminal. In other words, a common mode filter, a normal mode filter, a sub-module, etc. may be connected.

[0030] Similarly, an output terminal from the above-mentioned device connected to the DC side terminal may be connected to the AC side terminal. The AC side terminal may be connected to, for example, a motor, a generator, an AC system, a load made of passive components, or an entity that acts like a current source or voltage source. The DC side terminal may be connected to, for example, a solar cell, a fuel cell, a storage battery, a load made of passive components, an LED (Light-Emitting Diode), a power conversion device, or an entity that acts like a current source or voltage source.

[0031] Although the AC terminal side is illustrated as three-phase, it may be single-phase or multi-phase, and there are no restrictions on the phase wiring system. In the case of a single-phase configuration, a half-bridge configuration or a full-bridge configuration may be considered. In the case of a three-phase configuration, a V-connection system may be used in which one phase is connected to the AC terminal and the neutral point. The voltages of the submodules 7 may all be the same voltage or may be different voltages. The modulation system of the submodules 7 may be any known modulation system used in single-phase circuits, such as bipolar modulation, unipolar modulation, or hybrid modulation.

[0032] The switching frequency of the main converter 3 may be set to the fundamental frequency of the AC side to reduce switching loss. The switching frequencies of the main converter 3 and sub-converter 4 may be set to different frequencies to reduce switching loss. To reduce loss in the main converter 3, a one-pulse voltage may be output from the main converter 3, and control may be applied in which the sub-converter 4 compensates for the differential voltage. However, the absolute value of the voltage output by the sub-converter 4 must be lower than the absolute values ​​of the positive and negative pole voltages.

[0033] When the power conversion circuit 1 is formed using the sub-converter 4 in which the number of sub-modules 7 per phase (n=1) is one, the circuit diagram of the power conversion circuit 1x for one phase is as shown in FIG. 2. In FIG. 2, the switching element (element S x1 ~S x4 ) is configured as a T-type system, but it may also be configured as a diode clamp system, a flying capacitor system, a neutral point clamp system, or the like.

[0034] When no submodule 7 is interposed between the main converter 3 and the neutral point O of the capacitor circuit 5, three levels of output are possible, but by interposing one submodule 7, it becomes possible to output five levels. Since five levels of output are possible, when the cases are classified by output voltage, there are six types of switching states as shown in FIG.

[0035] In each of the six switching states, the switching elements (elements S x1 ~S x4 ) and a switching element (element S x7 ~S x10 ) is opened or closed, that is, the switch setting is determined. In addition, in the table format of FIG. 3, from the left, the switching state, the output terminal voltage Vxo, the switching element (element S x1 ~S x4 , S x7 ~S x10 ) represents the respective switch setting (on (closed) is "1" and off (open) is "0").

[0036] In a power conversion device with a three-level circuit, the output terminal voltages were only +Vmp, 0, and -Vmn. However, by inserting a sub-converter 4 between the neutral point O, it becomes possible to output voltages of +Vmp, 0, and -Vmn as well as +Vsx and -Vsx as output terminal voltages, as shown in Figure 3, and furthermore, multi-level output becomes possible.

[0037] 4A to 4F show the conduction paths within the power conversion circuit 1x in each of the six switching states shown in FIG. 3. Here, the current direction from AC to DC (to the right) is considered positive. That is, FIGS. 4A to 4F show the case where the current direction is positive.

[0038] Switching state 1 is when the converter output terminal voltage Vxo is +Vmp. In switching state 1, as shown in Figure 4A, no current flows into capacitor Csx of submodule 7, so the capacitor voltage Vsx does not fluctuate. On the other hand, in the capacitor circuit 5 on the DC terminal side, current flows into capacitors Cmp and Cmn, so the capacitor voltages Vmp and Vmn increase.

[0039] Switching state 2 is when the converter output terminal voltage Vxo is +Vsx. In switching state 2, as shown in FIG. 4B , current flows into capacitor Csx of submodule 7, causing the capacitor voltage Vsx to increase. Meanwhile, in the capacitor circuit 5, current flows out of capacitor Cmp, causing the capacitor voltage Vmp to decrease, and current flows into capacitor Cmn, causing the capacitor voltage Vmn to increase.

[0040] Switching state 3 is the case where the converter output terminal voltage Vxo is 0 V. In switching state 3, as shown in Fig. 4C, no current flows through capacitor Csx of submodule 7, so the capacitor voltage Vsx does not change. On the other hand, in the capacitor circuit 5, current flows out of capacitor Cmp, causing the capacitor voltage Vmp to decrease, and current flows into capacitor Cmn, causing the capacitor voltage Vmn to increase.

[0041] Switching state 4 is the case where the converter output terminal voltage Vxo is 0 V. In switching state 4, as shown in Fig. 4D, no current flows through capacitor Csx of submodule 7, so the capacitor voltage Vsx does not change. On the other hand, in the capacitor circuit 5, current flows out of capacitor Cmp, causing the capacitor voltage Vmp to decrease, and current flows into capacitor Cmn, causing the capacitor voltage Vmn to increase.

[0042] Switching state 5 is when the converter output terminal voltage Vxo is -Vsx. In switching state 5, as shown in Figure 4E, current flows out of capacitor Csx of submodule 7, causing the capacitor voltage Vsx to decrease. Meanwhile, in capacitor circuit 5, current flows out of capacitor Cmp, causing the capacitor voltage Vmp to decrease, and current flows into capacitor Cmn, causing the capacitor voltage Vmn to increase.

[0043] Switching state 6 is when the converter output terminal voltage Vxo is -Vmp. In switching state 6, as shown in FIG. 4F, no current flows into capacitor Csx of submodule 7, so the capacitor voltage Vsx does not fluctuate. On the other hand, in capacitor circuit 5, current flows out of capacitors Cmp and Cmn, so the capacitor voltages Vmp and Vmn decrease.

[0044] By quickly switching between the above-described switching states, the output terminal voltage Vxo averaged over a certain period can be controlled.

[0045] 5 shows in tabular form the converter output terminal voltage Vxo relative to the switching state and current direction, the current direction, the charge / discharge state of the capacitor Csx of the sub-converter 4, and the charge / discharge states of the positive-side capacitor Cmp and negative-side capacitor Cmn. The direction in which current flows from the AC side to the DC side is positive (+), and the opposite direction is negative (-).

[0046] As shown in Figure 5, when the current direction is positive, the capacitor of sub-converter 4 is charged in switching state 2 and discharged in switching state 5. In other words, the capacitor voltage can be controlled by adjusting the time ratio between switching state 2 and switching state 5. The same applies when the current direction is negative.

[0047] When the current direction is positive, the capacitor Cmp on the DC positive side is charged in switching state 1 and discharged in the other switching states. The capacitor Cmn on the DC negative side is discharged in switching state 5 and charged in the other switching states. When the current direction is negative, this charge / discharge relationship is reversed. This makes it possible to control the voltage of the capacitor circuit 5 on the DC side by changing the time ratio of each switching state.

[0048] An example of the contents of the control unit 6 will be described with reference to Fig. 6. The control system 301 has a power factor adjustment function, a DC side capacitor voltage balancing function, a capacitor voltage balancing function within the submodule 7, and a multi-level generation function. The control system 301 has a PLL unit 302 that calculates the frequency and phase from the AC voltage, a coordinate conversion unit 303 that performs dq transformation on the three-phase voltage, i.e., converts three AC signals into two DC signals, and a coordinate conversion unit 304 that performs dq transformation on the three-phase current.

[0049] Furthermore, it includes an inductor current control unit (power factor control unit) 305 that controls the current of the inductor L so that the error between the current command value and the actual current becomes zero, and a pulse width modulation (PWM) unit 306 that generates a high-frequency switching signal to modulate the pulse width of the main converter 3. Furthermore, it also includes a voltage control unit 307 that controls the voltage of the capacitor circuit 5 so that the difference between the capacitor voltage Vmp and the capacitor voltage Vmn in the capacitor circuit 5 becomes zero, and a logic unit 308 that imparts a dead time to the switching signal to prevent failure due to element short-circuiting.

[0050] Furthermore, it is provided with a capacitor voltage control unit 309 that controls the capacitor voltage Vsx in the submodule 7 so that the error between the capacitor voltage Vsx connected to each module and the target voltage command value becomes zero, and a command value generation unit 310 that generates a command value for the subconverter 4. Furthermore, it is provided with a PWM unit 311 that generates a high-frequency switching signal, a dead time generation unit 312 that provides a dead time to prevent failure due to element short-circuiting in the subconverter 4, and a zero voltage generation unit 313 that generates a signal so that the voltage between the terminals of the subconverter 4 becomes zero.

[0051] The PLL unit 302 to the logic unit 308 are functions for controlling the main converter 3, and the capacitor voltage control unit 309 to the zero voltage generation unit 313 are functions added in this disclosure to control the sub-converter 4. In the case of a three-level circuit configuration, the output voltage level becomes three levels, and the voltage of the sub-converter 4 cannot be balanced. On the other hand, by adding the above-mentioned new functions, the output voltage level becomes multi-level, making it possible to balance the voltage of the sub-converter 4 and making it possible to miniaturize the device.

[0052] Although the PLL unit 302 detects three-phase voltages, it is also possible to configure the PLL by detecting only one phase. The coordinate conversion units 303 and 304 detect three-phase voltages and currents, but they may also configure dq coordinate conversion by detecting only one or two phases. An αβ coordinate conversion may be used for the coordinate conversion. Current control may be performed for each of the three phases without performing coordinate conversion. The power factor control unit 305 may improve the power factor by using a PI controller.

[0053] Current command value id in the dq coordinate system * , iq * The error currents of the detected current values ​​id and iq are converted into compensation voltages using a PI controller, and AC voltages Vd and Vq in the dq coordinate system are added to the compensation voltage, which is then divided by the DC voltage. As a result, a voltage command value to be output by the power conversion device in the dq coordinate system is generated, and a three-phase voltage command value is generated using the voltage phase θ.

[0054] The voltage control unit 307 calculates the difference between the detected values ​​of the capacitor voltages Vmn and Vmp. Then, a BEF (Band Elimination Filter) removes a frequency three times the AC power supply frequency from the signal, converting the signal into a compensation current using a PI controller, and dividing the current by the maximum value of the inductor current to calculate the compensation amount. By adding the compensation amount to the three-phase voltage command value calculated by the inductor current control unit (power factor control unit) 305, the charge / discharge amount of the capacitor circuit 5 is changed, and the differential voltage between the capacitor voltages Vmp and Vmn approaches zero.

[0055] The PWM unit 306 compares the magnitude of the three-phase voltage command value and the triangular wave (or sawtooth wave, etc.) to generate a pulse. The logic unit 308 adds a dead time to prevent short circuits in the elements, and controls the semiconductor switching elements (elements S x1 ~S x4 ) and outputs an ON / OFF signal to the

[0056] The capacitor voltage control unit 309 calculates the capacitor voltage command value Vsr * , Vss * , Vst * The error voltage (difference) between the detected values ​​of the capacitor voltages Vsr, Vss, and Vst is converted into a compensation current using a PI controller. The maximum value of the inductor current is then divided, and since the charge / discharge direction changes depending on the polarity of the current as shown in Figure 5, the polarity is changed depending on the current polarity.

[0057] Capacitor voltage command value Vsr * , Vss * , Vst * When the detected values ​​of the capacitor voltages Vsr, Vss, and Vst are small relative to the command value, the compensation amount becomes a positive value, and when the current polarity is positive, the period of switching state 2 becomes longer relative to switching state 5, and when the current polarity is negative, the period of switching state 2 becomes shorter relative to switching state 5, and the capacitor is charged and follows the command value.

[0058] The PWM unit 311 generates pulses for the sub-converter 4 based on the compensation amount and the three-phase voltage command value of the main converter 3. The logic unit 308 provides a dead time to prevent short circuits of the elements, and controls the semiconductor switching elements (elements S) of the sub-converter 4. x7 ~S x10 ) and outputs an ON / OFF signal for the sub-module 7. A dead time generation unit 312 generates a signal according to the number of elements in the sub-module 7 from the ON / OFF signal and adds a dead time to avoid failure due to element short-circuiting. A zero voltage generation unit 313 shifts the switching pulse according to the current direction to realize switching state 3 and switching state 4, in which the voltage between the terminals of the sub-converter 4 is zero.

[0059] The transition of the modes and switching states when the current direction is positive will be explained using Fig. 7A, and when the current direction is negative using Fig. 7B. The notations enclosed in the ovals indicate, from the left, the type of mode, the output terminal voltage Vxo, the element S x7 ~S x10 The open / closed settings of each switch are shown.

[0060] When the current direction is positive, seven modes (M1, M2, M3, M4a, M4b, M5, M6) are switched to output five levels, as shown in Figure 7A. When the current direction is negative, seven modes (M1, M2, M4c, M4d, M3, M5, M6) are switched to output five levels, as shown in Figure 7B. By using the zero voltage generator 313, four new modes (M4a, M4b, M4c, M4d) are added, which has the effect of enabling zero voltage output.

[0061] FIG. 8 shows the transition of modes when the current direction is positive as explained in FIG. 7A, using the current path in the circuit of FIG. 2, and FIG. 9 shows the transition of modes when the current direction is negative as explained in FIG. 7B, using the current path in the circuit of FIG. 2.

[0062] When the current direction is positive, the current flows from mode M3 to element S as shown in FIG. x8 By turning on only the element S x8 and element S x10 The current is commutated to the diode of the element S, and the element S can transition to a mode M4a that outputs zero voltage. x9 By turning on the element S x8 , capacitor Csx, element S x9 Therefore, it is possible to transition to mode M5, which outputs −Vxs.

[0063] Mode M5 to element S x8 By turning off the element S x7 From the diode to the element S x9 The current is commutated to the element S, and the mode transitions to mode M4b, which outputs zero voltage. x9 By turning off the element S x7 diode, capacitor Csx, element S x10The diodes are commutated in this order, and the mode transitions to mode M3, which outputs +Vsx.

[0064] When the current direction is negative, the current flows from mode M2 ​​to element S as shown in FIG. x10 By turning on only the element S x8 and element S x10 The current is commutated to the diode of the element S, and the element S can transition to a mode M4c that outputs zero voltage. x10 By turning off the element S x8 , capacitor Csx, element S x9 Therefore, it is possible to transition to mode M3 which outputs −Vsx.

[0065] Mode M3 to element S x7 By turning on the element S x9 From the diode to the element S x7 The current is commutated to the element S, and the element S can transition to mode M4d, which outputs zero voltage. x10 By turning on the element S x10 , capacitor Csx, element S x7 and transition to mode M2 ​​in which +Vsx is output.

[0066] Next, the transition of modes when the zero voltage generator 313 is provided and when it is not provided will be explained using Figs. 10A to 10D. Fig. 10A shows the time series change in the operation setting (mode) set for the switching element when the current direction is positive and the zero voltage generator 313 is not provided, and Fig. 10B shows the time series change in the mode within the submodule 7 when the current direction is positive and the zero voltage generator 313 is provided. Fig. 10C shows the time series change in the switch operation when the current direction is negative and the zero voltage generator 313 is not provided, and Fig. 10D shows the time series change in the mode within the submodule 7 when the current direction is negative and the zero voltage generator 313 is provided. In Figs. 10A to 10D, from top to bottom, the elements S x7 ~S x10 The bottom row shows the output voltage for each switch setting.

[0067] If the zero voltage generating unit 313 is not provided, none of the four modes (M4a, M4b, M4c, M4d) exists, and only +Vsx or −Vsx can be output, as shown in FIGS. 10A and 10C. x9 Or element S x10 10B and 10D, four modes (M4a, M4b, M4c, M4d) can be generated by applying the zero voltage generator 313 that delays the switching of the inverter. This makes it possible to output zero voltage.

[0068] The control unit 6 of the present disclosure, or the multiple controllers that make up the control unit 6, can be configured from a processor 6H0 and a storage device 6H1, as shown in FIG. 11 , which is an example of hardware 6H. Although the storage device is not shown, it may include a volatile storage device such as a random access memory and a non-volatile auxiliary storage device such as a flash memory. Alternatively, a hard disk auxiliary storage device may be used instead of the flash memory. The processor 6H0 executes a program input from the storage device 6H1. In this case, the program is input from the auxiliary storage device to the processor 6H0 via the volatile storage device. The processor 6H0 may output data such as calculation results to the volatile storage device of the storage device 6H1, or may store data in the auxiliary storage device via the volatile storage device. The processor 6H0 may have a communication function, or may include a communication unit (not shown).

[0069] Although various exemplary embodiments and examples are described in this disclosure, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless variations not illustrated are anticipated within the scope of the technology disclosed in this disclosure specification. For example, this includes cases where at least one component is modified, added, or omitted, or where at least one component is extracted and combined with components of another embodiment.

[0070] As described above, the power conversion device 10 of the present disclosure includes the inductor 2 provided for each phase (R, S, T) on the AC side, the main converter 3 having one end connected to the inductor 2 and the other end to which a DC positive pole (P), a DC negative pole (N), and a DC neutral point (O) are set, the capacitor circuit 5 having a positive pole terminal (P), a negative pole terminal (N), and a DC neutral point (O) connected to the DC side, the capacitor Csx, and a plurality of semiconductor switching elements (elements S x7 ~Sx 10 ) and is connected between the neutral point (O) of the capacitor circuit 5 and the neutral point (O) of the main converter 3, and includes a plurality of semiconductor switching elements (elements S x7 ~Sx 10 The power supply includes a sub-converter 4 whose capacitor voltage Vsx changes according to the combination of open / close settings (switching states 1 to 6, modes M1 to M6) for the main converter 3, and a control unit 6 that controls the operation of the main converter 3 and the sub-converter 4. This allows the sub-converter 4 to be configured using low-voltage semiconductor switching elements, making it possible to output multi-level voltages without increasing the size and weight of the device.

[0071] If the control unit 6 is configured to control the absolute value of the capacitor voltage Vsx so that it is lower than the absolute value of the voltage (capacitor voltage Vmp) at the positive terminal (P) of the capacitor circuit 5 and the absolute value of the voltage (capacitor voltage Vmn) at the negative terminal (N), the voltages are balanced, thereby stabilizing operation.

[0072] The control unit 6 controls the sub-converter 4 so that the combination of open / close settings (modes M1 to M6) at which the output voltage of the sub-converter 4 is zero varies depending on the direction of the current flowing through the inductor 2. x7 ~S x10 The imbalance in behavior between the two is smoothed out.

[0073] The control unit 6 controls a plurality of semiconductor switching elements (elements S x7 ~S x10 ) by delaying the opening and closing operation of at least one element relative to the other elements by an amount of time corresponding to the period during which the output voltage of the sub-converter 4 is set to zero, the zero voltage period can be reliably controlled.

[0074] The control unit 6 selects different elements as targets for delaying the opening and closing operation depending on the direction of the current flowing through the inductor 2. x7 ~S x10 The imbalance in behavior between the two is smoothed out.

[0075] The sub-converter 4 forms a full-bridge circuit, and the control unit 6 controls the sub-converter 4 so as to insert a delay corresponding to the period during which the output voltage is set to zero in the switching signal of the upper semiconductor switching element or the lower semiconductor switching element depending on the direction of the current flowing through the inductor 2 for one leg of the full-bridge circuit, thereby making it possible to more reliably control the zero period.

[0076] The sub-converter 4 includes four semiconductor switching elements S x7 ~S x10 and the capacitor Csx, the capacitor voltage Vsx can be reliably controlled.

[0077] If the main converter 3 is a T-type converter including at least two semiconductor switching elements and two semiconductor rectifying elements, it is possible to reliably provide a multi-level output.

[0078] 1: Power conversion circuit, 2: Inductor, 3: Main converter, 4: Sub-converter, 5: Capacitor circuit, 6: Control unit, 7: Sub-module, 10: Power conversion device, Csx: Capacitor, S x1 ~S x4 , S x7 ~S x10 : element (semiconductor switching element), Vsr, Vss, Vst, Vsx: capacitor voltages.

Claims

1. an inductor provided for each phase on the AC side; a main converter having one end connected to the inductor and the other end to which a DC positive pole, a DC negative pole, and a DC neutral point are set; a capacitor circuit having a positive terminal connected to the DC side, a negative terminal, and a neutral point; a sub-converter including a capacitor and a plurality of semiconductor switching elements, connected between a neutral point of the capacitor circuit and a neutral point of the main converter, in which a capacitor voltage changes according to a combination of open / close settings of the plurality of semiconductor switching elements; a control unit that controls the operations of the main converter and the sub-converter; A power conversion device comprising:

2. 2. The power conversion device according to claim 1, wherein the control unit controls the capacitor voltage so that the absolute value of the capacitor voltage is lower than the absolute value of the voltage at the positive terminal and the absolute value of the voltage at the negative terminal of the capacitor circuit.

3. 3. The power conversion device according to claim 1, wherein the control unit controls the sub-converter so that the combination of opening and closing settings that results in the output voltage of the sub-converter being zero varies depending on the direction of the current flowing through the inductor.

4. The power conversion device according to claim 1 or 2, characterized in that the control unit targets at least one of the plurality of semiconductor switching elements and delays the opening and closing operation of other elements by a time period corresponding to the period during which the output voltage of the sub-converter is set to zero.

5. The power conversion device according to claim 4 , wherein the control unit selects different elements as targets for delaying the switching operation depending on the direction of current flowing through the inductor.

6. the sub-converter forms a full-bridge circuit, 4. The power conversion device according to claim 3, wherein the control unit controls the sub-converter so as to insert a delay of a time corresponding to a period during which the output voltage is set to zero in a switching signal of an upper semiconductor switching element or a lower semiconductor switching element depending on a direction of a current flowing through the inductor for one leg of the full bridge circuit.

7. 3. The power conversion device according to claim 1, wherein the sub-converter is a full-bridge circuit including four elements as the plurality of semiconductor switching elements and the capacitor.

8. 3. The power conversion device according to claim 1, wherein the main converter is a T-type converter including at least two semiconductor switching elements and two semiconductor rectifying elements.