Silicon carbide epitaxial substrate, method for manufacturing silicon carbide semiconductor device, and method for manufacturing silicon carbide epitaxial substrate

Abstract

This silicon carbide epitaxial substrate is provided with a silicon carbide substrate, a first silicon carbide epitaxial layer and a second silicon carbide epitaxial layer. A first main surface of the first silicon carbide epitaxial layer is in contact with the silicon carbide substrate. A second main surface of the second silicon carbide epitaxial layer is in contact with the silicon carbide substrate. The thickness of the first silicon carbide epitaxial layer is greater than the thickness of the second silicon carbide epitaxial layer. In a plan view, the area density of recesses in a central square region in the second silicon carbide epitaxial layer is 5 mm-2 or less. The length of one side of the central square region is 5 mm. In the plan view, the maximum width of the recesses is 10 μm to 100 μm inclusive.

Description

Silicon carbide epitaxial substrate, method for manufacturing silicon carbide semiconductor device, and method for manufacturing silicon carbide epitaxial substrate

[0001] The present disclosure relates to a silicon carbide epitaxial substrate, a method for manufacturing a silicon carbide semiconductor device, and a method for manufacturing a silicon carbide epitaxial substrate. This application claims priority to Japanese Patent Application No. 2023-099394, filed on June 16, 2023. The entire contents of this Japanese patent application are incorporated herein by reference.

[0002] Japanese Patent Laid-Open Publication No. 2016-149496 (Patent Document 1) discloses a susceptor on which a coating layer made of diamond is formed.

[0003] JP 2016-149496 A

[0004] A silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate, a first silicon carbide epitaxial layer, and a second silicon carbide epitaxial layer. The silicon carbide substrate has a first main surface and a second main surface opposite the first main surface. The first silicon carbide epitaxial layer contacts the silicon carbide substrate at the first main surface. The second silicon carbide epitaxial layer contacts the silicon carbide substrate at the second main surface. The thickness of the first silicon carbide epitaxial layer is greater than the thickness of the second silicon carbide epitaxial layer. In a plan view, the areal density of recesses in a central square region of the second silicon carbide epitaxial layer is 5 mm -2 The length of one side of the central square region is 5 mm. In plan view, the maximum width of the recess is 10 μm or more and 100 μm or less.

[0005] FIG. 1 is a plan view schematic showing the configuration of the front surface of a silicon carbide epitaxial substrate according to this embodiment. FIG. 2 is a cross-sectional view schematic showing the configuration of the back surface of a silicon carbide epitaxial substrate according to this embodiment. FIG. 3 is a cross-sectional view schematic showing the configuration of the back surface of a silicon carbide epitaxial substrate according to this embodiment. FIG. 4 is an enlarged view of region IV in FIG. 3. FIG. 5 is a cross-sectional view schematic showing the configuration of a silicon carbide epitaxial substrate manufacturing apparatus. FIG. 7 is a flowchart outlining a method for manufacturing a silicon carbide epitaxial substrate according to this embodiment. FIG. 8 is a cross-sectional view schematic showing the configuration of a susceptor. FIG. 9 is a cross-sectional view schematic showing the step of forming a silicon carbide coating layer on a susceptor. FIG. 10 is a cross-sectional view schematic showing the step of placing a silicon carbide substrate on a susceptor. FIG. 11 is a cross-sectional view schematic showing the step of forming a silicon carbide epitaxial layer on a silicon carbide substrate. Fig. 12 is a flowchart schematically showing a method for manufacturing a silicon carbide semiconductor device according to this embodiment. Fig. 13 is a cross-sectional view schematically showing a step of preparing a silicon carbide epitaxial substrate. Fig. 14 is a cross-sectional view schematically showing a step of forming a body region. Fig. 15 is a cross-sectional view schematically showing a step of forming a source region. Fig. 16 is a cross-sectional view schematically showing a step of forming a trench in a third main surface of the first silicon carbide epitaxial layer. Fig. 17 is a cross-sectional view schematically showing a step of forming a gate insulating film. Fig. 18 is a cross-sectional view schematically showing a step of forming a gate electrode and an interlayer insulating film. Fig. 19 is a cross-sectional view schematically showing a configuration of the silicon carbide semiconductor device according to this embodiment.

[0006] [Problem to be Solved by the Present Disclosure] An object of the present disclosure is to provide a silicon carbide epitaxial substrate, a method for manufacturing a silicon carbide semiconductor device, and a method for manufacturing a silicon carbide epitaxial substrate that are capable of improving the yield of silicon carbide semiconductor devices. [Effects of the Present Disclosure] According to the present disclosure, it is possible to provide a silicon carbide epitaxial substrate, a method for manufacturing a silicon carbide semiconductor device, and a method for manufacturing a silicon carbide epitaxial substrate that are capable of improving the yield of silicon carbide semiconductor devices.

[0007] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described.

[0008] (1) A silicon carbide epitaxial substrate 100 according to the present disclosure includes a silicon carbide substrate 30, a first silicon carbide epitaxial layer 10, and a second silicon carbide epitaxial layer 20. The silicon carbide substrate 30 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first silicon carbide epitaxial layer 10 contacts the silicon carbide substrate 30 at the first main surface 1. The second silicon carbide epitaxial layer 20 contacts the silicon carbide substrate 30 at the second main surface 2. The thickness of the first silicon carbide epitaxial layer 10 is greater than the thickness of the second silicon carbide epitaxial layer 20. In a plan view, the areal density of the recesses 5 in a central square region 4 of the second silicon carbide epitaxial layer 20 is 5 mm -2 The length of one side of the central square region 4 is 5 mm. In plan view, the maximum width of the recess 5 is 10 μm or more and 100 μm or less.

[0009] (2) According to silicon carbide epitaxial substrate 100 according to (1) above, recess 5 may have an outer shape that is arc-shaped in plan view.

[0010] (3) According to the silicon carbide epitaxial substrate 100 according to (1) or (2) above, the surface density of the recesses 5 in the central square region is 4 mm -2 It may be the following:

[0011] (4) In silicon carbide epitaxial substrate 100 according to any one of (1) to (3) above, second silicon carbide epitaxial layer 20 may have a thickness of 0.1 μm or more and 5 μm or less.

[0012] (5) A method for manufacturing a silicon carbide semiconductor device according to the present disclosure includes the following steps: Silicon carbide epitaxial substrate 100 according to any one of (1) to (4) above is prepared. An electrode is formed on first silicon carbide epitaxial layer 10.

[0013] (6) The method for manufacturing silicon carbide epitaxial substrate 100 according to the present disclosure includes the following steps: A silicon carbide coating layer 70 is formed on susceptor 210 without silicon carbide substrate 30 being placed thereon. The silicon carbide substrate 30 is placed on susceptor 210 so that the silicon carbide substrate 30 is in contact with the silicon carbide coating layer 70. A silicon carbide epitaxial layer 40 is formed on the silicon carbide substrate 30.

[0014] (7) According to the method for manufacturing silicon carbide epitaxial substrate 100 in accordance with (6) above, silicon carbide particles 9 may be present on susceptor 210. The thickness of silicon carbide coating layer 70 may be greater than the height of silicon carbide particles 9.

[0015] [Details of the Embodiments of the Present Disclosure] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the same or corresponding parts in the following drawings are given the same reference numerals, and their description will not be repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. Furthermore, for negative indices, in crystallography, a "-" (bar) is placed before the number, but in this specification, a negative sign is placed before the number.

[0016] (Silicon Carbide Epitaxial Substrate) FIG. 1 is a plan view schematic showing the configuration of the surface of a silicon carbide epitaxial substrate according to this embodiment. FIG. 2 is a cross-sectional view schematic taken along line II-II in FIG. 1 . As shown in FIGS. 1 and 2 , a silicon carbide epitaxial substrate 100 according to this embodiment has a silicon carbide substrate 30, a first silicon carbide epitaxial layer 10, and a second silicon carbide epitaxial layer 20. The silicon carbide substrate 30 has a first main surface 1 and a second main surface 2. The second main surface 2 is opposite to the first main surface 1. The first silicon carbide epitaxial layer 10 contacts the silicon carbide substrate 30 at the first main surface 1. The second silicon carbide epitaxial layer 20 contacts the silicon carbide substrate 30 at the second main surface 2.

[0017] As shown in Figure 2, first silicon carbide epitaxial layer 10 has third main surface 11 and fourth main surface 12. Third main surface 11 constitutes the surface of silicon carbide epitaxial substrate 100. Fourth main surface 12 is opposite third main surface 11. Fourth main surface 12 is in contact with first main surface 1. Second silicon carbide epitaxial layer 20 has fifth main surface 21 and sixth main surface 22. Sixth main surface 22 is opposite fifth main surface 21. Sixth main surface 22 is in contact with second main surface 2. Fifth main surface 21 constitutes the back surface of silicon carbide epitaxial substrate 100.

[0018] As shown in Figure 1, silicon carbide epitaxial substrate 100 has an outer peripheral edge 8. Outer peripheral edge 8 has, for example, an orientation flat 6 and an arc-shaped portion 7. As shown in Figure 1, orientation flat 6 is linear in plan view. Note that the plan view is a field of view seen along a direction from first main surface 1 toward second main surface 2. Orientation flat 6 extends along first direction 101. Arc-shaped portion 7 is continuous with orientation flat 6. In plan view, arc-shaped portion 7 is arc-shaped.

[0019] 1 , in a plan view, third main surface 11 extends along each of first direction 101 and second direction 102. In a plan view, second direction 102 is a direction perpendicular to first direction 101. Third direction 103 is a direction along the thickness of silicon carbide epitaxial substrate 100. Third direction 103 is perpendicular to each of first direction 101 and second direction 102.

[0020] The first direction 101 is, for example, the <11-20> direction. The first direction 101 may be, for example, the [11-20] direction. The first direction 101 may be, for example, a direction obtained by projecting the <11-20> direction onto the third main surface 11. From another perspective, the first direction 101 may be, for example, a direction including a <11-20> direction component.

[0021] The second direction 102 is, for example, the <1-100> direction. The second direction 102 may be, for example, the [1-100] direction. The second direction 102 may be, for example, a direction obtained by projecting the <1-100> direction onto the third main surface 11. From another perspective, the second direction 102 may be, for example, a direction including a <1-100> direction component.

[0022] The third main surface 11 may be a {0001} plane or a plane inclined with respect to the {0001} plane. When the third main surface 11 is inclined with respect to the {0001} plane, the inclination angle (off angle) with respect to the {0001} plane is, for example, greater than 0° and equal to or less than 8°. When the third main surface 11 is inclined with respect to the {0001} plane, the inclination direction (off direction) of the third main surface 11 is, for example, the <11-20> direction. The off angle may be equal to or greater than 2° and equal to or less than 6°.

[0023] As shown in FIG. 1 , the maximum diameter W1 of the third main surface 11 is not particularly limited, but is, for example, 100 mm (4 inches) or more. The maximum diameter W1 may be 125 mm (5 inches) or more, 150 mm (6 inches) or more, or 200 mm (8 inches) or more. The maximum diameter W1 may be, for example, 400 mm (16 inches) or less. In a plan view, the maximum diameter W1 is the longest linear distance between two different points on the outer circumferential edge 8.

[0024] As used herein, 4 inches refers to 100 mm or 101.6 mm (4 inches x 25.4 mm / inch). 6 inches refers to 150 mm or 152.4 mm (6 inches x 25.4 mm / inch). 8 inches refers to 200 mm or 203.2 mm (8 inches x 25.4 mm / inch). 16 inches refers to 400 mm or 406.4 mm (16 inches x 25.4 mm / inch).

[0025] 2, the thickness of first silicon carbide epitaxial layer 10 is defined as a first thickness H1. The thickness of second silicon carbide epitaxial layer 20 is defined as a second thickness H2. First thickness H1 is greater than second thickness H2.

[0026] The thickness of first silicon carbide epitaxial layer 10 is not particularly limited, but may be, for example, 5 μm or more, or 10 μm or more. The thickness of first silicon carbide epitaxial layer 10 is not particularly limited, but may be, for example, 100 μm or less, 50 μm or more, or 30 μm or less.

[0027] The thickness of second silicon carbide epitaxial layer 20 may be, for example, 0.1 μm or more and 5 μm or less. The thickness of second silicon carbide epitaxial layer 20 is not particularly limited, but may be, for example, 0.5 μm or more, or 1 μm or more. The thickness of second silicon carbide epitaxial layer 20 is not particularly limited, but may be, for example, 4 μm or less, or 3 μm or less.

[0028] Silicon carbide substrate 30 has a thickness designated as third thickness H3. Third thickness H3 may be greater than each of first thickness H1 and second thickness H2. Third thickness H3 is, for example, not less than 200 μm and not more than 600 μm. Third thickness H3 is not particularly limited, but may be, for example, not less than 250 μm or not less than 300 μm. Third thickness H3 is not particularly limited, but may be, for example, not more than 500 μm or not more than 350 μm.

[0029] Silicon carbide substrate 30 contains an n-type impurity such as nitrogen. The conductivity type of silicon carbide substrate 30 is, for example, n-type. Similarly, first silicon carbide epitaxial layer 10 and second silicon carbide epitaxial layer 20 each contain an n-type impurity such as nitrogen (N). The conductivity type of first silicon carbide epitaxial layer 10 and second silicon carbide epitaxial layer 20 is, for example, n-type.

[0030] The concentration of n-type impurities in silicon carbide substrate 30 may be higher than the concentration of n-type impurities in each of first silicon carbide epitaxial layer 10 and second silicon carbide epitaxial layer 20. The polytype of silicon carbide constituting silicon carbide substrate 30 is, for example, 4H. Similarly, the polytype of silicon carbide constituting each of first silicon carbide epitaxial layer 10 and second silicon carbide epitaxial layer 20 is, for example, 4H.

[0031] 3 is a plan view schematically illustrating the configuration of the back surface of silicon carbide epitaxial substrate 100 according to this embodiment. Second silicon carbide epitaxial layer 20 has a central square region 4. Central square region 4 is a square region centered at center 3 of fifth main surface 21. The length of one side of central square region 4 is 5 mm. Central square region 4 has a first side and a second side. In plan view, the first side is parallel to first direction 101. In plan view, the second side is parallel to second direction 102.

[0032] Fig. 4 is an enlarged view of region IV in Fig. 3. As shown in Fig. 4, one or more recesses 5 are formed in central square region 4 of second silicon carbide epitaxial layer 20. In plan view, maximum width W2 of recess 5 is 10 µm or more and 100 µm or less. Maximum width W2 of recess 5 is not particularly limited, but may be, for example, 20 µm or more or 30 µm or less. Maximum width W2 of recess 5 is not particularly limited, but may be 90 µm or less or 80 µm or less.

[0033] In a plan view, the outer shape of the recess 5 is, for example, circular. In a plan view, the outer shape of the recess 5 may be, for example, a perfect circle, an ellipse, or a shape other than a circle. In a plan view, the outer shape of the recess 5 has an arc-shaped portion. Specifically, the outer shape of the recess 5 may have a first outer shape portion 51 and a second outer shape portion 52. The first outer shape portion 51 is arc-shaped. The second outer shape portion 52 is, for example, V-shaped. The central angle of the arc-shaped first outer shape portion 51 may be, for example, 90° or more, 135° or more, or 180° or more. The second outer shape portion 52 may be connected to both ends of the arc-shaped first outer shape portion 51.

[0034] Fig. 5 is a schematic cross-sectional view taken along line VV in Fig. 4. As shown in Fig. 5, silicon carbide particles 9 may be present on second main surface 2 of silicon carbide substrate 30. Recesses 5 are formed due to silicon carbide particles 9. When second silicon carbide epitaxial layer 20 is formed on second main surface 2, second silicon carbide epitaxial layer 20 is not formed on silicon carbide particles 9. Therefore, recesses 5 of second silicon carbide epitaxial layer 20 are formed on silicon carbide particles 9.

[0035] The bottom surface of the recess 5 may be formed by the silicon carbide particles 9. The bottom surface of the recess 5 may be curved outward so that the center protrudes. The inner wall surface of the recess 5 may be formed by the second silicon carbide epitaxial layer 20. The silicon carbide particles 9 are approximately spherical. The height T (see FIG. 5 ) of the silicon carbide particles 9 in a direction perpendicular to the second main surface 2 is the diameter of the silicon carbide particles 9. The diameter of the silicon carbide particles 9 is substantially the same as the height of the silicon carbide particles 9. The height T of the silicon carbide particles 9 may be smaller than the second thickness H2 or may be the same as the second thickness H2.

[0036] In plan view, the surface density of the recesses 5 in the central square region 4 is 5 mm -2 In plan view, the surface density of the recesses 5 in the central square region 4 is not particularly limited, but may be, for example, 4 mm -2 It may be less than 3 mm -2 In plan view, the surface density of the recesses 5 in the central square region 4 is not particularly limited, but may be, for example, 1 mm -2 It may be 2 mm or more. -2 It may be more than that.

[0037] Next, a method for measuring the surface density of the recesses 5 will be described. The surface density of the recesses 5 can be determined using a WASAVI series "SICA 6X" confocal differential interference microscope manufactured by Lasertec Corporation. Light with a wavelength of 546 nm is irradiated onto the fifth main surface 21 of the silicon carbide epitaxial substrate 100 from a mercury xenon lamp light source, and the reflected light of the light is observed by a light-receiving element. An image of the fifth main surface 21 of the second silicon carbide epitaxial layer 20 is thus acquired. The magnification of the objective lens is set to 10x. The threshold, which is an index of the measurement sensitivity of the SICA, is set to ThreshS40. The number of recesses 5 in the central square region 4 of the fifth main surface 21 is measured. The surface density of the recesses 5 is determined by dividing the number of recesses 5 in the central square region 4 by the area of ​​the central square region 4.

[0038] (Apparatus for Manufacturing Silicon Carbide Epitaxial Substrate) Next, the configuration of an apparatus for manufacturing silicon carbide epitaxial substrate 100 will be described. FIG. 6 is a partial cross-sectional schematic diagram showing the configuration of an apparatus for manufacturing silicon carbide epitaxial substrate 100. Apparatus 200 for manufacturing silicon carbide epitaxial substrate is, for example, a hot-wall horizontal CVD (Chemical Vapor Deposition) apparatus. As shown in FIG. 6, apparatus 200 for manufacturing silicon carbide epitaxial substrate 100 mainly includes a reaction chamber 201, a gas supply unit 235, a control unit 245, a heating element 203, a quartz tube 204, a heat insulating material (not shown), and an induction heating coil (not shown).

[0039] The heating element 203 has, for example, a cylindrical shape, and defines a reaction chamber 201 therein. The heating element 203 is made of, for example, graphite. The heating element 203 is provided inside a quartz tube 204. A heat insulating material surrounds the outer periphery of the heating element 203. The induction heating coil is wound, for example, along the outer periphery of the quartz tube 204. The induction heating coil is configured so that an alternating current can be supplied to it from an external power source (not shown). This causes the heating element 203 to be induction heated. As a result, the reaction chamber 201 is heated by the heating element 203.

[0040] The reaction chamber 201 is a space surrounded by an inner wall surface 205 of a heating element 203. A susceptor 210 that holds a silicon carbide substrate 30 is provided in the reaction chamber 201. The susceptor 210 is made of silicon carbide. The silicon carbide substrate 30 is placed on the susceptor 210. The susceptor 210 is placed on a stage 202. The stage 202 is rotatably supported by a rotation shaft 209. The rotation of the stage 202 causes the susceptor 210 to rotate.

[0041] Manufacturing apparatus 200 for silicon carbide epitaxial substrate 100 further includes gas inlet 207 and gas outlet 208. Gas outlet 208 is connected to an exhaust pump (not shown). The hollow arrows in FIG. 6 indicate the flow of gas. Gas is introduced into reaction chamber 201 from gas inlet 207 and exhausted from gas exhaust outlet 208. The pressure inside reaction chamber 201 is adjusted by balancing the amount of gas supplied and the amount of gas exhausted.

[0042] The gas supply unit 235 is configured to be able to supply a mixed gas containing a source gas, a dopant gas, and a carrier gas to the reaction chamber 201. Specifically, the gas supply unit 235 includes, for example, a first gas supply unit 231, a second gas supply unit 232, a third gas supply unit 233, and a fourth gas supply unit 234.

[0043] The first gas supply unit 231 is configured to be able to supply a first gas containing, for example, carbon (C) atoms. The first gas supply unit 231 is, for example, a gas cylinder filled with the first gas. The first gas is, for example, propane (C3H8) gas. The first gas may also be, for example, methane (CH4) gas, ethane (C2H6) gas, acetylene (C2H2) gas, etc.

[0044] The second gas supply unit 232 is configured to be able to supply a second gas containing, for example, silane (SiH) gas. The second gas supply unit 232 is, for example, a gas cylinder filled with the second gas. The second gas is, for example, silane gas. The second gas may be a mixed gas of silane gas and a gas other than silane.

[0045] The third gas supply unit 233 is configured to be able to supply a third gas containing, for example, nitrogen atoms. The third gas supply unit 233 is, for example, a gas cylinder filled with the third gas. The third gas is a doping gas. The third gas is, for example, ammonia gas. Ammonia gas is more susceptible to thermal decomposition than nitrogen gas, which has a triple bond.

[0046] The fourth gas supply unit 234 is configured to be able to supply a fourth gas (carrier gas) such as hydrogen, for example. The fourth gas supply unit 234 is, for example, a gas cylinder filled with hydrogen.

[0047] The control unit 245 is configured to be able to control the flow rate of the mixed gas supplied from the gas supply unit 235 to the reaction chamber 201. Specifically, the control unit 245 may include a first gas flow rate control unit 241, a second gas flow rate control unit 242, a third gas flow rate control unit 243, and a fourth gas flow rate control unit 244. Each control unit may be, for example, an MFC (Mass Flow Controller). The control unit 245 is disposed between the gas supply unit 235 and the gas inlet 207.

[0048] (Method of Manufacturing Silicon Carbide Epitaxial Substrate) Next, a method of manufacturing silicon carbide epitaxial substrate 100 according to this embodiment will be described. FIG. 7 is a flowchart that schematically shows the method of manufacturing silicon carbide epitaxial substrate 100 according to this embodiment. As shown in FIG. 7 , the method of manufacturing silicon carbide epitaxial substrate 100 according to this embodiment mainly includes a step (S10) of forming silicon carbide coating layer 70 on susceptor 210, a step (S20) of placing silicon carbide substrate 30 on susceptor 210, and a step (S30) of forming a silicon carbide epitaxial layer on silicon carbide substrate 30.

[0049] Fig. 8 is a cross-sectional schematic diagram showing the configuration of a susceptor. As shown in Fig. 8, a substrate placement pocket 60 is formed on an upper surface 63 of the susceptor 210. The substrate placement pocket 60 has a pocket bottom surface 61 and a pocket inner peripheral surface 62. The pocket inner peripheral surface 62 is continuous with the pocket bottom surface 61. The substrate placement pocket 60 is defined by the pocket bottom surface 61 and the pocket inner peripheral surface 62. The susceptor 210 is made of silicon carbide.

[0050] Silicon carbide particles 9 may be present on susceptor 210. Silicon carbide particles 9 with large diameters are removed by air blowing, but silicon carbide particles 9 with small diameters may adhere to pocket bottom surface 61. The diameter of silicon carbide particles 9 adhering to pocket bottom surface 61 is, for example, 1 μm or more and 10 μm or less. The diameter of silicon carbide particles 9 is not particularly limited, but may be, for example, 2 μm or more, or 3 μm or more. The diameter of silicon carbide particles 9 is not particularly limited, but may be, for example, 8 μm or less, or 5 μm or less.

[0051] Next, a step (S10) is performed of forming silicon carbide coating layer 70 on susceptor 210. FIG. 9 is a cross-sectional schematic view showing the step of forming silicon carbide coating layer 70 on susceptor 210.

[0052] 9, the silicon carbide coating layer 70 is formed on the susceptor 210 in a state where the silicon carbide substrate 30 is not placed in the substrate placement pocket 60 of the susceptor 210. Specifically, when the pressure in the reaction chamber 201 is reduced from atmospheric pressure by, for example, 1×10 -6 The pressure in the reaction chamber is then reduced to about Pa. Next, the temperature of the reaction chamber starts to rise. During the temperature rise, hydrogen (H 2 ) gas, which is a carrier gas, is introduced into the reaction chamber 201 from the fourth gas supply unit 234.

[0053] Next, a mixed gas containing, for example, silane (SiH), propane (C3H8), ammonia (NH3), and hydrogen is introduced into the reaction chamber 201. The mixed gas may contain argon (Ar). The flow rate of the first gas (propane) is, for example, 29 sccm. The flow rate of the second gas (silane) is, for example, 46 sccm. The flow rate of the third gas (ammonia) is, for example, 1.5 sccm. The flow rate of the fourth gas (hydrogen gas) is, for example, 100 slm.

[0054] The pressure inside reaction chamber 201 is maintained at, for example, 2 kPa or more and 6 kPa or less. The temperature inside reaction chamber 201 is controlled to, for example, 1500° C. or more and 1700° C. or less. As a result, silane, propane, and ammonia are each thermally decomposed inside reaction chamber 201, and silicon carbide coating layer 70 is formed on susceptor 210.

[0055] The silicon carbide coating layer 70 is formed to cover the surface of the substrate placement pocket 60. Specifically, the silicon carbide coating layer 70 is formed to contact each of the pocket bottom surface 61 and the pocket inner peripheral surface 62. The silicon carbide coating layer 70 may be formed to contact the upper surface 63 of the susceptor 210, or may be formed to contact the outer peripheral surface 64 of the susceptor 210.

[0056] The thickness of the silicon carbide coating layer 70 is defined as a fourth thickness H4. The fourth thickness H4 may be greater than the height of the silicon carbide particles 9. The height of the silicon carbide particles 9 is substantially the same as the diameter of the silicon carbide particles 9. When there are multiple silicon carbide particles 9, the fourth thickness H4 may be greater than the height of the largest silicon carbide particle 9 or may be greater than the height of the smallest silicon carbide particle 9. Note that the thickness of the silicon carbide coating layer 70 and the height of the silicon carbide particles 9 are each measured in a direction perpendicular to the planar pocket bottom surface 61.

[0057] Next, a step (S20) is performed of placing silicon carbide substrate 30 on susceptor 210. Fig. 10 is a cross-sectional schematic view showing the step of placing silicon carbide substrate 30 on susceptor 210.

[0058] 10 , the silicon carbide substrate 30 is placed in a substrate placement pocket 60 formed in the susceptor 210. The silicon carbide substrate 30 is placed on a silicon carbide coating layer 70. The second main surface 2 of the silicon carbide substrate 30 is in contact with the silicon carbide coating layer 70. The first main surface 1 of the silicon carbide substrate 30 is spaced apart from the silicon carbide coating layer 70.

[0059] The silicon carbide substrate 30 is placed in the substrate placement pocket 60 so that the second main surface 2 covers each of the plurality of silicon carbide particles 9. When the silicon carbide substrate 30 is placed in the substrate placement pocket 60, some of the plurality of silicon carbide particles 9 may adhere to the second main surface 2 of the silicon carbide substrate 30. As described above, the silicon carbide substrate 30 is placed on the susceptor 210 so that the silicon carbide substrate 30 is in contact with the silicon carbide coating layer 70. A partial region of the second main surface 2 of the silicon carbide substrate 30 may be in contact with the silicon carbide coating layer 70, and another region of the second main surface 2 may be spaced apart from the silicon carbide coating layer 70.

[0060] Next, a step (S30) is performed of forming a silicon carbide epitaxial layer on silicon carbide substrate 30. Figure 11 is a cross-sectional schematic view showing the step of forming a silicon carbide epitaxial layer on silicon carbide substrate 30.

[0061] 11, a silicon carbide epitaxial layer 40 is formed on a silicon carbide substrate 30. The silicon carbide epitaxial layer 40 is formed by a step-flow growth method. Specifically, the pressure in the reaction chamber 201 is increased from atmospheric pressure to, for example, 1×10 -6 The pressure in the reaction chamber is then reduced to about Pa. Next, the temperature of the reaction chamber starts to rise. During the temperature rise, hydrogen gas, which is a carrier gas, is introduced into the reaction chamber 201 from the fourth gas supply unit 234.

[0062] Next, a mixed gas containing, for example, silane, propane, ammonia, and hydrogen is introduced into the reaction chamber 201. The mixed gas may contain argon. The flow rate of the first gas (propane) is, for example, 29 sccm. The flow rate of the second gas (silane) is, for example, 46 sccm. The flow rate of the third gas (ammonia) is, for example, 1.5 sccm. The flow rate of the fourth gas (hydrogen gas) is, for example, 100 slm.

[0063] The pressure inside reaction chamber 201 is maintained at, for example, 2 kPa or more and 6 kPa or less. The temperature inside reaction chamber 201 is controlled to, for example, 1500°C or more and 1700°C or less. As a result, each of silane, propane, and ammonia is thermally decomposed inside reaction chamber 201, and silicon carbide epitaxial layer 40 is formed on silicon carbide substrate 30. The growth conditions for silicon carbide epitaxial layer 40 are substantially the same as the growth conditions for silicon carbide coating layer 70.

[0064] 11 , a first silicon carbide epitaxial layer 10 is formed on a first main surface 1 of a silicon carbide substrate 30, and a second silicon carbide epitaxial layer 20 is formed on a second main surface 2 of the silicon carbide substrate 30. The thickness of the first silicon carbide epitaxial layer 10 is greater than the thickness of the second silicon carbide epitaxial layer 20. The silicon carbide epitaxial layer 40 may be formed on the silicon carbide substrate 30, and a silicon carbide layer 71 may be formed on the silicon carbide coating layer 70. In this manner, the silicon carbide epitaxial substrate 100 according to this embodiment is obtained.

[0065] (Method of Manufacturing Silicon Carbide Semiconductor Device) Next, a method of manufacturing silicon carbide semiconductor device 400 according to this embodiment will be described. FIG. 12 is a flowchart that schematically shows the method of manufacturing silicon carbide semiconductor device 400 according to this embodiment. As shown in FIG. 12 , the method of manufacturing silicon carbide semiconductor device 400 according to this embodiment mainly includes a step (S1) of preparing silicon carbide epitaxial substrate 100, and a step (S2) of forming electrodes on silicon carbide epitaxial substrate 100.

[0066] First, a step (S1) of preparing silicon carbide epitaxial substrate 100 is performed. FIG. 13 is a cross-sectional schematic diagram showing the step of preparing silicon carbide epitaxial substrate 100. First, in the step (S1) of preparing silicon carbide epitaxial substrate 100, silicon carbide epitaxial substrate 100 according to the present embodiment is prepared (see FIGS. 1 and 2 ). As shown in FIG. 13 , first silicon carbide epitaxial layer 10 may have a buffer layer 41 and a drift layer 42. Buffer layer 41 is in contact with silicon carbide substrate 30. Drift layer 42 is provided on buffer layer 41. Drift layer 42 constitutes third main surface 11 of first silicon carbide epitaxial layer 10. Second silicon carbide epitaxial layer 20 has been removed, for example, by a polishing step.

[0067] Next, ions are implanted into silicon carbide epitaxial substrate 100. FIG. 14 is a schematic cross-sectional view showing a step of forming a body region. In the step of forming the body region, p-type impurities such as aluminum are ion-implanted into third main surface 11 of first silicon carbide epitaxial layer 10. This forms body region 113 having p-type conductivity. Portions where body region 113 is not formed become drift layer 42 and buffer layer 41. The thickness of body region 113 is, for example, 0.9 μm. First silicon carbide epitaxial layer 10 includes buffer layer 41, drift layer 42, and body region 113.

[0068] Next, a step of forming a source region is performed. FIG. 15 is a schematic cross-sectional view showing the step of forming the source region. Specifically, n-type impurities such as phosphorus are ion-implanted into the body region 113. This forms a source region 114 having n-type conductivity. The thickness of the source region 114 is, for example, 0.4 μm. The concentration of the n-type impurities in the source region 114 is higher than the concentration of the p-type impurities in the body region 113.

[0069] Next, a p-type impurity such as aluminum is ion-implanted into the source region 114 to form a contact region 118. The contact region 118 is formed to penetrate the source region 114 and the body region 113 and to be in contact with the drift layer 42. The concentration of the p-type impurity in the contact region 118 is higher than the concentration of the n-type impurity in the source region 114.

[0070] Next, activation annealing is performed to activate the implanted impurities. The temperature of the activation annealing is, for example, 1500° C. or higher and 1900° C. or lower. The activation annealing time is, for example, about 30 minutes. The atmosphere of the activation annealing is, for example, an argon atmosphere.

[0071] Next, a step of forming trenches in the third main surface 11 of the first silicon carbide epitaxial layer 10 is performed. FIG. 16 is a cross-sectional schematic diagram showing the step of forming trenches in the third main surface 11 of the first silicon carbide epitaxial layer 10. A mask 117 having openings is formed on the third main surface 11 including the source region 114 and the contact region 118. The source region 114, the body region 113, and a portion of the drift layer 42 are removed by etching using the mask 117. For example, inductively coupled plasma reactive ion etching can be used as the etching method. Specifically, for example, inductively coupled plasma reactive ion etching using SF or a mixed gas of SF and O as the reactive gas is used. Recesses are formed in the third main surface 11 by etching.

[0072] Next, thermal etching is performed on the recesses. Thermal etching can be performed, for example, by heating the mask 117 formed on the third main surface 11 in an atmosphere containing a reactive gas having at least one type of halogen atom. The at least one type of halogen atom includes at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere includes, for example, Cl2, BCl3, SF6, or CF4. For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as the reactive gas, and setting the heat treatment temperature to, for example, 700°C or higher and 1000°C or lower. The reactive gas may contain a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. Examples of the carrier gas that can be used include nitrogen gas, argon gas, and helium gas.

[0073] 16 , trenches 56 are formed in third main surface 11 by thermal etching. Trench 56 is defined by sidewall surfaces 53 and a bottom wall surface 54. Sidewall surface 53 is formed by source region 114, body region 113, and drift layer 42. Bottom wall surface 54 is formed by drift layer 42. Next, mask 117 is removed from third main surface 11.

[0074] Next, a step of forming a gate insulating film is performed. FIG. 17 is a schematic cross-sectional view showing the step of forming a gate insulating film. Specifically, silicon carbide epitaxial substrate 100 having trench 56 formed in third main surface 11 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300° C. or higher and 1400° C. or lower. This forms gate insulating film 115 that is in contact with drift layer 42 at bottom wall surface 54, in contact with drift layer 42, body region 113, and source region 114 at sidewall surface 53, and in contact with source region 114 and contact region 118 at third main surface 11.

[0075] Next, a step of forming a gate electrode is performed. FIG. 18 is a schematic cross-sectional view showing the step of forming a gate electrode and an interlayer insulating film. The gate electrode 127 is formed inside the trench 56 so as to be in contact with the gate insulating film 115. The gate electrode 127 is disposed inside the trench 56 and is formed on the gate insulating film 115 so as to face each of the sidewall surface 53 and the bottom wall surface 54 of the trench 56. The gate electrode 127 is formed by, for example, a low pressure chemical vapor deposition (LPCVD) method.

[0076] Next, an interlayer insulating film 126 is formed. The interlayer insulating film 126 is formed so as to cover the gate electrode 127 and to be in contact with the gate insulating film 115. The interlayer insulating film 126 is formed by, for example, chemical vapor deposition. The interlayer insulating film 126 is made of, for example, a material containing silicon dioxide. Next, the interlayer insulating film 126 and part of the gate insulating film 115 are etched so as to form openings over the source region 114 and the contact region 118. As a result, the contact region 118 and the source region 114 are exposed from the gate insulating film 115.

[0077] Next, a step of forming a source electrode is performed. The source electrode 116 is formed so as to be in contact with each of the source region 114 and the contact region 118. The source electrode 116 is formed by, for example, a sputtering method. The source electrode 116 is made of a material containing, for example, Ti (titanium), Al (aluminum), and Si (silicon).

[0078] Next, alloying annealing is performed. Specifically, the source electrode 116 in contact with each of the source region 114 and the contact region 118 is maintained at a temperature of, for example, 900° C. or higher and 1100° C. or lower for about 5 minutes. As a result, at least a portion of the source electrode 116 is silicided. This forms the source electrode 116 in ohmic contact with the source region 114. The source electrode 116 may also form an ohmic contact with the contact region 118.

[0079] Next, the source wiring 119 is formed. The source wiring 119 is electrically connected to the source electrode 116. The source wiring 119 is formed so as to cover the source electrode 116 and the interlayer insulating film 126.

[0080] Next, a step of forming a drain electrode is carried out. First, silicon carbide substrate 30 is polished at second main surface 2. This reduces the thickness of silicon carbide substrate 30. Next, drain electrode 123 is formed. Drain electrode 123 is formed so as to be in contact with second main surface 2. In this manner, silicon carbide semiconductor device 400 according to this embodiment is manufactured.

[0081] 19 is a cross-sectional schematic diagram showing the configuration of a silicon carbide semiconductor device 400 according to this embodiment. The silicon carbide semiconductor device 400 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The silicon carbide semiconductor device 400 mainly includes a silicon carbide epitaxial substrate 100, a gate electrode 127, a gate insulating film 115, a source electrode 116, a drain electrode 123, a source wiring 119, and an interlayer insulating film 126. The silicon carbide epitaxial substrate 100 includes a buffer layer 41, a drift layer 42, a body region 113, a source region 114, and a contact region 118. Silicon carbide semiconductor device 400 may be, for example, an IGBT (Insulated Gate Bipolar Transistor).

[0082] Next, the effects of the silicon carbide epitaxial substrate 100, the method for manufacturing the silicon carbide semiconductor device 400, and the method for manufacturing the silicon carbide epitaxial substrate 100 according to this embodiment will be described.

[0083] When the silicon carbide substrate 30 is placed in the substrate placement pocket 60 of the susceptor 210, the silicon carbide particles 9 adhering to the substrate placement pocket 60 may adhere to the back surface of the silicon carbide substrate 30. When a silicon carbide epitaxial layer is formed on the silicon carbide substrate 30, silicon carbide from the susceptor 210 sublimes, forming a silicon carbide epitaxial layer on the back surface of the silicon carbide substrate 30. If the silicon carbide particles 9 are attached to the back surface of the silicon carbide substrate 30, a silicon carbide epitaxial layer is not formed on the silicon carbide particles 9. As a result, a localized depression 5 is formed in the silicon carbide epitaxial layer formed on the back surface of the silicon carbide substrate 30.

[0084] In the method for manufacturing silicon carbide epitaxial substrate 100 according to this embodiment, silicon carbide coating layer 70 is formed on susceptor 210 without silicon carbide substrate 30 being placed thereon. Silicon carbide substrate 30 is placed on susceptor 210 so that silicon carbide substrate 30 is in contact with silicon carbide coating layer 70. This prevents silicon carbide substrate 30 from directly contacting susceptor 210. This makes it possible to reduce the number of silicon carbide particles 9 adhering to silicon carbide substrate 30, even when silicon carbide particles 9 are present on susceptor 210. As a result, the areal density of recesses 5 can be reduced.

[0085] Furthermore, according to the method for manufacturing silicon carbide epitaxial substrate 100 in accordance with this embodiment, silicon carbide coating layer 70 is formed on susceptor 210. Therefore, compared to when a coating layer is formed from a material other than silicon carbide, generation of gases other than silicon carbide can be suppressed. As a result, deterioration in the quality of silicon carbide epitaxial substrate 100 due to generation of gases other than silicon carbide can be suppressed.

[0086] According to the method for manufacturing silicon carbide epitaxial substrate 100, the thickness of silicon carbide coating layer 70 may be greater than the height of silicon carbide particles 9. This makes it possible to further reduce the number of silicon carbide particles 9 adhering to silicon carbide substrate 30. As a result, it is possible to further reduce the areal density of recesses 5.

[0087] In the silicon carbide epitaxial substrate 100 according to this embodiment, the first silicon carbide epitaxial layer 10 contacts the silicon carbide substrate 30 at the first main surface 1. The second silicon carbide epitaxial layer 20 contacts the silicon carbide substrate 30 at the second main surface 2. The thickness of the first silicon carbide epitaxial layer 10 is greater than the thickness of the second silicon carbide epitaxial layer 20. In plan view, the areal density of the recesses 5 in the central square region 4 of the second silicon carbide epitaxial layer 20 is 5 mm -2 This makes it possible to reduce the surface density of recesses 5 having a specific size. This makes it possible to suppress deterioration of adsorption of silicon carbide epitaxial substrate 100 in processes such as photolithography. As a result, it is possible to improve the yield of silicon carbide semiconductor devices 400 manufactured using silicon carbide epitaxial substrate 100.

[0088] (Sample Preparation) First, silicon carbide epitaxial substrates 100 according to Samples 1 to 8 were prepared. Silicon carbide epitaxial substrates 100 according to Samples 1 to 4 are comparative examples. Silicon carbide epitaxial substrates 100 according to Samples 5 to 8 are examples. The silicon carbide epitaxial substrates 100 according to Samples 1 to 8 had a diameter of 150 mm.

[0089] In the method for manufacturing silicon carbide epitaxial substrate 100 according to Samples 5 to 8, silicon carbide coating layer 70 was formed in substrate placement pocket 60 of susceptor 210. Specifically, silicon carbide epitaxial substrate 100 according to Samples 5 to 8 was fabricated using the method for manufacturing silicon carbide epitaxial substrate 100 shown in FIGS.

[0090] On the other hand, in the manufacturing methods of silicon carbide epitaxial substrates 100 according to Samples 1 to 4, silicon carbide coating layer 70 was not formed in substrate placement pocket 60 of susceptor 210. Specifically, a silicon carbide epitaxial layer was formed on silicon carbide substrate 30 in a state in which silicon carbide substrate 30 was directly placed in substrate placement pocket 60 of susceptor 210. When silicon carbide substrate 30 was directly placed in substrate placement pocket 60 of susceptor 210, a large number of silicon carbide particles 9 adhered to the back surface of silicon carbide substrate 30.

[0091] (Evaluation Method) Using a WASAVI series "SICA 6X" confocal differential interference microscope manufactured by Lasertec Corporation, images of the fifth main surface 21 of the second silicon carbide epitaxial layer 20 of the silicon carbide epitaxial substrate 100 relating to Samples 1 to 8 were taken. The number of recesses 5 in the central square region 4 of the fifth main surface 21 was measured. The maximum width of the recesses 5 was set to 10 μm or more and 100 μm or less. The surface density of the recesses 5 was determined by dividing the number of recesses 5 in the central square region 4 by the area of ​​the central square region 4. The length of one side of the central square region 4 was set to 5 mm.

[0092] The magnification of the objective lens was 10. Light with a wavelength of 546 nm was irradiated onto fifth main surface 21 of silicon carbide epitaxial substrate 100 from a mercury xenon lamp light source, and the reflected light of the light was observed using a light-receiving element. The threshold value, which is an index of the measurement sensitivity of SICA, was set to ThreshS40.

[0093] (Evaluation results)

[0094]

[0095] Table 1 shows the number of recesses 5 and the areal density of recesses 5 in central square region 4 of second silicon carbide epitaxial layer 20 in silicon carbide epitaxial substrate 100 according to Samples 1 to 4.

[0096] As shown in Table 1, in silicon carbide epitaxial substrates 100 according to Samples 1 to 4, the number of recesses 5 in central square region 4 of second silicon carbide epitaxial layer 20 was 163 or more and 195 or less. In silicon carbide epitaxial substrates 100 according to Samples 1 to 4, the areal density of recesses 5 in central square region 4 of second silicon carbide epitaxial layer 20 was 6.52 mm -2 Over 7.8mm -2 It was as follows.

[0097]

[0098] Table 2 shows the number of recesses 5 and the areal density of recesses 5 in central square region 4 of second silicon carbide epitaxial layer 20 in silicon carbide epitaxial substrate 100 according to Samples 5 to 8.

[0099] As shown in Table 2, in silicon carbide epitaxial substrates 100 according to Samples 5 to 8, the number of recesses 5 in central square region 4 of second silicon carbide epitaxial layer 20 was 53 or more and 80 or less. In silicon carbide epitaxial substrates 100 according to Samples 5 to 8, the areal density of recesses 5 in central square region 4 of second silicon carbide epitaxial layer 20 was 2.12 mm -2 Over 3.2 mm -2 It was as follows.

[0100] From the above results, it was verified that by using the method for manufacturing silicon carbide epitaxial substrate 100 according to this embodiment, it is possible to reduce the number of recesses 5 and the areal density of recesses 5 in central square region 4 of second silicon carbide epitaxial layer 20.

[0101] The embodiments and examples disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined by the claims, not by the above-described embodiments, and is intended to include meanings equivalent to the claims and all modifications within the scope thereof.

[0102] 1 First main surface, 2 Second main surface, 3 Center, 4 Central square region, 5 Recess, 6 Orientation flat, 7 Arc-shaped portion, 8 Outer periphery, 9 Silicon carbide particle, 10 First silicon carbide epitaxial layer, 11 Third main surface, 12 Fourth main surface, 20 Second silicon carbide epitaxial layer, 21 Fifth main surface, 22 Sixth main surface, 30 Silicon carbide substrate, 40 Silicon carbide epitaxial layer, 41 Buffer layer, 42 Drift layer, 51 First outer portion, 52 Second outer portion, 53 Side wall surface, 54 Bottom wall surface, 56 Trench, 60 Substrate placement pocket, 61 Pocket bottom surface, 62 Pocket inner peripheral surface, 63 Top surface, 64 Outer peripheral surface, 70 Silicon carbide coating layer, 71 Silicon carbide layer, 100 Silicon carbide epitaxial substrate, 101 first direction, 102 second direction, 103 third direction, 113 body region, 114 source region, 115 gate insulating film, 116 source electrode, 117 mask, 118 contact region, 119 source wiring, 123 drain electrode, 126 interlayer insulating film, 127 gate electrode, 200 manufacturing apparatus, 201 reaction chamber, 202 stage, 203 heating element, 204 quartz tube, 205 inner wall surface, 207 gas inlet, 208 gas exhaust port, 209 rotating shaft, 210 susceptor, 231 first gas supply unit, 232 second gas supply unit, 233 third gas supply unit, 234 fourth gas supply unit, 235 gas supply unit, 241 first gas flow rate control unit, 242 second gas flow rate control unit, 243 Third gas flow rate control section, 244 Fourth gas flow rate control section, 245 Control section, 400 Silicon carbide semiconductor device, H1 First thickness, H2 Second thickness, H3 Third thickness, H4 Fourth thickness, T Height, W1 Maximum diameter, W2 Maximum width.

Claims

1. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, A first silicon carbide epitaxial layer in contact with the silicon carbide substrate on the first main surface, The second main surface comprises a second silicon carbide epitaxial layer in contact with the silicon carbide substrate, The thickness of the first silicon carbide epitaxial layer is greater than the thickness of the second silicon carbide epitaxial layer. In a plan view, the surface density of depressions in the central square region of the second silicon carbide epitaxial layer is 5 mm -2 The following: The length of one side of the aforementioned central square region is 5 mm. A silicon carbide epitaxial substrate in which, in a plan view, the maximum width of the recess is 10 μm or more and 100 μm or less.

2. In a plan view, the outer shape of the recess has an arc-shaped portion, as described in claim 1, for the silicon carbide epitaxial substrate.

3. The surface density of the recess in the central square region is 4 mm -2 The silicon carbide epitaxial substrate according to claim 1 or claim 2, which is as follows:

4. The silicon carbide epitaxial substrate according to claim 1 or claim 2, wherein the thickness of the second silicon carbide epitaxial layer is 0.1 μm or more and 5 μm or less.

5. A step of preparing a silicon carbide epitaxial substrate according to claim 1 or claim 2, A method for manufacturing a silicon carbide semiconductor device, comprising the step of forming an electrode on the first silicon carbide epitaxial layer.

6. A step of forming a silicon carbide coating layer on a susceptor without a silicon carbide substrate being placed, A step of placing the silicon carbide substrate in the susceptor such that the silicon carbide substrate is in contact with the silicon carbide coating layer, A method for manufacturing a silicon carbide epitaxial substrate, comprising the step of forming a silicon carbide epitaxial layer on the silicon carbide substrate.

7. Silicon carbide particles are present on the susceptor, The method for manufacturing a silicon carbide epitaxial substrate according to claim 6, wherein the thickness of the silicon carbide coating layer is greater than the height of the silicon carbide particles.